1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/firmware.h> 30 #include <linux/module.h> 31 #include <linux/pci.h> 32 #include <linux/seq_file.h> 33 #include <linux/slab.h> 34 35 #include <drm/drm_device.h> 36 #include <drm/drm_file.h> 37 #include <drm/drm_fourcc.h> 38 #include <drm/drm_framebuffer.h> 39 #include <drm/drm_vblank.h> 40 #include <drm/radeon_drm.h> 41 42 #include "atom.h" 43 #include "r100_reg_safe.h" 44 #include "r100d.h" 45 #include "radeon.h" 46 #include "radeon_asic.h" 47 #include "radeon_reg.h" 48 #include "rn50_reg_safe.h" 49 #include "rs100d.h" 50 #include "rv200d.h" 51 #include "rv250d.h" 52 53 /* Firmware Names */ 54 #define FIRMWARE_R100 "radeon/R100_cp.bin" 55 #define FIRMWARE_R200 "radeon/R200_cp.bin" 56 #define FIRMWARE_R300 "radeon/R300_cp.bin" 57 #define FIRMWARE_R420 "radeon/R420_cp.bin" 58 #define FIRMWARE_RS690 "radeon/RS690_cp.bin" 59 #define FIRMWARE_RS600 "radeon/RS600_cp.bin" 60 #define FIRMWARE_R520 "radeon/R520_cp.bin" 61 62 MODULE_FIRMWARE(FIRMWARE_R100); 63 MODULE_FIRMWARE(FIRMWARE_R200); 64 MODULE_FIRMWARE(FIRMWARE_R300); 65 MODULE_FIRMWARE(FIRMWARE_R420); 66 MODULE_FIRMWARE(FIRMWARE_RS690); 67 MODULE_FIRMWARE(FIRMWARE_RS600); 68 MODULE_FIRMWARE(FIRMWARE_R520); 69 70 #include "r100_track.h" 71 72 /* This files gather functions specifics to: 73 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 74 * and others in some cases. 75 */ 76 77 static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc) 78 { 79 if (crtc == 0) { 80 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) 81 return true; 82 else 83 return false; 84 } else { 85 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) 86 return true; 87 else 88 return false; 89 } 90 } 91 92 static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc) 93 { 94 u32 vline1, vline2; 95 96 if (crtc == 0) { 97 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 98 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 99 } else { 100 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 101 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 102 } 103 if (vline1 != vline2) 104 return true; 105 else 106 return false; 107 } 108 109 /** 110 * r100_wait_for_vblank - vblank wait asic callback. 111 * 112 * @rdev: radeon_device pointer 113 * @crtc: crtc to wait for vblank on 114 * 115 * Wait for vblank on the requested crtc (r1xx-r4xx). 116 */ 117 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc) 118 { 119 unsigned i = 0; 120 121 if (crtc >= rdev->num_crtc) 122 return; 123 124 if (crtc == 0) { 125 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN)) 126 return; 127 } else { 128 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN)) 129 return; 130 } 131 132 /* depending on when we hit vblank, we may be close to active; if so, 133 * wait for another frame. 134 */ 135 while (r100_is_in_vblank(rdev, crtc)) { 136 if (i++ % 100 == 0) { 137 if (!r100_is_counter_moving(rdev, crtc)) 138 break; 139 } 140 } 141 142 while (!r100_is_in_vblank(rdev, crtc)) { 143 if (i++ % 100 == 0) { 144 if (!r100_is_counter_moving(rdev, crtc)) 145 break; 146 } 147 } 148 } 149 150 /** 151 * r100_page_flip - pageflip callback. 152 * 153 * @rdev: radeon_device pointer 154 * @crtc_id: crtc to cleanup pageflip on 155 * @crtc_base: new address of the crtc (GPU MC address) 156 * @async: asynchronous flip 157 * 158 * Does the actual pageflip (r1xx-r4xx). 159 * During vblank we take the crtc lock and wait for the update_pending 160 * bit to go high, when it does, we release the lock, and allow the 161 * double buffered update to take place. 162 */ 163 void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async) 164 { 165 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 166 uint32_t crtc_pitch, pitch_pixels; 167 struct drm_framebuffer *fb = radeon_crtc->base.primary->fb; 168 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; 169 int i; 170 171 /* Lock the graphics update lock */ 172 /* update the scanout addresses */ 173 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 174 175 /* update pitch */ 176 pitch_pixels = fb->pitches[0] / fb->format->cpp[0]; 177 crtc_pitch = DIV_ROUND_UP(pitch_pixels * fb->format->cpp[0] * 8, 178 fb->format->cpp[0] * 8 * 8); 179 crtc_pitch |= crtc_pitch << 16; 180 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); 181 182 /* Wait for update_pending to go high. */ 183 for (i = 0; i < rdev->usec_timeout; i++) { 184 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) 185 break; 186 udelay(1); 187 } 188 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 189 190 /* Unlock the lock, so double-buffering can take place inside vblank */ 191 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK; 192 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 193 194 } 195 196 /** 197 * r100_page_flip_pending - check if page flip is still pending 198 * 199 * @rdev: radeon_device pointer 200 * @crtc_id: crtc to check 201 * 202 * Check if the last pagefilp is still pending (r1xx-r4xx). 203 * Returns the current update pending status. 204 */ 205 bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id) 206 { 207 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 208 209 /* Return current update_pending status: */ 210 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & 211 RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET); 212 } 213 214 /** 215 * r100_pm_get_dynpm_state - look up dynpm power state callback. 216 * 217 * @rdev: radeon_device pointer 218 * 219 * Look up the optimal power state based on the 220 * current state of the GPU (r1xx-r5xx). 221 * Used for dynpm only. 222 */ 223 void r100_pm_get_dynpm_state(struct radeon_device *rdev) 224 { 225 int i; 226 rdev->pm.dynpm_can_upclock = true; 227 rdev->pm.dynpm_can_downclock = true; 228 229 switch (rdev->pm.dynpm_planned_action) { 230 case DYNPM_ACTION_MINIMUM: 231 rdev->pm.requested_power_state_index = 0; 232 rdev->pm.dynpm_can_downclock = false; 233 break; 234 case DYNPM_ACTION_DOWNCLOCK: 235 if (rdev->pm.current_power_state_index == 0) { 236 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 237 rdev->pm.dynpm_can_downclock = false; 238 } else { 239 if (rdev->pm.active_crtc_count > 1) { 240 for (i = 0; i < rdev->pm.num_power_states; i++) { 241 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 242 continue; 243 else if (i >= rdev->pm.current_power_state_index) { 244 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 245 break; 246 } else { 247 rdev->pm.requested_power_state_index = i; 248 break; 249 } 250 } 251 } else 252 rdev->pm.requested_power_state_index = 253 rdev->pm.current_power_state_index - 1; 254 } 255 /* don't use the power state if crtcs are active and no display flag is set */ 256 if ((rdev->pm.active_crtc_count > 0) && 257 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & 258 RADEON_PM_MODE_NO_DISPLAY)) { 259 rdev->pm.requested_power_state_index++; 260 } 261 break; 262 case DYNPM_ACTION_UPCLOCK: 263 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 264 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 265 rdev->pm.dynpm_can_upclock = false; 266 } else { 267 if (rdev->pm.active_crtc_count > 1) { 268 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 269 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 270 continue; 271 else if (i <= rdev->pm.current_power_state_index) { 272 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 273 break; 274 } else { 275 rdev->pm.requested_power_state_index = i; 276 break; 277 } 278 } 279 } else 280 rdev->pm.requested_power_state_index = 281 rdev->pm.current_power_state_index + 1; 282 } 283 break; 284 case DYNPM_ACTION_DEFAULT: 285 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 286 rdev->pm.dynpm_can_upclock = false; 287 break; 288 case DYNPM_ACTION_NONE: 289 default: 290 DRM_ERROR("Requested mode for not defined action\n"); 291 return; 292 } 293 /* only one clock mode per power state */ 294 rdev->pm.requested_clock_mode_index = 0; 295 296 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 297 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 298 clock_info[rdev->pm.requested_clock_mode_index].sclk, 299 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 300 clock_info[rdev->pm.requested_clock_mode_index].mclk, 301 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 302 pcie_lanes); 303 } 304 305 /** 306 * r100_pm_init_profile - Initialize power profiles callback. 307 * 308 * @rdev: radeon_device pointer 309 * 310 * Initialize the power states used in profile mode 311 * (r1xx-r3xx). 312 * Used for profile mode only. 313 */ 314 void r100_pm_init_profile(struct radeon_device *rdev) 315 { 316 /* default */ 317 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 318 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 319 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 320 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 321 /* low sh */ 322 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 323 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 324 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 325 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 326 /* mid sh */ 327 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 328 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 329 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 330 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 331 /* high sh */ 332 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 333 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 334 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 335 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 336 /* low mh */ 337 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 338 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 339 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 340 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 341 /* mid mh */ 342 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 343 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 344 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 345 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 346 /* high mh */ 347 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 348 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 349 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 350 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 351 } 352 353 /** 354 * r100_pm_misc - set additional pm hw parameters callback. 355 * 356 * @rdev: radeon_device pointer 357 * 358 * Set non-clock parameters associated with a power state 359 * (voltage, pcie lanes, etc.) (r1xx-r4xx). 360 */ 361 void r100_pm_misc(struct radeon_device *rdev) 362 { 363 int requested_index = rdev->pm.requested_power_state_index; 364 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 365 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 366 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl; 367 368 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { 369 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { 370 tmp = RREG32(voltage->gpio.reg); 371 if (voltage->active_high) 372 tmp |= voltage->gpio.mask; 373 else 374 tmp &= ~(voltage->gpio.mask); 375 WREG32(voltage->gpio.reg, tmp); 376 if (voltage->delay) 377 udelay(voltage->delay); 378 } else { 379 tmp = RREG32(voltage->gpio.reg); 380 if (voltage->active_high) 381 tmp &= ~voltage->gpio.mask; 382 else 383 tmp |= voltage->gpio.mask; 384 WREG32(voltage->gpio.reg, tmp); 385 if (voltage->delay) 386 udelay(voltage->delay); 387 } 388 } 389 390 sclk_cntl = RREG32_PLL(SCLK_CNTL); 391 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2); 392 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3); 393 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL); 394 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3); 395 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { 396 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN; 397 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE) 398 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE; 399 else 400 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE; 401 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) 402 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0); 403 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) 404 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2); 405 } else 406 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN; 407 408 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { 409 sclk_more_cntl |= IO_CG_VOLTAGE_DROP; 410 if (voltage->delay) { 411 sclk_more_cntl |= VOLTAGE_DROP_SYNC; 412 switch (voltage->delay) { 413 case 33: 414 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0); 415 break; 416 case 66: 417 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1); 418 break; 419 case 99: 420 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2); 421 break; 422 case 132: 423 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3); 424 break; 425 } 426 } else 427 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC; 428 } else 429 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP; 430 431 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) 432 sclk_cntl &= ~FORCE_HDP; 433 else 434 sclk_cntl |= FORCE_HDP; 435 436 WREG32_PLL(SCLK_CNTL, sclk_cntl); 437 WREG32_PLL(SCLK_CNTL2, sclk_cntl2); 438 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl); 439 440 /* set pcie lanes */ 441 if ((rdev->flags & RADEON_IS_PCIE) && 442 !(rdev->flags & RADEON_IS_IGP) && 443 rdev->asic->pm.set_pcie_lanes && 444 (ps->pcie_lanes != 445 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { 446 radeon_set_pcie_lanes(rdev, 447 ps->pcie_lanes); 448 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes); 449 } 450 } 451 452 /** 453 * r100_pm_prepare - pre-power state change callback. 454 * 455 * @rdev: radeon_device pointer 456 * 457 * Prepare for a power state change (r1xx-r4xx). 458 */ 459 void r100_pm_prepare(struct radeon_device *rdev) 460 { 461 struct drm_device *ddev = rdev->ddev; 462 struct drm_crtc *crtc; 463 struct radeon_crtc *radeon_crtc; 464 u32 tmp; 465 466 /* disable any active CRTCs */ 467 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 468 radeon_crtc = to_radeon_crtc(crtc); 469 if (radeon_crtc->enabled) { 470 if (radeon_crtc->crtc_id) { 471 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 472 tmp |= RADEON_CRTC2_DISP_REQ_EN_B; 473 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 474 } else { 475 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 476 tmp |= RADEON_CRTC_DISP_REQ_EN_B; 477 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 478 } 479 } 480 } 481 } 482 483 /** 484 * r100_pm_finish - post-power state change callback. 485 * 486 * @rdev: radeon_device pointer 487 * 488 * Clean up after a power state change (r1xx-r4xx). 489 */ 490 void r100_pm_finish(struct radeon_device *rdev) 491 { 492 struct drm_device *ddev = rdev->ddev; 493 struct drm_crtc *crtc; 494 struct radeon_crtc *radeon_crtc; 495 u32 tmp; 496 497 /* enable any active CRTCs */ 498 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 499 radeon_crtc = to_radeon_crtc(crtc); 500 if (radeon_crtc->enabled) { 501 if (radeon_crtc->crtc_id) { 502 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 503 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B; 504 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 505 } else { 506 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 507 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B; 508 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 509 } 510 } 511 } 512 } 513 514 /** 515 * r100_gui_idle - gui idle callback. 516 * 517 * @rdev: radeon_device pointer 518 * 519 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx). 520 * Returns true if idle, false if not. 521 */ 522 bool r100_gui_idle(struct radeon_device *rdev) 523 { 524 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) 525 return false; 526 else 527 return true; 528 } 529 530 /* hpd for digital panel detect/disconnect */ 531 /** 532 * r100_hpd_sense - hpd sense callback. 533 * 534 * @rdev: radeon_device pointer 535 * @hpd: hpd (hotplug detect) pin 536 * 537 * Checks if a digital monitor is connected (r1xx-r4xx). 538 * Returns true if connected, false if not connected. 539 */ 540 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 541 { 542 bool connected = false; 543 544 switch (hpd) { 545 case RADEON_HPD_1: 546 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) 547 connected = true; 548 break; 549 case RADEON_HPD_2: 550 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) 551 connected = true; 552 break; 553 default: 554 break; 555 } 556 return connected; 557 } 558 559 /** 560 * r100_hpd_set_polarity - hpd set polarity callback. 561 * 562 * @rdev: radeon_device pointer 563 * @hpd: hpd (hotplug detect) pin 564 * 565 * Set the polarity of the hpd pin (r1xx-r4xx). 566 */ 567 void r100_hpd_set_polarity(struct radeon_device *rdev, 568 enum radeon_hpd_id hpd) 569 { 570 u32 tmp; 571 bool connected = r100_hpd_sense(rdev, hpd); 572 573 switch (hpd) { 574 case RADEON_HPD_1: 575 tmp = RREG32(RADEON_FP_GEN_CNTL); 576 if (connected) 577 tmp &= ~RADEON_FP_DETECT_INT_POL; 578 else 579 tmp |= RADEON_FP_DETECT_INT_POL; 580 WREG32(RADEON_FP_GEN_CNTL, tmp); 581 break; 582 case RADEON_HPD_2: 583 tmp = RREG32(RADEON_FP2_GEN_CNTL); 584 if (connected) 585 tmp &= ~RADEON_FP2_DETECT_INT_POL; 586 else 587 tmp |= RADEON_FP2_DETECT_INT_POL; 588 WREG32(RADEON_FP2_GEN_CNTL, tmp); 589 break; 590 default: 591 break; 592 } 593 } 594 595 /** 596 * r100_hpd_init - hpd setup callback. 597 * 598 * @rdev: radeon_device pointer 599 * 600 * Setup the hpd pins used by the card (r1xx-r4xx). 601 * Set the polarity, and enable the hpd interrupts. 602 */ 603 void r100_hpd_init(struct radeon_device *rdev) 604 { 605 struct drm_device *dev = rdev->ddev; 606 struct drm_connector *connector; 607 unsigned enable = 0; 608 609 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 610 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 611 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 612 enable |= 1 << radeon_connector->hpd.hpd; 613 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 614 } 615 radeon_irq_kms_enable_hpd(rdev, enable); 616 } 617 618 /** 619 * r100_hpd_fini - hpd tear down callback. 620 * 621 * @rdev: radeon_device pointer 622 * 623 * Tear down the hpd pins used by the card (r1xx-r4xx). 624 * Disable the hpd interrupts. 625 */ 626 void r100_hpd_fini(struct radeon_device *rdev) 627 { 628 struct drm_device *dev = rdev->ddev; 629 struct drm_connector *connector; 630 unsigned disable = 0; 631 632 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 633 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 634 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 635 disable |= 1 << radeon_connector->hpd.hpd; 636 } 637 radeon_irq_kms_disable_hpd(rdev, disable); 638 } 639 640 /* 641 * PCI GART 642 */ 643 void r100_pci_gart_tlb_flush(struct radeon_device *rdev) 644 { 645 /* TODO: can we do somethings here ? */ 646 /* It seems hw only cache one entry so we should discard this 647 * entry otherwise if first GPU GART read hit this entry it 648 * could end up in wrong address. */ 649 } 650 651 int r100_pci_gart_init(struct radeon_device *rdev) 652 { 653 int r; 654 655 if (rdev->gart.ptr) { 656 WARN(1, "R100 PCI GART already initialized\n"); 657 return 0; 658 } 659 /* Initialize common gart structure */ 660 r = radeon_gart_init(rdev); 661 if (r) 662 return r; 663 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 664 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 665 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; 666 rdev->asic->gart.set_page = &r100_pci_gart_set_page; 667 return radeon_gart_table_ram_alloc(rdev); 668 } 669 670 int r100_pci_gart_enable(struct radeon_device *rdev) 671 { 672 uint32_t tmp; 673 674 /* discard memory request outside of configured range */ 675 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 676 WREG32(RADEON_AIC_CNTL, tmp); 677 /* set address range for PCI address translate */ 678 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); 679 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); 680 /* set PCI GART page-table base address */ 681 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); 682 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; 683 WREG32(RADEON_AIC_CNTL, tmp); 684 r100_pci_gart_tlb_flush(rdev); 685 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n", 686 (unsigned)(rdev->mc.gtt_size >> 20), 687 (unsigned long long)rdev->gart.table_addr); 688 rdev->gart.ready = true; 689 return 0; 690 } 691 692 void r100_pci_gart_disable(struct radeon_device *rdev) 693 { 694 uint32_t tmp; 695 696 /* discard memory request outside of configured range */ 697 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 698 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); 699 WREG32(RADEON_AIC_LO_ADDR, 0); 700 WREG32(RADEON_AIC_HI_ADDR, 0); 701 } 702 703 uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags) 704 { 705 return addr; 706 } 707 708 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i, 709 uint64_t entry) 710 { 711 u32 *gtt = rdev->gart.ptr; 712 gtt[i] = cpu_to_le32(lower_32_bits(entry)); 713 } 714 715 void r100_pci_gart_fini(struct radeon_device *rdev) 716 { 717 radeon_gart_fini(rdev); 718 r100_pci_gart_disable(rdev); 719 radeon_gart_table_ram_free(rdev); 720 } 721 722 int r100_irq_set(struct radeon_device *rdev) 723 { 724 uint32_t tmp = 0; 725 726 if (!rdev->irq.installed) { 727 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 728 WREG32(R_000040_GEN_INT_CNTL, 0); 729 return -EINVAL; 730 } 731 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 732 tmp |= RADEON_SW_INT_ENABLE; 733 } 734 if (rdev->irq.crtc_vblank_int[0] || 735 atomic_read(&rdev->irq.pflip[0])) { 736 tmp |= RADEON_CRTC_VBLANK_MASK; 737 } 738 if (rdev->irq.crtc_vblank_int[1] || 739 atomic_read(&rdev->irq.pflip[1])) { 740 tmp |= RADEON_CRTC2_VBLANK_MASK; 741 } 742 if (rdev->irq.hpd[0]) { 743 tmp |= RADEON_FP_DETECT_MASK; 744 } 745 if (rdev->irq.hpd[1]) { 746 tmp |= RADEON_FP2_DETECT_MASK; 747 } 748 WREG32(RADEON_GEN_INT_CNTL, tmp); 749 750 /* read back to post the write */ 751 RREG32(RADEON_GEN_INT_CNTL); 752 753 return 0; 754 } 755 756 void r100_irq_disable(struct radeon_device *rdev) 757 { 758 u32 tmp; 759 760 WREG32(R_000040_GEN_INT_CNTL, 0); 761 /* Wait and acknowledge irq */ 762 mdelay(1); 763 tmp = RREG32(R_000044_GEN_INT_STATUS); 764 WREG32(R_000044_GEN_INT_STATUS, tmp); 765 } 766 767 static uint32_t r100_irq_ack(struct radeon_device *rdev) 768 { 769 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); 770 uint32_t irq_mask = RADEON_SW_INT_TEST | 771 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | 772 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; 773 774 if (irqs) { 775 WREG32(RADEON_GEN_INT_STATUS, irqs); 776 } 777 return irqs & irq_mask; 778 } 779 780 int r100_irq_process(struct radeon_device *rdev) 781 { 782 uint32_t status, msi_rearm; 783 bool queue_hotplug = false; 784 785 status = r100_irq_ack(rdev); 786 if (!status) { 787 return IRQ_NONE; 788 } 789 if (rdev->shutdown) { 790 return IRQ_NONE; 791 } 792 while (status) { 793 /* SW interrupt */ 794 if (status & RADEON_SW_INT_TEST) { 795 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 796 } 797 /* Vertical blank interrupts */ 798 if (status & RADEON_CRTC_VBLANK_STAT) { 799 if (rdev->irq.crtc_vblank_int[0]) { 800 drm_handle_vblank(rdev->ddev, 0); 801 rdev->pm.vblank_sync = true; 802 wake_up(&rdev->irq.vblank_queue); 803 } 804 if (atomic_read(&rdev->irq.pflip[0])) 805 radeon_crtc_handle_vblank(rdev, 0); 806 } 807 if (status & RADEON_CRTC2_VBLANK_STAT) { 808 if (rdev->irq.crtc_vblank_int[1]) { 809 drm_handle_vblank(rdev->ddev, 1); 810 rdev->pm.vblank_sync = true; 811 wake_up(&rdev->irq.vblank_queue); 812 } 813 if (atomic_read(&rdev->irq.pflip[1])) 814 radeon_crtc_handle_vblank(rdev, 1); 815 } 816 if (status & RADEON_FP_DETECT_STAT) { 817 queue_hotplug = true; 818 DRM_DEBUG("HPD1\n"); 819 } 820 if (status & RADEON_FP2_DETECT_STAT) { 821 queue_hotplug = true; 822 DRM_DEBUG("HPD2\n"); 823 } 824 status = r100_irq_ack(rdev); 825 } 826 if (queue_hotplug) 827 schedule_delayed_work(&rdev->hotplug_work, 0); 828 if (rdev->msi_enabled) { 829 switch (rdev->family) { 830 case CHIP_RS400: 831 case CHIP_RS480: 832 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; 833 WREG32(RADEON_AIC_CNTL, msi_rearm); 834 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); 835 break; 836 default: 837 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); 838 break; 839 } 840 } 841 return IRQ_HANDLED; 842 } 843 844 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) 845 { 846 if (crtc == 0) 847 return RREG32(RADEON_CRTC_CRNT_FRAME); 848 else 849 return RREG32(RADEON_CRTC2_CRNT_FRAME); 850 } 851 852 /** 853 * r100_ring_hdp_flush - flush Host Data Path via the ring buffer 854 * @rdev: radeon device structure 855 * @ring: ring buffer struct for emitting packets 856 */ 857 static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring) 858 { 859 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 860 radeon_ring_write(ring, rdev->config.r100.hdp_cntl | 861 RADEON_HDP_READ_BUFFER_INVALIDATE); 862 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 863 radeon_ring_write(ring, rdev->config.r100.hdp_cntl); 864 } 865 866 /* Who ever call radeon_fence_emit should call ring_lock and ask 867 * for enough space (today caller are ib schedule and buffer move) */ 868 void r100_fence_ring_emit(struct radeon_device *rdev, 869 struct radeon_fence *fence) 870 { 871 struct radeon_ring *ring = &rdev->ring[fence->ring]; 872 873 /* We have to make sure that caches are flushed before 874 * CPU might read something from VRAM. */ 875 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); 876 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL); 877 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); 878 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL); 879 /* Wait until IDLE & CLEAN */ 880 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 881 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 882 r100_ring_hdp_flush(rdev, ring); 883 /* Emit fence sequence & fire IRQ */ 884 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); 885 radeon_ring_write(ring, fence->seq); 886 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); 887 radeon_ring_write(ring, RADEON_SW_INT_FIRE); 888 } 889 890 bool r100_semaphore_ring_emit(struct radeon_device *rdev, 891 struct radeon_ring *ring, 892 struct radeon_semaphore *semaphore, 893 bool emit_wait) 894 { 895 /* Unused on older asics, since we don't have semaphores or multiple rings */ 896 BUG(); 897 return false; 898 } 899 900 struct radeon_fence *r100_copy_blit(struct radeon_device *rdev, 901 uint64_t src_offset, 902 uint64_t dst_offset, 903 unsigned num_gpu_pages, 904 struct dma_resv *resv) 905 { 906 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 907 struct radeon_fence *fence; 908 uint32_t cur_pages; 909 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE; 910 uint32_t pitch; 911 uint32_t stride_pixels; 912 unsigned ndw; 913 int num_loops; 914 int r = 0; 915 916 /* radeon limited to 16k stride */ 917 stride_bytes &= 0x3fff; 918 /* radeon pitch is /64 */ 919 pitch = stride_bytes / 64; 920 stride_pixels = stride_bytes / 4; 921 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191); 922 923 /* Ask for enough room for blit + flush + fence */ 924 ndw = 64 + (10 * num_loops); 925 r = radeon_ring_lock(rdev, ring, ndw); 926 if (r) { 927 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); 928 return ERR_PTR(-EINVAL); 929 } 930 while (num_gpu_pages > 0) { 931 cur_pages = num_gpu_pages; 932 if (cur_pages > 8191) { 933 cur_pages = 8191; 934 } 935 num_gpu_pages -= cur_pages; 936 937 /* pages are in Y direction - height 938 page width in X direction - width */ 939 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8)); 940 radeon_ring_write(ring, 941 RADEON_GMC_SRC_PITCH_OFFSET_CNTL | 942 RADEON_GMC_DST_PITCH_OFFSET_CNTL | 943 RADEON_GMC_SRC_CLIPPING | 944 RADEON_GMC_DST_CLIPPING | 945 RADEON_GMC_BRUSH_NONE | 946 (RADEON_COLOR_FORMAT_ARGB8888 << 8) | 947 RADEON_GMC_SRC_DATATYPE_COLOR | 948 RADEON_ROP3_S | 949 RADEON_DP_SRC_SOURCE_MEMORY | 950 RADEON_GMC_CLR_CMP_CNTL_DIS | 951 RADEON_GMC_WR_MSK_DIS); 952 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10)); 953 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10)); 954 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); 955 radeon_ring_write(ring, 0); 956 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); 957 radeon_ring_write(ring, num_gpu_pages); 958 radeon_ring_write(ring, num_gpu_pages); 959 radeon_ring_write(ring, cur_pages | (stride_pixels << 16)); 960 } 961 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); 962 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL); 963 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 964 radeon_ring_write(ring, 965 RADEON_WAIT_2D_IDLECLEAN | 966 RADEON_WAIT_HOST_IDLECLEAN | 967 RADEON_WAIT_DMA_GUI_IDLE); 968 r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX); 969 if (r) { 970 radeon_ring_unlock_undo(rdev, ring); 971 return ERR_PTR(r); 972 } 973 radeon_ring_unlock_commit(rdev, ring, false); 974 return fence; 975 } 976 977 static int r100_cp_wait_for_idle(struct radeon_device *rdev) 978 { 979 unsigned i; 980 u32 tmp; 981 982 for (i = 0; i < rdev->usec_timeout; i++) { 983 tmp = RREG32(R_000E40_RBBM_STATUS); 984 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { 985 return 0; 986 } 987 udelay(1); 988 } 989 return -1; 990 } 991 992 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 993 { 994 int r; 995 996 r = radeon_ring_lock(rdev, ring, 2); 997 if (r) { 998 return; 999 } 1000 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); 1001 radeon_ring_write(ring, 1002 RADEON_ISYNC_ANY2D_IDLE3D | 1003 RADEON_ISYNC_ANY3D_IDLE2D | 1004 RADEON_ISYNC_WAIT_IDLEGUI | 1005 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 1006 radeon_ring_unlock_commit(rdev, ring, false); 1007 } 1008 1009 1010 /* Load the microcode for the CP */ 1011 static int r100_cp_init_microcode(struct radeon_device *rdev) 1012 { 1013 const char *fw_name = NULL; 1014 int err; 1015 1016 DRM_DEBUG_KMS("\n"); 1017 1018 switch (rdev->family) { 1019 case CHIP_R100: 1020 case CHIP_RV100: 1021 case CHIP_RV200: 1022 case CHIP_RS100: 1023 case CHIP_RS200: 1024 DRM_INFO("Loading R100 Microcode\n"); 1025 fw_name = FIRMWARE_R100; 1026 break; 1027 1028 case CHIP_R200: 1029 case CHIP_RV250: 1030 case CHIP_RV280: 1031 case CHIP_RS300: 1032 DRM_INFO("Loading R200 Microcode\n"); 1033 fw_name = FIRMWARE_R200; 1034 break; 1035 1036 case CHIP_R300: 1037 case CHIP_R350: 1038 case CHIP_RV350: 1039 case CHIP_RV380: 1040 case CHIP_RS400: 1041 case CHIP_RS480: 1042 DRM_INFO("Loading R300 Microcode\n"); 1043 fw_name = FIRMWARE_R300; 1044 break; 1045 1046 case CHIP_R420: 1047 case CHIP_R423: 1048 case CHIP_RV410: 1049 DRM_INFO("Loading R400 Microcode\n"); 1050 fw_name = FIRMWARE_R420; 1051 break; 1052 1053 case CHIP_RS690: 1054 case CHIP_RS740: 1055 DRM_INFO("Loading RS690/RS740 Microcode\n"); 1056 fw_name = FIRMWARE_RS690; 1057 break; 1058 1059 case CHIP_RS600: 1060 DRM_INFO("Loading RS600 Microcode\n"); 1061 fw_name = FIRMWARE_RS600; 1062 break; 1063 1064 case CHIP_RV515: 1065 case CHIP_R520: 1066 case CHIP_RV530: 1067 case CHIP_R580: 1068 case CHIP_RV560: 1069 case CHIP_RV570: 1070 DRM_INFO("Loading R500 Microcode\n"); 1071 fw_name = FIRMWARE_R520; 1072 break; 1073 1074 default: 1075 DRM_ERROR("Unsupported Radeon family %u\n", rdev->family); 1076 return -EINVAL; 1077 } 1078 1079 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); 1080 if (err) { 1081 pr_err("radeon_cp: Failed to load firmware \"%s\"\n", fw_name); 1082 } else if (rdev->me_fw->size % 8) { 1083 pr_err("radeon_cp: Bogus length %zu in firmware \"%s\"\n", 1084 rdev->me_fw->size, fw_name); 1085 err = -EINVAL; 1086 release_firmware(rdev->me_fw); 1087 rdev->me_fw = NULL; 1088 } 1089 return err; 1090 } 1091 1092 u32 r100_gfx_get_rptr(struct radeon_device *rdev, 1093 struct radeon_ring *ring) 1094 { 1095 u32 rptr; 1096 1097 if (rdev->wb.enabled) 1098 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); 1099 else 1100 rptr = RREG32(RADEON_CP_RB_RPTR); 1101 1102 return rptr; 1103 } 1104 1105 u32 r100_gfx_get_wptr(struct radeon_device *rdev, 1106 struct radeon_ring *ring) 1107 { 1108 return RREG32(RADEON_CP_RB_WPTR); 1109 } 1110 1111 void r100_gfx_set_wptr(struct radeon_device *rdev, 1112 struct radeon_ring *ring) 1113 { 1114 WREG32(RADEON_CP_RB_WPTR, ring->wptr); 1115 (void)RREG32(RADEON_CP_RB_WPTR); 1116 } 1117 1118 static void r100_cp_load_microcode(struct radeon_device *rdev) 1119 { 1120 const __be32 *fw_data; 1121 int i, size; 1122 1123 if (r100_gui_wait_for_idle(rdev)) { 1124 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 1125 } 1126 1127 if (rdev->me_fw) { 1128 size = rdev->me_fw->size / 4; 1129 fw_data = (const __be32 *)&rdev->me_fw->data[0]; 1130 WREG32(RADEON_CP_ME_RAM_ADDR, 0); 1131 for (i = 0; i < size; i += 2) { 1132 WREG32(RADEON_CP_ME_RAM_DATAH, 1133 be32_to_cpup(&fw_data[i])); 1134 WREG32(RADEON_CP_ME_RAM_DATAL, 1135 be32_to_cpup(&fw_data[i + 1])); 1136 } 1137 } 1138 } 1139 1140 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) 1141 { 1142 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1143 unsigned rb_bufsz; 1144 unsigned rb_blksz; 1145 unsigned max_fetch; 1146 unsigned pre_write_timer; 1147 unsigned pre_write_limit; 1148 unsigned indirect2_start; 1149 unsigned indirect1_start; 1150 uint32_t tmp; 1151 int r; 1152 1153 r100_debugfs_cp_init(rdev); 1154 if (!rdev->me_fw) { 1155 r = r100_cp_init_microcode(rdev); 1156 if (r) { 1157 DRM_ERROR("Failed to load firmware!\n"); 1158 return r; 1159 } 1160 } 1161 1162 /* Align ring size */ 1163 rb_bufsz = order_base_2(ring_size / 8); 1164 ring_size = (1 << (rb_bufsz + 1)) * 4; 1165 r100_cp_load_microcode(rdev); 1166 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET, 1167 RADEON_CP_PACKET2); 1168 if (r) { 1169 return r; 1170 } 1171 /* Each time the cp read 1024 bytes (16 dword/quadword) update 1172 * the rptr copy in system ram */ 1173 rb_blksz = 9; 1174 /* cp will read 128bytes at a time (4 dwords) */ 1175 max_fetch = 1; 1176 ring->align_mask = 16 - 1; 1177 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ 1178 pre_write_timer = 64; 1179 /* Force CP_RB_WPTR write if written more than one time before the 1180 * delay expire 1181 */ 1182 pre_write_limit = 0; 1183 /* Setup the cp cache like this (cache size is 96 dwords) : 1184 * RING 0 to 15 1185 * INDIRECT1 16 to 79 1186 * INDIRECT2 80 to 95 1187 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1188 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) 1189 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1190 * Idea being that most of the gpu cmd will be through indirect1 buffer 1191 * so it gets the bigger cache. 1192 */ 1193 indirect2_start = 80; 1194 indirect1_start = 16; 1195 /* cp setup */ 1196 WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); 1197 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | 1198 REG_SET(RADEON_RB_BLKSZ, rb_blksz) | 1199 REG_SET(RADEON_MAX_FETCH, max_fetch)); 1200 #ifdef __BIG_ENDIAN 1201 tmp |= RADEON_BUF_SWAP_32BIT; 1202 #endif 1203 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); 1204 1205 /* Set ring address */ 1206 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr); 1207 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr); 1208 /* Force read & write ptr to 0 */ 1209 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); 1210 WREG32(RADEON_CP_RB_RPTR_WR, 0); 1211 ring->wptr = 0; 1212 WREG32(RADEON_CP_RB_WPTR, ring->wptr); 1213 1214 /* set the wb address whether it's enabled or not */ 1215 WREG32(R_00070C_CP_RB_RPTR_ADDR, 1216 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); 1217 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); 1218 1219 if (rdev->wb.enabled) 1220 WREG32(R_000770_SCRATCH_UMSK, 0xff); 1221 else { 1222 tmp |= RADEON_RB_NO_UPDATE; 1223 WREG32(R_000770_SCRATCH_UMSK, 0); 1224 } 1225 1226 WREG32(RADEON_CP_RB_CNTL, tmp); 1227 udelay(10); 1228 /* Set cp mode to bus mastering & enable cp*/ 1229 WREG32(RADEON_CP_CSQ_MODE, 1230 REG_SET(RADEON_INDIRECT2_START, indirect2_start) | 1231 REG_SET(RADEON_INDIRECT1_START, indirect1_start)); 1232 WREG32(RADEON_CP_RB_WPTR_DELAY, 0); 1233 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); 1234 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); 1235 1236 /* at this point everything should be setup correctly to enable master */ 1237 pci_set_master(rdev->pdev); 1238 1239 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1240 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 1241 if (r) { 1242 DRM_ERROR("radeon: cp isn't working (%d).\n", r); 1243 return r; 1244 } 1245 ring->ready = true; 1246 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 1247 1248 if (!ring->rptr_save_reg /* not resuming from suspend */ 1249 && radeon_ring_supports_scratch_reg(rdev, ring)) { 1250 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 1251 if (r) { 1252 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 1253 ring->rptr_save_reg = 0; 1254 } 1255 } 1256 return 0; 1257 } 1258 1259 void r100_cp_fini(struct radeon_device *rdev) 1260 { 1261 if (r100_cp_wait_for_idle(rdev)) { 1262 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); 1263 } 1264 /* Disable ring */ 1265 r100_cp_disable(rdev); 1266 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg); 1267 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1268 DRM_INFO("radeon: cp finalized\n"); 1269 } 1270 1271 void r100_cp_disable(struct radeon_device *rdev) 1272 { 1273 /* Disable ring */ 1274 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1275 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1276 WREG32(RADEON_CP_CSQ_MODE, 0); 1277 WREG32(RADEON_CP_CSQ_CNTL, 0); 1278 WREG32(R_000770_SCRATCH_UMSK, 0); 1279 if (r100_gui_wait_for_idle(rdev)) { 1280 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 1281 } 1282 } 1283 1284 /* 1285 * CS functions 1286 */ 1287 int r100_reloc_pitch_offset(struct radeon_cs_parser *p, 1288 struct radeon_cs_packet *pkt, 1289 unsigned idx, 1290 unsigned reg) 1291 { 1292 int r; 1293 u32 tile_flags = 0; 1294 u32 tmp; 1295 struct radeon_bo_list *reloc; 1296 u32 value; 1297 1298 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1299 if (r) { 1300 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1301 idx, reg); 1302 radeon_cs_dump_packet(p, pkt); 1303 return r; 1304 } 1305 1306 value = radeon_get_ib_value(p, idx); 1307 tmp = value & 0x003fffff; 1308 tmp += (((u32)reloc->gpu_offset) >> 10); 1309 1310 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1311 if (reloc->tiling_flags & RADEON_TILING_MACRO) 1312 tile_flags |= RADEON_DST_TILE_MACRO; 1313 if (reloc->tiling_flags & RADEON_TILING_MICRO) { 1314 if (reg == RADEON_SRC_PITCH_OFFSET) { 1315 DRM_ERROR("Cannot src blit from microtiled surface\n"); 1316 radeon_cs_dump_packet(p, pkt); 1317 return -EINVAL; 1318 } 1319 tile_flags |= RADEON_DST_TILE_MICRO; 1320 } 1321 1322 tmp |= tile_flags; 1323 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp; 1324 } else 1325 p->ib.ptr[idx] = (value & 0xffc00000) | tmp; 1326 return 0; 1327 } 1328 1329 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, 1330 struct radeon_cs_packet *pkt, 1331 int idx) 1332 { 1333 unsigned c, i; 1334 struct radeon_bo_list *reloc; 1335 struct r100_cs_track *track; 1336 int r = 0; 1337 volatile uint32_t *ib; 1338 u32 idx_value; 1339 1340 ib = p->ib.ptr; 1341 track = (struct r100_cs_track *)p->track; 1342 c = radeon_get_ib_value(p, idx++) & 0x1F; 1343 if (c > 16) { 1344 DRM_ERROR("Only 16 vertex buffers are allowed %d\n", 1345 pkt->opcode); 1346 radeon_cs_dump_packet(p, pkt); 1347 return -EINVAL; 1348 } 1349 track->num_arrays = c; 1350 for (i = 0; i < (c - 1); i+=2, idx+=3) { 1351 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1352 if (r) { 1353 DRM_ERROR("No reloc for packet3 %d\n", 1354 pkt->opcode); 1355 radeon_cs_dump_packet(p, pkt); 1356 return r; 1357 } 1358 idx_value = radeon_get_ib_value(p, idx); 1359 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); 1360 1361 track->arrays[i + 0].esize = idx_value >> 8; 1362 track->arrays[i + 0].robj = reloc->robj; 1363 track->arrays[i + 0].esize &= 0x7F; 1364 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1365 if (r) { 1366 DRM_ERROR("No reloc for packet3 %d\n", 1367 pkt->opcode); 1368 radeon_cs_dump_packet(p, pkt); 1369 return r; 1370 } 1371 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset); 1372 track->arrays[i + 1].robj = reloc->robj; 1373 track->arrays[i + 1].esize = idx_value >> 24; 1374 track->arrays[i + 1].esize &= 0x7F; 1375 } 1376 if (c & 1) { 1377 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1378 if (r) { 1379 DRM_ERROR("No reloc for packet3 %d\n", 1380 pkt->opcode); 1381 radeon_cs_dump_packet(p, pkt); 1382 return r; 1383 } 1384 idx_value = radeon_get_ib_value(p, idx); 1385 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); 1386 track->arrays[i + 0].robj = reloc->robj; 1387 track->arrays[i + 0].esize = idx_value >> 8; 1388 track->arrays[i + 0].esize &= 0x7F; 1389 } 1390 return r; 1391 } 1392 1393 int r100_cs_parse_packet0(struct radeon_cs_parser *p, 1394 struct radeon_cs_packet *pkt, 1395 const unsigned *auth, unsigned n, 1396 radeon_packet0_check_t check) 1397 { 1398 unsigned reg; 1399 unsigned i, j, m; 1400 unsigned idx; 1401 int r; 1402 1403 idx = pkt->idx + 1; 1404 reg = pkt->reg; 1405 /* Check that register fall into register range 1406 * determined by the number of entry (n) in the 1407 * safe register bitmap. 1408 */ 1409 if (pkt->one_reg_wr) { 1410 if ((reg >> 7) > n) { 1411 return -EINVAL; 1412 } 1413 } else { 1414 if (((reg + (pkt->count << 2)) >> 7) > n) { 1415 return -EINVAL; 1416 } 1417 } 1418 for (i = 0; i <= pkt->count; i++, idx++) { 1419 j = (reg >> 7); 1420 m = 1 << ((reg >> 2) & 31); 1421 if (auth[j] & m) { 1422 r = check(p, pkt, idx, reg); 1423 if (r) { 1424 return r; 1425 } 1426 } 1427 if (pkt->one_reg_wr) { 1428 if (!(auth[j] & m)) { 1429 break; 1430 } 1431 } else { 1432 reg += 4; 1433 } 1434 } 1435 return 0; 1436 } 1437 1438 /** 1439 * r100_cs_packet_parse_vline() - parse userspace VLINE packet 1440 * @p: parser structure holding parsing context. 1441 * 1442 * Userspace sends a special sequence for VLINE waits. 1443 * PACKET0 - VLINE_START_END + value 1444 * PACKET0 - WAIT_UNTIL +_value 1445 * RELOC (P3) - crtc_id in reloc. 1446 * 1447 * This function parses this and relocates the VLINE START END 1448 * and WAIT UNTIL packets to the correct crtc. 1449 * It also detects a switched off crtc and nulls out the 1450 * wait in that case. 1451 */ 1452 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) 1453 { 1454 struct drm_crtc *crtc; 1455 struct radeon_crtc *radeon_crtc; 1456 struct radeon_cs_packet p3reloc, waitreloc; 1457 int crtc_id; 1458 int r; 1459 uint32_t header, h_idx, reg; 1460 volatile uint32_t *ib; 1461 1462 ib = p->ib.ptr; 1463 1464 /* parse the wait until */ 1465 r = radeon_cs_packet_parse(p, &waitreloc, p->idx); 1466 if (r) 1467 return r; 1468 1469 /* check its a wait until and only 1 count */ 1470 if (waitreloc.reg != RADEON_WAIT_UNTIL || 1471 waitreloc.count != 0) { 1472 DRM_ERROR("vline wait had illegal wait until segment\n"); 1473 return -EINVAL; 1474 } 1475 1476 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { 1477 DRM_ERROR("vline wait had illegal wait until\n"); 1478 return -EINVAL; 1479 } 1480 1481 /* jump over the NOP */ 1482 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); 1483 if (r) 1484 return r; 1485 1486 h_idx = p->idx - 2; 1487 p->idx += waitreloc.count + 2; 1488 p->idx += p3reloc.count + 2; 1489 1490 header = radeon_get_ib_value(p, h_idx); 1491 crtc_id = radeon_get_ib_value(p, h_idx + 5); 1492 reg = R100_CP_PACKET0_GET_REG(header); 1493 crtc = drm_crtc_find(p->rdev->ddev, p->filp, crtc_id); 1494 if (!crtc) { 1495 DRM_ERROR("cannot find crtc %d\n", crtc_id); 1496 return -ENOENT; 1497 } 1498 radeon_crtc = to_radeon_crtc(crtc); 1499 crtc_id = radeon_crtc->crtc_id; 1500 1501 if (!crtc->enabled) { 1502 /* if the CRTC isn't enabled - we need to nop out the wait until */ 1503 ib[h_idx + 2] = PACKET2(0); 1504 ib[h_idx + 3] = PACKET2(0); 1505 } else if (crtc_id == 1) { 1506 switch (reg) { 1507 case AVIVO_D1MODE_VLINE_START_END: 1508 header &= ~R300_CP_PACKET0_REG_MASK; 1509 header |= AVIVO_D2MODE_VLINE_START_END >> 2; 1510 break; 1511 case RADEON_CRTC_GUI_TRIG_VLINE: 1512 header &= ~R300_CP_PACKET0_REG_MASK; 1513 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; 1514 break; 1515 default: 1516 DRM_ERROR("unknown crtc reloc\n"); 1517 return -EINVAL; 1518 } 1519 ib[h_idx] = header; 1520 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; 1521 } 1522 1523 return 0; 1524 } 1525 1526 static int r100_get_vtx_size(uint32_t vtx_fmt) 1527 { 1528 int vtx_size; 1529 vtx_size = 2; 1530 /* ordered according to bits in spec */ 1531 if (vtx_fmt & RADEON_SE_VTX_FMT_W0) 1532 vtx_size++; 1533 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) 1534 vtx_size += 3; 1535 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) 1536 vtx_size++; 1537 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) 1538 vtx_size++; 1539 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) 1540 vtx_size += 3; 1541 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) 1542 vtx_size++; 1543 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) 1544 vtx_size++; 1545 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) 1546 vtx_size += 2; 1547 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) 1548 vtx_size += 2; 1549 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) 1550 vtx_size++; 1551 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) 1552 vtx_size += 2; 1553 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) 1554 vtx_size++; 1555 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) 1556 vtx_size += 2; 1557 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) 1558 vtx_size++; 1559 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) 1560 vtx_size++; 1561 /* blend weight */ 1562 if (vtx_fmt & (0x7 << 15)) 1563 vtx_size += (vtx_fmt >> 15) & 0x7; 1564 if (vtx_fmt & RADEON_SE_VTX_FMT_N0) 1565 vtx_size += 3; 1566 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) 1567 vtx_size += 2; 1568 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) 1569 vtx_size++; 1570 if (vtx_fmt & RADEON_SE_VTX_FMT_W1) 1571 vtx_size++; 1572 if (vtx_fmt & RADEON_SE_VTX_FMT_N1) 1573 vtx_size++; 1574 if (vtx_fmt & RADEON_SE_VTX_FMT_Z) 1575 vtx_size++; 1576 return vtx_size; 1577 } 1578 1579 static int r100_packet0_check(struct radeon_cs_parser *p, 1580 struct radeon_cs_packet *pkt, 1581 unsigned idx, unsigned reg) 1582 { 1583 struct radeon_bo_list *reloc; 1584 struct r100_cs_track *track; 1585 volatile uint32_t *ib; 1586 uint32_t tmp; 1587 int r; 1588 int i, face; 1589 u32 tile_flags = 0; 1590 u32 idx_value; 1591 1592 ib = p->ib.ptr; 1593 track = (struct r100_cs_track *)p->track; 1594 1595 idx_value = radeon_get_ib_value(p, idx); 1596 1597 switch (reg) { 1598 case RADEON_CRTC_GUI_TRIG_VLINE: 1599 r = r100_cs_packet_parse_vline(p); 1600 if (r) { 1601 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1602 idx, reg); 1603 radeon_cs_dump_packet(p, pkt); 1604 return r; 1605 } 1606 break; 1607 /* FIXME: only allow PACKET3 blit? easier to check for out of 1608 * range access */ 1609 case RADEON_DST_PITCH_OFFSET: 1610 case RADEON_SRC_PITCH_OFFSET: 1611 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 1612 if (r) 1613 return r; 1614 break; 1615 case RADEON_RB3D_DEPTHOFFSET: 1616 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1617 if (r) { 1618 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1619 idx, reg); 1620 radeon_cs_dump_packet(p, pkt); 1621 return r; 1622 } 1623 track->zb.robj = reloc->robj; 1624 track->zb.offset = idx_value; 1625 track->zb_dirty = true; 1626 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1627 break; 1628 case RADEON_RB3D_COLOROFFSET: 1629 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1630 if (r) { 1631 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1632 idx, reg); 1633 radeon_cs_dump_packet(p, pkt); 1634 return r; 1635 } 1636 track->cb[0].robj = reloc->robj; 1637 track->cb[0].offset = idx_value; 1638 track->cb_dirty = true; 1639 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1640 break; 1641 case RADEON_PP_TXOFFSET_0: 1642 case RADEON_PP_TXOFFSET_1: 1643 case RADEON_PP_TXOFFSET_2: 1644 i = (reg - RADEON_PP_TXOFFSET_0) / 24; 1645 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1646 if (r) { 1647 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1648 idx, reg); 1649 radeon_cs_dump_packet(p, pkt); 1650 return r; 1651 } 1652 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1653 if (reloc->tiling_flags & RADEON_TILING_MACRO) 1654 tile_flags |= RADEON_TXO_MACRO_TILE; 1655 if (reloc->tiling_flags & RADEON_TILING_MICRO) 1656 tile_flags |= RADEON_TXO_MICRO_TILE_X2; 1657 1658 tmp = idx_value & ~(0x7 << 2); 1659 tmp |= tile_flags; 1660 ib[idx] = tmp + ((u32)reloc->gpu_offset); 1661 } else 1662 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1663 track->textures[i].robj = reloc->robj; 1664 track->tex_dirty = true; 1665 break; 1666 case RADEON_PP_CUBIC_OFFSET_T0_0: 1667 case RADEON_PP_CUBIC_OFFSET_T0_1: 1668 case RADEON_PP_CUBIC_OFFSET_T0_2: 1669 case RADEON_PP_CUBIC_OFFSET_T0_3: 1670 case RADEON_PP_CUBIC_OFFSET_T0_4: 1671 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; 1672 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1673 if (r) { 1674 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1675 idx, reg); 1676 radeon_cs_dump_packet(p, pkt); 1677 return r; 1678 } 1679 track->textures[0].cube_info[i].offset = idx_value; 1680 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1681 track->textures[0].cube_info[i].robj = reloc->robj; 1682 track->tex_dirty = true; 1683 break; 1684 case RADEON_PP_CUBIC_OFFSET_T1_0: 1685 case RADEON_PP_CUBIC_OFFSET_T1_1: 1686 case RADEON_PP_CUBIC_OFFSET_T1_2: 1687 case RADEON_PP_CUBIC_OFFSET_T1_3: 1688 case RADEON_PP_CUBIC_OFFSET_T1_4: 1689 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; 1690 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1691 if (r) { 1692 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1693 idx, reg); 1694 radeon_cs_dump_packet(p, pkt); 1695 return r; 1696 } 1697 track->textures[1].cube_info[i].offset = idx_value; 1698 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1699 track->textures[1].cube_info[i].robj = reloc->robj; 1700 track->tex_dirty = true; 1701 break; 1702 case RADEON_PP_CUBIC_OFFSET_T2_0: 1703 case RADEON_PP_CUBIC_OFFSET_T2_1: 1704 case RADEON_PP_CUBIC_OFFSET_T2_2: 1705 case RADEON_PP_CUBIC_OFFSET_T2_3: 1706 case RADEON_PP_CUBIC_OFFSET_T2_4: 1707 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; 1708 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1709 if (r) { 1710 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1711 idx, reg); 1712 radeon_cs_dump_packet(p, pkt); 1713 return r; 1714 } 1715 track->textures[2].cube_info[i].offset = idx_value; 1716 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1717 track->textures[2].cube_info[i].robj = reloc->robj; 1718 track->tex_dirty = true; 1719 break; 1720 case RADEON_RE_WIDTH_HEIGHT: 1721 track->maxy = ((idx_value >> 16) & 0x7FF); 1722 track->cb_dirty = true; 1723 track->zb_dirty = true; 1724 break; 1725 case RADEON_RB3D_COLORPITCH: 1726 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1727 if (r) { 1728 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1729 idx, reg); 1730 radeon_cs_dump_packet(p, pkt); 1731 return r; 1732 } 1733 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1734 if (reloc->tiling_flags & RADEON_TILING_MACRO) 1735 tile_flags |= RADEON_COLOR_TILE_ENABLE; 1736 if (reloc->tiling_flags & RADEON_TILING_MICRO) 1737 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; 1738 1739 tmp = idx_value & ~(0x7 << 16); 1740 tmp |= tile_flags; 1741 ib[idx] = tmp; 1742 } else 1743 ib[idx] = idx_value; 1744 1745 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; 1746 track->cb_dirty = true; 1747 break; 1748 case RADEON_RB3D_DEPTHPITCH: 1749 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; 1750 track->zb_dirty = true; 1751 break; 1752 case RADEON_RB3D_CNTL: 1753 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { 1754 case 7: 1755 case 8: 1756 case 9: 1757 case 11: 1758 case 12: 1759 track->cb[0].cpp = 1; 1760 break; 1761 case 3: 1762 case 4: 1763 case 15: 1764 track->cb[0].cpp = 2; 1765 break; 1766 case 6: 1767 track->cb[0].cpp = 4; 1768 break; 1769 default: 1770 DRM_ERROR("Invalid color buffer format (%d) !\n", 1771 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); 1772 return -EINVAL; 1773 } 1774 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); 1775 track->cb_dirty = true; 1776 track->zb_dirty = true; 1777 break; 1778 case RADEON_RB3D_ZSTENCILCNTL: 1779 switch (idx_value & 0xf) { 1780 case 0: 1781 track->zb.cpp = 2; 1782 break; 1783 case 2: 1784 case 3: 1785 case 4: 1786 case 5: 1787 case 9: 1788 case 11: 1789 track->zb.cpp = 4; 1790 break; 1791 default: 1792 break; 1793 } 1794 track->zb_dirty = true; 1795 break; 1796 case RADEON_RB3D_ZPASS_ADDR: 1797 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1798 if (r) { 1799 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1800 idx, reg); 1801 radeon_cs_dump_packet(p, pkt); 1802 return r; 1803 } 1804 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1805 break; 1806 case RADEON_PP_CNTL: 1807 { 1808 uint32_t temp = idx_value >> 4; 1809 for (i = 0; i < track->num_texture; i++) 1810 track->textures[i].enabled = !!(temp & (1 << i)); 1811 track->tex_dirty = true; 1812 } 1813 break; 1814 case RADEON_SE_VF_CNTL: 1815 track->vap_vf_cntl = idx_value; 1816 break; 1817 case RADEON_SE_VTX_FMT: 1818 track->vtx_size = r100_get_vtx_size(idx_value); 1819 break; 1820 case RADEON_PP_TEX_SIZE_0: 1821 case RADEON_PP_TEX_SIZE_1: 1822 case RADEON_PP_TEX_SIZE_2: 1823 i = (reg - RADEON_PP_TEX_SIZE_0) / 8; 1824 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; 1825 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; 1826 track->tex_dirty = true; 1827 break; 1828 case RADEON_PP_TEX_PITCH_0: 1829 case RADEON_PP_TEX_PITCH_1: 1830 case RADEON_PP_TEX_PITCH_2: 1831 i = (reg - RADEON_PP_TEX_PITCH_0) / 8; 1832 track->textures[i].pitch = idx_value + 32; 1833 track->tex_dirty = true; 1834 break; 1835 case RADEON_PP_TXFILTER_0: 1836 case RADEON_PP_TXFILTER_1: 1837 case RADEON_PP_TXFILTER_2: 1838 i = (reg - RADEON_PP_TXFILTER_0) / 24; 1839 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) 1840 >> RADEON_MAX_MIP_LEVEL_SHIFT); 1841 tmp = (idx_value >> 23) & 0x7; 1842 if (tmp == 2 || tmp == 6) 1843 track->textures[i].roundup_w = false; 1844 tmp = (idx_value >> 27) & 0x7; 1845 if (tmp == 2 || tmp == 6) 1846 track->textures[i].roundup_h = false; 1847 track->tex_dirty = true; 1848 break; 1849 case RADEON_PP_TXFORMAT_0: 1850 case RADEON_PP_TXFORMAT_1: 1851 case RADEON_PP_TXFORMAT_2: 1852 i = (reg - RADEON_PP_TXFORMAT_0) / 24; 1853 if (idx_value & RADEON_TXFORMAT_NON_POWER2) { 1854 track->textures[i].use_pitch = true; 1855 } else { 1856 track->textures[i].use_pitch = false; 1857 track->textures[i].width = 1 << ((idx_value & RADEON_TXFORMAT_WIDTH_MASK) >> RADEON_TXFORMAT_WIDTH_SHIFT); 1858 track->textures[i].height = 1 << ((idx_value & RADEON_TXFORMAT_HEIGHT_MASK) >> RADEON_TXFORMAT_HEIGHT_SHIFT); 1859 } 1860 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) 1861 track->textures[i].tex_coord_type = 2; 1862 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { 1863 case RADEON_TXFORMAT_I8: 1864 case RADEON_TXFORMAT_RGB332: 1865 case RADEON_TXFORMAT_Y8: 1866 track->textures[i].cpp = 1; 1867 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1868 break; 1869 case RADEON_TXFORMAT_AI88: 1870 case RADEON_TXFORMAT_ARGB1555: 1871 case RADEON_TXFORMAT_RGB565: 1872 case RADEON_TXFORMAT_ARGB4444: 1873 case RADEON_TXFORMAT_VYUY422: 1874 case RADEON_TXFORMAT_YVYU422: 1875 case RADEON_TXFORMAT_SHADOW16: 1876 case RADEON_TXFORMAT_LDUDV655: 1877 case RADEON_TXFORMAT_DUDV88: 1878 track->textures[i].cpp = 2; 1879 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1880 break; 1881 case RADEON_TXFORMAT_ARGB8888: 1882 case RADEON_TXFORMAT_RGBA8888: 1883 case RADEON_TXFORMAT_SHADOW32: 1884 case RADEON_TXFORMAT_LDUDUV8888: 1885 track->textures[i].cpp = 4; 1886 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1887 break; 1888 case RADEON_TXFORMAT_DXT1: 1889 track->textures[i].cpp = 1; 1890 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 1891 break; 1892 case RADEON_TXFORMAT_DXT23: 1893 case RADEON_TXFORMAT_DXT45: 1894 track->textures[i].cpp = 1; 1895 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 1896 break; 1897 } 1898 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); 1899 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); 1900 track->tex_dirty = true; 1901 break; 1902 case RADEON_PP_CUBIC_FACES_0: 1903 case RADEON_PP_CUBIC_FACES_1: 1904 case RADEON_PP_CUBIC_FACES_2: 1905 tmp = idx_value; 1906 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; 1907 for (face = 0; face < 4; face++) { 1908 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); 1909 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); 1910 } 1911 track->tex_dirty = true; 1912 break; 1913 default: 1914 pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx); 1915 return -EINVAL; 1916 } 1917 return 0; 1918 } 1919 1920 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 1921 struct radeon_cs_packet *pkt, 1922 struct radeon_bo *robj) 1923 { 1924 unsigned idx; 1925 u32 value; 1926 idx = pkt->idx + 1; 1927 value = radeon_get_ib_value(p, idx + 2); 1928 if ((value + 1) > radeon_bo_size(robj)) { 1929 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " 1930 "(need %u have %lu) !\n", 1931 value + 1, 1932 radeon_bo_size(robj)); 1933 return -EINVAL; 1934 } 1935 return 0; 1936 } 1937 1938 static int r100_packet3_check(struct radeon_cs_parser *p, 1939 struct radeon_cs_packet *pkt) 1940 { 1941 struct radeon_bo_list *reloc; 1942 struct r100_cs_track *track; 1943 unsigned idx; 1944 volatile uint32_t *ib; 1945 int r; 1946 1947 ib = p->ib.ptr; 1948 idx = pkt->idx + 1; 1949 track = (struct r100_cs_track *)p->track; 1950 switch (pkt->opcode) { 1951 case PACKET3_3D_LOAD_VBPNTR: 1952 r = r100_packet3_load_vbpntr(p, pkt, idx); 1953 if (r) 1954 return r; 1955 break; 1956 case PACKET3_INDX_BUFFER: 1957 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1958 if (r) { 1959 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1960 radeon_cs_dump_packet(p, pkt); 1961 return r; 1962 } 1963 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset); 1964 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1965 if (r) { 1966 return r; 1967 } 1968 break; 1969 case 0x23: 1970 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ 1971 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1972 if (r) { 1973 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1974 radeon_cs_dump_packet(p, pkt); 1975 return r; 1976 } 1977 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset); 1978 track->num_arrays = 1; 1979 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); 1980 1981 track->arrays[0].robj = reloc->robj; 1982 track->arrays[0].esize = track->vtx_size; 1983 1984 track->max_indx = radeon_get_ib_value(p, idx+1); 1985 1986 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); 1987 track->immd_dwords = pkt->count - 1; 1988 r = r100_cs_track_check(p->rdev, track); 1989 if (r) 1990 return r; 1991 break; 1992 case PACKET3_3D_DRAW_IMMD: 1993 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1994 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1995 return -EINVAL; 1996 } 1997 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); 1998 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1999 track->immd_dwords = pkt->count - 1; 2000 r = r100_cs_track_check(p->rdev, track); 2001 if (r) 2002 return r; 2003 break; 2004 /* triggers drawing using in-packet vertex data */ 2005 case PACKET3_3D_DRAW_IMMD_2: 2006 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 2007 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 2008 return -EINVAL; 2009 } 2010 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 2011 track->immd_dwords = pkt->count; 2012 r = r100_cs_track_check(p->rdev, track); 2013 if (r) 2014 return r; 2015 break; 2016 /* triggers drawing using in-packet vertex data */ 2017 case PACKET3_3D_DRAW_VBUF_2: 2018 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 2019 r = r100_cs_track_check(p->rdev, track); 2020 if (r) 2021 return r; 2022 break; 2023 /* triggers drawing of vertex buffers setup elsewhere */ 2024 case PACKET3_3D_DRAW_INDX_2: 2025 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 2026 r = r100_cs_track_check(p->rdev, track); 2027 if (r) 2028 return r; 2029 break; 2030 /* triggers drawing using indices to vertex buffer */ 2031 case PACKET3_3D_DRAW_VBUF: 2032 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 2033 r = r100_cs_track_check(p->rdev, track); 2034 if (r) 2035 return r; 2036 break; 2037 /* triggers drawing of vertex buffers setup elsewhere */ 2038 case PACKET3_3D_DRAW_INDX: 2039 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 2040 r = r100_cs_track_check(p->rdev, track); 2041 if (r) 2042 return r; 2043 break; 2044 /* triggers drawing using indices to vertex buffer */ 2045 case PACKET3_3D_CLEAR_HIZ: 2046 case PACKET3_3D_CLEAR_ZMASK: 2047 if (p->rdev->hyperz_filp != p->filp) 2048 return -EINVAL; 2049 break; 2050 case PACKET3_NOP: 2051 break; 2052 default: 2053 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 2054 return -EINVAL; 2055 } 2056 return 0; 2057 } 2058 2059 int r100_cs_parse(struct radeon_cs_parser *p) 2060 { 2061 struct radeon_cs_packet pkt; 2062 struct r100_cs_track *track; 2063 int r; 2064 2065 track = kzalloc(sizeof(*track), GFP_KERNEL); 2066 if (!track) 2067 return -ENOMEM; 2068 r100_cs_track_clear(p->rdev, track); 2069 p->track = track; 2070 do { 2071 r = radeon_cs_packet_parse(p, &pkt, p->idx); 2072 if (r) { 2073 return r; 2074 } 2075 p->idx += pkt.count + 2; 2076 switch (pkt.type) { 2077 case RADEON_PACKET_TYPE0: 2078 if (p->rdev->family >= CHIP_R200) 2079 r = r100_cs_parse_packet0(p, &pkt, 2080 p->rdev->config.r100.reg_safe_bm, 2081 p->rdev->config.r100.reg_safe_bm_size, 2082 &r200_packet0_check); 2083 else 2084 r = r100_cs_parse_packet0(p, &pkt, 2085 p->rdev->config.r100.reg_safe_bm, 2086 p->rdev->config.r100.reg_safe_bm_size, 2087 &r100_packet0_check); 2088 break; 2089 case RADEON_PACKET_TYPE2: 2090 break; 2091 case RADEON_PACKET_TYPE3: 2092 r = r100_packet3_check(p, &pkt); 2093 break; 2094 default: 2095 DRM_ERROR("Unknown packet type %d !\n", 2096 pkt.type); 2097 return -EINVAL; 2098 } 2099 if (r) 2100 return r; 2101 } while (p->idx < p->chunk_ib->length_dw); 2102 return 0; 2103 } 2104 2105 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t) 2106 { 2107 DRM_ERROR("pitch %d\n", t->pitch); 2108 DRM_ERROR("use_pitch %d\n", t->use_pitch); 2109 DRM_ERROR("width %d\n", t->width); 2110 DRM_ERROR("width_11 %d\n", t->width_11); 2111 DRM_ERROR("height %d\n", t->height); 2112 DRM_ERROR("height_11 %d\n", t->height_11); 2113 DRM_ERROR("num levels %d\n", t->num_levels); 2114 DRM_ERROR("depth %d\n", t->txdepth); 2115 DRM_ERROR("bpp %d\n", t->cpp); 2116 DRM_ERROR("coordinate type %d\n", t->tex_coord_type); 2117 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); 2118 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); 2119 DRM_ERROR("compress format %d\n", t->compress_format); 2120 } 2121 2122 static int r100_track_compress_size(int compress_format, int w, int h) 2123 { 2124 int block_width, block_height, block_bytes; 2125 int wblocks, hblocks; 2126 int min_wblocks; 2127 int sz; 2128 2129 block_width = 4; 2130 block_height = 4; 2131 2132 switch (compress_format) { 2133 case R100_TRACK_COMP_DXT1: 2134 block_bytes = 8; 2135 min_wblocks = 4; 2136 break; 2137 default: 2138 case R100_TRACK_COMP_DXT35: 2139 block_bytes = 16; 2140 min_wblocks = 2; 2141 break; 2142 } 2143 2144 hblocks = (h + block_height - 1) / block_height; 2145 wblocks = (w + block_width - 1) / block_width; 2146 if (wblocks < min_wblocks) 2147 wblocks = min_wblocks; 2148 sz = wblocks * hblocks * block_bytes; 2149 return sz; 2150 } 2151 2152 static int r100_cs_track_cube(struct radeon_device *rdev, 2153 struct r100_cs_track *track, unsigned idx) 2154 { 2155 unsigned face, w, h; 2156 struct radeon_bo *cube_robj; 2157 unsigned long size; 2158 unsigned compress_format = track->textures[idx].compress_format; 2159 2160 for (face = 0; face < 5; face++) { 2161 cube_robj = track->textures[idx].cube_info[face].robj; 2162 w = track->textures[idx].cube_info[face].width; 2163 h = track->textures[idx].cube_info[face].height; 2164 2165 if (compress_format) { 2166 size = r100_track_compress_size(compress_format, w, h); 2167 } else 2168 size = w * h; 2169 size *= track->textures[idx].cpp; 2170 2171 size += track->textures[idx].cube_info[face].offset; 2172 2173 if (size > radeon_bo_size(cube_robj)) { 2174 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", 2175 size, radeon_bo_size(cube_robj)); 2176 r100_cs_track_texture_print(&track->textures[idx]); 2177 return -1; 2178 } 2179 } 2180 return 0; 2181 } 2182 2183 static int r100_cs_track_texture_check(struct radeon_device *rdev, 2184 struct r100_cs_track *track) 2185 { 2186 struct radeon_bo *robj; 2187 unsigned long size; 2188 unsigned u, i, w, h, d; 2189 int ret; 2190 2191 for (u = 0; u < track->num_texture; u++) { 2192 if (!track->textures[u].enabled) 2193 continue; 2194 if (track->textures[u].lookup_disable) 2195 continue; 2196 robj = track->textures[u].robj; 2197 if (robj == NULL) { 2198 DRM_ERROR("No texture bound to unit %u\n", u); 2199 return -EINVAL; 2200 } 2201 size = 0; 2202 for (i = 0; i <= track->textures[u].num_levels; i++) { 2203 if (track->textures[u].use_pitch) { 2204 if (rdev->family < CHIP_R300) 2205 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); 2206 else 2207 w = track->textures[u].pitch / (1 << i); 2208 } else { 2209 w = track->textures[u].width; 2210 if (rdev->family >= CHIP_RV515) 2211 w |= track->textures[u].width_11; 2212 w = w / (1 << i); 2213 if (track->textures[u].roundup_w) 2214 w = roundup_pow_of_two(w); 2215 } 2216 h = track->textures[u].height; 2217 if (rdev->family >= CHIP_RV515) 2218 h |= track->textures[u].height_11; 2219 h = h / (1 << i); 2220 if (track->textures[u].roundup_h) 2221 h = roundup_pow_of_two(h); 2222 if (track->textures[u].tex_coord_type == 1) { 2223 d = (1 << track->textures[u].txdepth) / (1 << i); 2224 if (!d) 2225 d = 1; 2226 } else { 2227 d = 1; 2228 } 2229 if (track->textures[u].compress_format) { 2230 2231 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d; 2232 /* compressed textures are block based */ 2233 } else 2234 size += w * h * d; 2235 } 2236 size *= track->textures[u].cpp; 2237 2238 switch (track->textures[u].tex_coord_type) { 2239 case 0: 2240 case 1: 2241 break; 2242 case 2: 2243 if (track->separate_cube) { 2244 ret = r100_cs_track_cube(rdev, track, u); 2245 if (ret) 2246 return ret; 2247 } else 2248 size *= 6; 2249 break; 2250 default: 2251 DRM_ERROR("Invalid texture coordinate type %u for unit " 2252 "%u\n", track->textures[u].tex_coord_type, u); 2253 return -EINVAL; 2254 } 2255 if (size > radeon_bo_size(robj)) { 2256 DRM_ERROR("Texture of unit %u needs %lu bytes but is " 2257 "%lu\n", u, size, radeon_bo_size(robj)); 2258 r100_cs_track_texture_print(&track->textures[u]); 2259 return -EINVAL; 2260 } 2261 } 2262 return 0; 2263 } 2264 2265 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) 2266 { 2267 unsigned i; 2268 unsigned long size; 2269 unsigned prim_walk; 2270 unsigned nverts; 2271 unsigned num_cb = track->cb_dirty ? track->num_cb : 0; 2272 2273 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask && 2274 !track->blend_read_enable) 2275 num_cb = 0; 2276 2277 for (i = 0; i < num_cb; i++) { 2278 if (track->cb[i].robj == NULL) { 2279 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); 2280 return -EINVAL; 2281 } 2282 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; 2283 size += track->cb[i].offset; 2284 if (size > radeon_bo_size(track->cb[i].robj)) { 2285 DRM_ERROR("[drm] Buffer too small for color buffer %d " 2286 "(need %lu have %lu) !\n", i, size, 2287 radeon_bo_size(track->cb[i].robj)); 2288 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", 2289 i, track->cb[i].pitch, track->cb[i].cpp, 2290 track->cb[i].offset, track->maxy); 2291 return -EINVAL; 2292 } 2293 } 2294 track->cb_dirty = false; 2295 2296 if (track->zb_dirty && track->z_enabled) { 2297 if (track->zb.robj == NULL) { 2298 DRM_ERROR("[drm] No buffer for z buffer !\n"); 2299 return -EINVAL; 2300 } 2301 size = track->zb.pitch * track->zb.cpp * track->maxy; 2302 size += track->zb.offset; 2303 if (size > radeon_bo_size(track->zb.robj)) { 2304 DRM_ERROR("[drm] Buffer too small for z buffer " 2305 "(need %lu have %lu) !\n", size, 2306 radeon_bo_size(track->zb.robj)); 2307 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", 2308 track->zb.pitch, track->zb.cpp, 2309 track->zb.offset, track->maxy); 2310 return -EINVAL; 2311 } 2312 } 2313 track->zb_dirty = false; 2314 2315 if (track->aa_dirty && track->aaresolve) { 2316 if (track->aa.robj == NULL) { 2317 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i); 2318 return -EINVAL; 2319 } 2320 /* I believe the format comes from colorbuffer0. */ 2321 size = track->aa.pitch * track->cb[0].cpp * track->maxy; 2322 size += track->aa.offset; 2323 if (size > radeon_bo_size(track->aa.robj)) { 2324 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d " 2325 "(need %lu have %lu) !\n", i, size, 2326 radeon_bo_size(track->aa.robj)); 2327 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n", 2328 i, track->aa.pitch, track->cb[0].cpp, 2329 track->aa.offset, track->maxy); 2330 return -EINVAL; 2331 } 2332 } 2333 track->aa_dirty = false; 2334 2335 prim_walk = (track->vap_vf_cntl >> 4) & 0x3; 2336 if (track->vap_vf_cntl & (1 << 14)) { 2337 nverts = track->vap_alt_nverts; 2338 } else { 2339 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; 2340 } 2341 switch (prim_walk) { 2342 case 1: 2343 for (i = 0; i < track->num_arrays; i++) { 2344 size = track->arrays[i].esize * track->max_indx * 4UL; 2345 if (track->arrays[i].robj == NULL) { 2346 DRM_ERROR("(PW %u) Vertex array %u no buffer " 2347 "bound\n", prim_walk, i); 2348 return -EINVAL; 2349 } 2350 if (size > radeon_bo_size(track->arrays[i].robj)) { 2351 dev_err(rdev->dev, "(PW %u) Vertex array %u " 2352 "need %lu dwords have %lu dwords\n", 2353 prim_walk, i, size >> 2, 2354 radeon_bo_size(track->arrays[i].robj) 2355 >> 2); 2356 DRM_ERROR("Max indices %u\n", track->max_indx); 2357 return -EINVAL; 2358 } 2359 } 2360 break; 2361 case 2: 2362 for (i = 0; i < track->num_arrays; i++) { 2363 size = track->arrays[i].esize * (nverts - 1) * 4UL; 2364 if (track->arrays[i].robj == NULL) { 2365 DRM_ERROR("(PW %u) Vertex array %u no buffer " 2366 "bound\n", prim_walk, i); 2367 return -EINVAL; 2368 } 2369 if (size > radeon_bo_size(track->arrays[i].robj)) { 2370 dev_err(rdev->dev, "(PW %u) Vertex array %u " 2371 "need %lu dwords have %lu dwords\n", 2372 prim_walk, i, size >> 2, 2373 radeon_bo_size(track->arrays[i].robj) 2374 >> 2); 2375 return -EINVAL; 2376 } 2377 } 2378 break; 2379 case 3: 2380 size = track->vtx_size * nverts; 2381 if (size != track->immd_dwords) { 2382 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", 2383 track->immd_dwords, size); 2384 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", 2385 nverts, track->vtx_size); 2386 return -EINVAL; 2387 } 2388 break; 2389 default: 2390 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", 2391 prim_walk); 2392 return -EINVAL; 2393 } 2394 2395 if (track->tex_dirty) { 2396 track->tex_dirty = false; 2397 return r100_cs_track_texture_check(rdev, track); 2398 } 2399 return 0; 2400 } 2401 2402 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) 2403 { 2404 unsigned i, face; 2405 2406 track->cb_dirty = true; 2407 track->zb_dirty = true; 2408 track->tex_dirty = true; 2409 track->aa_dirty = true; 2410 2411 if (rdev->family < CHIP_R300) { 2412 track->num_cb = 1; 2413 if (rdev->family <= CHIP_RS200) 2414 track->num_texture = 3; 2415 else 2416 track->num_texture = 6; 2417 track->maxy = 2048; 2418 track->separate_cube = true; 2419 } else { 2420 track->num_cb = 4; 2421 track->num_texture = 16; 2422 track->maxy = 4096; 2423 track->separate_cube = false; 2424 track->aaresolve = false; 2425 track->aa.robj = NULL; 2426 } 2427 2428 for (i = 0; i < track->num_cb; i++) { 2429 track->cb[i].robj = NULL; 2430 track->cb[i].pitch = 8192; 2431 track->cb[i].cpp = 16; 2432 track->cb[i].offset = 0; 2433 } 2434 track->z_enabled = true; 2435 track->zb.robj = NULL; 2436 track->zb.pitch = 8192; 2437 track->zb.cpp = 4; 2438 track->zb.offset = 0; 2439 track->vtx_size = 0x7F; 2440 track->immd_dwords = 0xFFFFFFFFUL; 2441 track->num_arrays = 11; 2442 track->max_indx = 0x00FFFFFFUL; 2443 for (i = 0; i < track->num_arrays; i++) { 2444 track->arrays[i].robj = NULL; 2445 track->arrays[i].esize = 0x7F; 2446 } 2447 for (i = 0; i < track->num_texture; i++) { 2448 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 2449 track->textures[i].pitch = 16536; 2450 track->textures[i].width = 16536; 2451 track->textures[i].height = 16536; 2452 track->textures[i].width_11 = 1 << 11; 2453 track->textures[i].height_11 = 1 << 11; 2454 track->textures[i].num_levels = 12; 2455 if (rdev->family <= CHIP_RS200) { 2456 track->textures[i].tex_coord_type = 0; 2457 track->textures[i].txdepth = 0; 2458 } else { 2459 track->textures[i].txdepth = 16; 2460 track->textures[i].tex_coord_type = 1; 2461 } 2462 track->textures[i].cpp = 64; 2463 track->textures[i].robj = NULL; 2464 /* CS IB emission code makes sure texture unit are disabled */ 2465 track->textures[i].enabled = false; 2466 track->textures[i].lookup_disable = false; 2467 track->textures[i].roundup_w = true; 2468 track->textures[i].roundup_h = true; 2469 if (track->separate_cube) 2470 for (face = 0; face < 5; face++) { 2471 track->textures[i].cube_info[face].robj = NULL; 2472 track->textures[i].cube_info[face].width = 16536; 2473 track->textures[i].cube_info[face].height = 16536; 2474 track->textures[i].cube_info[face].offset = 0; 2475 } 2476 } 2477 } 2478 2479 /* 2480 * Global GPU functions 2481 */ 2482 static void r100_errata(struct radeon_device *rdev) 2483 { 2484 rdev->pll_errata = 0; 2485 2486 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { 2487 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; 2488 } 2489 2490 if (rdev->family == CHIP_RV100 || 2491 rdev->family == CHIP_RS100 || 2492 rdev->family == CHIP_RS200) { 2493 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; 2494 } 2495 } 2496 2497 static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) 2498 { 2499 unsigned i; 2500 uint32_t tmp; 2501 2502 for (i = 0; i < rdev->usec_timeout; i++) { 2503 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; 2504 if (tmp >= n) { 2505 return 0; 2506 } 2507 udelay(1); 2508 } 2509 return -1; 2510 } 2511 2512 int r100_gui_wait_for_idle(struct radeon_device *rdev) 2513 { 2514 unsigned i; 2515 uint32_t tmp; 2516 2517 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { 2518 pr_warn("radeon: wait for empty RBBM fifo failed! Bad things might happen.\n"); 2519 } 2520 for (i = 0; i < rdev->usec_timeout; i++) { 2521 tmp = RREG32(RADEON_RBBM_STATUS); 2522 if (!(tmp & RADEON_RBBM_ACTIVE)) { 2523 return 0; 2524 } 2525 udelay(1); 2526 } 2527 return -1; 2528 } 2529 2530 int r100_mc_wait_for_idle(struct radeon_device *rdev) 2531 { 2532 unsigned i; 2533 uint32_t tmp; 2534 2535 for (i = 0; i < rdev->usec_timeout; i++) { 2536 /* read MC_STATUS */ 2537 tmp = RREG32(RADEON_MC_STATUS); 2538 if (tmp & RADEON_MC_IDLE) { 2539 return 0; 2540 } 2541 udelay(1); 2542 } 2543 return -1; 2544 } 2545 2546 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 2547 { 2548 u32 rbbm_status; 2549 2550 rbbm_status = RREG32(R_000E40_RBBM_STATUS); 2551 if (!G_000E40_GUI_ACTIVE(rbbm_status)) { 2552 radeon_ring_lockup_update(rdev, ring); 2553 return false; 2554 } 2555 return radeon_ring_test_lockup(rdev, ring); 2556 } 2557 2558 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 2559 void r100_enable_bm(struct radeon_device *rdev) 2560 { 2561 uint32_t tmp; 2562 /* Enable bus mastering */ 2563 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 2564 WREG32(RADEON_BUS_CNTL, tmp); 2565 } 2566 2567 void r100_bm_disable(struct radeon_device *rdev) 2568 { 2569 u32 tmp; 2570 2571 /* disable bus mastering */ 2572 tmp = RREG32(R_000030_BUS_CNTL); 2573 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044); 2574 mdelay(1); 2575 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042); 2576 mdelay(1); 2577 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); 2578 tmp = RREG32(RADEON_BUS_CNTL); 2579 mdelay(1); 2580 pci_clear_master(rdev->pdev); 2581 mdelay(1); 2582 } 2583 2584 int r100_asic_reset(struct radeon_device *rdev, bool hard) 2585 { 2586 struct r100_mc_save save; 2587 u32 status, tmp; 2588 int ret = 0; 2589 2590 status = RREG32(R_000E40_RBBM_STATUS); 2591 if (!G_000E40_GUI_ACTIVE(status)) { 2592 return 0; 2593 } 2594 r100_mc_stop(rdev, &save); 2595 status = RREG32(R_000E40_RBBM_STATUS); 2596 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2597 /* stop CP */ 2598 WREG32(RADEON_CP_CSQ_CNTL, 0); 2599 tmp = RREG32(RADEON_CP_RB_CNTL); 2600 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 2601 WREG32(RADEON_CP_RB_RPTR_WR, 0); 2602 WREG32(RADEON_CP_RB_WPTR, 0); 2603 WREG32(RADEON_CP_RB_CNTL, tmp); 2604 /* save PCI state */ 2605 pci_save_state(rdev->pdev); 2606 /* disable bus mastering */ 2607 r100_bm_disable(rdev); 2608 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) | 2609 S_0000F0_SOFT_RESET_RE(1) | 2610 S_0000F0_SOFT_RESET_PP(1) | 2611 S_0000F0_SOFT_RESET_RB(1)); 2612 RREG32(R_0000F0_RBBM_SOFT_RESET); 2613 mdelay(500); 2614 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2615 mdelay(1); 2616 status = RREG32(R_000E40_RBBM_STATUS); 2617 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2618 /* reset CP */ 2619 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 2620 RREG32(R_0000F0_RBBM_SOFT_RESET); 2621 mdelay(500); 2622 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2623 mdelay(1); 2624 status = RREG32(R_000E40_RBBM_STATUS); 2625 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2626 /* restore PCI & busmastering */ 2627 pci_restore_state(rdev->pdev); 2628 r100_enable_bm(rdev); 2629 /* Check if GPU is idle */ 2630 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) || 2631 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) { 2632 dev_err(rdev->dev, "failed to reset GPU\n"); 2633 ret = -1; 2634 } else 2635 dev_info(rdev->dev, "GPU reset succeed\n"); 2636 r100_mc_resume(rdev, &save); 2637 return ret; 2638 } 2639 2640 void r100_set_common_regs(struct radeon_device *rdev) 2641 { 2642 bool force_dac2 = false; 2643 u32 tmp; 2644 2645 /* set these so they don't interfere with anything */ 2646 WREG32(RADEON_OV0_SCALE_CNTL, 0); 2647 WREG32(RADEON_SUBPIC_CNTL, 0); 2648 WREG32(RADEON_VIPH_CONTROL, 0); 2649 WREG32(RADEON_I2C_CNTL_1, 0); 2650 WREG32(RADEON_DVI_I2C_CNTL_1, 0); 2651 WREG32(RADEON_CAP0_TRIG_CNTL, 0); 2652 WREG32(RADEON_CAP1_TRIG_CNTL, 0); 2653 2654 /* always set up dac2 on rn50 and some rv100 as lots 2655 * of servers seem to wire it up to a VGA port but 2656 * don't report it in the bios connector 2657 * table. 2658 */ 2659 switch (rdev->pdev->device) { 2660 /* RN50 */ 2661 case 0x515e: 2662 case 0x5969: 2663 force_dac2 = true; 2664 break; 2665 /* RV100*/ 2666 case 0x5159: 2667 case 0x515a: 2668 /* DELL triple head servers */ 2669 if ((rdev->pdev->subsystem_vendor == 0x1028 /* DELL */) && 2670 ((rdev->pdev->subsystem_device == 0x016c) || 2671 (rdev->pdev->subsystem_device == 0x016d) || 2672 (rdev->pdev->subsystem_device == 0x016e) || 2673 (rdev->pdev->subsystem_device == 0x016f) || 2674 (rdev->pdev->subsystem_device == 0x0170) || 2675 (rdev->pdev->subsystem_device == 0x017d) || 2676 (rdev->pdev->subsystem_device == 0x017e) || 2677 (rdev->pdev->subsystem_device == 0x0183) || 2678 (rdev->pdev->subsystem_device == 0x018a) || 2679 (rdev->pdev->subsystem_device == 0x019a))) 2680 force_dac2 = true; 2681 break; 2682 } 2683 2684 if (force_dac2) { 2685 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 2686 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 2687 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 2688 2689 /* For CRT on DAC2, don't turn it on if BIOS didn't 2690 enable it, even it's detected. 2691 */ 2692 2693 /* force it to crtc0 */ 2694 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; 2695 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; 2696 disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 2697 2698 /* set up the TV DAC */ 2699 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL | 2700 RADEON_TV_DAC_STD_MASK | 2701 RADEON_TV_DAC_RDACPD | 2702 RADEON_TV_DAC_GDACPD | 2703 RADEON_TV_DAC_BDACPD | 2704 RADEON_TV_DAC_BGADJ_MASK | 2705 RADEON_TV_DAC_DACADJ_MASK); 2706 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | 2707 RADEON_TV_DAC_NHOLD | 2708 RADEON_TV_DAC_STD_PS2 | 2709 (0x58 << 16)); 2710 2711 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 2712 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 2713 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 2714 } 2715 2716 /* switch PM block to ACPI mode */ 2717 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); 2718 tmp &= ~RADEON_PM_MODE_SEL; 2719 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); 2720 2721 } 2722 2723 /* 2724 * VRAM info 2725 */ 2726 static void r100_vram_get_type(struct radeon_device *rdev) 2727 { 2728 uint32_t tmp; 2729 2730 rdev->mc.vram_is_ddr = false; 2731 if (rdev->flags & RADEON_IS_IGP) 2732 rdev->mc.vram_is_ddr = true; 2733 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) 2734 rdev->mc.vram_is_ddr = true; 2735 if ((rdev->family == CHIP_RV100) || 2736 (rdev->family == CHIP_RS100) || 2737 (rdev->family == CHIP_RS200)) { 2738 tmp = RREG32(RADEON_MEM_CNTL); 2739 if (tmp & RV100_HALF_MODE) { 2740 rdev->mc.vram_width = 32; 2741 } else { 2742 rdev->mc.vram_width = 64; 2743 } 2744 if (rdev->flags & RADEON_SINGLE_CRTC) { 2745 rdev->mc.vram_width /= 4; 2746 rdev->mc.vram_is_ddr = true; 2747 } 2748 } else if (rdev->family <= CHIP_RV280) { 2749 tmp = RREG32(RADEON_MEM_CNTL); 2750 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { 2751 rdev->mc.vram_width = 128; 2752 } else { 2753 rdev->mc.vram_width = 64; 2754 } 2755 } else { 2756 /* newer IGPs */ 2757 rdev->mc.vram_width = 128; 2758 } 2759 } 2760 2761 static u32 r100_get_accessible_vram(struct radeon_device *rdev) 2762 { 2763 u32 aper_size; 2764 u8 byte; 2765 2766 aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2767 2768 /* Set HDP_APER_CNTL only on cards that are known not to be broken, 2769 * that is has the 2nd generation multifunction PCI interface 2770 */ 2771 if (rdev->family == CHIP_RV280 || 2772 rdev->family >= CHIP_RV350) { 2773 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, 2774 ~RADEON_HDP_APER_CNTL); 2775 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); 2776 return aper_size * 2; 2777 } 2778 2779 /* Older cards have all sorts of funny issues to deal with. First 2780 * check if it's a multifunction card by reading the PCI config 2781 * header type... Limit those to one aperture size 2782 */ 2783 pci_read_config_byte(rdev->pdev, 0xe, &byte); 2784 if (byte & 0x80) { 2785 DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); 2786 DRM_INFO("Limiting VRAM to one aperture\n"); 2787 return aper_size; 2788 } 2789 2790 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS 2791 * have set it up. We don't write this as it's broken on some ASICs but 2792 * we expect the BIOS to have done the right thing (might be too optimistic...) 2793 */ 2794 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) 2795 return aper_size * 2; 2796 return aper_size; 2797 } 2798 2799 void r100_vram_init_sizes(struct radeon_device *rdev) 2800 { 2801 u64 config_aper_size; 2802 2803 /* work out accessible VRAM */ 2804 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 2805 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 2806 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); 2807 /* FIXME we don't use the second aperture yet when we could use it */ 2808 if (rdev->mc.visible_vram_size > rdev->mc.aper_size) 2809 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2810 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2811 if (rdev->flags & RADEON_IS_IGP) { 2812 uint32_t tom; 2813 /* read NB_TOM to get the amount of ram stolen for the GPU */ 2814 tom = RREG32(RADEON_NB_TOM); 2815 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); 2816 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2817 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2818 } else { 2819 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 2820 /* Some production boards of m6 will report 0 2821 * if it's 8 MB 2822 */ 2823 if (rdev->mc.real_vram_size == 0) { 2824 rdev->mc.real_vram_size = 8192 * 1024; 2825 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2826 } 2827 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 2828 * Novell bug 204882 + along with lots of ubuntu ones 2829 */ 2830 if (rdev->mc.aper_size > config_aper_size) 2831 config_aper_size = rdev->mc.aper_size; 2832 2833 if (config_aper_size > rdev->mc.real_vram_size) 2834 rdev->mc.mc_vram_size = config_aper_size; 2835 else 2836 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2837 } 2838 } 2839 2840 void r100_vga_set_state(struct radeon_device *rdev, bool state) 2841 { 2842 uint32_t temp; 2843 2844 temp = RREG32(RADEON_CONFIG_CNTL); 2845 if (!state) { 2846 temp &= ~RADEON_CFG_VGA_RAM_EN; 2847 temp |= RADEON_CFG_VGA_IO_DIS; 2848 } else { 2849 temp &= ~RADEON_CFG_VGA_IO_DIS; 2850 } 2851 WREG32(RADEON_CONFIG_CNTL, temp); 2852 } 2853 2854 static void r100_mc_init(struct radeon_device *rdev) 2855 { 2856 u64 base; 2857 2858 r100_vram_get_type(rdev); 2859 r100_vram_init_sizes(rdev); 2860 base = rdev->mc.aper_base; 2861 if (rdev->flags & RADEON_IS_IGP) 2862 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 2863 radeon_vram_location(rdev, &rdev->mc, base); 2864 rdev->mc.gtt_base_align = 0; 2865 if (!(rdev->flags & RADEON_IS_AGP)) 2866 radeon_gtt_location(rdev, &rdev->mc); 2867 radeon_update_bandwidth_info(rdev); 2868 } 2869 2870 2871 /* 2872 * Indirect registers accessor 2873 */ 2874 void r100_pll_errata_after_index(struct radeon_device *rdev) 2875 { 2876 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) { 2877 (void)RREG32(RADEON_CLOCK_CNTL_DATA); 2878 (void)RREG32(RADEON_CRTC_GEN_CNTL); 2879 } 2880 } 2881 2882 static void r100_pll_errata_after_data(struct radeon_device *rdev) 2883 { 2884 /* This workarounds is necessary on RV100, RS100 and RS200 chips 2885 * or the chip could hang on a subsequent access 2886 */ 2887 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { 2888 mdelay(5); 2889 } 2890 2891 /* This function is required to workaround a hardware bug in some (all?) 2892 * revisions of the R300. This workaround should be called after every 2893 * CLOCK_CNTL_INDEX register access. If not, register reads afterward 2894 * may not be correct. 2895 */ 2896 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { 2897 uint32_t save, tmp; 2898 2899 save = RREG32(RADEON_CLOCK_CNTL_INDEX); 2900 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2901 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); 2902 tmp = RREG32(RADEON_CLOCK_CNTL_DATA); 2903 WREG32(RADEON_CLOCK_CNTL_INDEX, save); 2904 } 2905 } 2906 2907 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) 2908 { 2909 unsigned long flags; 2910 uint32_t data; 2911 2912 spin_lock_irqsave(&rdev->pll_idx_lock, flags); 2913 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); 2914 r100_pll_errata_after_index(rdev); 2915 data = RREG32(RADEON_CLOCK_CNTL_DATA); 2916 r100_pll_errata_after_data(rdev); 2917 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); 2918 return data; 2919 } 2920 2921 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2922 { 2923 unsigned long flags; 2924 2925 spin_lock_irqsave(&rdev->pll_idx_lock, flags); 2926 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); 2927 r100_pll_errata_after_index(rdev); 2928 WREG32(RADEON_CLOCK_CNTL_DATA, v); 2929 r100_pll_errata_after_data(rdev); 2930 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); 2931 } 2932 2933 static void r100_set_safe_registers(struct radeon_device *rdev) 2934 { 2935 if (ASIC_IS_RN50(rdev)) { 2936 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; 2937 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); 2938 } else if (rdev->family < CHIP_R200) { 2939 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; 2940 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); 2941 } else { 2942 r200_set_safe_registers(rdev); 2943 } 2944 } 2945 2946 /* 2947 * Debugfs info 2948 */ 2949 #if defined(CONFIG_DEBUG_FS) 2950 static int r100_debugfs_rbbm_info_show(struct seq_file *m, void *unused) 2951 { 2952 struct radeon_device *rdev = m->private; 2953 uint32_t reg, value; 2954 unsigned i; 2955 2956 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); 2957 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); 2958 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2959 for (i = 0; i < 64; i++) { 2960 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); 2961 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; 2962 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); 2963 value = RREG32(RADEON_RBBM_CMDFIFO_DATA); 2964 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); 2965 } 2966 return 0; 2967 } 2968 2969 static int r100_debugfs_cp_ring_info_show(struct seq_file *m, void *unused) 2970 { 2971 struct radeon_device *rdev = m->private; 2972 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2973 uint32_t rdp, wdp; 2974 unsigned count, i, j; 2975 2976 radeon_ring_free_size(rdev, ring); 2977 rdp = RREG32(RADEON_CP_RB_RPTR); 2978 wdp = RREG32(RADEON_CP_RB_WPTR); 2979 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask; 2980 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2981 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); 2982 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); 2983 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); 2984 seq_printf(m, "%u dwords in ring\n", count); 2985 if (ring->ready) { 2986 for (j = 0; j <= count; j++) { 2987 i = (rdp + j) & ring->ptr_mask; 2988 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); 2989 } 2990 } 2991 return 0; 2992 } 2993 2994 2995 static int r100_debugfs_cp_csq_fifo_show(struct seq_file *m, void *unused) 2996 { 2997 struct radeon_device *rdev = m->private; 2998 uint32_t csq_stat, csq2_stat, tmp; 2999 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; 3000 unsigned i; 3001 3002 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 3003 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); 3004 csq_stat = RREG32(RADEON_CP_CSQ_STAT); 3005 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); 3006 r_rptr = (csq_stat >> 0) & 0x3ff; 3007 r_wptr = (csq_stat >> 10) & 0x3ff; 3008 ib1_rptr = (csq_stat >> 20) & 0x3ff; 3009 ib1_wptr = (csq2_stat >> 0) & 0x3ff; 3010 ib2_rptr = (csq2_stat >> 10) & 0x3ff; 3011 ib2_wptr = (csq2_stat >> 20) & 0x3ff; 3012 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); 3013 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); 3014 seq_printf(m, "Ring rptr %u\n", r_rptr); 3015 seq_printf(m, "Ring wptr %u\n", r_wptr); 3016 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); 3017 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); 3018 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); 3019 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); 3020 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms 3021 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ 3022 seq_printf(m, "Ring fifo:\n"); 3023 for (i = 0; i < 256; i++) { 3024 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 3025 tmp = RREG32(RADEON_CP_CSQ_DATA); 3026 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); 3027 } 3028 seq_printf(m, "Indirect1 fifo:\n"); 3029 for (i = 256; i <= 512; i++) { 3030 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 3031 tmp = RREG32(RADEON_CP_CSQ_DATA); 3032 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); 3033 } 3034 seq_printf(m, "Indirect2 fifo:\n"); 3035 for (i = 640; i < ib1_wptr; i++) { 3036 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 3037 tmp = RREG32(RADEON_CP_CSQ_DATA); 3038 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); 3039 } 3040 return 0; 3041 } 3042 3043 static int r100_debugfs_mc_info_show(struct seq_file *m, void *unused) 3044 { 3045 struct radeon_device *rdev = m->private; 3046 uint32_t tmp; 3047 3048 tmp = RREG32(RADEON_CONFIG_MEMSIZE); 3049 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); 3050 tmp = RREG32(RADEON_MC_FB_LOCATION); 3051 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); 3052 tmp = RREG32(RADEON_BUS_CNTL); 3053 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 3054 tmp = RREG32(RADEON_MC_AGP_LOCATION); 3055 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 3056 tmp = RREG32(RADEON_AGP_BASE); 3057 seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 3058 tmp = RREG32(RADEON_HOST_PATH_CNTL); 3059 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 3060 tmp = RREG32(0x01D0); 3061 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); 3062 tmp = RREG32(RADEON_AIC_LO_ADDR); 3063 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); 3064 tmp = RREG32(RADEON_AIC_HI_ADDR); 3065 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); 3066 tmp = RREG32(0x01E4); 3067 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); 3068 return 0; 3069 } 3070 3071 DEFINE_SHOW_ATTRIBUTE(r100_debugfs_rbbm_info); 3072 DEFINE_SHOW_ATTRIBUTE(r100_debugfs_cp_ring_info); 3073 DEFINE_SHOW_ATTRIBUTE(r100_debugfs_cp_csq_fifo); 3074 DEFINE_SHOW_ATTRIBUTE(r100_debugfs_mc_info); 3075 3076 #endif 3077 3078 void r100_debugfs_rbbm_init(struct radeon_device *rdev) 3079 { 3080 #if defined(CONFIG_DEBUG_FS) 3081 struct dentry *root = rdev->ddev->primary->debugfs_root; 3082 3083 debugfs_create_file("r100_rbbm_info", 0444, root, rdev, 3084 &r100_debugfs_rbbm_info_fops); 3085 #endif 3086 } 3087 3088 void r100_debugfs_cp_init(struct radeon_device *rdev) 3089 { 3090 #if defined(CONFIG_DEBUG_FS) 3091 struct dentry *root = rdev->ddev->primary->debugfs_root; 3092 3093 debugfs_create_file("r100_cp_ring_info", 0444, root, rdev, 3094 &r100_debugfs_cp_ring_info_fops); 3095 debugfs_create_file("r100_cp_csq_fifo", 0444, root, rdev, 3096 &r100_debugfs_cp_csq_fifo_fops); 3097 #endif 3098 } 3099 3100 void r100_debugfs_mc_info_init(struct radeon_device *rdev) 3101 { 3102 #if defined(CONFIG_DEBUG_FS) 3103 struct dentry *root = rdev->ddev->primary->debugfs_root; 3104 3105 debugfs_create_file("r100_mc_info", 0444, root, rdev, 3106 &r100_debugfs_mc_info_fops); 3107 #endif 3108 } 3109 3110 int r100_set_surface_reg(struct radeon_device *rdev, int reg, 3111 uint32_t tiling_flags, uint32_t pitch, 3112 uint32_t offset, uint32_t obj_size) 3113 { 3114 int surf_index = reg * 16; 3115 int flags = 0; 3116 3117 if (rdev->family <= CHIP_RS200) { 3118 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3119 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3120 flags |= RADEON_SURF_TILE_COLOR_BOTH; 3121 if (tiling_flags & RADEON_TILING_MACRO) 3122 flags |= RADEON_SURF_TILE_COLOR_MACRO; 3123 /* setting pitch to 0 disables tiling */ 3124 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3125 == 0) 3126 pitch = 0; 3127 } else if (rdev->family <= CHIP_RV280) { 3128 if (tiling_flags & (RADEON_TILING_MACRO)) 3129 flags |= R200_SURF_TILE_COLOR_MACRO; 3130 if (tiling_flags & RADEON_TILING_MICRO) 3131 flags |= R200_SURF_TILE_COLOR_MICRO; 3132 } else { 3133 if (tiling_flags & RADEON_TILING_MACRO) 3134 flags |= R300_SURF_TILE_MACRO; 3135 if (tiling_flags & RADEON_TILING_MICRO) 3136 flags |= R300_SURF_TILE_MICRO; 3137 } 3138 3139 if (tiling_flags & RADEON_TILING_SWAP_16BIT) 3140 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; 3141 if (tiling_flags & RADEON_TILING_SWAP_32BIT) 3142 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; 3143 3144 /* r100/r200 divide by 16 */ 3145 if (rdev->family < CHIP_R300) 3146 flags |= pitch / 16; 3147 else 3148 flags |= pitch / 8; 3149 3150 3151 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); 3152 WREG32(RADEON_SURFACE0_INFO + surf_index, flags); 3153 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); 3154 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); 3155 return 0; 3156 } 3157 3158 void r100_clear_surface_reg(struct radeon_device *rdev, int reg) 3159 { 3160 int surf_index = reg * 16; 3161 WREG32(RADEON_SURFACE0_INFO + surf_index, 0); 3162 } 3163 3164 void r100_bandwidth_update(struct radeon_device *rdev) 3165 { 3166 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; 3167 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; 3168 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff; 3169 fixed20_12 crit_point_ff = {0}; 3170 uint32_t temp, data, mem_trcd, mem_trp, mem_tras; 3171 fixed20_12 memtcas_ff[8] = { 3172 dfixed_init(1), 3173 dfixed_init(2), 3174 dfixed_init(3), 3175 dfixed_init(0), 3176 dfixed_init_half(1), 3177 dfixed_init_half(2), 3178 dfixed_init(0), 3179 }; 3180 fixed20_12 memtcas_rs480_ff[8] = { 3181 dfixed_init(0), 3182 dfixed_init(1), 3183 dfixed_init(2), 3184 dfixed_init(3), 3185 dfixed_init(0), 3186 dfixed_init_half(1), 3187 dfixed_init_half(2), 3188 dfixed_init_half(3), 3189 }; 3190 fixed20_12 memtcas2_ff[8] = { 3191 dfixed_init(0), 3192 dfixed_init(1), 3193 dfixed_init(2), 3194 dfixed_init(3), 3195 dfixed_init(4), 3196 dfixed_init(5), 3197 dfixed_init(6), 3198 dfixed_init(7), 3199 }; 3200 fixed20_12 memtrbs[8] = { 3201 dfixed_init(1), 3202 dfixed_init_half(1), 3203 dfixed_init(2), 3204 dfixed_init_half(2), 3205 dfixed_init(3), 3206 dfixed_init_half(3), 3207 dfixed_init(4), 3208 dfixed_init_half(4) 3209 }; 3210 fixed20_12 memtrbs_r4xx[8] = { 3211 dfixed_init(4), 3212 dfixed_init(5), 3213 dfixed_init(6), 3214 dfixed_init(7), 3215 dfixed_init(8), 3216 dfixed_init(9), 3217 dfixed_init(10), 3218 dfixed_init(11) 3219 }; 3220 fixed20_12 min_mem_eff; 3221 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; 3222 fixed20_12 cur_latency_mclk, cur_latency_sclk; 3223 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate = {0}, 3224 disp_drain_rate2, read_return_rate; 3225 fixed20_12 time_disp1_drop_priority; 3226 int c; 3227 int cur_size = 16; /* in octawords */ 3228 int critical_point = 0, critical_point2; 3229 /* uint32_t read_return_rate, time_disp1_drop_priority; */ 3230 int stop_req, max_stop_req; 3231 struct drm_display_mode *mode1 = NULL; 3232 struct drm_display_mode *mode2 = NULL; 3233 uint32_t pixel_bytes1 = 0; 3234 uint32_t pixel_bytes2 = 0; 3235 3236 /* Guess line buffer size to be 8192 pixels */ 3237 u32 lb_size = 8192; 3238 3239 if (!rdev->mode_info.mode_config_initialized) 3240 return; 3241 3242 radeon_update_display_priority(rdev); 3243 3244 if (rdev->mode_info.crtcs[0]->base.enabled) { 3245 const struct drm_framebuffer *fb = 3246 rdev->mode_info.crtcs[0]->base.primary->fb; 3247 3248 mode1 = &rdev->mode_info.crtcs[0]->base.mode; 3249 pixel_bytes1 = fb->format->cpp[0]; 3250 } 3251 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3252 if (rdev->mode_info.crtcs[1]->base.enabled) { 3253 const struct drm_framebuffer *fb = 3254 rdev->mode_info.crtcs[1]->base.primary->fb; 3255 3256 mode2 = &rdev->mode_info.crtcs[1]->base.mode; 3257 pixel_bytes2 = fb->format->cpp[0]; 3258 } 3259 } 3260 3261 min_mem_eff.full = dfixed_const_8(0); 3262 /* get modes */ 3263 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { 3264 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); 3265 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); 3266 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); 3267 /* check crtc enables */ 3268 if (mode2) 3269 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); 3270 if (mode1) 3271 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); 3272 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); 3273 } 3274 3275 /* 3276 * determine is there is enough bw for current mode 3277 */ 3278 sclk_ff = rdev->pm.sclk; 3279 mclk_ff = rdev->pm.mclk; 3280 3281 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); 3282 temp_ff.full = dfixed_const(temp); 3283 mem_bw.full = dfixed_mul(mclk_ff, temp_ff); 3284 3285 pix_clk.full = 0; 3286 pix_clk2.full = 0; 3287 peak_disp_bw.full = 0; 3288 if (mode1) { 3289 temp_ff.full = dfixed_const(1000); 3290 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ 3291 pix_clk.full = dfixed_div(pix_clk, temp_ff); 3292 temp_ff.full = dfixed_const(pixel_bytes1); 3293 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); 3294 } 3295 if (mode2) { 3296 temp_ff.full = dfixed_const(1000); 3297 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ 3298 pix_clk2.full = dfixed_div(pix_clk2, temp_ff); 3299 temp_ff.full = dfixed_const(pixel_bytes2); 3300 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); 3301 } 3302 3303 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); 3304 if (peak_disp_bw.full >= mem_bw.full) { 3305 DRM_ERROR("You may not have enough display bandwidth for current mode\n" 3306 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); 3307 } 3308 3309 /* Get values from the EXT_MEM_CNTL register...converting its contents. */ 3310 temp = RREG32(RADEON_MEM_TIMING_CNTL); 3311 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ 3312 mem_trcd = ((temp >> 2) & 0x3) + 1; 3313 mem_trp = ((temp & 0x3)) + 1; 3314 mem_tras = ((temp & 0x70) >> 4) + 1; 3315 } else if (rdev->family == CHIP_R300 || 3316 rdev->family == CHIP_R350) { /* r300, r350 */ 3317 mem_trcd = (temp & 0x7) + 1; 3318 mem_trp = ((temp >> 8) & 0x7) + 1; 3319 mem_tras = ((temp >> 11) & 0xf) + 4; 3320 } else if (rdev->family == CHIP_RV350 || 3321 rdev->family == CHIP_RV380) { 3322 /* rv3x0 */ 3323 mem_trcd = (temp & 0x7) + 3; 3324 mem_trp = ((temp >> 8) & 0x7) + 3; 3325 mem_tras = ((temp >> 11) & 0xf) + 6; 3326 } else if (rdev->family == CHIP_R420 || 3327 rdev->family == CHIP_R423 || 3328 rdev->family == CHIP_RV410) { 3329 /* r4xx */ 3330 mem_trcd = (temp & 0xf) + 3; 3331 if (mem_trcd > 15) 3332 mem_trcd = 15; 3333 mem_trp = ((temp >> 8) & 0xf) + 3; 3334 if (mem_trp > 15) 3335 mem_trp = 15; 3336 mem_tras = ((temp >> 12) & 0x1f) + 6; 3337 if (mem_tras > 31) 3338 mem_tras = 31; 3339 } else { /* RV200, R200 */ 3340 mem_trcd = (temp & 0x7) + 1; 3341 mem_trp = ((temp >> 8) & 0x7) + 1; 3342 mem_tras = ((temp >> 12) & 0xf) + 4; 3343 } 3344 /* convert to FF */ 3345 trcd_ff.full = dfixed_const(mem_trcd); 3346 trp_ff.full = dfixed_const(mem_trp); 3347 tras_ff.full = dfixed_const(mem_tras); 3348 3349 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ 3350 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3351 data = (temp & (7 << 20)) >> 20; 3352 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { 3353 if (rdev->family == CHIP_RS480) /* don't think rs400 */ 3354 tcas_ff = memtcas_rs480_ff[data]; 3355 else 3356 tcas_ff = memtcas_ff[data]; 3357 } else 3358 tcas_ff = memtcas2_ff[data]; 3359 3360 if (rdev->family == CHIP_RS400 || 3361 rdev->family == CHIP_RS480) { 3362 /* extra cas latency stored in bits 23-25 0-4 clocks */ 3363 data = (temp >> 23) & 0x7; 3364 if (data < 5) 3365 tcas_ff.full += dfixed_const(data); 3366 } 3367 3368 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { 3369 /* on the R300, Tcas is included in Trbs. 3370 */ 3371 temp = RREG32(RADEON_MEM_CNTL); 3372 data = (R300_MEM_NUM_CHANNELS_MASK & temp); 3373 if (data == 1) { 3374 if (R300_MEM_USE_CD_CH_ONLY & temp) { 3375 temp = RREG32(R300_MC_IND_INDEX); 3376 temp &= ~R300_MC_IND_ADDR_MASK; 3377 temp |= R300_MC_READ_CNTL_CD_mcind; 3378 WREG32(R300_MC_IND_INDEX, temp); 3379 temp = RREG32(R300_MC_IND_DATA); 3380 data = (R300_MEM_RBS_POSITION_C_MASK & temp); 3381 } else { 3382 temp = RREG32(R300_MC_READ_CNTL_AB); 3383 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 3384 } 3385 } else { 3386 temp = RREG32(R300_MC_READ_CNTL_AB); 3387 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 3388 } 3389 if (rdev->family == CHIP_RV410 || 3390 rdev->family == CHIP_R420 || 3391 rdev->family == CHIP_R423) 3392 trbs_ff = memtrbs_r4xx[data]; 3393 else 3394 trbs_ff = memtrbs[data]; 3395 tcas_ff.full += trbs_ff.full; 3396 } 3397 3398 sclk_eff_ff.full = sclk_ff.full; 3399 3400 if (rdev->flags & RADEON_IS_AGP) { 3401 fixed20_12 agpmode_ff; 3402 agpmode_ff.full = dfixed_const(radeon_agpmode); 3403 temp_ff.full = dfixed_const_666(16); 3404 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); 3405 } 3406 /* TODO PCIE lanes may affect this - agpmode == 16?? */ 3407 3408 if (ASIC_IS_R300(rdev)) { 3409 sclk_delay_ff.full = dfixed_const(250); 3410 } else { 3411 if ((rdev->family == CHIP_RV100) || 3412 rdev->flags & RADEON_IS_IGP) { 3413 if (rdev->mc.vram_is_ddr) 3414 sclk_delay_ff.full = dfixed_const(41); 3415 else 3416 sclk_delay_ff.full = dfixed_const(33); 3417 } else { 3418 if (rdev->mc.vram_width == 128) 3419 sclk_delay_ff.full = dfixed_const(57); 3420 else 3421 sclk_delay_ff.full = dfixed_const(41); 3422 } 3423 } 3424 3425 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff); 3426 3427 if (rdev->mc.vram_is_ddr) { 3428 if (rdev->mc.vram_width == 32) { 3429 k1.full = dfixed_const(40); 3430 c = 3; 3431 } else { 3432 k1.full = dfixed_const(20); 3433 c = 1; 3434 } 3435 } else { 3436 k1.full = dfixed_const(40); 3437 c = 3; 3438 } 3439 3440 temp_ff.full = dfixed_const(2); 3441 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); 3442 temp_ff.full = dfixed_const(c); 3443 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); 3444 temp_ff.full = dfixed_const(4); 3445 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); 3446 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); 3447 mc_latency_mclk.full += k1.full; 3448 3449 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff); 3450 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff); 3451 3452 /* 3453 HW cursor time assuming worst case of full size colour cursor. 3454 */ 3455 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); 3456 temp_ff.full += trcd_ff.full; 3457 if (temp_ff.full < tras_ff.full) 3458 temp_ff.full = tras_ff.full; 3459 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff); 3460 3461 temp_ff.full = dfixed_const(cur_size); 3462 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff); 3463 /* 3464 Find the total latency for the display data. 3465 */ 3466 disp_latency_overhead.full = dfixed_const(8); 3467 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff); 3468 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; 3469 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; 3470 3471 if (mc_latency_mclk.full > mc_latency_sclk.full) 3472 disp_latency.full = mc_latency_mclk.full; 3473 else 3474 disp_latency.full = mc_latency_sclk.full; 3475 3476 /* setup Max GRPH_STOP_REQ default value */ 3477 if (ASIC_IS_RV100(rdev)) 3478 max_stop_req = 0x5c; 3479 else 3480 max_stop_req = 0x7c; 3481 3482 if (mode1) { 3483 /* CRTC1 3484 Set GRPH_BUFFER_CNTL register using h/w defined optimal values. 3485 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] 3486 */ 3487 stop_req = mode1->hdisplay * pixel_bytes1 / 16; 3488 3489 if (stop_req > max_stop_req) 3490 stop_req = max_stop_req; 3491 3492 /* 3493 Find the drain rate of the display buffer. 3494 */ 3495 temp_ff.full = dfixed_const((16/pixel_bytes1)); 3496 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); 3497 3498 /* 3499 Find the critical point of the display buffer. 3500 */ 3501 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); 3502 crit_point_ff.full += dfixed_const_half(0); 3503 3504 critical_point = dfixed_trunc(crit_point_ff); 3505 3506 if (rdev->disp_priority == 2) { 3507 critical_point = 0; 3508 } 3509 3510 /* 3511 The critical point should never be above max_stop_req-4. Setting 3512 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. 3513 */ 3514 if (max_stop_req - critical_point < 4) 3515 critical_point = 0; 3516 3517 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { 3518 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ 3519 critical_point = 0x10; 3520 } 3521 3522 temp = RREG32(RADEON_GRPH_BUFFER_CNTL); 3523 temp &= ~(RADEON_GRPH_STOP_REQ_MASK); 3524 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3525 temp &= ~(RADEON_GRPH_START_REQ_MASK); 3526 if ((rdev->family == CHIP_R350) && 3527 (stop_req > 0x15)) { 3528 stop_req -= 0x10; 3529 } 3530 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3531 temp |= RADEON_GRPH_BUFFER_SIZE; 3532 temp &= ~(RADEON_GRPH_CRITICAL_CNTL | 3533 RADEON_GRPH_CRITICAL_AT_SOF | 3534 RADEON_GRPH_STOP_CNTL); 3535 /* 3536 Write the result into the register. 3537 */ 3538 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3539 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3540 3541 #if 0 3542 if ((rdev->family == CHIP_RS400) || 3543 (rdev->family == CHIP_RS480)) { 3544 /* attempt to program RS400 disp regs correctly ??? */ 3545 temp = RREG32(RS400_DISP1_REG_CNTL); 3546 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | 3547 RS400_DISP1_STOP_REQ_LEVEL_MASK); 3548 WREG32(RS400_DISP1_REQ_CNTL1, (temp | 3549 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3550 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3551 temp = RREG32(RS400_DMIF_MEM_CNTL1); 3552 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | 3553 RS400_DISP1_CRITICAL_POINT_STOP_MASK); 3554 WREG32(RS400_DMIF_MEM_CNTL1, (temp | 3555 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | 3556 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); 3557 } 3558 #endif 3559 3560 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n", 3561 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ 3562 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); 3563 } 3564 3565 if (mode2) { 3566 u32 grph2_cntl; 3567 stop_req = mode2->hdisplay * pixel_bytes2 / 16; 3568 3569 if (stop_req > max_stop_req) 3570 stop_req = max_stop_req; 3571 3572 /* 3573 Find the drain rate of the display buffer. 3574 */ 3575 temp_ff.full = dfixed_const((16/pixel_bytes2)); 3576 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff); 3577 3578 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); 3579 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); 3580 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3581 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); 3582 if ((rdev->family == CHIP_R350) && 3583 (stop_req > 0x15)) { 3584 stop_req -= 0x10; 3585 } 3586 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3587 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; 3588 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | 3589 RADEON_GRPH_CRITICAL_AT_SOF | 3590 RADEON_GRPH_STOP_CNTL); 3591 3592 if ((rdev->family == CHIP_RS100) || 3593 (rdev->family == CHIP_RS200)) 3594 critical_point2 = 0; 3595 else { 3596 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; 3597 temp_ff.full = dfixed_const(temp); 3598 temp_ff.full = dfixed_mul(mclk_ff, temp_ff); 3599 if (sclk_ff.full < temp_ff.full) 3600 temp_ff.full = sclk_ff.full; 3601 3602 read_return_rate.full = temp_ff.full; 3603 3604 if (mode1) { 3605 temp_ff.full = read_return_rate.full - disp_drain_rate.full; 3606 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff); 3607 } else { 3608 time_disp1_drop_priority.full = 0; 3609 } 3610 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; 3611 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2); 3612 crit_point_ff.full += dfixed_const_half(0); 3613 3614 critical_point2 = dfixed_trunc(crit_point_ff); 3615 3616 if (rdev->disp_priority == 2) { 3617 critical_point2 = 0; 3618 } 3619 3620 if (max_stop_req - critical_point2 < 4) 3621 critical_point2 = 0; 3622 3623 } 3624 3625 if (critical_point2 == 0 && rdev->family == CHIP_R300) { 3626 /* some R300 cards have problem with this set to 0 */ 3627 critical_point2 = 0x10; 3628 } 3629 3630 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3631 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3632 3633 if ((rdev->family == CHIP_RS400) || 3634 (rdev->family == CHIP_RS480)) { 3635 #if 0 3636 /* attempt to program RS400 disp2 regs correctly ??? */ 3637 temp = RREG32(RS400_DISP2_REQ_CNTL1); 3638 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | 3639 RS400_DISP2_STOP_REQ_LEVEL_MASK); 3640 WREG32(RS400_DISP2_REQ_CNTL1, (temp | 3641 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3642 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3643 temp = RREG32(RS400_DISP2_REQ_CNTL2); 3644 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | 3645 RS400_DISP2_CRITICAL_POINT_STOP_MASK); 3646 WREG32(RS400_DISP2_REQ_CNTL2, (temp | 3647 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | 3648 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); 3649 #endif 3650 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); 3651 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); 3652 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); 3653 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); 3654 } 3655 3656 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n", 3657 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); 3658 } 3659 3660 /* Save number of lines the linebuffer leads before the scanout */ 3661 if (mode1) 3662 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); 3663 3664 if (mode2) 3665 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); 3666 } 3667 3668 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 3669 { 3670 uint32_t scratch; 3671 uint32_t tmp = 0; 3672 unsigned i; 3673 int r; 3674 3675 r = radeon_scratch_get(rdev, &scratch); 3676 if (r) { 3677 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 3678 return r; 3679 } 3680 WREG32(scratch, 0xCAFEDEAD); 3681 r = radeon_ring_lock(rdev, ring, 2); 3682 if (r) { 3683 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 3684 radeon_scratch_free(rdev, scratch); 3685 return r; 3686 } 3687 radeon_ring_write(ring, PACKET0(scratch, 0)); 3688 radeon_ring_write(ring, 0xDEADBEEF); 3689 radeon_ring_unlock_commit(rdev, ring, false); 3690 for (i = 0; i < rdev->usec_timeout; i++) { 3691 tmp = RREG32(scratch); 3692 if (tmp == 0xDEADBEEF) { 3693 break; 3694 } 3695 udelay(1); 3696 } 3697 if (i < rdev->usec_timeout) { 3698 DRM_INFO("ring test succeeded in %d usecs\n", i); 3699 } else { 3700 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", 3701 scratch, tmp); 3702 r = -EINVAL; 3703 } 3704 radeon_scratch_free(rdev, scratch); 3705 return r; 3706 } 3707 3708 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3709 { 3710 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3711 3712 if (ring->rptr_save_reg) { 3713 u32 next_rptr = ring->wptr + 2 + 3; 3714 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0)); 3715 radeon_ring_write(ring, next_rptr); 3716 } 3717 3718 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1)); 3719 radeon_ring_write(ring, ib->gpu_addr); 3720 radeon_ring_write(ring, ib->length_dw); 3721 } 3722 3723 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3724 { 3725 struct radeon_ib ib; 3726 uint32_t scratch; 3727 uint32_t tmp = 0; 3728 unsigned i; 3729 int r; 3730 3731 r = radeon_scratch_get(rdev, &scratch); 3732 if (r) { 3733 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3734 return r; 3735 } 3736 WREG32(scratch, 0xCAFEDEAD); 3737 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256); 3738 if (r) { 3739 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3740 goto free_scratch; 3741 } 3742 ib.ptr[0] = PACKET0(scratch, 0); 3743 ib.ptr[1] = 0xDEADBEEF; 3744 ib.ptr[2] = PACKET2(0); 3745 ib.ptr[3] = PACKET2(0); 3746 ib.ptr[4] = PACKET2(0); 3747 ib.ptr[5] = PACKET2(0); 3748 ib.ptr[6] = PACKET2(0); 3749 ib.ptr[7] = PACKET2(0); 3750 ib.length_dw = 8; 3751 r = radeon_ib_schedule(rdev, &ib, NULL, false); 3752 if (r) { 3753 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3754 goto free_ib; 3755 } 3756 r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies( 3757 RADEON_USEC_IB_TEST_TIMEOUT)); 3758 if (r < 0) { 3759 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3760 goto free_ib; 3761 } else if (r == 0) { 3762 DRM_ERROR("radeon: fence wait timed out.\n"); 3763 r = -ETIMEDOUT; 3764 goto free_ib; 3765 } 3766 r = 0; 3767 for (i = 0; i < rdev->usec_timeout; i++) { 3768 tmp = RREG32(scratch); 3769 if (tmp == 0xDEADBEEF) { 3770 break; 3771 } 3772 udelay(1); 3773 } 3774 if (i < rdev->usec_timeout) { 3775 DRM_INFO("ib test succeeded in %u usecs\n", i); 3776 } else { 3777 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3778 scratch, tmp); 3779 r = -EINVAL; 3780 } 3781 free_ib: 3782 radeon_ib_free(rdev, &ib); 3783 free_scratch: 3784 radeon_scratch_free(rdev, scratch); 3785 return r; 3786 } 3787 3788 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) 3789 { 3790 /* Shutdown CP we shouldn't need to do that but better be safe than 3791 * sorry 3792 */ 3793 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 3794 WREG32(R_000740_CP_CSQ_CNTL, 0); 3795 3796 /* Save few CRTC registers */ 3797 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); 3798 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); 3799 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); 3800 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); 3801 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3802 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); 3803 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); 3804 } 3805 3806 /* Disable VGA aperture access */ 3807 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); 3808 /* Disable cursor, overlay, crtc */ 3809 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); 3810 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | 3811 S_000054_CRTC_DISPLAY_DIS(1)); 3812 WREG32(R_000050_CRTC_GEN_CNTL, 3813 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | 3814 S_000050_CRTC_DISP_REQ_EN_B(1)); 3815 WREG32(R_000420_OV0_SCALE_CNTL, 3816 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); 3817 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); 3818 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3819 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | 3820 S_000360_CUR2_LOCK(1)); 3821 WREG32(R_0003F8_CRTC2_GEN_CNTL, 3822 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | 3823 S_0003F8_CRTC2_DISPLAY_DIS(1) | 3824 S_0003F8_CRTC2_DISP_REQ_EN_B(1)); 3825 WREG32(R_000360_CUR2_OFFSET, 3826 C_000360_CUR2_LOCK & save->CUR2_OFFSET); 3827 } 3828 } 3829 3830 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) 3831 { 3832 /* Update base address for crtc */ 3833 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3834 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3835 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3836 } 3837 /* Restore CRTC registers */ 3838 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); 3839 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); 3840 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); 3841 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3842 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); 3843 } 3844 } 3845 3846 void r100_vga_render_disable(struct radeon_device *rdev) 3847 { 3848 u32 tmp; 3849 3850 tmp = RREG8(R_0003C2_GENMO_WT); 3851 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); 3852 } 3853 3854 static void r100_mc_program(struct radeon_device *rdev) 3855 { 3856 struct r100_mc_save save; 3857 3858 /* Stops all mc clients */ 3859 r100_mc_stop(rdev, &save); 3860 if (rdev->flags & RADEON_IS_AGP) { 3861 WREG32(R_00014C_MC_AGP_LOCATION, 3862 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 3863 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 3864 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 3865 if (rdev->family > CHIP_RV200) 3866 WREG32(R_00015C_AGP_BASE_2, 3867 upper_32_bits(rdev->mc.agp_base) & 0xff); 3868 } else { 3869 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 3870 WREG32(R_000170_AGP_BASE, 0); 3871 if (rdev->family > CHIP_RV200) 3872 WREG32(R_00015C_AGP_BASE_2, 0); 3873 } 3874 /* Wait for mc idle */ 3875 if (r100_mc_wait_for_idle(rdev)) 3876 dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); 3877 /* Program MC, should be a 32bits limited address space */ 3878 WREG32(R_000148_MC_FB_LOCATION, 3879 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 3880 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 3881 r100_mc_resume(rdev, &save); 3882 } 3883 3884 static void r100_clock_startup(struct radeon_device *rdev) 3885 { 3886 u32 tmp; 3887 3888 if (radeon_dynclks != -1 && radeon_dynclks) 3889 radeon_legacy_set_clock_gating(rdev, 1); 3890 /* We need to force on some of the block */ 3891 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 3892 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 3893 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) 3894 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); 3895 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 3896 } 3897 3898 static int r100_startup(struct radeon_device *rdev) 3899 { 3900 int r; 3901 3902 /* set common regs */ 3903 r100_set_common_regs(rdev); 3904 /* program mc */ 3905 r100_mc_program(rdev); 3906 /* Resume clock */ 3907 r100_clock_startup(rdev); 3908 /* Initialize GART (initialize after TTM so we can allocate 3909 * memory through TTM but finalize after TTM) */ 3910 r100_enable_bm(rdev); 3911 if (rdev->flags & RADEON_IS_PCI) { 3912 r = r100_pci_gart_enable(rdev); 3913 if (r) 3914 return r; 3915 } 3916 3917 /* allocate wb buffer */ 3918 r = radeon_wb_init(rdev); 3919 if (r) 3920 return r; 3921 3922 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 3923 if (r) { 3924 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 3925 return r; 3926 } 3927 3928 /* Enable IRQ */ 3929 if (!rdev->irq.installed) { 3930 r = radeon_irq_kms_init(rdev); 3931 if (r) 3932 return r; 3933 } 3934 3935 r100_irq_set(rdev); 3936 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 3937 /* 1M ring buffer */ 3938 r = r100_cp_init(rdev, 1024 * 1024); 3939 if (r) { 3940 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 3941 return r; 3942 } 3943 3944 r = radeon_ib_pool_init(rdev); 3945 if (r) { 3946 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 3947 return r; 3948 } 3949 3950 return 0; 3951 } 3952 3953 int r100_resume(struct radeon_device *rdev) 3954 { 3955 int r; 3956 3957 /* Make sur GART are not working */ 3958 if (rdev->flags & RADEON_IS_PCI) 3959 r100_pci_gart_disable(rdev); 3960 /* Resume clock before doing reset */ 3961 r100_clock_startup(rdev); 3962 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 3963 if (radeon_asic_reset(rdev)) { 3964 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 3965 RREG32(R_000E40_RBBM_STATUS), 3966 RREG32(R_0007C0_CP_STAT)); 3967 } 3968 /* post */ 3969 radeon_combios_asic_init(rdev->ddev); 3970 /* Resume clock after posting */ 3971 r100_clock_startup(rdev); 3972 /* Initialize surface registers */ 3973 radeon_surface_init(rdev); 3974 3975 rdev->accel_working = true; 3976 r = r100_startup(rdev); 3977 if (r) { 3978 rdev->accel_working = false; 3979 } 3980 return r; 3981 } 3982 3983 int r100_suspend(struct radeon_device *rdev) 3984 { 3985 radeon_pm_suspend(rdev); 3986 r100_cp_disable(rdev); 3987 radeon_wb_disable(rdev); 3988 r100_irq_disable(rdev); 3989 if (rdev->flags & RADEON_IS_PCI) 3990 r100_pci_gart_disable(rdev); 3991 return 0; 3992 } 3993 3994 void r100_fini(struct radeon_device *rdev) 3995 { 3996 radeon_pm_fini(rdev); 3997 r100_cp_fini(rdev); 3998 radeon_wb_fini(rdev); 3999 radeon_ib_pool_fini(rdev); 4000 radeon_gem_fini(rdev); 4001 if (rdev->flags & RADEON_IS_PCI) 4002 r100_pci_gart_fini(rdev); 4003 radeon_agp_fini(rdev); 4004 radeon_irq_kms_fini(rdev); 4005 radeon_fence_driver_fini(rdev); 4006 radeon_bo_fini(rdev); 4007 radeon_atombios_fini(rdev); 4008 kfree(rdev->bios); 4009 rdev->bios = NULL; 4010 } 4011 4012 /* 4013 * Due to how kexec works, it can leave the hw fully initialised when it 4014 * boots the new kernel. However doing our init sequence with the CP and 4015 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup 4016 * do some quick sanity checks and restore sane values to avoid this 4017 * problem. 4018 */ 4019 void r100_restore_sanity(struct radeon_device *rdev) 4020 { 4021 u32 tmp; 4022 4023 tmp = RREG32(RADEON_CP_CSQ_CNTL); 4024 if (tmp) { 4025 WREG32(RADEON_CP_CSQ_CNTL, 0); 4026 } 4027 tmp = RREG32(RADEON_CP_RB_CNTL); 4028 if (tmp) { 4029 WREG32(RADEON_CP_RB_CNTL, 0); 4030 } 4031 tmp = RREG32(RADEON_SCRATCH_UMSK); 4032 if (tmp) { 4033 WREG32(RADEON_SCRATCH_UMSK, 0); 4034 } 4035 } 4036 4037 int r100_init(struct radeon_device *rdev) 4038 { 4039 int r; 4040 4041 /* Register debugfs file specific to this group of asics */ 4042 r100_debugfs_mc_info_init(rdev); 4043 /* Disable VGA */ 4044 r100_vga_render_disable(rdev); 4045 /* Initialize scratch registers */ 4046 radeon_scratch_init(rdev); 4047 /* Initialize surface registers */ 4048 radeon_surface_init(rdev); 4049 /* sanity check some register to avoid hangs like after kexec */ 4050 r100_restore_sanity(rdev); 4051 /* TODO: disable VGA need to use VGA request */ 4052 /* BIOS*/ 4053 if (!radeon_get_bios(rdev)) { 4054 if (ASIC_IS_AVIVO(rdev)) 4055 return -EINVAL; 4056 } 4057 if (rdev->is_atom_bios) { 4058 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 4059 return -EINVAL; 4060 } else { 4061 r = radeon_combios_init(rdev); 4062 if (r) 4063 return r; 4064 } 4065 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 4066 if (radeon_asic_reset(rdev)) { 4067 dev_warn(rdev->dev, 4068 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 4069 RREG32(R_000E40_RBBM_STATUS), 4070 RREG32(R_0007C0_CP_STAT)); 4071 } 4072 /* check if cards are posted or not */ 4073 if (radeon_boot_test_post_card(rdev) == false) 4074 return -EINVAL; 4075 /* Set asic errata */ 4076 r100_errata(rdev); 4077 /* Initialize clocks */ 4078 radeon_get_clock_info(rdev->ddev); 4079 /* initialize AGP */ 4080 if (rdev->flags & RADEON_IS_AGP) { 4081 r = radeon_agp_init(rdev); 4082 if (r) { 4083 radeon_agp_disable(rdev); 4084 } 4085 } 4086 /* initialize VRAM */ 4087 r100_mc_init(rdev); 4088 /* Fence driver */ 4089 radeon_fence_driver_init(rdev); 4090 /* Memory manager */ 4091 r = radeon_bo_init(rdev); 4092 if (r) 4093 return r; 4094 if (rdev->flags & RADEON_IS_PCI) { 4095 r = r100_pci_gart_init(rdev); 4096 if (r) 4097 return r; 4098 } 4099 r100_set_safe_registers(rdev); 4100 4101 /* Initialize power management */ 4102 radeon_pm_init(rdev); 4103 4104 rdev->accel_working = true; 4105 r = r100_startup(rdev); 4106 if (r) { 4107 /* Somethings want wront with the accel init stop accel */ 4108 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 4109 r100_cp_fini(rdev); 4110 radeon_wb_fini(rdev); 4111 radeon_ib_pool_fini(rdev); 4112 radeon_irq_kms_fini(rdev); 4113 if (rdev->flags & RADEON_IS_PCI) 4114 r100_pci_gart_fini(rdev); 4115 rdev->accel_working = false; 4116 } 4117 return 0; 4118 } 4119 4120 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg) 4121 { 4122 unsigned long flags; 4123 uint32_t ret; 4124 4125 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 4126 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 4127 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 4128 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 4129 return ret; 4130 } 4131 4132 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v) 4133 { 4134 unsigned long flags; 4135 4136 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 4137 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 4138 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 4139 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 4140 } 4141 4142 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) 4143 { 4144 if (reg < rdev->rio_mem_size) 4145 return ioread32(rdev->rio_mem + reg); 4146 else { 4147 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); 4148 return ioread32(rdev->rio_mem + RADEON_MM_DATA); 4149 } 4150 } 4151 4152 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) 4153 { 4154 if (reg < rdev->rio_mem_size) 4155 iowrite32(v, rdev->rio_mem + reg); 4156 else { 4157 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); 4158 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); 4159 } 4160 } 4161