1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include <linux/slab.h> 30 #include "drmP.h" 31 #include "drm.h" 32 #include "radeon_drm.h" 33 #include "radeon_reg.h" 34 #include "radeon.h" 35 #include "radeon_asic.h" 36 #include "r100d.h" 37 #include "rs100d.h" 38 #include "rv200d.h" 39 #include "rv250d.h" 40 #include "atom.h" 41 42 #include <linux/firmware.h> 43 #include <linux/platform_device.h> 44 45 #include "r100_reg_safe.h" 46 #include "rn50_reg_safe.h" 47 48 /* Firmware Names */ 49 #define FIRMWARE_R100 "radeon/R100_cp.bin" 50 #define FIRMWARE_R200 "radeon/R200_cp.bin" 51 #define FIRMWARE_R300 "radeon/R300_cp.bin" 52 #define FIRMWARE_R420 "radeon/R420_cp.bin" 53 #define FIRMWARE_RS690 "radeon/RS690_cp.bin" 54 #define FIRMWARE_RS600 "radeon/RS600_cp.bin" 55 #define FIRMWARE_R520 "radeon/R520_cp.bin" 56 57 MODULE_FIRMWARE(FIRMWARE_R100); 58 MODULE_FIRMWARE(FIRMWARE_R200); 59 MODULE_FIRMWARE(FIRMWARE_R300); 60 MODULE_FIRMWARE(FIRMWARE_R420); 61 MODULE_FIRMWARE(FIRMWARE_RS690); 62 MODULE_FIRMWARE(FIRMWARE_RS600); 63 MODULE_FIRMWARE(FIRMWARE_R520); 64 65 #include "r100_track.h" 66 67 /* This files gather functions specifics to: 68 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 69 */ 70 71 void r100_pre_page_flip(struct radeon_device *rdev, int crtc) 72 { 73 /* enable the pflip int */ 74 radeon_irq_kms_pflip_irq_get(rdev, crtc); 75 } 76 77 void r100_post_page_flip(struct radeon_device *rdev, int crtc) 78 { 79 /* disable the pflip int */ 80 radeon_irq_kms_pflip_irq_put(rdev, crtc); 81 } 82 83 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 84 { 85 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 86 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; 87 88 /* Lock the graphics update lock */ 89 /* update the scanout addresses */ 90 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 91 92 /* Wait for update_pending to go high. */ 93 while (!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)); 94 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 95 96 /* Unlock the lock, so double-buffering can take place inside vblank */ 97 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK; 98 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 99 100 /* Return current update_pending status: */ 101 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET; 102 } 103 104 void r100_pm_get_dynpm_state(struct radeon_device *rdev) 105 { 106 int i; 107 rdev->pm.dynpm_can_upclock = true; 108 rdev->pm.dynpm_can_downclock = true; 109 110 switch (rdev->pm.dynpm_planned_action) { 111 case DYNPM_ACTION_MINIMUM: 112 rdev->pm.requested_power_state_index = 0; 113 rdev->pm.dynpm_can_downclock = false; 114 break; 115 case DYNPM_ACTION_DOWNCLOCK: 116 if (rdev->pm.current_power_state_index == 0) { 117 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 118 rdev->pm.dynpm_can_downclock = false; 119 } else { 120 if (rdev->pm.active_crtc_count > 1) { 121 for (i = 0; i < rdev->pm.num_power_states; i++) { 122 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 123 continue; 124 else if (i >= rdev->pm.current_power_state_index) { 125 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 126 break; 127 } else { 128 rdev->pm.requested_power_state_index = i; 129 break; 130 } 131 } 132 } else 133 rdev->pm.requested_power_state_index = 134 rdev->pm.current_power_state_index - 1; 135 } 136 /* don't use the power state if crtcs are active and no display flag is set */ 137 if ((rdev->pm.active_crtc_count > 0) && 138 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & 139 RADEON_PM_MODE_NO_DISPLAY)) { 140 rdev->pm.requested_power_state_index++; 141 } 142 break; 143 case DYNPM_ACTION_UPCLOCK: 144 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 145 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 146 rdev->pm.dynpm_can_upclock = false; 147 } else { 148 if (rdev->pm.active_crtc_count > 1) { 149 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 150 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 151 continue; 152 else if (i <= rdev->pm.current_power_state_index) { 153 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 154 break; 155 } else { 156 rdev->pm.requested_power_state_index = i; 157 break; 158 } 159 } 160 } else 161 rdev->pm.requested_power_state_index = 162 rdev->pm.current_power_state_index + 1; 163 } 164 break; 165 case DYNPM_ACTION_DEFAULT: 166 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 167 rdev->pm.dynpm_can_upclock = false; 168 break; 169 case DYNPM_ACTION_NONE: 170 default: 171 DRM_ERROR("Requested mode for not defined action\n"); 172 return; 173 } 174 /* only one clock mode per power state */ 175 rdev->pm.requested_clock_mode_index = 0; 176 177 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 178 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 179 clock_info[rdev->pm.requested_clock_mode_index].sclk, 180 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 181 clock_info[rdev->pm.requested_clock_mode_index].mclk, 182 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 183 pcie_lanes); 184 } 185 186 void r100_pm_init_profile(struct radeon_device *rdev) 187 { 188 /* default */ 189 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 190 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 191 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 192 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 193 /* low sh */ 194 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 195 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 196 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 197 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 198 /* mid sh */ 199 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 200 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 201 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 202 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 203 /* high sh */ 204 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 205 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 206 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 207 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 208 /* low mh */ 209 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 210 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 211 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 212 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 213 /* mid mh */ 214 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 215 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 216 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 217 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 218 /* high mh */ 219 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 220 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 221 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 222 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 223 } 224 225 void r100_pm_misc(struct radeon_device *rdev) 226 { 227 int requested_index = rdev->pm.requested_power_state_index; 228 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 229 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 230 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl; 231 232 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { 233 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { 234 tmp = RREG32(voltage->gpio.reg); 235 if (voltage->active_high) 236 tmp |= voltage->gpio.mask; 237 else 238 tmp &= ~(voltage->gpio.mask); 239 WREG32(voltage->gpio.reg, tmp); 240 if (voltage->delay) 241 udelay(voltage->delay); 242 } else { 243 tmp = RREG32(voltage->gpio.reg); 244 if (voltage->active_high) 245 tmp &= ~voltage->gpio.mask; 246 else 247 tmp |= voltage->gpio.mask; 248 WREG32(voltage->gpio.reg, tmp); 249 if (voltage->delay) 250 udelay(voltage->delay); 251 } 252 } 253 254 sclk_cntl = RREG32_PLL(SCLK_CNTL); 255 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2); 256 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3); 257 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL); 258 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3); 259 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { 260 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN; 261 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE) 262 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE; 263 else 264 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE; 265 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) 266 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0); 267 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) 268 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2); 269 } else 270 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN; 271 272 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { 273 sclk_more_cntl |= IO_CG_VOLTAGE_DROP; 274 if (voltage->delay) { 275 sclk_more_cntl |= VOLTAGE_DROP_SYNC; 276 switch (voltage->delay) { 277 case 33: 278 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0); 279 break; 280 case 66: 281 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1); 282 break; 283 case 99: 284 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2); 285 break; 286 case 132: 287 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3); 288 break; 289 } 290 } else 291 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC; 292 } else 293 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP; 294 295 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) 296 sclk_cntl &= ~FORCE_HDP; 297 else 298 sclk_cntl |= FORCE_HDP; 299 300 WREG32_PLL(SCLK_CNTL, sclk_cntl); 301 WREG32_PLL(SCLK_CNTL2, sclk_cntl2); 302 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl); 303 304 /* set pcie lanes */ 305 if ((rdev->flags & RADEON_IS_PCIE) && 306 !(rdev->flags & RADEON_IS_IGP) && 307 rdev->asic->set_pcie_lanes && 308 (ps->pcie_lanes != 309 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { 310 radeon_set_pcie_lanes(rdev, 311 ps->pcie_lanes); 312 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes); 313 } 314 } 315 316 void r100_pm_prepare(struct radeon_device *rdev) 317 { 318 struct drm_device *ddev = rdev->ddev; 319 struct drm_crtc *crtc; 320 struct radeon_crtc *radeon_crtc; 321 u32 tmp; 322 323 /* disable any active CRTCs */ 324 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 325 radeon_crtc = to_radeon_crtc(crtc); 326 if (radeon_crtc->enabled) { 327 if (radeon_crtc->crtc_id) { 328 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 329 tmp |= RADEON_CRTC2_DISP_REQ_EN_B; 330 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 331 } else { 332 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 333 tmp |= RADEON_CRTC_DISP_REQ_EN_B; 334 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 335 } 336 } 337 } 338 } 339 340 void r100_pm_finish(struct radeon_device *rdev) 341 { 342 struct drm_device *ddev = rdev->ddev; 343 struct drm_crtc *crtc; 344 struct radeon_crtc *radeon_crtc; 345 u32 tmp; 346 347 /* enable any active CRTCs */ 348 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 349 radeon_crtc = to_radeon_crtc(crtc); 350 if (radeon_crtc->enabled) { 351 if (radeon_crtc->crtc_id) { 352 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 353 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B; 354 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 355 } else { 356 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 357 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B; 358 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 359 } 360 } 361 } 362 } 363 364 bool r100_gui_idle(struct radeon_device *rdev) 365 { 366 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) 367 return false; 368 else 369 return true; 370 } 371 372 /* hpd for digital panel detect/disconnect */ 373 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 374 { 375 bool connected = false; 376 377 switch (hpd) { 378 case RADEON_HPD_1: 379 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) 380 connected = true; 381 break; 382 case RADEON_HPD_2: 383 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) 384 connected = true; 385 break; 386 default: 387 break; 388 } 389 return connected; 390 } 391 392 void r100_hpd_set_polarity(struct radeon_device *rdev, 393 enum radeon_hpd_id hpd) 394 { 395 u32 tmp; 396 bool connected = r100_hpd_sense(rdev, hpd); 397 398 switch (hpd) { 399 case RADEON_HPD_1: 400 tmp = RREG32(RADEON_FP_GEN_CNTL); 401 if (connected) 402 tmp &= ~RADEON_FP_DETECT_INT_POL; 403 else 404 tmp |= RADEON_FP_DETECT_INT_POL; 405 WREG32(RADEON_FP_GEN_CNTL, tmp); 406 break; 407 case RADEON_HPD_2: 408 tmp = RREG32(RADEON_FP2_GEN_CNTL); 409 if (connected) 410 tmp &= ~RADEON_FP2_DETECT_INT_POL; 411 else 412 tmp |= RADEON_FP2_DETECT_INT_POL; 413 WREG32(RADEON_FP2_GEN_CNTL, tmp); 414 break; 415 default: 416 break; 417 } 418 } 419 420 void r100_hpd_init(struct radeon_device *rdev) 421 { 422 struct drm_device *dev = rdev->ddev; 423 struct drm_connector *connector; 424 425 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 426 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 427 switch (radeon_connector->hpd.hpd) { 428 case RADEON_HPD_1: 429 rdev->irq.hpd[0] = true; 430 break; 431 case RADEON_HPD_2: 432 rdev->irq.hpd[1] = true; 433 break; 434 default: 435 break; 436 } 437 } 438 if (rdev->irq.installed) 439 r100_irq_set(rdev); 440 } 441 442 void r100_hpd_fini(struct radeon_device *rdev) 443 { 444 struct drm_device *dev = rdev->ddev; 445 struct drm_connector *connector; 446 447 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 448 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 449 switch (radeon_connector->hpd.hpd) { 450 case RADEON_HPD_1: 451 rdev->irq.hpd[0] = false; 452 break; 453 case RADEON_HPD_2: 454 rdev->irq.hpd[1] = false; 455 break; 456 default: 457 break; 458 } 459 } 460 } 461 462 /* 463 * PCI GART 464 */ 465 void r100_pci_gart_tlb_flush(struct radeon_device *rdev) 466 { 467 /* TODO: can we do somethings here ? */ 468 /* It seems hw only cache one entry so we should discard this 469 * entry otherwise if first GPU GART read hit this entry it 470 * could end up in wrong address. */ 471 } 472 473 int r100_pci_gart_init(struct radeon_device *rdev) 474 { 475 int r; 476 477 if (rdev->gart.table.ram.ptr) { 478 WARN(1, "R100 PCI GART already initialized\n"); 479 return 0; 480 } 481 /* Initialize common gart structure */ 482 r = radeon_gart_init(rdev); 483 if (r) 484 return r; 485 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 486 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; 487 rdev->asic->gart_set_page = &r100_pci_gart_set_page; 488 return radeon_gart_table_ram_alloc(rdev); 489 } 490 491 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 492 void r100_enable_bm(struct radeon_device *rdev) 493 { 494 uint32_t tmp; 495 /* Enable bus mastering */ 496 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 497 WREG32(RADEON_BUS_CNTL, tmp); 498 } 499 500 int r100_pci_gart_enable(struct radeon_device *rdev) 501 { 502 uint32_t tmp; 503 504 radeon_gart_restore(rdev); 505 /* discard memory request outside of configured range */ 506 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 507 WREG32(RADEON_AIC_CNTL, tmp); 508 /* set address range for PCI address translate */ 509 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); 510 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); 511 /* set PCI GART page-table base address */ 512 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); 513 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; 514 WREG32(RADEON_AIC_CNTL, tmp); 515 r100_pci_gart_tlb_flush(rdev); 516 rdev->gart.ready = true; 517 return 0; 518 } 519 520 void r100_pci_gart_disable(struct radeon_device *rdev) 521 { 522 uint32_t tmp; 523 524 /* discard memory request outside of configured range */ 525 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 526 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); 527 WREG32(RADEON_AIC_LO_ADDR, 0); 528 WREG32(RADEON_AIC_HI_ADDR, 0); 529 } 530 531 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 532 { 533 if (i < 0 || i > rdev->gart.num_gpu_pages) { 534 return -EINVAL; 535 } 536 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr)); 537 return 0; 538 } 539 540 void r100_pci_gart_fini(struct radeon_device *rdev) 541 { 542 radeon_gart_fini(rdev); 543 r100_pci_gart_disable(rdev); 544 radeon_gart_table_ram_free(rdev); 545 } 546 547 int r100_irq_set(struct radeon_device *rdev) 548 { 549 uint32_t tmp = 0; 550 551 if (!rdev->irq.installed) { 552 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 553 WREG32(R_000040_GEN_INT_CNTL, 0); 554 return -EINVAL; 555 } 556 if (rdev->irq.sw_int) { 557 tmp |= RADEON_SW_INT_ENABLE; 558 } 559 if (rdev->irq.gui_idle) { 560 tmp |= RADEON_GUI_IDLE_MASK; 561 } 562 if (rdev->irq.crtc_vblank_int[0] || 563 rdev->irq.pflip[0]) { 564 tmp |= RADEON_CRTC_VBLANK_MASK; 565 } 566 if (rdev->irq.crtc_vblank_int[1] || 567 rdev->irq.pflip[1]) { 568 tmp |= RADEON_CRTC2_VBLANK_MASK; 569 } 570 if (rdev->irq.hpd[0]) { 571 tmp |= RADEON_FP_DETECT_MASK; 572 } 573 if (rdev->irq.hpd[1]) { 574 tmp |= RADEON_FP2_DETECT_MASK; 575 } 576 WREG32(RADEON_GEN_INT_CNTL, tmp); 577 return 0; 578 } 579 580 void r100_irq_disable(struct radeon_device *rdev) 581 { 582 u32 tmp; 583 584 WREG32(R_000040_GEN_INT_CNTL, 0); 585 /* Wait and acknowledge irq */ 586 mdelay(1); 587 tmp = RREG32(R_000044_GEN_INT_STATUS); 588 WREG32(R_000044_GEN_INT_STATUS, tmp); 589 } 590 591 static inline uint32_t r100_irq_ack(struct radeon_device *rdev) 592 { 593 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); 594 uint32_t irq_mask = RADEON_SW_INT_TEST | 595 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | 596 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; 597 598 /* the interrupt works, but the status bit is permanently asserted */ 599 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) { 600 if (!rdev->irq.gui_idle_acked) 601 irq_mask |= RADEON_GUI_IDLE_STAT; 602 } 603 604 if (irqs) { 605 WREG32(RADEON_GEN_INT_STATUS, irqs); 606 } 607 return irqs & irq_mask; 608 } 609 610 int r100_irq_process(struct radeon_device *rdev) 611 { 612 uint32_t status, msi_rearm; 613 bool queue_hotplug = false; 614 615 /* reset gui idle ack. the status bit is broken */ 616 rdev->irq.gui_idle_acked = false; 617 618 status = r100_irq_ack(rdev); 619 if (!status) { 620 return IRQ_NONE; 621 } 622 if (rdev->shutdown) { 623 return IRQ_NONE; 624 } 625 while (status) { 626 /* SW interrupt */ 627 if (status & RADEON_SW_INT_TEST) { 628 radeon_fence_process(rdev); 629 } 630 /* gui idle interrupt */ 631 if (status & RADEON_GUI_IDLE_STAT) { 632 rdev->irq.gui_idle_acked = true; 633 rdev->pm.gui_idle = true; 634 wake_up(&rdev->irq.idle_queue); 635 } 636 /* Vertical blank interrupts */ 637 if (status & RADEON_CRTC_VBLANK_STAT) { 638 if (rdev->irq.crtc_vblank_int[0]) { 639 drm_handle_vblank(rdev->ddev, 0); 640 rdev->pm.vblank_sync = true; 641 wake_up(&rdev->irq.vblank_queue); 642 } 643 if (rdev->irq.pflip[0]) 644 radeon_crtc_handle_flip(rdev, 0); 645 } 646 if (status & RADEON_CRTC2_VBLANK_STAT) { 647 if (rdev->irq.crtc_vblank_int[1]) { 648 drm_handle_vblank(rdev->ddev, 1); 649 rdev->pm.vblank_sync = true; 650 wake_up(&rdev->irq.vblank_queue); 651 } 652 if (rdev->irq.pflip[1]) 653 radeon_crtc_handle_flip(rdev, 1); 654 } 655 if (status & RADEON_FP_DETECT_STAT) { 656 queue_hotplug = true; 657 DRM_DEBUG("HPD1\n"); 658 } 659 if (status & RADEON_FP2_DETECT_STAT) { 660 queue_hotplug = true; 661 DRM_DEBUG("HPD2\n"); 662 } 663 status = r100_irq_ack(rdev); 664 } 665 /* reset gui idle ack. the status bit is broken */ 666 rdev->irq.gui_idle_acked = false; 667 if (queue_hotplug) 668 schedule_work(&rdev->hotplug_work); 669 if (rdev->msi_enabled) { 670 switch (rdev->family) { 671 case CHIP_RS400: 672 case CHIP_RS480: 673 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; 674 WREG32(RADEON_AIC_CNTL, msi_rearm); 675 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); 676 break; 677 default: 678 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN; 679 WREG32(RADEON_MSI_REARM_EN, msi_rearm); 680 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN); 681 break; 682 } 683 } 684 return IRQ_HANDLED; 685 } 686 687 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) 688 { 689 if (crtc == 0) 690 return RREG32(RADEON_CRTC_CRNT_FRAME); 691 else 692 return RREG32(RADEON_CRTC2_CRNT_FRAME); 693 } 694 695 /* Who ever call radeon_fence_emit should call ring_lock and ask 696 * for enough space (today caller are ib schedule and buffer move) */ 697 void r100_fence_ring_emit(struct radeon_device *rdev, 698 struct radeon_fence *fence) 699 { 700 /* We have to make sure that caches are flushed before 701 * CPU might read something from VRAM. */ 702 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); 703 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL); 704 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); 705 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL); 706 /* Wait until IDLE & CLEAN */ 707 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 708 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 709 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 710 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl | 711 RADEON_HDP_READ_BUFFER_INVALIDATE); 712 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 713 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl); 714 /* Emit fence sequence & fire IRQ */ 715 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); 716 radeon_ring_write(rdev, fence->seq); 717 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); 718 radeon_ring_write(rdev, RADEON_SW_INT_FIRE); 719 } 720 721 int r100_copy_blit(struct radeon_device *rdev, 722 uint64_t src_offset, 723 uint64_t dst_offset, 724 unsigned num_pages, 725 struct radeon_fence *fence) 726 { 727 uint32_t cur_pages; 728 uint32_t stride_bytes = PAGE_SIZE; 729 uint32_t pitch; 730 uint32_t stride_pixels; 731 unsigned ndw; 732 int num_loops; 733 int r = 0; 734 735 /* radeon limited to 16k stride */ 736 stride_bytes &= 0x3fff; 737 /* radeon pitch is /64 */ 738 pitch = stride_bytes / 64; 739 stride_pixels = stride_bytes / 4; 740 num_loops = DIV_ROUND_UP(num_pages, 8191); 741 742 /* Ask for enough room for blit + flush + fence */ 743 ndw = 64 + (10 * num_loops); 744 r = radeon_ring_lock(rdev, ndw); 745 if (r) { 746 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); 747 return -EINVAL; 748 } 749 while (num_pages > 0) { 750 cur_pages = num_pages; 751 if (cur_pages > 8191) { 752 cur_pages = 8191; 753 } 754 num_pages -= cur_pages; 755 756 /* pages are in Y direction - height 757 page width in X direction - width */ 758 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8)); 759 radeon_ring_write(rdev, 760 RADEON_GMC_SRC_PITCH_OFFSET_CNTL | 761 RADEON_GMC_DST_PITCH_OFFSET_CNTL | 762 RADEON_GMC_SRC_CLIPPING | 763 RADEON_GMC_DST_CLIPPING | 764 RADEON_GMC_BRUSH_NONE | 765 (RADEON_COLOR_FORMAT_ARGB8888 << 8) | 766 RADEON_GMC_SRC_DATATYPE_COLOR | 767 RADEON_ROP3_S | 768 RADEON_DP_SRC_SOURCE_MEMORY | 769 RADEON_GMC_CLR_CMP_CNTL_DIS | 770 RADEON_GMC_WR_MSK_DIS); 771 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10)); 772 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10)); 773 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16)); 774 radeon_ring_write(rdev, 0); 775 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16)); 776 radeon_ring_write(rdev, num_pages); 777 radeon_ring_write(rdev, num_pages); 778 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16)); 779 } 780 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); 781 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL); 782 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 783 radeon_ring_write(rdev, 784 RADEON_WAIT_2D_IDLECLEAN | 785 RADEON_WAIT_HOST_IDLECLEAN | 786 RADEON_WAIT_DMA_GUI_IDLE); 787 if (fence) { 788 r = radeon_fence_emit(rdev, fence); 789 } 790 radeon_ring_unlock_commit(rdev); 791 return r; 792 } 793 794 static int r100_cp_wait_for_idle(struct radeon_device *rdev) 795 { 796 unsigned i; 797 u32 tmp; 798 799 for (i = 0; i < rdev->usec_timeout; i++) { 800 tmp = RREG32(R_000E40_RBBM_STATUS); 801 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { 802 return 0; 803 } 804 udelay(1); 805 } 806 return -1; 807 } 808 809 void r100_ring_start(struct radeon_device *rdev) 810 { 811 int r; 812 813 r = radeon_ring_lock(rdev, 2); 814 if (r) { 815 return; 816 } 817 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); 818 radeon_ring_write(rdev, 819 RADEON_ISYNC_ANY2D_IDLE3D | 820 RADEON_ISYNC_ANY3D_IDLE2D | 821 RADEON_ISYNC_WAIT_IDLEGUI | 822 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 823 radeon_ring_unlock_commit(rdev); 824 } 825 826 827 /* Load the microcode for the CP */ 828 static int r100_cp_init_microcode(struct radeon_device *rdev) 829 { 830 struct platform_device *pdev; 831 const char *fw_name = NULL; 832 int err; 833 834 DRM_DEBUG_KMS("\n"); 835 836 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); 837 err = IS_ERR(pdev); 838 if (err) { 839 printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); 840 return -EINVAL; 841 } 842 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || 843 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || 844 (rdev->family == CHIP_RS200)) { 845 DRM_INFO("Loading R100 Microcode\n"); 846 fw_name = FIRMWARE_R100; 847 } else if ((rdev->family == CHIP_R200) || 848 (rdev->family == CHIP_RV250) || 849 (rdev->family == CHIP_RV280) || 850 (rdev->family == CHIP_RS300)) { 851 DRM_INFO("Loading R200 Microcode\n"); 852 fw_name = FIRMWARE_R200; 853 } else if ((rdev->family == CHIP_R300) || 854 (rdev->family == CHIP_R350) || 855 (rdev->family == CHIP_RV350) || 856 (rdev->family == CHIP_RV380) || 857 (rdev->family == CHIP_RS400) || 858 (rdev->family == CHIP_RS480)) { 859 DRM_INFO("Loading R300 Microcode\n"); 860 fw_name = FIRMWARE_R300; 861 } else if ((rdev->family == CHIP_R420) || 862 (rdev->family == CHIP_R423) || 863 (rdev->family == CHIP_RV410)) { 864 DRM_INFO("Loading R400 Microcode\n"); 865 fw_name = FIRMWARE_R420; 866 } else if ((rdev->family == CHIP_RS690) || 867 (rdev->family == CHIP_RS740)) { 868 DRM_INFO("Loading RS690/RS740 Microcode\n"); 869 fw_name = FIRMWARE_RS690; 870 } else if (rdev->family == CHIP_RS600) { 871 DRM_INFO("Loading RS600 Microcode\n"); 872 fw_name = FIRMWARE_RS600; 873 } else if ((rdev->family == CHIP_RV515) || 874 (rdev->family == CHIP_R520) || 875 (rdev->family == CHIP_RV530) || 876 (rdev->family == CHIP_R580) || 877 (rdev->family == CHIP_RV560) || 878 (rdev->family == CHIP_RV570)) { 879 DRM_INFO("Loading R500 Microcode\n"); 880 fw_name = FIRMWARE_R520; 881 } 882 883 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); 884 platform_device_unregister(pdev); 885 if (err) { 886 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", 887 fw_name); 888 } else if (rdev->me_fw->size % 8) { 889 printk(KERN_ERR 890 "radeon_cp: Bogus length %zu in firmware \"%s\"\n", 891 rdev->me_fw->size, fw_name); 892 err = -EINVAL; 893 release_firmware(rdev->me_fw); 894 rdev->me_fw = NULL; 895 } 896 return err; 897 } 898 899 static void r100_cp_load_microcode(struct radeon_device *rdev) 900 { 901 const __be32 *fw_data; 902 int i, size; 903 904 if (r100_gui_wait_for_idle(rdev)) { 905 printk(KERN_WARNING "Failed to wait GUI idle while " 906 "programming pipes. Bad things might happen.\n"); 907 } 908 909 if (rdev->me_fw) { 910 size = rdev->me_fw->size / 4; 911 fw_data = (const __be32 *)&rdev->me_fw->data[0]; 912 WREG32(RADEON_CP_ME_RAM_ADDR, 0); 913 for (i = 0; i < size; i += 2) { 914 WREG32(RADEON_CP_ME_RAM_DATAH, 915 be32_to_cpup(&fw_data[i])); 916 WREG32(RADEON_CP_ME_RAM_DATAL, 917 be32_to_cpup(&fw_data[i + 1])); 918 } 919 } 920 } 921 922 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) 923 { 924 unsigned rb_bufsz; 925 unsigned rb_blksz; 926 unsigned max_fetch; 927 unsigned pre_write_timer; 928 unsigned pre_write_limit; 929 unsigned indirect2_start; 930 unsigned indirect1_start; 931 uint32_t tmp; 932 int r; 933 934 if (r100_debugfs_cp_init(rdev)) { 935 DRM_ERROR("Failed to register debugfs file for CP !\n"); 936 } 937 if (!rdev->me_fw) { 938 r = r100_cp_init_microcode(rdev); 939 if (r) { 940 DRM_ERROR("Failed to load firmware!\n"); 941 return r; 942 } 943 } 944 945 /* Align ring size */ 946 rb_bufsz = drm_order(ring_size / 8); 947 ring_size = (1 << (rb_bufsz + 1)) * 4; 948 r100_cp_load_microcode(rdev); 949 r = radeon_ring_init(rdev, ring_size); 950 if (r) { 951 return r; 952 } 953 /* Each time the cp read 1024 bytes (16 dword/quadword) update 954 * the rptr copy in system ram */ 955 rb_blksz = 9; 956 /* cp will read 128bytes at a time (4 dwords) */ 957 max_fetch = 1; 958 rdev->cp.align_mask = 16 - 1; 959 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ 960 pre_write_timer = 64; 961 /* Force CP_RB_WPTR write if written more than one time before the 962 * delay expire 963 */ 964 pre_write_limit = 0; 965 /* Setup the cp cache like this (cache size is 96 dwords) : 966 * RING 0 to 15 967 * INDIRECT1 16 to 79 968 * INDIRECT2 80 to 95 969 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 970 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) 971 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 972 * Idea being that most of the gpu cmd will be through indirect1 buffer 973 * so it gets the bigger cache. 974 */ 975 indirect2_start = 80; 976 indirect1_start = 16; 977 /* cp setup */ 978 WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); 979 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | 980 REG_SET(RADEON_RB_BLKSZ, rb_blksz) | 981 REG_SET(RADEON_MAX_FETCH, max_fetch)); 982 #ifdef __BIG_ENDIAN 983 tmp |= RADEON_BUF_SWAP_32BIT; 984 #endif 985 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); 986 987 /* Set ring address */ 988 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr); 989 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr); 990 /* Force read & write ptr to 0 */ 991 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); 992 WREG32(RADEON_CP_RB_RPTR_WR, 0); 993 WREG32(RADEON_CP_RB_WPTR, 0); 994 995 /* set the wb address whether it's enabled or not */ 996 WREG32(R_00070C_CP_RB_RPTR_ADDR, 997 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); 998 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); 999 1000 if (rdev->wb.enabled) 1001 WREG32(R_000770_SCRATCH_UMSK, 0xff); 1002 else { 1003 tmp |= RADEON_RB_NO_UPDATE; 1004 WREG32(R_000770_SCRATCH_UMSK, 0); 1005 } 1006 1007 WREG32(RADEON_CP_RB_CNTL, tmp); 1008 udelay(10); 1009 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); 1010 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR); 1011 /* protect against crazy HW on resume */ 1012 rdev->cp.wptr &= rdev->cp.ptr_mask; 1013 /* Set cp mode to bus mastering & enable cp*/ 1014 WREG32(RADEON_CP_CSQ_MODE, 1015 REG_SET(RADEON_INDIRECT2_START, indirect2_start) | 1016 REG_SET(RADEON_INDIRECT1_START, indirect1_start)); 1017 WREG32(RADEON_CP_RB_WPTR_DELAY, 0); 1018 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); 1019 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); 1020 radeon_ring_start(rdev); 1021 r = radeon_ring_test(rdev); 1022 if (r) { 1023 DRM_ERROR("radeon: cp isn't working (%d).\n", r); 1024 return r; 1025 } 1026 rdev->cp.ready = true; 1027 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 1028 return 0; 1029 } 1030 1031 void r100_cp_fini(struct radeon_device *rdev) 1032 { 1033 if (r100_cp_wait_for_idle(rdev)) { 1034 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); 1035 } 1036 /* Disable ring */ 1037 r100_cp_disable(rdev); 1038 radeon_ring_fini(rdev); 1039 DRM_INFO("radeon: cp finalized\n"); 1040 } 1041 1042 void r100_cp_disable(struct radeon_device *rdev) 1043 { 1044 /* Disable ring */ 1045 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1046 rdev->cp.ready = false; 1047 WREG32(RADEON_CP_CSQ_MODE, 0); 1048 WREG32(RADEON_CP_CSQ_CNTL, 0); 1049 WREG32(R_000770_SCRATCH_UMSK, 0); 1050 if (r100_gui_wait_for_idle(rdev)) { 1051 printk(KERN_WARNING "Failed to wait GUI idle while " 1052 "programming pipes. Bad things might happen.\n"); 1053 } 1054 } 1055 1056 void r100_cp_commit(struct radeon_device *rdev) 1057 { 1058 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr); 1059 (void)RREG32(RADEON_CP_RB_WPTR); 1060 } 1061 1062 1063 /* 1064 * CS functions 1065 */ 1066 int r100_cs_parse_packet0(struct radeon_cs_parser *p, 1067 struct radeon_cs_packet *pkt, 1068 const unsigned *auth, unsigned n, 1069 radeon_packet0_check_t check) 1070 { 1071 unsigned reg; 1072 unsigned i, j, m; 1073 unsigned idx; 1074 int r; 1075 1076 idx = pkt->idx + 1; 1077 reg = pkt->reg; 1078 /* Check that register fall into register range 1079 * determined by the number of entry (n) in the 1080 * safe register bitmap. 1081 */ 1082 if (pkt->one_reg_wr) { 1083 if ((reg >> 7) > n) { 1084 return -EINVAL; 1085 } 1086 } else { 1087 if (((reg + (pkt->count << 2)) >> 7) > n) { 1088 return -EINVAL; 1089 } 1090 } 1091 for (i = 0; i <= pkt->count; i++, idx++) { 1092 j = (reg >> 7); 1093 m = 1 << ((reg >> 2) & 31); 1094 if (auth[j] & m) { 1095 r = check(p, pkt, idx, reg); 1096 if (r) { 1097 return r; 1098 } 1099 } 1100 if (pkt->one_reg_wr) { 1101 if (!(auth[j] & m)) { 1102 break; 1103 } 1104 } else { 1105 reg += 4; 1106 } 1107 } 1108 return 0; 1109 } 1110 1111 void r100_cs_dump_packet(struct radeon_cs_parser *p, 1112 struct radeon_cs_packet *pkt) 1113 { 1114 volatile uint32_t *ib; 1115 unsigned i; 1116 unsigned idx; 1117 1118 ib = p->ib->ptr; 1119 idx = pkt->idx; 1120 for (i = 0; i <= (pkt->count + 1); i++, idx++) { 1121 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); 1122 } 1123 } 1124 1125 /** 1126 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet 1127 * @parser: parser structure holding parsing context. 1128 * @pkt: where to store packet informations 1129 * 1130 * Assume that chunk_ib_index is properly set. Will return -EINVAL 1131 * if packet is bigger than remaining ib size. or if packets is unknown. 1132 **/ 1133 int r100_cs_packet_parse(struct radeon_cs_parser *p, 1134 struct radeon_cs_packet *pkt, 1135 unsigned idx) 1136 { 1137 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; 1138 uint32_t header; 1139 1140 if (idx >= ib_chunk->length_dw) { 1141 DRM_ERROR("Can not parse packet at %d after CS end %d !\n", 1142 idx, ib_chunk->length_dw); 1143 return -EINVAL; 1144 } 1145 header = radeon_get_ib_value(p, idx); 1146 pkt->idx = idx; 1147 pkt->type = CP_PACKET_GET_TYPE(header); 1148 pkt->count = CP_PACKET_GET_COUNT(header); 1149 switch (pkt->type) { 1150 case PACKET_TYPE0: 1151 pkt->reg = CP_PACKET0_GET_REG(header); 1152 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header); 1153 break; 1154 case PACKET_TYPE3: 1155 pkt->opcode = CP_PACKET3_GET_OPCODE(header); 1156 break; 1157 case PACKET_TYPE2: 1158 pkt->count = -1; 1159 break; 1160 default: 1161 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); 1162 return -EINVAL; 1163 } 1164 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { 1165 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", 1166 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); 1167 return -EINVAL; 1168 } 1169 return 0; 1170 } 1171 1172 /** 1173 * r100_cs_packet_next_vline() - parse userspace VLINE packet 1174 * @parser: parser structure holding parsing context. 1175 * 1176 * Userspace sends a special sequence for VLINE waits. 1177 * PACKET0 - VLINE_START_END + value 1178 * PACKET0 - WAIT_UNTIL +_value 1179 * RELOC (P3) - crtc_id in reloc. 1180 * 1181 * This function parses this and relocates the VLINE START END 1182 * and WAIT UNTIL packets to the correct crtc. 1183 * It also detects a switched off crtc and nulls out the 1184 * wait in that case. 1185 */ 1186 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) 1187 { 1188 struct drm_mode_object *obj; 1189 struct drm_crtc *crtc; 1190 struct radeon_crtc *radeon_crtc; 1191 struct radeon_cs_packet p3reloc, waitreloc; 1192 int crtc_id; 1193 int r; 1194 uint32_t header, h_idx, reg; 1195 volatile uint32_t *ib; 1196 1197 ib = p->ib->ptr; 1198 1199 /* parse the wait until */ 1200 r = r100_cs_packet_parse(p, &waitreloc, p->idx); 1201 if (r) 1202 return r; 1203 1204 /* check its a wait until and only 1 count */ 1205 if (waitreloc.reg != RADEON_WAIT_UNTIL || 1206 waitreloc.count != 0) { 1207 DRM_ERROR("vline wait had illegal wait until segment\n"); 1208 r = -EINVAL; 1209 return r; 1210 } 1211 1212 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { 1213 DRM_ERROR("vline wait had illegal wait until\n"); 1214 r = -EINVAL; 1215 return r; 1216 } 1217 1218 /* jump over the NOP */ 1219 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); 1220 if (r) 1221 return r; 1222 1223 h_idx = p->idx - 2; 1224 p->idx += waitreloc.count + 2; 1225 p->idx += p3reloc.count + 2; 1226 1227 header = radeon_get_ib_value(p, h_idx); 1228 crtc_id = radeon_get_ib_value(p, h_idx + 5); 1229 reg = CP_PACKET0_GET_REG(header); 1230 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); 1231 if (!obj) { 1232 DRM_ERROR("cannot find crtc %d\n", crtc_id); 1233 r = -EINVAL; 1234 goto out; 1235 } 1236 crtc = obj_to_crtc(obj); 1237 radeon_crtc = to_radeon_crtc(crtc); 1238 crtc_id = radeon_crtc->crtc_id; 1239 1240 if (!crtc->enabled) { 1241 /* if the CRTC isn't enabled - we need to nop out the wait until */ 1242 ib[h_idx + 2] = PACKET2(0); 1243 ib[h_idx + 3] = PACKET2(0); 1244 } else if (crtc_id == 1) { 1245 switch (reg) { 1246 case AVIVO_D1MODE_VLINE_START_END: 1247 header &= ~R300_CP_PACKET0_REG_MASK; 1248 header |= AVIVO_D2MODE_VLINE_START_END >> 2; 1249 break; 1250 case RADEON_CRTC_GUI_TRIG_VLINE: 1251 header &= ~R300_CP_PACKET0_REG_MASK; 1252 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; 1253 break; 1254 default: 1255 DRM_ERROR("unknown crtc reloc\n"); 1256 r = -EINVAL; 1257 goto out; 1258 } 1259 ib[h_idx] = header; 1260 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; 1261 } 1262 out: 1263 return r; 1264 } 1265 1266 /** 1267 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3 1268 * @parser: parser structure holding parsing context. 1269 * @data: pointer to relocation data 1270 * @offset_start: starting offset 1271 * @offset_mask: offset mask (to align start offset on) 1272 * @reloc: reloc informations 1273 * 1274 * Check next packet is relocation packet3, do bo validation and compute 1275 * GPU offset using the provided start. 1276 **/ 1277 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, 1278 struct radeon_cs_reloc **cs_reloc) 1279 { 1280 struct radeon_cs_chunk *relocs_chunk; 1281 struct radeon_cs_packet p3reloc; 1282 unsigned idx; 1283 int r; 1284 1285 if (p->chunk_relocs_idx == -1) { 1286 DRM_ERROR("No relocation chunk !\n"); 1287 return -EINVAL; 1288 } 1289 *cs_reloc = NULL; 1290 relocs_chunk = &p->chunks[p->chunk_relocs_idx]; 1291 r = r100_cs_packet_parse(p, &p3reloc, p->idx); 1292 if (r) { 1293 return r; 1294 } 1295 p->idx += p3reloc.count + 2; 1296 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { 1297 DRM_ERROR("No packet3 for relocation for packet at %d.\n", 1298 p3reloc.idx); 1299 r100_cs_dump_packet(p, &p3reloc); 1300 return -EINVAL; 1301 } 1302 idx = radeon_get_ib_value(p, p3reloc.idx + 1); 1303 if (idx >= relocs_chunk->length_dw) { 1304 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 1305 idx, relocs_chunk->length_dw); 1306 r100_cs_dump_packet(p, &p3reloc); 1307 return -EINVAL; 1308 } 1309 /* FIXME: we assume reloc size is 4 dwords */ 1310 *cs_reloc = p->relocs_ptr[(idx / 4)]; 1311 return 0; 1312 } 1313 1314 static int r100_get_vtx_size(uint32_t vtx_fmt) 1315 { 1316 int vtx_size; 1317 vtx_size = 2; 1318 /* ordered according to bits in spec */ 1319 if (vtx_fmt & RADEON_SE_VTX_FMT_W0) 1320 vtx_size++; 1321 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) 1322 vtx_size += 3; 1323 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) 1324 vtx_size++; 1325 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) 1326 vtx_size++; 1327 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) 1328 vtx_size += 3; 1329 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) 1330 vtx_size++; 1331 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) 1332 vtx_size++; 1333 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) 1334 vtx_size += 2; 1335 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) 1336 vtx_size += 2; 1337 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) 1338 vtx_size++; 1339 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) 1340 vtx_size += 2; 1341 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) 1342 vtx_size++; 1343 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) 1344 vtx_size += 2; 1345 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) 1346 vtx_size++; 1347 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) 1348 vtx_size++; 1349 /* blend weight */ 1350 if (vtx_fmt & (0x7 << 15)) 1351 vtx_size += (vtx_fmt >> 15) & 0x7; 1352 if (vtx_fmt & RADEON_SE_VTX_FMT_N0) 1353 vtx_size += 3; 1354 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) 1355 vtx_size += 2; 1356 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) 1357 vtx_size++; 1358 if (vtx_fmt & RADEON_SE_VTX_FMT_W1) 1359 vtx_size++; 1360 if (vtx_fmt & RADEON_SE_VTX_FMT_N1) 1361 vtx_size++; 1362 if (vtx_fmt & RADEON_SE_VTX_FMT_Z) 1363 vtx_size++; 1364 return vtx_size; 1365 } 1366 1367 static int r100_packet0_check(struct radeon_cs_parser *p, 1368 struct radeon_cs_packet *pkt, 1369 unsigned idx, unsigned reg) 1370 { 1371 struct radeon_cs_reloc *reloc; 1372 struct r100_cs_track *track; 1373 volatile uint32_t *ib; 1374 uint32_t tmp; 1375 int r; 1376 int i, face; 1377 u32 tile_flags = 0; 1378 u32 idx_value; 1379 1380 ib = p->ib->ptr; 1381 track = (struct r100_cs_track *)p->track; 1382 1383 idx_value = radeon_get_ib_value(p, idx); 1384 1385 switch (reg) { 1386 case RADEON_CRTC_GUI_TRIG_VLINE: 1387 r = r100_cs_packet_parse_vline(p); 1388 if (r) { 1389 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1390 idx, reg); 1391 r100_cs_dump_packet(p, pkt); 1392 return r; 1393 } 1394 break; 1395 /* FIXME: only allow PACKET3 blit? easier to check for out of 1396 * range access */ 1397 case RADEON_DST_PITCH_OFFSET: 1398 case RADEON_SRC_PITCH_OFFSET: 1399 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 1400 if (r) 1401 return r; 1402 break; 1403 case RADEON_RB3D_DEPTHOFFSET: 1404 r = r100_cs_packet_next_reloc(p, &reloc); 1405 if (r) { 1406 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1407 idx, reg); 1408 r100_cs_dump_packet(p, pkt); 1409 return r; 1410 } 1411 track->zb.robj = reloc->robj; 1412 track->zb.offset = idx_value; 1413 track->zb_dirty = true; 1414 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1415 break; 1416 case RADEON_RB3D_COLOROFFSET: 1417 r = r100_cs_packet_next_reloc(p, &reloc); 1418 if (r) { 1419 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1420 idx, reg); 1421 r100_cs_dump_packet(p, pkt); 1422 return r; 1423 } 1424 track->cb[0].robj = reloc->robj; 1425 track->cb[0].offset = idx_value; 1426 track->cb_dirty = true; 1427 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1428 break; 1429 case RADEON_PP_TXOFFSET_0: 1430 case RADEON_PP_TXOFFSET_1: 1431 case RADEON_PP_TXOFFSET_2: 1432 i = (reg - RADEON_PP_TXOFFSET_0) / 24; 1433 r = r100_cs_packet_next_reloc(p, &reloc); 1434 if (r) { 1435 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1436 idx, reg); 1437 r100_cs_dump_packet(p, pkt); 1438 return r; 1439 } 1440 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1441 track->textures[i].robj = reloc->robj; 1442 track->tex_dirty = true; 1443 break; 1444 case RADEON_PP_CUBIC_OFFSET_T0_0: 1445 case RADEON_PP_CUBIC_OFFSET_T0_1: 1446 case RADEON_PP_CUBIC_OFFSET_T0_2: 1447 case RADEON_PP_CUBIC_OFFSET_T0_3: 1448 case RADEON_PP_CUBIC_OFFSET_T0_4: 1449 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; 1450 r = r100_cs_packet_next_reloc(p, &reloc); 1451 if (r) { 1452 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1453 idx, reg); 1454 r100_cs_dump_packet(p, pkt); 1455 return r; 1456 } 1457 track->textures[0].cube_info[i].offset = idx_value; 1458 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1459 track->textures[0].cube_info[i].robj = reloc->robj; 1460 track->tex_dirty = true; 1461 break; 1462 case RADEON_PP_CUBIC_OFFSET_T1_0: 1463 case RADEON_PP_CUBIC_OFFSET_T1_1: 1464 case RADEON_PP_CUBIC_OFFSET_T1_2: 1465 case RADEON_PP_CUBIC_OFFSET_T1_3: 1466 case RADEON_PP_CUBIC_OFFSET_T1_4: 1467 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; 1468 r = r100_cs_packet_next_reloc(p, &reloc); 1469 if (r) { 1470 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1471 idx, reg); 1472 r100_cs_dump_packet(p, pkt); 1473 return r; 1474 } 1475 track->textures[1].cube_info[i].offset = idx_value; 1476 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1477 track->textures[1].cube_info[i].robj = reloc->robj; 1478 track->tex_dirty = true; 1479 break; 1480 case RADEON_PP_CUBIC_OFFSET_T2_0: 1481 case RADEON_PP_CUBIC_OFFSET_T2_1: 1482 case RADEON_PP_CUBIC_OFFSET_T2_2: 1483 case RADEON_PP_CUBIC_OFFSET_T2_3: 1484 case RADEON_PP_CUBIC_OFFSET_T2_4: 1485 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; 1486 r = r100_cs_packet_next_reloc(p, &reloc); 1487 if (r) { 1488 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1489 idx, reg); 1490 r100_cs_dump_packet(p, pkt); 1491 return r; 1492 } 1493 track->textures[2].cube_info[i].offset = idx_value; 1494 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1495 track->textures[2].cube_info[i].robj = reloc->robj; 1496 track->tex_dirty = true; 1497 break; 1498 case RADEON_RE_WIDTH_HEIGHT: 1499 track->maxy = ((idx_value >> 16) & 0x7FF); 1500 track->cb_dirty = true; 1501 track->zb_dirty = true; 1502 break; 1503 case RADEON_RB3D_COLORPITCH: 1504 r = r100_cs_packet_next_reloc(p, &reloc); 1505 if (r) { 1506 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1507 idx, reg); 1508 r100_cs_dump_packet(p, pkt); 1509 return r; 1510 } 1511 1512 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1513 tile_flags |= RADEON_COLOR_TILE_ENABLE; 1514 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 1515 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; 1516 1517 tmp = idx_value & ~(0x7 << 16); 1518 tmp |= tile_flags; 1519 ib[idx] = tmp; 1520 1521 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; 1522 track->cb_dirty = true; 1523 break; 1524 case RADEON_RB3D_DEPTHPITCH: 1525 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; 1526 track->zb_dirty = true; 1527 break; 1528 case RADEON_RB3D_CNTL: 1529 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { 1530 case 7: 1531 case 8: 1532 case 9: 1533 case 11: 1534 case 12: 1535 track->cb[0].cpp = 1; 1536 break; 1537 case 3: 1538 case 4: 1539 case 15: 1540 track->cb[0].cpp = 2; 1541 break; 1542 case 6: 1543 track->cb[0].cpp = 4; 1544 break; 1545 default: 1546 DRM_ERROR("Invalid color buffer format (%d) !\n", 1547 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); 1548 return -EINVAL; 1549 } 1550 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); 1551 track->cb_dirty = true; 1552 track->zb_dirty = true; 1553 break; 1554 case RADEON_RB3D_ZSTENCILCNTL: 1555 switch (idx_value & 0xf) { 1556 case 0: 1557 track->zb.cpp = 2; 1558 break; 1559 case 2: 1560 case 3: 1561 case 4: 1562 case 5: 1563 case 9: 1564 case 11: 1565 track->zb.cpp = 4; 1566 break; 1567 default: 1568 break; 1569 } 1570 track->zb_dirty = true; 1571 break; 1572 case RADEON_RB3D_ZPASS_ADDR: 1573 r = r100_cs_packet_next_reloc(p, &reloc); 1574 if (r) { 1575 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1576 idx, reg); 1577 r100_cs_dump_packet(p, pkt); 1578 return r; 1579 } 1580 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1581 break; 1582 case RADEON_PP_CNTL: 1583 { 1584 uint32_t temp = idx_value >> 4; 1585 for (i = 0; i < track->num_texture; i++) 1586 track->textures[i].enabled = !!(temp & (1 << i)); 1587 track->tex_dirty = true; 1588 } 1589 break; 1590 case RADEON_SE_VF_CNTL: 1591 track->vap_vf_cntl = idx_value; 1592 break; 1593 case RADEON_SE_VTX_FMT: 1594 track->vtx_size = r100_get_vtx_size(idx_value); 1595 break; 1596 case RADEON_PP_TEX_SIZE_0: 1597 case RADEON_PP_TEX_SIZE_1: 1598 case RADEON_PP_TEX_SIZE_2: 1599 i = (reg - RADEON_PP_TEX_SIZE_0) / 8; 1600 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; 1601 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; 1602 track->tex_dirty = true; 1603 break; 1604 case RADEON_PP_TEX_PITCH_0: 1605 case RADEON_PP_TEX_PITCH_1: 1606 case RADEON_PP_TEX_PITCH_2: 1607 i = (reg - RADEON_PP_TEX_PITCH_0) / 8; 1608 track->textures[i].pitch = idx_value + 32; 1609 track->tex_dirty = true; 1610 break; 1611 case RADEON_PP_TXFILTER_0: 1612 case RADEON_PP_TXFILTER_1: 1613 case RADEON_PP_TXFILTER_2: 1614 i = (reg - RADEON_PP_TXFILTER_0) / 24; 1615 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) 1616 >> RADEON_MAX_MIP_LEVEL_SHIFT); 1617 tmp = (idx_value >> 23) & 0x7; 1618 if (tmp == 2 || tmp == 6) 1619 track->textures[i].roundup_w = false; 1620 tmp = (idx_value >> 27) & 0x7; 1621 if (tmp == 2 || tmp == 6) 1622 track->textures[i].roundup_h = false; 1623 track->tex_dirty = true; 1624 break; 1625 case RADEON_PP_TXFORMAT_0: 1626 case RADEON_PP_TXFORMAT_1: 1627 case RADEON_PP_TXFORMAT_2: 1628 i = (reg - RADEON_PP_TXFORMAT_0) / 24; 1629 if (idx_value & RADEON_TXFORMAT_NON_POWER2) { 1630 track->textures[i].use_pitch = 1; 1631 } else { 1632 track->textures[i].use_pitch = 0; 1633 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); 1634 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); 1635 } 1636 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) 1637 track->textures[i].tex_coord_type = 2; 1638 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { 1639 case RADEON_TXFORMAT_I8: 1640 case RADEON_TXFORMAT_RGB332: 1641 case RADEON_TXFORMAT_Y8: 1642 track->textures[i].cpp = 1; 1643 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1644 break; 1645 case RADEON_TXFORMAT_AI88: 1646 case RADEON_TXFORMAT_ARGB1555: 1647 case RADEON_TXFORMAT_RGB565: 1648 case RADEON_TXFORMAT_ARGB4444: 1649 case RADEON_TXFORMAT_VYUY422: 1650 case RADEON_TXFORMAT_YVYU422: 1651 case RADEON_TXFORMAT_SHADOW16: 1652 case RADEON_TXFORMAT_LDUDV655: 1653 case RADEON_TXFORMAT_DUDV88: 1654 track->textures[i].cpp = 2; 1655 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1656 break; 1657 case RADEON_TXFORMAT_ARGB8888: 1658 case RADEON_TXFORMAT_RGBA8888: 1659 case RADEON_TXFORMAT_SHADOW32: 1660 case RADEON_TXFORMAT_LDUDUV8888: 1661 track->textures[i].cpp = 4; 1662 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1663 break; 1664 case RADEON_TXFORMAT_DXT1: 1665 track->textures[i].cpp = 1; 1666 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 1667 break; 1668 case RADEON_TXFORMAT_DXT23: 1669 case RADEON_TXFORMAT_DXT45: 1670 track->textures[i].cpp = 1; 1671 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 1672 break; 1673 } 1674 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); 1675 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); 1676 track->tex_dirty = true; 1677 break; 1678 case RADEON_PP_CUBIC_FACES_0: 1679 case RADEON_PP_CUBIC_FACES_1: 1680 case RADEON_PP_CUBIC_FACES_2: 1681 tmp = idx_value; 1682 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; 1683 for (face = 0; face < 4; face++) { 1684 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); 1685 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); 1686 } 1687 track->tex_dirty = true; 1688 break; 1689 default: 1690 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", 1691 reg, idx); 1692 return -EINVAL; 1693 } 1694 return 0; 1695 } 1696 1697 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 1698 struct radeon_cs_packet *pkt, 1699 struct radeon_bo *robj) 1700 { 1701 unsigned idx; 1702 u32 value; 1703 idx = pkt->idx + 1; 1704 value = radeon_get_ib_value(p, idx + 2); 1705 if ((value + 1) > radeon_bo_size(robj)) { 1706 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " 1707 "(need %u have %lu) !\n", 1708 value + 1, 1709 radeon_bo_size(robj)); 1710 return -EINVAL; 1711 } 1712 return 0; 1713 } 1714 1715 static int r100_packet3_check(struct radeon_cs_parser *p, 1716 struct radeon_cs_packet *pkt) 1717 { 1718 struct radeon_cs_reloc *reloc; 1719 struct r100_cs_track *track; 1720 unsigned idx; 1721 volatile uint32_t *ib; 1722 int r; 1723 1724 ib = p->ib->ptr; 1725 idx = pkt->idx + 1; 1726 track = (struct r100_cs_track *)p->track; 1727 switch (pkt->opcode) { 1728 case PACKET3_3D_LOAD_VBPNTR: 1729 r = r100_packet3_load_vbpntr(p, pkt, idx); 1730 if (r) 1731 return r; 1732 break; 1733 case PACKET3_INDX_BUFFER: 1734 r = r100_cs_packet_next_reloc(p, &reloc); 1735 if (r) { 1736 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1737 r100_cs_dump_packet(p, pkt); 1738 return r; 1739 } 1740 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset); 1741 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1742 if (r) { 1743 return r; 1744 } 1745 break; 1746 case 0x23: 1747 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ 1748 r = r100_cs_packet_next_reloc(p, &reloc); 1749 if (r) { 1750 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1751 r100_cs_dump_packet(p, pkt); 1752 return r; 1753 } 1754 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset); 1755 track->num_arrays = 1; 1756 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); 1757 1758 track->arrays[0].robj = reloc->robj; 1759 track->arrays[0].esize = track->vtx_size; 1760 1761 track->max_indx = radeon_get_ib_value(p, idx+1); 1762 1763 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); 1764 track->immd_dwords = pkt->count - 1; 1765 r = r100_cs_track_check(p->rdev, track); 1766 if (r) 1767 return r; 1768 break; 1769 case PACKET3_3D_DRAW_IMMD: 1770 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1771 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1772 return -EINVAL; 1773 } 1774 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); 1775 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1776 track->immd_dwords = pkt->count - 1; 1777 r = r100_cs_track_check(p->rdev, track); 1778 if (r) 1779 return r; 1780 break; 1781 /* triggers drawing using in-packet vertex data */ 1782 case PACKET3_3D_DRAW_IMMD_2: 1783 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1784 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1785 return -EINVAL; 1786 } 1787 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1788 track->immd_dwords = pkt->count; 1789 r = r100_cs_track_check(p->rdev, track); 1790 if (r) 1791 return r; 1792 break; 1793 /* triggers drawing using in-packet vertex data */ 1794 case PACKET3_3D_DRAW_VBUF_2: 1795 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1796 r = r100_cs_track_check(p->rdev, track); 1797 if (r) 1798 return r; 1799 break; 1800 /* triggers drawing of vertex buffers setup elsewhere */ 1801 case PACKET3_3D_DRAW_INDX_2: 1802 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1803 r = r100_cs_track_check(p->rdev, track); 1804 if (r) 1805 return r; 1806 break; 1807 /* triggers drawing using indices to vertex buffer */ 1808 case PACKET3_3D_DRAW_VBUF: 1809 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1810 r = r100_cs_track_check(p->rdev, track); 1811 if (r) 1812 return r; 1813 break; 1814 /* triggers drawing of vertex buffers setup elsewhere */ 1815 case PACKET3_3D_DRAW_INDX: 1816 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1817 r = r100_cs_track_check(p->rdev, track); 1818 if (r) 1819 return r; 1820 break; 1821 /* triggers drawing using indices to vertex buffer */ 1822 case PACKET3_3D_CLEAR_HIZ: 1823 case PACKET3_3D_CLEAR_ZMASK: 1824 if (p->rdev->hyperz_filp != p->filp) 1825 return -EINVAL; 1826 break; 1827 case PACKET3_NOP: 1828 break; 1829 default: 1830 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 1831 return -EINVAL; 1832 } 1833 return 0; 1834 } 1835 1836 int r100_cs_parse(struct radeon_cs_parser *p) 1837 { 1838 struct radeon_cs_packet pkt; 1839 struct r100_cs_track *track; 1840 int r; 1841 1842 track = kzalloc(sizeof(*track), GFP_KERNEL); 1843 r100_cs_track_clear(p->rdev, track); 1844 p->track = track; 1845 do { 1846 r = r100_cs_packet_parse(p, &pkt, p->idx); 1847 if (r) { 1848 return r; 1849 } 1850 p->idx += pkt.count + 2; 1851 switch (pkt.type) { 1852 case PACKET_TYPE0: 1853 if (p->rdev->family >= CHIP_R200) 1854 r = r100_cs_parse_packet0(p, &pkt, 1855 p->rdev->config.r100.reg_safe_bm, 1856 p->rdev->config.r100.reg_safe_bm_size, 1857 &r200_packet0_check); 1858 else 1859 r = r100_cs_parse_packet0(p, &pkt, 1860 p->rdev->config.r100.reg_safe_bm, 1861 p->rdev->config.r100.reg_safe_bm_size, 1862 &r100_packet0_check); 1863 break; 1864 case PACKET_TYPE2: 1865 break; 1866 case PACKET_TYPE3: 1867 r = r100_packet3_check(p, &pkt); 1868 break; 1869 default: 1870 DRM_ERROR("Unknown packet type %d !\n", 1871 pkt.type); 1872 return -EINVAL; 1873 } 1874 if (r) { 1875 return r; 1876 } 1877 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 1878 return 0; 1879 } 1880 1881 1882 /* 1883 * Global GPU functions 1884 */ 1885 void r100_errata(struct radeon_device *rdev) 1886 { 1887 rdev->pll_errata = 0; 1888 1889 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { 1890 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; 1891 } 1892 1893 if (rdev->family == CHIP_RV100 || 1894 rdev->family == CHIP_RS100 || 1895 rdev->family == CHIP_RS200) { 1896 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; 1897 } 1898 } 1899 1900 /* Wait for vertical sync on primary CRTC */ 1901 void r100_gpu_wait_for_vsync(struct radeon_device *rdev) 1902 { 1903 uint32_t crtc_gen_cntl, tmp; 1904 int i; 1905 1906 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 1907 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) || 1908 !(crtc_gen_cntl & RADEON_CRTC_EN)) { 1909 return; 1910 } 1911 /* Clear the CRTC_VBLANK_SAVE bit */ 1912 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR); 1913 for (i = 0; i < rdev->usec_timeout; i++) { 1914 tmp = RREG32(RADEON_CRTC_STATUS); 1915 if (tmp & RADEON_CRTC_VBLANK_SAVE) { 1916 return; 1917 } 1918 DRM_UDELAY(1); 1919 } 1920 } 1921 1922 /* Wait for vertical sync on secondary CRTC */ 1923 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev) 1924 { 1925 uint32_t crtc2_gen_cntl, tmp; 1926 int i; 1927 1928 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 1929 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) || 1930 !(crtc2_gen_cntl & RADEON_CRTC2_EN)) 1931 return; 1932 1933 /* Clear the CRTC_VBLANK_SAVE bit */ 1934 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR); 1935 for (i = 0; i < rdev->usec_timeout; i++) { 1936 tmp = RREG32(RADEON_CRTC2_STATUS); 1937 if (tmp & RADEON_CRTC2_VBLANK_SAVE) { 1938 return; 1939 } 1940 DRM_UDELAY(1); 1941 } 1942 } 1943 1944 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) 1945 { 1946 unsigned i; 1947 uint32_t tmp; 1948 1949 for (i = 0; i < rdev->usec_timeout; i++) { 1950 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; 1951 if (tmp >= n) { 1952 return 0; 1953 } 1954 DRM_UDELAY(1); 1955 } 1956 return -1; 1957 } 1958 1959 int r100_gui_wait_for_idle(struct radeon_device *rdev) 1960 { 1961 unsigned i; 1962 uint32_t tmp; 1963 1964 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { 1965 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !" 1966 " Bad things might happen.\n"); 1967 } 1968 for (i = 0; i < rdev->usec_timeout; i++) { 1969 tmp = RREG32(RADEON_RBBM_STATUS); 1970 if (!(tmp & RADEON_RBBM_ACTIVE)) { 1971 return 0; 1972 } 1973 DRM_UDELAY(1); 1974 } 1975 return -1; 1976 } 1977 1978 int r100_mc_wait_for_idle(struct radeon_device *rdev) 1979 { 1980 unsigned i; 1981 uint32_t tmp; 1982 1983 for (i = 0; i < rdev->usec_timeout; i++) { 1984 /* read MC_STATUS */ 1985 tmp = RREG32(RADEON_MC_STATUS); 1986 if (tmp & RADEON_MC_IDLE) { 1987 return 0; 1988 } 1989 DRM_UDELAY(1); 1990 } 1991 return -1; 1992 } 1993 1994 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp) 1995 { 1996 lockup->last_cp_rptr = cp->rptr; 1997 lockup->last_jiffies = jiffies; 1998 } 1999 2000 /** 2001 * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information 2002 * @rdev: radeon device structure 2003 * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations 2004 * @cp: radeon_cp structure holding CP information 2005 * 2006 * We don't need to initialize the lockup tracking information as we will either 2007 * have CP rptr to a different value of jiffies wrap around which will force 2008 * initialization of the lockup tracking informations. 2009 * 2010 * A possible false positivie is if we get call after while and last_cp_rptr == 2011 * the current CP rptr, even if it's unlikely it might happen. To avoid this 2012 * if the elapsed time since last call is bigger than 2 second than we return 2013 * false and update the tracking information. Due to this the caller must call 2014 * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported 2015 * the fencing code should be cautious about that. 2016 * 2017 * Caller should write to the ring to force CP to do something so we don't get 2018 * false positive when CP is just gived nothing to do. 2019 * 2020 **/ 2021 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp) 2022 { 2023 unsigned long cjiffies, elapsed; 2024 2025 cjiffies = jiffies; 2026 if (!time_after(cjiffies, lockup->last_jiffies)) { 2027 /* likely a wrap around */ 2028 lockup->last_cp_rptr = cp->rptr; 2029 lockup->last_jiffies = jiffies; 2030 return false; 2031 } 2032 if (cp->rptr != lockup->last_cp_rptr) { 2033 /* CP is still working no lockup */ 2034 lockup->last_cp_rptr = cp->rptr; 2035 lockup->last_jiffies = jiffies; 2036 return false; 2037 } 2038 elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies); 2039 if (elapsed >= 10000) { 2040 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); 2041 return true; 2042 } 2043 /* give a chance to the GPU ... */ 2044 return false; 2045 } 2046 2047 bool r100_gpu_is_lockup(struct radeon_device *rdev) 2048 { 2049 u32 rbbm_status; 2050 int r; 2051 2052 rbbm_status = RREG32(R_000E40_RBBM_STATUS); 2053 if (!G_000E40_GUI_ACTIVE(rbbm_status)) { 2054 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp); 2055 return false; 2056 } 2057 /* force CP activities */ 2058 r = radeon_ring_lock(rdev, 2); 2059 if (!r) { 2060 /* PACKET2 NOP */ 2061 radeon_ring_write(rdev, 0x80000000); 2062 radeon_ring_write(rdev, 0x80000000); 2063 radeon_ring_unlock_commit(rdev); 2064 } 2065 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); 2066 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp); 2067 } 2068 2069 void r100_bm_disable(struct radeon_device *rdev) 2070 { 2071 u32 tmp; 2072 2073 /* disable bus mastering */ 2074 tmp = RREG32(R_000030_BUS_CNTL); 2075 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044); 2076 mdelay(1); 2077 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042); 2078 mdelay(1); 2079 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); 2080 tmp = RREG32(RADEON_BUS_CNTL); 2081 mdelay(1); 2082 pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp); 2083 pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB); 2084 mdelay(1); 2085 } 2086 2087 int r100_asic_reset(struct radeon_device *rdev) 2088 { 2089 struct r100_mc_save save; 2090 u32 status, tmp; 2091 int ret = 0; 2092 2093 status = RREG32(R_000E40_RBBM_STATUS); 2094 if (!G_000E40_GUI_ACTIVE(status)) { 2095 return 0; 2096 } 2097 r100_mc_stop(rdev, &save); 2098 status = RREG32(R_000E40_RBBM_STATUS); 2099 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2100 /* stop CP */ 2101 WREG32(RADEON_CP_CSQ_CNTL, 0); 2102 tmp = RREG32(RADEON_CP_RB_CNTL); 2103 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 2104 WREG32(RADEON_CP_RB_RPTR_WR, 0); 2105 WREG32(RADEON_CP_RB_WPTR, 0); 2106 WREG32(RADEON_CP_RB_CNTL, tmp); 2107 /* save PCI state */ 2108 pci_save_state(rdev->pdev); 2109 /* disable bus mastering */ 2110 r100_bm_disable(rdev); 2111 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) | 2112 S_0000F0_SOFT_RESET_RE(1) | 2113 S_0000F0_SOFT_RESET_PP(1) | 2114 S_0000F0_SOFT_RESET_RB(1)); 2115 RREG32(R_0000F0_RBBM_SOFT_RESET); 2116 mdelay(500); 2117 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2118 mdelay(1); 2119 status = RREG32(R_000E40_RBBM_STATUS); 2120 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2121 /* reset CP */ 2122 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 2123 RREG32(R_0000F0_RBBM_SOFT_RESET); 2124 mdelay(500); 2125 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2126 mdelay(1); 2127 status = RREG32(R_000E40_RBBM_STATUS); 2128 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2129 /* restore PCI & busmastering */ 2130 pci_restore_state(rdev->pdev); 2131 r100_enable_bm(rdev); 2132 /* Check if GPU is idle */ 2133 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) || 2134 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) { 2135 dev_err(rdev->dev, "failed to reset GPU\n"); 2136 rdev->gpu_lockup = true; 2137 ret = -1; 2138 } else 2139 dev_info(rdev->dev, "GPU reset succeed\n"); 2140 r100_mc_resume(rdev, &save); 2141 return ret; 2142 } 2143 2144 void r100_set_common_regs(struct radeon_device *rdev) 2145 { 2146 struct drm_device *dev = rdev->ddev; 2147 bool force_dac2 = false; 2148 u32 tmp; 2149 2150 /* set these so they don't interfere with anything */ 2151 WREG32(RADEON_OV0_SCALE_CNTL, 0); 2152 WREG32(RADEON_SUBPIC_CNTL, 0); 2153 WREG32(RADEON_VIPH_CONTROL, 0); 2154 WREG32(RADEON_I2C_CNTL_1, 0); 2155 WREG32(RADEON_DVI_I2C_CNTL_1, 0); 2156 WREG32(RADEON_CAP0_TRIG_CNTL, 0); 2157 WREG32(RADEON_CAP1_TRIG_CNTL, 0); 2158 2159 /* always set up dac2 on rn50 and some rv100 as lots 2160 * of servers seem to wire it up to a VGA port but 2161 * don't report it in the bios connector 2162 * table. 2163 */ 2164 switch (dev->pdev->device) { 2165 /* RN50 */ 2166 case 0x515e: 2167 case 0x5969: 2168 force_dac2 = true; 2169 break; 2170 /* RV100*/ 2171 case 0x5159: 2172 case 0x515a: 2173 /* DELL triple head servers */ 2174 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) && 2175 ((dev->pdev->subsystem_device == 0x016c) || 2176 (dev->pdev->subsystem_device == 0x016d) || 2177 (dev->pdev->subsystem_device == 0x016e) || 2178 (dev->pdev->subsystem_device == 0x016f) || 2179 (dev->pdev->subsystem_device == 0x0170) || 2180 (dev->pdev->subsystem_device == 0x017d) || 2181 (dev->pdev->subsystem_device == 0x017e) || 2182 (dev->pdev->subsystem_device == 0x0183) || 2183 (dev->pdev->subsystem_device == 0x018a) || 2184 (dev->pdev->subsystem_device == 0x019a))) 2185 force_dac2 = true; 2186 break; 2187 } 2188 2189 if (force_dac2) { 2190 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 2191 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 2192 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 2193 2194 /* For CRT on DAC2, don't turn it on if BIOS didn't 2195 enable it, even it's detected. 2196 */ 2197 2198 /* force it to crtc0 */ 2199 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; 2200 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; 2201 disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 2202 2203 /* set up the TV DAC */ 2204 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL | 2205 RADEON_TV_DAC_STD_MASK | 2206 RADEON_TV_DAC_RDACPD | 2207 RADEON_TV_DAC_GDACPD | 2208 RADEON_TV_DAC_BDACPD | 2209 RADEON_TV_DAC_BGADJ_MASK | 2210 RADEON_TV_DAC_DACADJ_MASK); 2211 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | 2212 RADEON_TV_DAC_NHOLD | 2213 RADEON_TV_DAC_STD_PS2 | 2214 (0x58 << 16)); 2215 2216 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 2217 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 2218 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 2219 } 2220 2221 /* switch PM block to ACPI mode */ 2222 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); 2223 tmp &= ~RADEON_PM_MODE_SEL; 2224 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); 2225 2226 } 2227 2228 /* 2229 * VRAM info 2230 */ 2231 static void r100_vram_get_type(struct radeon_device *rdev) 2232 { 2233 uint32_t tmp; 2234 2235 rdev->mc.vram_is_ddr = false; 2236 if (rdev->flags & RADEON_IS_IGP) 2237 rdev->mc.vram_is_ddr = true; 2238 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) 2239 rdev->mc.vram_is_ddr = true; 2240 if ((rdev->family == CHIP_RV100) || 2241 (rdev->family == CHIP_RS100) || 2242 (rdev->family == CHIP_RS200)) { 2243 tmp = RREG32(RADEON_MEM_CNTL); 2244 if (tmp & RV100_HALF_MODE) { 2245 rdev->mc.vram_width = 32; 2246 } else { 2247 rdev->mc.vram_width = 64; 2248 } 2249 if (rdev->flags & RADEON_SINGLE_CRTC) { 2250 rdev->mc.vram_width /= 4; 2251 rdev->mc.vram_is_ddr = true; 2252 } 2253 } else if (rdev->family <= CHIP_RV280) { 2254 tmp = RREG32(RADEON_MEM_CNTL); 2255 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { 2256 rdev->mc.vram_width = 128; 2257 } else { 2258 rdev->mc.vram_width = 64; 2259 } 2260 } else { 2261 /* newer IGPs */ 2262 rdev->mc.vram_width = 128; 2263 } 2264 } 2265 2266 static u32 r100_get_accessible_vram(struct radeon_device *rdev) 2267 { 2268 u32 aper_size; 2269 u8 byte; 2270 2271 aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2272 2273 /* Set HDP_APER_CNTL only on cards that are known not to be broken, 2274 * that is has the 2nd generation multifunction PCI interface 2275 */ 2276 if (rdev->family == CHIP_RV280 || 2277 rdev->family >= CHIP_RV350) { 2278 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, 2279 ~RADEON_HDP_APER_CNTL); 2280 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); 2281 return aper_size * 2; 2282 } 2283 2284 /* Older cards have all sorts of funny issues to deal with. First 2285 * check if it's a multifunction card by reading the PCI config 2286 * header type... Limit those to one aperture size 2287 */ 2288 pci_read_config_byte(rdev->pdev, 0xe, &byte); 2289 if (byte & 0x80) { 2290 DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); 2291 DRM_INFO("Limiting VRAM to one aperture\n"); 2292 return aper_size; 2293 } 2294 2295 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS 2296 * have set it up. We don't write this as it's broken on some ASICs but 2297 * we expect the BIOS to have done the right thing (might be too optimistic...) 2298 */ 2299 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) 2300 return aper_size * 2; 2301 return aper_size; 2302 } 2303 2304 void r100_vram_init_sizes(struct radeon_device *rdev) 2305 { 2306 u64 config_aper_size; 2307 2308 /* work out accessible VRAM */ 2309 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 2310 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 2311 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); 2312 /* FIXME we don't use the second aperture yet when we could use it */ 2313 if (rdev->mc.visible_vram_size > rdev->mc.aper_size) 2314 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2315 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2316 if (rdev->flags & RADEON_IS_IGP) { 2317 uint32_t tom; 2318 /* read NB_TOM to get the amount of ram stolen for the GPU */ 2319 tom = RREG32(RADEON_NB_TOM); 2320 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); 2321 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2322 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2323 } else { 2324 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 2325 /* Some production boards of m6 will report 0 2326 * if it's 8 MB 2327 */ 2328 if (rdev->mc.real_vram_size == 0) { 2329 rdev->mc.real_vram_size = 8192 * 1024; 2330 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2331 } 2332 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 2333 * Novell bug 204882 + along with lots of ubuntu ones 2334 */ 2335 if (rdev->mc.aper_size > config_aper_size) 2336 config_aper_size = rdev->mc.aper_size; 2337 2338 if (config_aper_size > rdev->mc.real_vram_size) 2339 rdev->mc.mc_vram_size = config_aper_size; 2340 else 2341 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2342 } 2343 } 2344 2345 void r100_vga_set_state(struct radeon_device *rdev, bool state) 2346 { 2347 uint32_t temp; 2348 2349 temp = RREG32(RADEON_CONFIG_CNTL); 2350 if (state == false) { 2351 temp &= ~RADEON_CFG_VGA_RAM_EN; 2352 temp |= RADEON_CFG_VGA_IO_DIS; 2353 } else { 2354 temp &= ~RADEON_CFG_VGA_IO_DIS; 2355 } 2356 WREG32(RADEON_CONFIG_CNTL, temp); 2357 } 2358 2359 void r100_mc_init(struct radeon_device *rdev) 2360 { 2361 u64 base; 2362 2363 r100_vram_get_type(rdev); 2364 r100_vram_init_sizes(rdev); 2365 base = rdev->mc.aper_base; 2366 if (rdev->flags & RADEON_IS_IGP) 2367 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 2368 radeon_vram_location(rdev, &rdev->mc, base); 2369 rdev->mc.gtt_base_align = 0; 2370 if (!(rdev->flags & RADEON_IS_AGP)) 2371 radeon_gtt_location(rdev, &rdev->mc); 2372 radeon_update_bandwidth_info(rdev); 2373 } 2374 2375 2376 /* 2377 * Indirect registers accessor 2378 */ 2379 void r100_pll_errata_after_index(struct radeon_device *rdev) 2380 { 2381 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) { 2382 (void)RREG32(RADEON_CLOCK_CNTL_DATA); 2383 (void)RREG32(RADEON_CRTC_GEN_CNTL); 2384 } 2385 } 2386 2387 static void r100_pll_errata_after_data(struct radeon_device *rdev) 2388 { 2389 /* This workarounds is necessary on RV100, RS100 and RS200 chips 2390 * or the chip could hang on a subsequent access 2391 */ 2392 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { 2393 udelay(5000); 2394 } 2395 2396 /* This function is required to workaround a hardware bug in some (all?) 2397 * revisions of the R300. This workaround should be called after every 2398 * CLOCK_CNTL_INDEX register access. If not, register reads afterward 2399 * may not be correct. 2400 */ 2401 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { 2402 uint32_t save, tmp; 2403 2404 save = RREG32(RADEON_CLOCK_CNTL_INDEX); 2405 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2406 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); 2407 tmp = RREG32(RADEON_CLOCK_CNTL_DATA); 2408 WREG32(RADEON_CLOCK_CNTL_INDEX, save); 2409 } 2410 } 2411 2412 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) 2413 { 2414 uint32_t data; 2415 2416 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); 2417 r100_pll_errata_after_index(rdev); 2418 data = RREG32(RADEON_CLOCK_CNTL_DATA); 2419 r100_pll_errata_after_data(rdev); 2420 return data; 2421 } 2422 2423 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2424 { 2425 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); 2426 r100_pll_errata_after_index(rdev); 2427 WREG32(RADEON_CLOCK_CNTL_DATA, v); 2428 r100_pll_errata_after_data(rdev); 2429 } 2430 2431 void r100_set_safe_registers(struct radeon_device *rdev) 2432 { 2433 if (ASIC_IS_RN50(rdev)) { 2434 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; 2435 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); 2436 } else if (rdev->family < CHIP_R200) { 2437 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; 2438 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); 2439 } else { 2440 r200_set_safe_registers(rdev); 2441 } 2442 } 2443 2444 /* 2445 * Debugfs info 2446 */ 2447 #if defined(CONFIG_DEBUG_FS) 2448 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data) 2449 { 2450 struct drm_info_node *node = (struct drm_info_node *) m->private; 2451 struct drm_device *dev = node->minor->dev; 2452 struct radeon_device *rdev = dev->dev_private; 2453 uint32_t reg, value; 2454 unsigned i; 2455 2456 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); 2457 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); 2458 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2459 for (i = 0; i < 64; i++) { 2460 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); 2461 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; 2462 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); 2463 value = RREG32(RADEON_RBBM_CMDFIFO_DATA); 2464 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); 2465 } 2466 return 0; 2467 } 2468 2469 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data) 2470 { 2471 struct drm_info_node *node = (struct drm_info_node *) m->private; 2472 struct drm_device *dev = node->minor->dev; 2473 struct radeon_device *rdev = dev->dev_private; 2474 uint32_t rdp, wdp; 2475 unsigned count, i, j; 2476 2477 radeon_ring_free_size(rdev); 2478 rdp = RREG32(RADEON_CP_RB_RPTR); 2479 wdp = RREG32(RADEON_CP_RB_WPTR); 2480 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask; 2481 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2482 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); 2483 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); 2484 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw); 2485 seq_printf(m, "%u dwords in ring\n", count); 2486 for (j = 0; j <= count; j++) { 2487 i = (rdp + j) & rdev->cp.ptr_mask; 2488 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]); 2489 } 2490 return 0; 2491 } 2492 2493 2494 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data) 2495 { 2496 struct drm_info_node *node = (struct drm_info_node *) m->private; 2497 struct drm_device *dev = node->minor->dev; 2498 struct radeon_device *rdev = dev->dev_private; 2499 uint32_t csq_stat, csq2_stat, tmp; 2500 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; 2501 unsigned i; 2502 2503 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2504 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); 2505 csq_stat = RREG32(RADEON_CP_CSQ_STAT); 2506 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); 2507 r_rptr = (csq_stat >> 0) & 0x3ff; 2508 r_wptr = (csq_stat >> 10) & 0x3ff; 2509 ib1_rptr = (csq_stat >> 20) & 0x3ff; 2510 ib1_wptr = (csq2_stat >> 0) & 0x3ff; 2511 ib2_rptr = (csq2_stat >> 10) & 0x3ff; 2512 ib2_wptr = (csq2_stat >> 20) & 0x3ff; 2513 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); 2514 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); 2515 seq_printf(m, "Ring rptr %u\n", r_rptr); 2516 seq_printf(m, "Ring wptr %u\n", r_wptr); 2517 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); 2518 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); 2519 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); 2520 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); 2521 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms 2522 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ 2523 seq_printf(m, "Ring fifo:\n"); 2524 for (i = 0; i < 256; i++) { 2525 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2526 tmp = RREG32(RADEON_CP_CSQ_DATA); 2527 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); 2528 } 2529 seq_printf(m, "Indirect1 fifo:\n"); 2530 for (i = 256; i <= 512; i++) { 2531 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2532 tmp = RREG32(RADEON_CP_CSQ_DATA); 2533 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); 2534 } 2535 seq_printf(m, "Indirect2 fifo:\n"); 2536 for (i = 640; i < ib1_wptr; i++) { 2537 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2538 tmp = RREG32(RADEON_CP_CSQ_DATA); 2539 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); 2540 } 2541 return 0; 2542 } 2543 2544 static int r100_debugfs_mc_info(struct seq_file *m, void *data) 2545 { 2546 struct drm_info_node *node = (struct drm_info_node *) m->private; 2547 struct drm_device *dev = node->minor->dev; 2548 struct radeon_device *rdev = dev->dev_private; 2549 uint32_t tmp; 2550 2551 tmp = RREG32(RADEON_CONFIG_MEMSIZE); 2552 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); 2553 tmp = RREG32(RADEON_MC_FB_LOCATION); 2554 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); 2555 tmp = RREG32(RADEON_BUS_CNTL); 2556 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 2557 tmp = RREG32(RADEON_MC_AGP_LOCATION); 2558 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 2559 tmp = RREG32(RADEON_AGP_BASE); 2560 seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 2561 tmp = RREG32(RADEON_HOST_PATH_CNTL); 2562 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 2563 tmp = RREG32(0x01D0); 2564 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); 2565 tmp = RREG32(RADEON_AIC_LO_ADDR); 2566 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); 2567 tmp = RREG32(RADEON_AIC_HI_ADDR); 2568 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); 2569 tmp = RREG32(0x01E4); 2570 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); 2571 return 0; 2572 } 2573 2574 static struct drm_info_list r100_debugfs_rbbm_list[] = { 2575 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL}, 2576 }; 2577 2578 static struct drm_info_list r100_debugfs_cp_list[] = { 2579 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL}, 2580 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL}, 2581 }; 2582 2583 static struct drm_info_list r100_debugfs_mc_info_list[] = { 2584 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL}, 2585 }; 2586 #endif 2587 2588 int r100_debugfs_rbbm_init(struct radeon_device *rdev) 2589 { 2590 #if defined(CONFIG_DEBUG_FS) 2591 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1); 2592 #else 2593 return 0; 2594 #endif 2595 } 2596 2597 int r100_debugfs_cp_init(struct radeon_device *rdev) 2598 { 2599 #if defined(CONFIG_DEBUG_FS) 2600 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2); 2601 #else 2602 return 0; 2603 #endif 2604 } 2605 2606 int r100_debugfs_mc_info_init(struct radeon_device *rdev) 2607 { 2608 #if defined(CONFIG_DEBUG_FS) 2609 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1); 2610 #else 2611 return 0; 2612 #endif 2613 } 2614 2615 int r100_set_surface_reg(struct radeon_device *rdev, int reg, 2616 uint32_t tiling_flags, uint32_t pitch, 2617 uint32_t offset, uint32_t obj_size) 2618 { 2619 int surf_index = reg * 16; 2620 int flags = 0; 2621 2622 if (rdev->family <= CHIP_RS200) { 2623 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 2624 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 2625 flags |= RADEON_SURF_TILE_COLOR_BOTH; 2626 if (tiling_flags & RADEON_TILING_MACRO) 2627 flags |= RADEON_SURF_TILE_COLOR_MACRO; 2628 } else if (rdev->family <= CHIP_RV280) { 2629 if (tiling_flags & (RADEON_TILING_MACRO)) 2630 flags |= R200_SURF_TILE_COLOR_MACRO; 2631 if (tiling_flags & RADEON_TILING_MICRO) 2632 flags |= R200_SURF_TILE_COLOR_MICRO; 2633 } else { 2634 if (tiling_flags & RADEON_TILING_MACRO) 2635 flags |= R300_SURF_TILE_MACRO; 2636 if (tiling_flags & RADEON_TILING_MICRO) 2637 flags |= R300_SURF_TILE_MICRO; 2638 } 2639 2640 if (tiling_flags & RADEON_TILING_SWAP_16BIT) 2641 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; 2642 if (tiling_flags & RADEON_TILING_SWAP_32BIT) 2643 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; 2644 2645 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */ 2646 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) { 2647 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) 2648 if (ASIC_IS_RN50(rdev)) 2649 pitch /= 16; 2650 } 2651 2652 /* r100/r200 divide by 16 */ 2653 if (rdev->family < CHIP_R300) 2654 flags |= pitch / 16; 2655 else 2656 flags |= pitch / 8; 2657 2658 2659 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); 2660 WREG32(RADEON_SURFACE0_INFO + surf_index, flags); 2661 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); 2662 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); 2663 return 0; 2664 } 2665 2666 void r100_clear_surface_reg(struct radeon_device *rdev, int reg) 2667 { 2668 int surf_index = reg * 16; 2669 WREG32(RADEON_SURFACE0_INFO + surf_index, 0); 2670 } 2671 2672 void r100_bandwidth_update(struct radeon_device *rdev) 2673 { 2674 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; 2675 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; 2676 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; 2677 uint32_t temp, data, mem_trcd, mem_trp, mem_tras; 2678 fixed20_12 memtcas_ff[8] = { 2679 dfixed_init(1), 2680 dfixed_init(2), 2681 dfixed_init(3), 2682 dfixed_init(0), 2683 dfixed_init_half(1), 2684 dfixed_init_half(2), 2685 dfixed_init(0), 2686 }; 2687 fixed20_12 memtcas_rs480_ff[8] = { 2688 dfixed_init(0), 2689 dfixed_init(1), 2690 dfixed_init(2), 2691 dfixed_init(3), 2692 dfixed_init(0), 2693 dfixed_init_half(1), 2694 dfixed_init_half(2), 2695 dfixed_init_half(3), 2696 }; 2697 fixed20_12 memtcas2_ff[8] = { 2698 dfixed_init(0), 2699 dfixed_init(1), 2700 dfixed_init(2), 2701 dfixed_init(3), 2702 dfixed_init(4), 2703 dfixed_init(5), 2704 dfixed_init(6), 2705 dfixed_init(7), 2706 }; 2707 fixed20_12 memtrbs[8] = { 2708 dfixed_init(1), 2709 dfixed_init_half(1), 2710 dfixed_init(2), 2711 dfixed_init_half(2), 2712 dfixed_init(3), 2713 dfixed_init_half(3), 2714 dfixed_init(4), 2715 dfixed_init_half(4) 2716 }; 2717 fixed20_12 memtrbs_r4xx[8] = { 2718 dfixed_init(4), 2719 dfixed_init(5), 2720 dfixed_init(6), 2721 dfixed_init(7), 2722 dfixed_init(8), 2723 dfixed_init(9), 2724 dfixed_init(10), 2725 dfixed_init(11) 2726 }; 2727 fixed20_12 min_mem_eff; 2728 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; 2729 fixed20_12 cur_latency_mclk, cur_latency_sclk; 2730 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate, 2731 disp_drain_rate2, read_return_rate; 2732 fixed20_12 time_disp1_drop_priority; 2733 int c; 2734 int cur_size = 16; /* in octawords */ 2735 int critical_point = 0, critical_point2; 2736 /* uint32_t read_return_rate, time_disp1_drop_priority; */ 2737 int stop_req, max_stop_req; 2738 struct drm_display_mode *mode1 = NULL; 2739 struct drm_display_mode *mode2 = NULL; 2740 uint32_t pixel_bytes1 = 0; 2741 uint32_t pixel_bytes2 = 0; 2742 2743 radeon_update_display_priority(rdev); 2744 2745 if (rdev->mode_info.crtcs[0]->base.enabled) { 2746 mode1 = &rdev->mode_info.crtcs[0]->base.mode; 2747 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8; 2748 } 2749 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 2750 if (rdev->mode_info.crtcs[1]->base.enabled) { 2751 mode2 = &rdev->mode_info.crtcs[1]->base.mode; 2752 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8; 2753 } 2754 } 2755 2756 min_mem_eff.full = dfixed_const_8(0); 2757 /* get modes */ 2758 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { 2759 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); 2760 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); 2761 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); 2762 /* check crtc enables */ 2763 if (mode2) 2764 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); 2765 if (mode1) 2766 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); 2767 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); 2768 } 2769 2770 /* 2771 * determine is there is enough bw for current mode 2772 */ 2773 sclk_ff = rdev->pm.sclk; 2774 mclk_ff = rdev->pm.mclk; 2775 2776 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); 2777 temp_ff.full = dfixed_const(temp); 2778 mem_bw.full = dfixed_mul(mclk_ff, temp_ff); 2779 2780 pix_clk.full = 0; 2781 pix_clk2.full = 0; 2782 peak_disp_bw.full = 0; 2783 if (mode1) { 2784 temp_ff.full = dfixed_const(1000); 2785 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ 2786 pix_clk.full = dfixed_div(pix_clk, temp_ff); 2787 temp_ff.full = dfixed_const(pixel_bytes1); 2788 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); 2789 } 2790 if (mode2) { 2791 temp_ff.full = dfixed_const(1000); 2792 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ 2793 pix_clk2.full = dfixed_div(pix_clk2, temp_ff); 2794 temp_ff.full = dfixed_const(pixel_bytes2); 2795 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); 2796 } 2797 2798 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); 2799 if (peak_disp_bw.full >= mem_bw.full) { 2800 DRM_ERROR("You may not have enough display bandwidth for current mode\n" 2801 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); 2802 } 2803 2804 /* Get values from the EXT_MEM_CNTL register...converting its contents. */ 2805 temp = RREG32(RADEON_MEM_TIMING_CNTL); 2806 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ 2807 mem_trcd = ((temp >> 2) & 0x3) + 1; 2808 mem_trp = ((temp & 0x3)) + 1; 2809 mem_tras = ((temp & 0x70) >> 4) + 1; 2810 } else if (rdev->family == CHIP_R300 || 2811 rdev->family == CHIP_R350) { /* r300, r350 */ 2812 mem_trcd = (temp & 0x7) + 1; 2813 mem_trp = ((temp >> 8) & 0x7) + 1; 2814 mem_tras = ((temp >> 11) & 0xf) + 4; 2815 } else if (rdev->family == CHIP_RV350 || 2816 rdev->family <= CHIP_RV380) { 2817 /* rv3x0 */ 2818 mem_trcd = (temp & 0x7) + 3; 2819 mem_trp = ((temp >> 8) & 0x7) + 3; 2820 mem_tras = ((temp >> 11) & 0xf) + 6; 2821 } else if (rdev->family == CHIP_R420 || 2822 rdev->family == CHIP_R423 || 2823 rdev->family == CHIP_RV410) { 2824 /* r4xx */ 2825 mem_trcd = (temp & 0xf) + 3; 2826 if (mem_trcd > 15) 2827 mem_trcd = 15; 2828 mem_trp = ((temp >> 8) & 0xf) + 3; 2829 if (mem_trp > 15) 2830 mem_trp = 15; 2831 mem_tras = ((temp >> 12) & 0x1f) + 6; 2832 if (mem_tras > 31) 2833 mem_tras = 31; 2834 } else { /* RV200, R200 */ 2835 mem_trcd = (temp & 0x7) + 1; 2836 mem_trp = ((temp >> 8) & 0x7) + 1; 2837 mem_tras = ((temp >> 12) & 0xf) + 4; 2838 } 2839 /* convert to FF */ 2840 trcd_ff.full = dfixed_const(mem_trcd); 2841 trp_ff.full = dfixed_const(mem_trp); 2842 tras_ff.full = dfixed_const(mem_tras); 2843 2844 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ 2845 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 2846 data = (temp & (7 << 20)) >> 20; 2847 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { 2848 if (rdev->family == CHIP_RS480) /* don't think rs400 */ 2849 tcas_ff = memtcas_rs480_ff[data]; 2850 else 2851 tcas_ff = memtcas_ff[data]; 2852 } else 2853 tcas_ff = memtcas2_ff[data]; 2854 2855 if (rdev->family == CHIP_RS400 || 2856 rdev->family == CHIP_RS480) { 2857 /* extra cas latency stored in bits 23-25 0-4 clocks */ 2858 data = (temp >> 23) & 0x7; 2859 if (data < 5) 2860 tcas_ff.full += dfixed_const(data); 2861 } 2862 2863 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { 2864 /* on the R300, Tcas is included in Trbs. 2865 */ 2866 temp = RREG32(RADEON_MEM_CNTL); 2867 data = (R300_MEM_NUM_CHANNELS_MASK & temp); 2868 if (data == 1) { 2869 if (R300_MEM_USE_CD_CH_ONLY & temp) { 2870 temp = RREG32(R300_MC_IND_INDEX); 2871 temp &= ~R300_MC_IND_ADDR_MASK; 2872 temp |= R300_MC_READ_CNTL_CD_mcind; 2873 WREG32(R300_MC_IND_INDEX, temp); 2874 temp = RREG32(R300_MC_IND_DATA); 2875 data = (R300_MEM_RBS_POSITION_C_MASK & temp); 2876 } else { 2877 temp = RREG32(R300_MC_READ_CNTL_AB); 2878 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 2879 } 2880 } else { 2881 temp = RREG32(R300_MC_READ_CNTL_AB); 2882 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 2883 } 2884 if (rdev->family == CHIP_RV410 || 2885 rdev->family == CHIP_R420 || 2886 rdev->family == CHIP_R423) 2887 trbs_ff = memtrbs_r4xx[data]; 2888 else 2889 trbs_ff = memtrbs[data]; 2890 tcas_ff.full += trbs_ff.full; 2891 } 2892 2893 sclk_eff_ff.full = sclk_ff.full; 2894 2895 if (rdev->flags & RADEON_IS_AGP) { 2896 fixed20_12 agpmode_ff; 2897 agpmode_ff.full = dfixed_const(radeon_agpmode); 2898 temp_ff.full = dfixed_const_666(16); 2899 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); 2900 } 2901 /* TODO PCIE lanes may affect this - agpmode == 16?? */ 2902 2903 if (ASIC_IS_R300(rdev)) { 2904 sclk_delay_ff.full = dfixed_const(250); 2905 } else { 2906 if ((rdev->family == CHIP_RV100) || 2907 rdev->flags & RADEON_IS_IGP) { 2908 if (rdev->mc.vram_is_ddr) 2909 sclk_delay_ff.full = dfixed_const(41); 2910 else 2911 sclk_delay_ff.full = dfixed_const(33); 2912 } else { 2913 if (rdev->mc.vram_width == 128) 2914 sclk_delay_ff.full = dfixed_const(57); 2915 else 2916 sclk_delay_ff.full = dfixed_const(41); 2917 } 2918 } 2919 2920 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff); 2921 2922 if (rdev->mc.vram_is_ddr) { 2923 if (rdev->mc.vram_width == 32) { 2924 k1.full = dfixed_const(40); 2925 c = 3; 2926 } else { 2927 k1.full = dfixed_const(20); 2928 c = 1; 2929 } 2930 } else { 2931 k1.full = dfixed_const(40); 2932 c = 3; 2933 } 2934 2935 temp_ff.full = dfixed_const(2); 2936 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); 2937 temp_ff.full = dfixed_const(c); 2938 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); 2939 temp_ff.full = dfixed_const(4); 2940 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); 2941 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); 2942 mc_latency_mclk.full += k1.full; 2943 2944 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff); 2945 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff); 2946 2947 /* 2948 HW cursor time assuming worst case of full size colour cursor. 2949 */ 2950 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); 2951 temp_ff.full += trcd_ff.full; 2952 if (temp_ff.full < tras_ff.full) 2953 temp_ff.full = tras_ff.full; 2954 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff); 2955 2956 temp_ff.full = dfixed_const(cur_size); 2957 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff); 2958 /* 2959 Find the total latency for the display data. 2960 */ 2961 disp_latency_overhead.full = dfixed_const(8); 2962 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff); 2963 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; 2964 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; 2965 2966 if (mc_latency_mclk.full > mc_latency_sclk.full) 2967 disp_latency.full = mc_latency_mclk.full; 2968 else 2969 disp_latency.full = mc_latency_sclk.full; 2970 2971 /* setup Max GRPH_STOP_REQ default value */ 2972 if (ASIC_IS_RV100(rdev)) 2973 max_stop_req = 0x5c; 2974 else 2975 max_stop_req = 0x7c; 2976 2977 if (mode1) { 2978 /* CRTC1 2979 Set GRPH_BUFFER_CNTL register using h/w defined optimal values. 2980 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] 2981 */ 2982 stop_req = mode1->hdisplay * pixel_bytes1 / 16; 2983 2984 if (stop_req > max_stop_req) 2985 stop_req = max_stop_req; 2986 2987 /* 2988 Find the drain rate of the display buffer. 2989 */ 2990 temp_ff.full = dfixed_const((16/pixel_bytes1)); 2991 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); 2992 2993 /* 2994 Find the critical point of the display buffer. 2995 */ 2996 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); 2997 crit_point_ff.full += dfixed_const_half(0); 2998 2999 critical_point = dfixed_trunc(crit_point_ff); 3000 3001 if (rdev->disp_priority == 2) { 3002 critical_point = 0; 3003 } 3004 3005 /* 3006 The critical point should never be above max_stop_req-4. Setting 3007 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. 3008 */ 3009 if (max_stop_req - critical_point < 4) 3010 critical_point = 0; 3011 3012 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { 3013 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ 3014 critical_point = 0x10; 3015 } 3016 3017 temp = RREG32(RADEON_GRPH_BUFFER_CNTL); 3018 temp &= ~(RADEON_GRPH_STOP_REQ_MASK); 3019 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3020 temp &= ~(RADEON_GRPH_START_REQ_MASK); 3021 if ((rdev->family == CHIP_R350) && 3022 (stop_req > 0x15)) { 3023 stop_req -= 0x10; 3024 } 3025 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3026 temp |= RADEON_GRPH_BUFFER_SIZE; 3027 temp &= ~(RADEON_GRPH_CRITICAL_CNTL | 3028 RADEON_GRPH_CRITICAL_AT_SOF | 3029 RADEON_GRPH_STOP_CNTL); 3030 /* 3031 Write the result into the register. 3032 */ 3033 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3034 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3035 3036 #if 0 3037 if ((rdev->family == CHIP_RS400) || 3038 (rdev->family == CHIP_RS480)) { 3039 /* attempt to program RS400 disp regs correctly ??? */ 3040 temp = RREG32(RS400_DISP1_REG_CNTL); 3041 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | 3042 RS400_DISP1_STOP_REQ_LEVEL_MASK); 3043 WREG32(RS400_DISP1_REQ_CNTL1, (temp | 3044 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3045 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3046 temp = RREG32(RS400_DMIF_MEM_CNTL1); 3047 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | 3048 RS400_DISP1_CRITICAL_POINT_STOP_MASK); 3049 WREG32(RS400_DMIF_MEM_CNTL1, (temp | 3050 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | 3051 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); 3052 } 3053 #endif 3054 3055 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n", 3056 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ 3057 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); 3058 } 3059 3060 if (mode2) { 3061 u32 grph2_cntl; 3062 stop_req = mode2->hdisplay * pixel_bytes2 / 16; 3063 3064 if (stop_req > max_stop_req) 3065 stop_req = max_stop_req; 3066 3067 /* 3068 Find the drain rate of the display buffer. 3069 */ 3070 temp_ff.full = dfixed_const((16/pixel_bytes2)); 3071 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff); 3072 3073 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); 3074 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); 3075 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3076 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); 3077 if ((rdev->family == CHIP_R350) && 3078 (stop_req > 0x15)) { 3079 stop_req -= 0x10; 3080 } 3081 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3082 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; 3083 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | 3084 RADEON_GRPH_CRITICAL_AT_SOF | 3085 RADEON_GRPH_STOP_CNTL); 3086 3087 if ((rdev->family == CHIP_RS100) || 3088 (rdev->family == CHIP_RS200)) 3089 critical_point2 = 0; 3090 else { 3091 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; 3092 temp_ff.full = dfixed_const(temp); 3093 temp_ff.full = dfixed_mul(mclk_ff, temp_ff); 3094 if (sclk_ff.full < temp_ff.full) 3095 temp_ff.full = sclk_ff.full; 3096 3097 read_return_rate.full = temp_ff.full; 3098 3099 if (mode1) { 3100 temp_ff.full = read_return_rate.full - disp_drain_rate.full; 3101 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff); 3102 } else { 3103 time_disp1_drop_priority.full = 0; 3104 } 3105 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; 3106 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2); 3107 crit_point_ff.full += dfixed_const_half(0); 3108 3109 critical_point2 = dfixed_trunc(crit_point_ff); 3110 3111 if (rdev->disp_priority == 2) { 3112 critical_point2 = 0; 3113 } 3114 3115 if (max_stop_req - critical_point2 < 4) 3116 critical_point2 = 0; 3117 3118 } 3119 3120 if (critical_point2 == 0 && rdev->family == CHIP_R300) { 3121 /* some R300 cards have problem with this set to 0 */ 3122 critical_point2 = 0x10; 3123 } 3124 3125 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3126 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3127 3128 if ((rdev->family == CHIP_RS400) || 3129 (rdev->family == CHIP_RS480)) { 3130 #if 0 3131 /* attempt to program RS400 disp2 regs correctly ??? */ 3132 temp = RREG32(RS400_DISP2_REQ_CNTL1); 3133 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | 3134 RS400_DISP2_STOP_REQ_LEVEL_MASK); 3135 WREG32(RS400_DISP2_REQ_CNTL1, (temp | 3136 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3137 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3138 temp = RREG32(RS400_DISP2_REQ_CNTL2); 3139 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | 3140 RS400_DISP2_CRITICAL_POINT_STOP_MASK); 3141 WREG32(RS400_DISP2_REQ_CNTL2, (temp | 3142 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | 3143 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); 3144 #endif 3145 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); 3146 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); 3147 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); 3148 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); 3149 } 3150 3151 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n", 3152 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); 3153 } 3154 } 3155 3156 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t) 3157 { 3158 DRM_ERROR("pitch %d\n", t->pitch); 3159 DRM_ERROR("use_pitch %d\n", t->use_pitch); 3160 DRM_ERROR("width %d\n", t->width); 3161 DRM_ERROR("width_11 %d\n", t->width_11); 3162 DRM_ERROR("height %d\n", t->height); 3163 DRM_ERROR("height_11 %d\n", t->height_11); 3164 DRM_ERROR("num levels %d\n", t->num_levels); 3165 DRM_ERROR("depth %d\n", t->txdepth); 3166 DRM_ERROR("bpp %d\n", t->cpp); 3167 DRM_ERROR("coordinate type %d\n", t->tex_coord_type); 3168 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); 3169 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); 3170 DRM_ERROR("compress format %d\n", t->compress_format); 3171 } 3172 3173 static int r100_track_compress_size(int compress_format, int w, int h) 3174 { 3175 int block_width, block_height, block_bytes; 3176 int wblocks, hblocks; 3177 int min_wblocks; 3178 int sz; 3179 3180 block_width = 4; 3181 block_height = 4; 3182 3183 switch (compress_format) { 3184 case R100_TRACK_COMP_DXT1: 3185 block_bytes = 8; 3186 min_wblocks = 4; 3187 break; 3188 default: 3189 case R100_TRACK_COMP_DXT35: 3190 block_bytes = 16; 3191 min_wblocks = 2; 3192 break; 3193 } 3194 3195 hblocks = (h + block_height - 1) / block_height; 3196 wblocks = (w + block_width - 1) / block_width; 3197 if (wblocks < min_wblocks) 3198 wblocks = min_wblocks; 3199 sz = wblocks * hblocks * block_bytes; 3200 return sz; 3201 } 3202 3203 static int r100_cs_track_cube(struct radeon_device *rdev, 3204 struct r100_cs_track *track, unsigned idx) 3205 { 3206 unsigned face, w, h; 3207 struct radeon_bo *cube_robj; 3208 unsigned long size; 3209 unsigned compress_format = track->textures[idx].compress_format; 3210 3211 for (face = 0; face < 5; face++) { 3212 cube_robj = track->textures[idx].cube_info[face].robj; 3213 w = track->textures[idx].cube_info[face].width; 3214 h = track->textures[idx].cube_info[face].height; 3215 3216 if (compress_format) { 3217 size = r100_track_compress_size(compress_format, w, h); 3218 } else 3219 size = w * h; 3220 size *= track->textures[idx].cpp; 3221 3222 size += track->textures[idx].cube_info[face].offset; 3223 3224 if (size > radeon_bo_size(cube_robj)) { 3225 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", 3226 size, radeon_bo_size(cube_robj)); 3227 r100_cs_track_texture_print(&track->textures[idx]); 3228 return -1; 3229 } 3230 } 3231 return 0; 3232 } 3233 3234 static int r100_cs_track_texture_check(struct radeon_device *rdev, 3235 struct r100_cs_track *track) 3236 { 3237 struct radeon_bo *robj; 3238 unsigned long size; 3239 unsigned u, i, w, h, d; 3240 int ret; 3241 3242 for (u = 0; u < track->num_texture; u++) { 3243 if (!track->textures[u].enabled) 3244 continue; 3245 if (track->textures[u].lookup_disable) 3246 continue; 3247 robj = track->textures[u].robj; 3248 if (robj == NULL) { 3249 DRM_ERROR("No texture bound to unit %u\n", u); 3250 return -EINVAL; 3251 } 3252 size = 0; 3253 for (i = 0; i <= track->textures[u].num_levels; i++) { 3254 if (track->textures[u].use_pitch) { 3255 if (rdev->family < CHIP_R300) 3256 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); 3257 else 3258 w = track->textures[u].pitch / (1 << i); 3259 } else { 3260 w = track->textures[u].width; 3261 if (rdev->family >= CHIP_RV515) 3262 w |= track->textures[u].width_11; 3263 w = w / (1 << i); 3264 if (track->textures[u].roundup_w) 3265 w = roundup_pow_of_two(w); 3266 } 3267 h = track->textures[u].height; 3268 if (rdev->family >= CHIP_RV515) 3269 h |= track->textures[u].height_11; 3270 h = h / (1 << i); 3271 if (track->textures[u].roundup_h) 3272 h = roundup_pow_of_two(h); 3273 if (track->textures[u].tex_coord_type == 1) { 3274 d = (1 << track->textures[u].txdepth) / (1 << i); 3275 if (!d) 3276 d = 1; 3277 } else { 3278 d = 1; 3279 } 3280 if (track->textures[u].compress_format) { 3281 3282 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d; 3283 /* compressed textures are block based */ 3284 } else 3285 size += w * h * d; 3286 } 3287 size *= track->textures[u].cpp; 3288 3289 switch (track->textures[u].tex_coord_type) { 3290 case 0: 3291 case 1: 3292 break; 3293 case 2: 3294 if (track->separate_cube) { 3295 ret = r100_cs_track_cube(rdev, track, u); 3296 if (ret) 3297 return ret; 3298 } else 3299 size *= 6; 3300 break; 3301 default: 3302 DRM_ERROR("Invalid texture coordinate type %u for unit " 3303 "%u\n", track->textures[u].tex_coord_type, u); 3304 return -EINVAL; 3305 } 3306 if (size > radeon_bo_size(robj)) { 3307 DRM_ERROR("Texture of unit %u needs %lu bytes but is " 3308 "%lu\n", u, size, radeon_bo_size(robj)); 3309 r100_cs_track_texture_print(&track->textures[u]); 3310 return -EINVAL; 3311 } 3312 } 3313 return 0; 3314 } 3315 3316 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) 3317 { 3318 unsigned i; 3319 unsigned long size; 3320 unsigned prim_walk; 3321 unsigned nverts; 3322 unsigned num_cb = track->cb_dirty ? track->num_cb : 0; 3323 3324 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask && 3325 !track->blend_read_enable) 3326 num_cb = 0; 3327 3328 for (i = 0; i < num_cb; i++) { 3329 if (track->cb[i].robj == NULL) { 3330 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); 3331 return -EINVAL; 3332 } 3333 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; 3334 size += track->cb[i].offset; 3335 if (size > radeon_bo_size(track->cb[i].robj)) { 3336 DRM_ERROR("[drm] Buffer too small for color buffer %d " 3337 "(need %lu have %lu) !\n", i, size, 3338 radeon_bo_size(track->cb[i].robj)); 3339 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", 3340 i, track->cb[i].pitch, track->cb[i].cpp, 3341 track->cb[i].offset, track->maxy); 3342 return -EINVAL; 3343 } 3344 } 3345 track->cb_dirty = false; 3346 3347 if (track->zb_dirty && track->z_enabled) { 3348 if (track->zb.robj == NULL) { 3349 DRM_ERROR("[drm] No buffer for z buffer !\n"); 3350 return -EINVAL; 3351 } 3352 size = track->zb.pitch * track->zb.cpp * track->maxy; 3353 size += track->zb.offset; 3354 if (size > radeon_bo_size(track->zb.robj)) { 3355 DRM_ERROR("[drm] Buffer too small for z buffer " 3356 "(need %lu have %lu) !\n", size, 3357 radeon_bo_size(track->zb.robj)); 3358 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", 3359 track->zb.pitch, track->zb.cpp, 3360 track->zb.offset, track->maxy); 3361 return -EINVAL; 3362 } 3363 } 3364 track->zb_dirty = false; 3365 3366 if (track->aa_dirty && track->aaresolve) { 3367 if (track->aa.robj == NULL) { 3368 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i); 3369 return -EINVAL; 3370 } 3371 /* I believe the format comes from colorbuffer0. */ 3372 size = track->aa.pitch * track->cb[0].cpp * track->maxy; 3373 size += track->aa.offset; 3374 if (size > radeon_bo_size(track->aa.robj)) { 3375 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d " 3376 "(need %lu have %lu) !\n", i, size, 3377 radeon_bo_size(track->aa.robj)); 3378 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n", 3379 i, track->aa.pitch, track->cb[0].cpp, 3380 track->aa.offset, track->maxy); 3381 return -EINVAL; 3382 } 3383 } 3384 track->aa_dirty = false; 3385 3386 prim_walk = (track->vap_vf_cntl >> 4) & 0x3; 3387 if (track->vap_vf_cntl & (1 << 14)) { 3388 nverts = track->vap_alt_nverts; 3389 } else { 3390 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; 3391 } 3392 switch (prim_walk) { 3393 case 1: 3394 for (i = 0; i < track->num_arrays; i++) { 3395 size = track->arrays[i].esize * track->max_indx * 4; 3396 if (track->arrays[i].robj == NULL) { 3397 DRM_ERROR("(PW %u) Vertex array %u no buffer " 3398 "bound\n", prim_walk, i); 3399 return -EINVAL; 3400 } 3401 if (size > radeon_bo_size(track->arrays[i].robj)) { 3402 dev_err(rdev->dev, "(PW %u) Vertex array %u " 3403 "need %lu dwords have %lu dwords\n", 3404 prim_walk, i, size >> 2, 3405 radeon_bo_size(track->arrays[i].robj) 3406 >> 2); 3407 DRM_ERROR("Max indices %u\n", track->max_indx); 3408 return -EINVAL; 3409 } 3410 } 3411 break; 3412 case 2: 3413 for (i = 0; i < track->num_arrays; i++) { 3414 size = track->arrays[i].esize * (nverts - 1) * 4; 3415 if (track->arrays[i].robj == NULL) { 3416 DRM_ERROR("(PW %u) Vertex array %u no buffer " 3417 "bound\n", prim_walk, i); 3418 return -EINVAL; 3419 } 3420 if (size > radeon_bo_size(track->arrays[i].robj)) { 3421 dev_err(rdev->dev, "(PW %u) Vertex array %u " 3422 "need %lu dwords have %lu dwords\n", 3423 prim_walk, i, size >> 2, 3424 radeon_bo_size(track->arrays[i].robj) 3425 >> 2); 3426 return -EINVAL; 3427 } 3428 } 3429 break; 3430 case 3: 3431 size = track->vtx_size * nverts; 3432 if (size != track->immd_dwords) { 3433 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", 3434 track->immd_dwords, size); 3435 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", 3436 nverts, track->vtx_size); 3437 return -EINVAL; 3438 } 3439 break; 3440 default: 3441 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", 3442 prim_walk); 3443 return -EINVAL; 3444 } 3445 3446 if (track->tex_dirty) { 3447 track->tex_dirty = false; 3448 return r100_cs_track_texture_check(rdev, track); 3449 } 3450 return 0; 3451 } 3452 3453 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) 3454 { 3455 unsigned i, face; 3456 3457 track->cb_dirty = true; 3458 track->zb_dirty = true; 3459 track->tex_dirty = true; 3460 track->aa_dirty = true; 3461 3462 if (rdev->family < CHIP_R300) { 3463 track->num_cb = 1; 3464 if (rdev->family <= CHIP_RS200) 3465 track->num_texture = 3; 3466 else 3467 track->num_texture = 6; 3468 track->maxy = 2048; 3469 track->separate_cube = 1; 3470 } else { 3471 track->num_cb = 4; 3472 track->num_texture = 16; 3473 track->maxy = 4096; 3474 track->separate_cube = 0; 3475 track->aaresolve = false; 3476 track->aa.robj = NULL; 3477 } 3478 3479 for (i = 0; i < track->num_cb; i++) { 3480 track->cb[i].robj = NULL; 3481 track->cb[i].pitch = 8192; 3482 track->cb[i].cpp = 16; 3483 track->cb[i].offset = 0; 3484 } 3485 track->z_enabled = true; 3486 track->zb.robj = NULL; 3487 track->zb.pitch = 8192; 3488 track->zb.cpp = 4; 3489 track->zb.offset = 0; 3490 track->vtx_size = 0x7F; 3491 track->immd_dwords = 0xFFFFFFFFUL; 3492 track->num_arrays = 11; 3493 track->max_indx = 0x00FFFFFFUL; 3494 for (i = 0; i < track->num_arrays; i++) { 3495 track->arrays[i].robj = NULL; 3496 track->arrays[i].esize = 0x7F; 3497 } 3498 for (i = 0; i < track->num_texture; i++) { 3499 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 3500 track->textures[i].pitch = 16536; 3501 track->textures[i].width = 16536; 3502 track->textures[i].height = 16536; 3503 track->textures[i].width_11 = 1 << 11; 3504 track->textures[i].height_11 = 1 << 11; 3505 track->textures[i].num_levels = 12; 3506 if (rdev->family <= CHIP_RS200) { 3507 track->textures[i].tex_coord_type = 0; 3508 track->textures[i].txdepth = 0; 3509 } else { 3510 track->textures[i].txdepth = 16; 3511 track->textures[i].tex_coord_type = 1; 3512 } 3513 track->textures[i].cpp = 64; 3514 track->textures[i].robj = NULL; 3515 /* CS IB emission code makes sure texture unit are disabled */ 3516 track->textures[i].enabled = false; 3517 track->textures[i].lookup_disable = false; 3518 track->textures[i].roundup_w = true; 3519 track->textures[i].roundup_h = true; 3520 if (track->separate_cube) 3521 for (face = 0; face < 5; face++) { 3522 track->textures[i].cube_info[face].robj = NULL; 3523 track->textures[i].cube_info[face].width = 16536; 3524 track->textures[i].cube_info[face].height = 16536; 3525 track->textures[i].cube_info[face].offset = 0; 3526 } 3527 } 3528 } 3529 3530 int r100_ring_test(struct radeon_device *rdev) 3531 { 3532 uint32_t scratch; 3533 uint32_t tmp = 0; 3534 unsigned i; 3535 int r; 3536 3537 r = radeon_scratch_get(rdev, &scratch); 3538 if (r) { 3539 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 3540 return r; 3541 } 3542 WREG32(scratch, 0xCAFEDEAD); 3543 r = radeon_ring_lock(rdev, 2); 3544 if (r) { 3545 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 3546 radeon_scratch_free(rdev, scratch); 3547 return r; 3548 } 3549 radeon_ring_write(rdev, PACKET0(scratch, 0)); 3550 radeon_ring_write(rdev, 0xDEADBEEF); 3551 radeon_ring_unlock_commit(rdev); 3552 for (i = 0; i < rdev->usec_timeout; i++) { 3553 tmp = RREG32(scratch); 3554 if (tmp == 0xDEADBEEF) { 3555 break; 3556 } 3557 DRM_UDELAY(1); 3558 } 3559 if (i < rdev->usec_timeout) { 3560 DRM_INFO("ring test succeeded in %d usecs\n", i); 3561 } else { 3562 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", 3563 scratch, tmp); 3564 r = -EINVAL; 3565 } 3566 radeon_scratch_free(rdev, scratch); 3567 return r; 3568 } 3569 3570 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3571 { 3572 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1)); 3573 radeon_ring_write(rdev, ib->gpu_addr); 3574 radeon_ring_write(rdev, ib->length_dw); 3575 } 3576 3577 int r100_ib_test(struct radeon_device *rdev) 3578 { 3579 struct radeon_ib *ib; 3580 uint32_t scratch; 3581 uint32_t tmp = 0; 3582 unsigned i; 3583 int r; 3584 3585 r = radeon_scratch_get(rdev, &scratch); 3586 if (r) { 3587 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3588 return r; 3589 } 3590 WREG32(scratch, 0xCAFEDEAD); 3591 r = radeon_ib_get(rdev, &ib); 3592 if (r) { 3593 return r; 3594 } 3595 ib->ptr[0] = PACKET0(scratch, 0); 3596 ib->ptr[1] = 0xDEADBEEF; 3597 ib->ptr[2] = PACKET2(0); 3598 ib->ptr[3] = PACKET2(0); 3599 ib->ptr[4] = PACKET2(0); 3600 ib->ptr[5] = PACKET2(0); 3601 ib->ptr[6] = PACKET2(0); 3602 ib->ptr[7] = PACKET2(0); 3603 ib->length_dw = 8; 3604 r = radeon_ib_schedule(rdev, ib); 3605 if (r) { 3606 radeon_scratch_free(rdev, scratch); 3607 radeon_ib_free(rdev, &ib); 3608 return r; 3609 } 3610 r = radeon_fence_wait(ib->fence, false); 3611 if (r) { 3612 return r; 3613 } 3614 for (i = 0; i < rdev->usec_timeout; i++) { 3615 tmp = RREG32(scratch); 3616 if (tmp == 0xDEADBEEF) { 3617 break; 3618 } 3619 DRM_UDELAY(1); 3620 } 3621 if (i < rdev->usec_timeout) { 3622 DRM_INFO("ib test succeeded in %u usecs\n", i); 3623 } else { 3624 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n", 3625 scratch, tmp); 3626 r = -EINVAL; 3627 } 3628 radeon_scratch_free(rdev, scratch); 3629 radeon_ib_free(rdev, &ib); 3630 return r; 3631 } 3632 3633 void r100_ib_fini(struct radeon_device *rdev) 3634 { 3635 radeon_ib_pool_fini(rdev); 3636 } 3637 3638 int r100_ib_init(struct radeon_device *rdev) 3639 { 3640 int r; 3641 3642 r = radeon_ib_pool_init(rdev); 3643 if (r) { 3644 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r); 3645 r100_ib_fini(rdev); 3646 return r; 3647 } 3648 r = r100_ib_test(rdev); 3649 if (r) { 3650 dev_err(rdev->dev, "failled testing IB (%d).\n", r); 3651 r100_ib_fini(rdev); 3652 return r; 3653 } 3654 return 0; 3655 } 3656 3657 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) 3658 { 3659 /* Shutdown CP we shouldn't need to do that but better be safe than 3660 * sorry 3661 */ 3662 rdev->cp.ready = false; 3663 WREG32(R_000740_CP_CSQ_CNTL, 0); 3664 3665 /* Save few CRTC registers */ 3666 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); 3667 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); 3668 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); 3669 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); 3670 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3671 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); 3672 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); 3673 } 3674 3675 /* Disable VGA aperture access */ 3676 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); 3677 /* Disable cursor, overlay, crtc */ 3678 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); 3679 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | 3680 S_000054_CRTC_DISPLAY_DIS(1)); 3681 WREG32(R_000050_CRTC_GEN_CNTL, 3682 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | 3683 S_000050_CRTC_DISP_REQ_EN_B(1)); 3684 WREG32(R_000420_OV0_SCALE_CNTL, 3685 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); 3686 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); 3687 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3688 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | 3689 S_000360_CUR2_LOCK(1)); 3690 WREG32(R_0003F8_CRTC2_GEN_CNTL, 3691 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | 3692 S_0003F8_CRTC2_DISPLAY_DIS(1) | 3693 S_0003F8_CRTC2_DISP_REQ_EN_B(1)); 3694 WREG32(R_000360_CUR2_OFFSET, 3695 C_000360_CUR2_LOCK & save->CUR2_OFFSET); 3696 } 3697 } 3698 3699 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) 3700 { 3701 /* Update base address for crtc */ 3702 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3703 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3704 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3705 } 3706 /* Restore CRTC registers */ 3707 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); 3708 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); 3709 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); 3710 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3711 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); 3712 } 3713 } 3714 3715 void r100_vga_render_disable(struct radeon_device *rdev) 3716 { 3717 u32 tmp; 3718 3719 tmp = RREG8(R_0003C2_GENMO_WT); 3720 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); 3721 } 3722 3723 static void r100_debugfs(struct radeon_device *rdev) 3724 { 3725 int r; 3726 3727 r = r100_debugfs_mc_info_init(rdev); 3728 if (r) 3729 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n"); 3730 } 3731 3732 static void r100_mc_program(struct radeon_device *rdev) 3733 { 3734 struct r100_mc_save save; 3735 3736 /* Stops all mc clients */ 3737 r100_mc_stop(rdev, &save); 3738 if (rdev->flags & RADEON_IS_AGP) { 3739 WREG32(R_00014C_MC_AGP_LOCATION, 3740 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 3741 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 3742 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 3743 if (rdev->family > CHIP_RV200) 3744 WREG32(R_00015C_AGP_BASE_2, 3745 upper_32_bits(rdev->mc.agp_base) & 0xff); 3746 } else { 3747 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 3748 WREG32(R_000170_AGP_BASE, 0); 3749 if (rdev->family > CHIP_RV200) 3750 WREG32(R_00015C_AGP_BASE_2, 0); 3751 } 3752 /* Wait for mc idle */ 3753 if (r100_mc_wait_for_idle(rdev)) 3754 dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); 3755 /* Program MC, should be a 32bits limited address space */ 3756 WREG32(R_000148_MC_FB_LOCATION, 3757 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 3758 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 3759 r100_mc_resume(rdev, &save); 3760 } 3761 3762 void r100_clock_startup(struct radeon_device *rdev) 3763 { 3764 u32 tmp; 3765 3766 if (radeon_dynclks != -1 && radeon_dynclks) 3767 radeon_legacy_set_clock_gating(rdev, 1); 3768 /* We need to force on some of the block */ 3769 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 3770 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 3771 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) 3772 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); 3773 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 3774 } 3775 3776 static int r100_startup(struct radeon_device *rdev) 3777 { 3778 int r; 3779 3780 /* set common regs */ 3781 r100_set_common_regs(rdev); 3782 /* program mc */ 3783 r100_mc_program(rdev); 3784 /* Resume clock */ 3785 r100_clock_startup(rdev); 3786 /* Initialize GART (initialize after TTM so we can allocate 3787 * memory through TTM but finalize after TTM) */ 3788 r100_enable_bm(rdev); 3789 if (rdev->flags & RADEON_IS_PCI) { 3790 r = r100_pci_gart_enable(rdev); 3791 if (r) 3792 return r; 3793 } 3794 3795 /* allocate wb buffer */ 3796 r = radeon_wb_init(rdev); 3797 if (r) 3798 return r; 3799 3800 /* Enable IRQ */ 3801 r100_irq_set(rdev); 3802 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 3803 /* 1M ring buffer */ 3804 r = r100_cp_init(rdev, 1024 * 1024); 3805 if (r) { 3806 dev_err(rdev->dev, "failled initializing CP (%d).\n", r); 3807 return r; 3808 } 3809 r = r100_ib_init(rdev); 3810 if (r) { 3811 dev_err(rdev->dev, "failled initializing IB (%d).\n", r); 3812 return r; 3813 } 3814 return 0; 3815 } 3816 3817 int r100_resume(struct radeon_device *rdev) 3818 { 3819 /* Make sur GART are not working */ 3820 if (rdev->flags & RADEON_IS_PCI) 3821 r100_pci_gart_disable(rdev); 3822 /* Resume clock before doing reset */ 3823 r100_clock_startup(rdev); 3824 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 3825 if (radeon_asic_reset(rdev)) { 3826 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 3827 RREG32(R_000E40_RBBM_STATUS), 3828 RREG32(R_0007C0_CP_STAT)); 3829 } 3830 /* post */ 3831 radeon_combios_asic_init(rdev->ddev); 3832 /* Resume clock after posting */ 3833 r100_clock_startup(rdev); 3834 /* Initialize surface registers */ 3835 radeon_surface_init(rdev); 3836 return r100_startup(rdev); 3837 } 3838 3839 int r100_suspend(struct radeon_device *rdev) 3840 { 3841 r100_cp_disable(rdev); 3842 radeon_wb_disable(rdev); 3843 r100_irq_disable(rdev); 3844 if (rdev->flags & RADEON_IS_PCI) 3845 r100_pci_gart_disable(rdev); 3846 return 0; 3847 } 3848 3849 void r100_fini(struct radeon_device *rdev) 3850 { 3851 r100_cp_fini(rdev); 3852 radeon_wb_fini(rdev); 3853 r100_ib_fini(rdev); 3854 radeon_gem_fini(rdev); 3855 if (rdev->flags & RADEON_IS_PCI) 3856 r100_pci_gart_fini(rdev); 3857 radeon_agp_fini(rdev); 3858 radeon_irq_kms_fini(rdev); 3859 radeon_fence_driver_fini(rdev); 3860 radeon_bo_fini(rdev); 3861 radeon_atombios_fini(rdev); 3862 kfree(rdev->bios); 3863 rdev->bios = NULL; 3864 } 3865 3866 /* 3867 * Due to how kexec works, it can leave the hw fully initialised when it 3868 * boots the new kernel. However doing our init sequence with the CP and 3869 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup 3870 * do some quick sanity checks and restore sane values to avoid this 3871 * problem. 3872 */ 3873 void r100_restore_sanity(struct radeon_device *rdev) 3874 { 3875 u32 tmp; 3876 3877 tmp = RREG32(RADEON_CP_CSQ_CNTL); 3878 if (tmp) { 3879 WREG32(RADEON_CP_CSQ_CNTL, 0); 3880 } 3881 tmp = RREG32(RADEON_CP_RB_CNTL); 3882 if (tmp) { 3883 WREG32(RADEON_CP_RB_CNTL, 0); 3884 } 3885 tmp = RREG32(RADEON_SCRATCH_UMSK); 3886 if (tmp) { 3887 WREG32(RADEON_SCRATCH_UMSK, 0); 3888 } 3889 } 3890 3891 int r100_init(struct radeon_device *rdev) 3892 { 3893 int r; 3894 3895 /* Register debugfs file specific to this group of asics */ 3896 r100_debugfs(rdev); 3897 /* Disable VGA */ 3898 r100_vga_render_disable(rdev); 3899 /* Initialize scratch registers */ 3900 radeon_scratch_init(rdev); 3901 /* Initialize surface registers */ 3902 radeon_surface_init(rdev); 3903 /* sanity check some register to avoid hangs like after kexec */ 3904 r100_restore_sanity(rdev); 3905 /* TODO: disable VGA need to use VGA request */ 3906 /* BIOS*/ 3907 if (!radeon_get_bios(rdev)) { 3908 if (ASIC_IS_AVIVO(rdev)) 3909 return -EINVAL; 3910 } 3911 if (rdev->is_atom_bios) { 3912 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 3913 return -EINVAL; 3914 } else { 3915 r = radeon_combios_init(rdev); 3916 if (r) 3917 return r; 3918 } 3919 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 3920 if (radeon_asic_reset(rdev)) { 3921 dev_warn(rdev->dev, 3922 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 3923 RREG32(R_000E40_RBBM_STATUS), 3924 RREG32(R_0007C0_CP_STAT)); 3925 } 3926 /* check if cards are posted or not */ 3927 if (radeon_boot_test_post_card(rdev) == false) 3928 return -EINVAL; 3929 /* Set asic errata */ 3930 r100_errata(rdev); 3931 /* Initialize clocks */ 3932 radeon_get_clock_info(rdev->ddev); 3933 /* initialize AGP */ 3934 if (rdev->flags & RADEON_IS_AGP) { 3935 r = radeon_agp_init(rdev); 3936 if (r) { 3937 radeon_agp_disable(rdev); 3938 } 3939 } 3940 /* initialize VRAM */ 3941 r100_mc_init(rdev); 3942 /* Fence driver */ 3943 r = radeon_fence_driver_init(rdev); 3944 if (r) 3945 return r; 3946 r = radeon_irq_kms_init(rdev); 3947 if (r) 3948 return r; 3949 /* Memory manager */ 3950 r = radeon_bo_init(rdev); 3951 if (r) 3952 return r; 3953 if (rdev->flags & RADEON_IS_PCI) { 3954 r = r100_pci_gart_init(rdev); 3955 if (r) 3956 return r; 3957 } 3958 r100_set_safe_registers(rdev); 3959 rdev->accel_working = true; 3960 r = r100_startup(rdev); 3961 if (r) { 3962 /* Somethings want wront with the accel init stop accel */ 3963 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 3964 r100_cp_fini(rdev); 3965 radeon_wb_fini(rdev); 3966 r100_ib_fini(rdev); 3967 radeon_irq_kms_fini(rdev); 3968 if (rdev->flags & RADEON_IS_PCI) 3969 r100_pci_gart_fini(rdev); 3970 rdev->accel_working = false; 3971 } 3972 return 0; 3973 } 3974