1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include <linux/slab.h> 30 #include <drm/drmP.h> 31 #include <drm/radeon_drm.h> 32 #include "radeon_reg.h" 33 #include "radeon.h" 34 #include "radeon_asic.h" 35 #include "r100d.h" 36 #include "rs100d.h" 37 #include "rv200d.h" 38 #include "rv250d.h" 39 #include "atom.h" 40 41 #include <linux/firmware.h> 42 #include <linux/module.h> 43 44 #include "r100_reg_safe.h" 45 #include "rn50_reg_safe.h" 46 47 /* Firmware Names */ 48 #define FIRMWARE_R100 "radeon/R100_cp.bin" 49 #define FIRMWARE_R200 "radeon/R200_cp.bin" 50 #define FIRMWARE_R300 "radeon/R300_cp.bin" 51 #define FIRMWARE_R420 "radeon/R420_cp.bin" 52 #define FIRMWARE_RS690 "radeon/RS690_cp.bin" 53 #define FIRMWARE_RS600 "radeon/RS600_cp.bin" 54 #define FIRMWARE_R520 "radeon/R520_cp.bin" 55 56 MODULE_FIRMWARE(FIRMWARE_R100); 57 MODULE_FIRMWARE(FIRMWARE_R200); 58 MODULE_FIRMWARE(FIRMWARE_R300); 59 MODULE_FIRMWARE(FIRMWARE_R420); 60 MODULE_FIRMWARE(FIRMWARE_RS690); 61 MODULE_FIRMWARE(FIRMWARE_RS600); 62 MODULE_FIRMWARE(FIRMWARE_R520); 63 64 #include "r100_track.h" 65 66 /* This files gather functions specifics to: 67 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 68 * and others in some cases. 69 */ 70 71 static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc) 72 { 73 if (crtc == 0) { 74 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) 75 return true; 76 else 77 return false; 78 } else { 79 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) 80 return true; 81 else 82 return false; 83 } 84 } 85 86 static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc) 87 { 88 u32 vline1, vline2; 89 90 if (crtc == 0) { 91 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 92 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 93 } else { 94 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 95 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 96 } 97 if (vline1 != vline2) 98 return true; 99 else 100 return false; 101 } 102 103 /** 104 * r100_wait_for_vblank - vblank wait asic callback. 105 * 106 * @rdev: radeon_device pointer 107 * @crtc: crtc to wait for vblank on 108 * 109 * Wait for vblank on the requested crtc (r1xx-r4xx). 110 */ 111 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc) 112 { 113 unsigned i = 0; 114 115 if (crtc >= rdev->num_crtc) 116 return; 117 118 if (crtc == 0) { 119 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN)) 120 return; 121 } else { 122 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN)) 123 return; 124 } 125 126 /* depending on when we hit vblank, we may be close to active; if so, 127 * wait for another frame. 128 */ 129 while (r100_is_in_vblank(rdev, crtc)) { 130 if (i++ % 100 == 0) { 131 if (!r100_is_counter_moving(rdev, crtc)) 132 break; 133 } 134 } 135 136 while (!r100_is_in_vblank(rdev, crtc)) { 137 if (i++ % 100 == 0) { 138 if (!r100_is_counter_moving(rdev, crtc)) 139 break; 140 } 141 } 142 } 143 144 /** 145 * r100_pre_page_flip - pre-pageflip callback. 146 * 147 * @rdev: radeon_device pointer 148 * @crtc: crtc to prepare for pageflip on 149 * 150 * Pre-pageflip callback (r1xx-r4xx). 151 * Enables the pageflip irq (vblank irq). 152 */ 153 void r100_pre_page_flip(struct radeon_device *rdev, int crtc) 154 { 155 /* enable the pflip int */ 156 radeon_irq_kms_pflip_irq_get(rdev, crtc); 157 } 158 159 /** 160 * r100_post_page_flip - pos-pageflip callback. 161 * 162 * @rdev: radeon_device pointer 163 * @crtc: crtc to cleanup pageflip on 164 * 165 * Post-pageflip callback (r1xx-r4xx). 166 * Disables the pageflip irq (vblank irq). 167 */ 168 void r100_post_page_flip(struct radeon_device *rdev, int crtc) 169 { 170 /* disable the pflip int */ 171 radeon_irq_kms_pflip_irq_put(rdev, crtc); 172 } 173 174 /** 175 * r100_page_flip - pageflip callback. 176 * 177 * @rdev: radeon_device pointer 178 * @crtc_id: crtc to cleanup pageflip on 179 * @crtc_base: new address of the crtc (GPU MC address) 180 * 181 * Does the actual pageflip (r1xx-r4xx). 182 * During vblank we take the crtc lock and wait for the update_pending 183 * bit to go high, when it does, we release the lock, and allow the 184 * double buffered update to take place. 185 * Returns the current update pending status. 186 */ 187 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 188 { 189 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 190 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; 191 int i; 192 193 /* Lock the graphics update lock */ 194 /* update the scanout addresses */ 195 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 196 197 /* Wait for update_pending to go high. */ 198 for (i = 0; i < rdev->usec_timeout; i++) { 199 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) 200 break; 201 udelay(1); 202 } 203 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 204 205 /* Unlock the lock, so double-buffering can take place inside vblank */ 206 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK; 207 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 208 209 /* Return current update_pending status: */ 210 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET; 211 } 212 213 /** 214 * r100_pm_get_dynpm_state - look up dynpm power state callback. 215 * 216 * @rdev: radeon_device pointer 217 * 218 * Look up the optimal power state based on the 219 * current state of the GPU (r1xx-r5xx). 220 * Used for dynpm only. 221 */ 222 void r100_pm_get_dynpm_state(struct radeon_device *rdev) 223 { 224 int i; 225 rdev->pm.dynpm_can_upclock = true; 226 rdev->pm.dynpm_can_downclock = true; 227 228 switch (rdev->pm.dynpm_planned_action) { 229 case DYNPM_ACTION_MINIMUM: 230 rdev->pm.requested_power_state_index = 0; 231 rdev->pm.dynpm_can_downclock = false; 232 break; 233 case DYNPM_ACTION_DOWNCLOCK: 234 if (rdev->pm.current_power_state_index == 0) { 235 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 236 rdev->pm.dynpm_can_downclock = false; 237 } else { 238 if (rdev->pm.active_crtc_count > 1) { 239 for (i = 0; i < rdev->pm.num_power_states; i++) { 240 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 241 continue; 242 else if (i >= rdev->pm.current_power_state_index) { 243 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 244 break; 245 } else { 246 rdev->pm.requested_power_state_index = i; 247 break; 248 } 249 } 250 } else 251 rdev->pm.requested_power_state_index = 252 rdev->pm.current_power_state_index - 1; 253 } 254 /* don't use the power state if crtcs are active and no display flag is set */ 255 if ((rdev->pm.active_crtc_count > 0) && 256 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & 257 RADEON_PM_MODE_NO_DISPLAY)) { 258 rdev->pm.requested_power_state_index++; 259 } 260 break; 261 case DYNPM_ACTION_UPCLOCK: 262 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 263 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 264 rdev->pm.dynpm_can_upclock = false; 265 } else { 266 if (rdev->pm.active_crtc_count > 1) { 267 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 268 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 269 continue; 270 else if (i <= rdev->pm.current_power_state_index) { 271 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 272 break; 273 } else { 274 rdev->pm.requested_power_state_index = i; 275 break; 276 } 277 } 278 } else 279 rdev->pm.requested_power_state_index = 280 rdev->pm.current_power_state_index + 1; 281 } 282 break; 283 case DYNPM_ACTION_DEFAULT: 284 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 285 rdev->pm.dynpm_can_upclock = false; 286 break; 287 case DYNPM_ACTION_NONE: 288 default: 289 DRM_ERROR("Requested mode for not defined action\n"); 290 return; 291 } 292 /* only one clock mode per power state */ 293 rdev->pm.requested_clock_mode_index = 0; 294 295 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 296 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 297 clock_info[rdev->pm.requested_clock_mode_index].sclk, 298 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 299 clock_info[rdev->pm.requested_clock_mode_index].mclk, 300 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 301 pcie_lanes); 302 } 303 304 /** 305 * r100_pm_init_profile - Initialize power profiles callback. 306 * 307 * @rdev: radeon_device pointer 308 * 309 * Initialize the power states used in profile mode 310 * (r1xx-r3xx). 311 * Used for profile mode only. 312 */ 313 void r100_pm_init_profile(struct radeon_device *rdev) 314 { 315 /* default */ 316 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 317 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 318 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 319 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 320 /* low sh */ 321 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 322 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 323 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 324 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 325 /* mid sh */ 326 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 327 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 328 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 329 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 330 /* high sh */ 331 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 332 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 333 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 334 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 335 /* low mh */ 336 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 337 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 338 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 339 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 340 /* mid mh */ 341 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 342 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 343 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 344 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 345 /* high mh */ 346 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 347 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 348 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 349 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 350 } 351 352 /** 353 * r100_pm_misc - set additional pm hw parameters callback. 354 * 355 * @rdev: radeon_device pointer 356 * 357 * Set non-clock parameters associated with a power state 358 * (voltage, pcie lanes, etc.) (r1xx-r4xx). 359 */ 360 void r100_pm_misc(struct radeon_device *rdev) 361 { 362 int requested_index = rdev->pm.requested_power_state_index; 363 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 364 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 365 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl; 366 367 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { 368 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { 369 tmp = RREG32(voltage->gpio.reg); 370 if (voltage->active_high) 371 tmp |= voltage->gpio.mask; 372 else 373 tmp &= ~(voltage->gpio.mask); 374 WREG32(voltage->gpio.reg, tmp); 375 if (voltage->delay) 376 udelay(voltage->delay); 377 } else { 378 tmp = RREG32(voltage->gpio.reg); 379 if (voltage->active_high) 380 tmp &= ~voltage->gpio.mask; 381 else 382 tmp |= voltage->gpio.mask; 383 WREG32(voltage->gpio.reg, tmp); 384 if (voltage->delay) 385 udelay(voltage->delay); 386 } 387 } 388 389 sclk_cntl = RREG32_PLL(SCLK_CNTL); 390 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2); 391 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3); 392 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL); 393 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3); 394 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { 395 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN; 396 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE) 397 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE; 398 else 399 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE; 400 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) 401 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0); 402 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) 403 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2); 404 } else 405 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN; 406 407 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { 408 sclk_more_cntl |= IO_CG_VOLTAGE_DROP; 409 if (voltage->delay) { 410 sclk_more_cntl |= VOLTAGE_DROP_SYNC; 411 switch (voltage->delay) { 412 case 33: 413 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0); 414 break; 415 case 66: 416 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1); 417 break; 418 case 99: 419 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2); 420 break; 421 case 132: 422 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3); 423 break; 424 } 425 } else 426 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC; 427 } else 428 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP; 429 430 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) 431 sclk_cntl &= ~FORCE_HDP; 432 else 433 sclk_cntl |= FORCE_HDP; 434 435 WREG32_PLL(SCLK_CNTL, sclk_cntl); 436 WREG32_PLL(SCLK_CNTL2, sclk_cntl2); 437 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl); 438 439 /* set pcie lanes */ 440 if ((rdev->flags & RADEON_IS_PCIE) && 441 !(rdev->flags & RADEON_IS_IGP) && 442 rdev->asic->pm.set_pcie_lanes && 443 (ps->pcie_lanes != 444 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { 445 radeon_set_pcie_lanes(rdev, 446 ps->pcie_lanes); 447 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes); 448 } 449 } 450 451 /** 452 * r100_pm_prepare - pre-power state change callback. 453 * 454 * @rdev: radeon_device pointer 455 * 456 * Prepare for a power state change (r1xx-r4xx). 457 */ 458 void r100_pm_prepare(struct radeon_device *rdev) 459 { 460 struct drm_device *ddev = rdev->ddev; 461 struct drm_crtc *crtc; 462 struct radeon_crtc *radeon_crtc; 463 u32 tmp; 464 465 /* disable any active CRTCs */ 466 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 467 radeon_crtc = to_radeon_crtc(crtc); 468 if (radeon_crtc->enabled) { 469 if (radeon_crtc->crtc_id) { 470 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 471 tmp |= RADEON_CRTC2_DISP_REQ_EN_B; 472 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 473 } else { 474 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 475 tmp |= RADEON_CRTC_DISP_REQ_EN_B; 476 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 477 } 478 } 479 } 480 } 481 482 /** 483 * r100_pm_finish - post-power state change callback. 484 * 485 * @rdev: radeon_device pointer 486 * 487 * Clean up after a power state change (r1xx-r4xx). 488 */ 489 void r100_pm_finish(struct radeon_device *rdev) 490 { 491 struct drm_device *ddev = rdev->ddev; 492 struct drm_crtc *crtc; 493 struct radeon_crtc *radeon_crtc; 494 u32 tmp; 495 496 /* enable any active CRTCs */ 497 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 498 radeon_crtc = to_radeon_crtc(crtc); 499 if (radeon_crtc->enabled) { 500 if (radeon_crtc->crtc_id) { 501 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 502 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B; 503 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 504 } else { 505 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 506 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B; 507 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 508 } 509 } 510 } 511 } 512 513 /** 514 * r100_gui_idle - gui idle callback. 515 * 516 * @rdev: radeon_device pointer 517 * 518 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx). 519 * Returns true if idle, false if not. 520 */ 521 bool r100_gui_idle(struct radeon_device *rdev) 522 { 523 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) 524 return false; 525 else 526 return true; 527 } 528 529 /* hpd for digital panel detect/disconnect */ 530 /** 531 * r100_hpd_sense - hpd sense callback. 532 * 533 * @rdev: radeon_device pointer 534 * @hpd: hpd (hotplug detect) pin 535 * 536 * Checks if a digital monitor is connected (r1xx-r4xx). 537 * Returns true if connected, false if not connected. 538 */ 539 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 540 { 541 bool connected = false; 542 543 switch (hpd) { 544 case RADEON_HPD_1: 545 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) 546 connected = true; 547 break; 548 case RADEON_HPD_2: 549 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) 550 connected = true; 551 break; 552 default: 553 break; 554 } 555 return connected; 556 } 557 558 /** 559 * r100_hpd_set_polarity - hpd set polarity callback. 560 * 561 * @rdev: radeon_device pointer 562 * @hpd: hpd (hotplug detect) pin 563 * 564 * Set the polarity of the hpd pin (r1xx-r4xx). 565 */ 566 void r100_hpd_set_polarity(struct radeon_device *rdev, 567 enum radeon_hpd_id hpd) 568 { 569 u32 tmp; 570 bool connected = r100_hpd_sense(rdev, hpd); 571 572 switch (hpd) { 573 case RADEON_HPD_1: 574 tmp = RREG32(RADEON_FP_GEN_CNTL); 575 if (connected) 576 tmp &= ~RADEON_FP_DETECT_INT_POL; 577 else 578 tmp |= RADEON_FP_DETECT_INT_POL; 579 WREG32(RADEON_FP_GEN_CNTL, tmp); 580 break; 581 case RADEON_HPD_2: 582 tmp = RREG32(RADEON_FP2_GEN_CNTL); 583 if (connected) 584 tmp &= ~RADEON_FP2_DETECT_INT_POL; 585 else 586 tmp |= RADEON_FP2_DETECT_INT_POL; 587 WREG32(RADEON_FP2_GEN_CNTL, tmp); 588 break; 589 default: 590 break; 591 } 592 } 593 594 /** 595 * r100_hpd_init - hpd setup callback. 596 * 597 * @rdev: radeon_device pointer 598 * 599 * Setup the hpd pins used by the card (r1xx-r4xx). 600 * Set the polarity, and enable the hpd interrupts. 601 */ 602 void r100_hpd_init(struct radeon_device *rdev) 603 { 604 struct drm_device *dev = rdev->ddev; 605 struct drm_connector *connector; 606 unsigned enable = 0; 607 608 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 609 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 610 enable |= 1 << radeon_connector->hpd.hpd; 611 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 612 } 613 radeon_irq_kms_enable_hpd(rdev, enable); 614 } 615 616 /** 617 * r100_hpd_fini - hpd tear down callback. 618 * 619 * @rdev: radeon_device pointer 620 * 621 * Tear down the hpd pins used by the card (r1xx-r4xx). 622 * Disable the hpd interrupts. 623 */ 624 void r100_hpd_fini(struct radeon_device *rdev) 625 { 626 struct drm_device *dev = rdev->ddev; 627 struct drm_connector *connector; 628 unsigned disable = 0; 629 630 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 631 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 632 disable |= 1 << radeon_connector->hpd.hpd; 633 } 634 radeon_irq_kms_disable_hpd(rdev, disable); 635 } 636 637 /* 638 * PCI GART 639 */ 640 void r100_pci_gart_tlb_flush(struct radeon_device *rdev) 641 { 642 /* TODO: can we do somethings here ? */ 643 /* It seems hw only cache one entry so we should discard this 644 * entry otherwise if first GPU GART read hit this entry it 645 * could end up in wrong address. */ 646 } 647 648 int r100_pci_gart_init(struct radeon_device *rdev) 649 { 650 int r; 651 652 if (rdev->gart.ptr) { 653 WARN(1, "R100 PCI GART already initialized\n"); 654 return 0; 655 } 656 /* Initialize common gart structure */ 657 r = radeon_gart_init(rdev); 658 if (r) 659 return r; 660 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 661 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 662 rdev->asic->gart.set_page = &r100_pci_gart_set_page; 663 return radeon_gart_table_ram_alloc(rdev); 664 } 665 666 int r100_pci_gart_enable(struct radeon_device *rdev) 667 { 668 uint32_t tmp; 669 670 radeon_gart_restore(rdev); 671 /* discard memory request outside of configured range */ 672 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 673 WREG32(RADEON_AIC_CNTL, tmp); 674 /* set address range for PCI address translate */ 675 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); 676 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); 677 /* set PCI GART page-table base address */ 678 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); 679 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; 680 WREG32(RADEON_AIC_CNTL, tmp); 681 r100_pci_gart_tlb_flush(rdev); 682 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n", 683 (unsigned)(rdev->mc.gtt_size >> 20), 684 (unsigned long long)rdev->gart.table_addr); 685 rdev->gart.ready = true; 686 return 0; 687 } 688 689 void r100_pci_gart_disable(struct radeon_device *rdev) 690 { 691 uint32_t tmp; 692 693 /* discard memory request outside of configured range */ 694 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 695 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); 696 WREG32(RADEON_AIC_LO_ADDR, 0); 697 WREG32(RADEON_AIC_HI_ADDR, 0); 698 } 699 700 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 701 { 702 u32 *gtt = rdev->gart.ptr; 703 704 if (i < 0 || i > rdev->gart.num_gpu_pages) { 705 return -EINVAL; 706 } 707 gtt[i] = cpu_to_le32(lower_32_bits(addr)); 708 return 0; 709 } 710 711 void r100_pci_gart_fini(struct radeon_device *rdev) 712 { 713 radeon_gart_fini(rdev); 714 r100_pci_gart_disable(rdev); 715 radeon_gart_table_ram_free(rdev); 716 } 717 718 int r100_irq_set(struct radeon_device *rdev) 719 { 720 uint32_t tmp = 0; 721 722 if (!rdev->irq.installed) { 723 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 724 WREG32(R_000040_GEN_INT_CNTL, 0); 725 return -EINVAL; 726 } 727 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 728 tmp |= RADEON_SW_INT_ENABLE; 729 } 730 if (rdev->irq.crtc_vblank_int[0] || 731 atomic_read(&rdev->irq.pflip[0])) { 732 tmp |= RADEON_CRTC_VBLANK_MASK; 733 } 734 if (rdev->irq.crtc_vblank_int[1] || 735 atomic_read(&rdev->irq.pflip[1])) { 736 tmp |= RADEON_CRTC2_VBLANK_MASK; 737 } 738 if (rdev->irq.hpd[0]) { 739 tmp |= RADEON_FP_DETECT_MASK; 740 } 741 if (rdev->irq.hpd[1]) { 742 tmp |= RADEON_FP2_DETECT_MASK; 743 } 744 WREG32(RADEON_GEN_INT_CNTL, tmp); 745 return 0; 746 } 747 748 void r100_irq_disable(struct radeon_device *rdev) 749 { 750 u32 tmp; 751 752 WREG32(R_000040_GEN_INT_CNTL, 0); 753 /* Wait and acknowledge irq */ 754 mdelay(1); 755 tmp = RREG32(R_000044_GEN_INT_STATUS); 756 WREG32(R_000044_GEN_INT_STATUS, tmp); 757 } 758 759 static uint32_t r100_irq_ack(struct radeon_device *rdev) 760 { 761 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); 762 uint32_t irq_mask = RADEON_SW_INT_TEST | 763 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | 764 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; 765 766 if (irqs) { 767 WREG32(RADEON_GEN_INT_STATUS, irqs); 768 } 769 return irqs & irq_mask; 770 } 771 772 int r100_irq_process(struct radeon_device *rdev) 773 { 774 uint32_t status, msi_rearm; 775 bool queue_hotplug = false; 776 777 status = r100_irq_ack(rdev); 778 if (!status) { 779 return IRQ_NONE; 780 } 781 if (rdev->shutdown) { 782 return IRQ_NONE; 783 } 784 while (status) { 785 /* SW interrupt */ 786 if (status & RADEON_SW_INT_TEST) { 787 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 788 } 789 /* Vertical blank interrupts */ 790 if (status & RADEON_CRTC_VBLANK_STAT) { 791 if (rdev->irq.crtc_vblank_int[0]) { 792 drm_handle_vblank(rdev->ddev, 0); 793 rdev->pm.vblank_sync = true; 794 wake_up(&rdev->irq.vblank_queue); 795 } 796 if (atomic_read(&rdev->irq.pflip[0])) 797 radeon_crtc_handle_flip(rdev, 0); 798 } 799 if (status & RADEON_CRTC2_VBLANK_STAT) { 800 if (rdev->irq.crtc_vblank_int[1]) { 801 drm_handle_vblank(rdev->ddev, 1); 802 rdev->pm.vblank_sync = true; 803 wake_up(&rdev->irq.vblank_queue); 804 } 805 if (atomic_read(&rdev->irq.pflip[1])) 806 radeon_crtc_handle_flip(rdev, 1); 807 } 808 if (status & RADEON_FP_DETECT_STAT) { 809 queue_hotplug = true; 810 DRM_DEBUG("HPD1\n"); 811 } 812 if (status & RADEON_FP2_DETECT_STAT) { 813 queue_hotplug = true; 814 DRM_DEBUG("HPD2\n"); 815 } 816 status = r100_irq_ack(rdev); 817 } 818 if (queue_hotplug) 819 schedule_work(&rdev->hotplug_work); 820 if (rdev->msi_enabled) { 821 switch (rdev->family) { 822 case CHIP_RS400: 823 case CHIP_RS480: 824 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; 825 WREG32(RADEON_AIC_CNTL, msi_rearm); 826 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); 827 break; 828 default: 829 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); 830 break; 831 } 832 } 833 return IRQ_HANDLED; 834 } 835 836 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) 837 { 838 if (crtc == 0) 839 return RREG32(RADEON_CRTC_CRNT_FRAME); 840 else 841 return RREG32(RADEON_CRTC2_CRNT_FRAME); 842 } 843 844 /* Who ever call radeon_fence_emit should call ring_lock and ask 845 * for enough space (today caller are ib schedule and buffer move) */ 846 void r100_fence_ring_emit(struct radeon_device *rdev, 847 struct radeon_fence *fence) 848 { 849 struct radeon_ring *ring = &rdev->ring[fence->ring]; 850 851 /* We have to make sure that caches are flushed before 852 * CPU might read something from VRAM. */ 853 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); 854 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL); 855 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); 856 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL); 857 /* Wait until IDLE & CLEAN */ 858 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 859 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 860 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 861 radeon_ring_write(ring, rdev->config.r100.hdp_cntl | 862 RADEON_HDP_READ_BUFFER_INVALIDATE); 863 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 864 radeon_ring_write(ring, rdev->config.r100.hdp_cntl); 865 /* Emit fence sequence & fire IRQ */ 866 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); 867 radeon_ring_write(ring, fence->seq); 868 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); 869 radeon_ring_write(ring, RADEON_SW_INT_FIRE); 870 } 871 872 bool r100_semaphore_ring_emit(struct radeon_device *rdev, 873 struct radeon_ring *ring, 874 struct radeon_semaphore *semaphore, 875 bool emit_wait) 876 { 877 /* Unused on older asics, since we don't have semaphores or multiple rings */ 878 BUG(); 879 return false; 880 } 881 882 int r100_copy_blit(struct radeon_device *rdev, 883 uint64_t src_offset, 884 uint64_t dst_offset, 885 unsigned num_gpu_pages, 886 struct radeon_fence **fence) 887 { 888 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 889 uint32_t cur_pages; 890 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE; 891 uint32_t pitch; 892 uint32_t stride_pixels; 893 unsigned ndw; 894 int num_loops; 895 int r = 0; 896 897 /* radeon limited to 16k stride */ 898 stride_bytes &= 0x3fff; 899 /* radeon pitch is /64 */ 900 pitch = stride_bytes / 64; 901 stride_pixels = stride_bytes / 4; 902 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191); 903 904 /* Ask for enough room for blit + flush + fence */ 905 ndw = 64 + (10 * num_loops); 906 r = radeon_ring_lock(rdev, ring, ndw); 907 if (r) { 908 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); 909 return -EINVAL; 910 } 911 while (num_gpu_pages > 0) { 912 cur_pages = num_gpu_pages; 913 if (cur_pages > 8191) { 914 cur_pages = 8191; 915 } 916 num_gpu_pages -= cur_pages; 917 918 /* pages are in Y direction - height 919 page width in X direction - width */ 920 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8)); 921 radeon_ring_write(ring, 922 RADEON_GMC_SRC_PITCH_OFFSET_CNTL | 923 RADEON_GMC_DST_PITCH_OFFSET_CNTL | 924 RADEON_GMC_SRC_CLIPPING | 925 RADEON_GMC_DST_CLIPPING | 926 RADEON_GMC_BRUSH_NONE | 927 (RADEON_COLOR_FORMAT_ARGB8888 << 8) | 928 RADEON_GMC_SRC_DATATYPE_COLOR | 929 RADEON_ROP3_S | 930 RADEON_DP_SRC_SOURCE_MEMORY | 931 RADEON_GMC_CLR_CMP_CNTL_DIS | 932 RADEON_GMC_WR_MSK_DIS); 933 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10)); 934 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10)); 935 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); 936 radeon_ring_write(ring, 0); 937 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); 938 radeon_ring_write(ring, num_gpu_pages); 939 radeon_ring_write(ring, num_gpu_pages); 940 radeon_ring_write(ring, cur_pages | (stride_pixels << 16)); 941 } 942 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); 943 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL); 944 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 945 radeon_ring_write(ring, 946 RADEON_WAIT_2D_IDLECLEAN | 947 RADEON_WAIT_HOST_IDLECLEAN | 948 RADEON_WAIT_DMA_GUI_IDLE); 949 if (fence) { 950 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX); 951 } 952 radeon_ring_unlock_commit(rdev, ring); 953 return r; 954 } 955 956 static int r100_cp_wait_for_idle(struct radeon_device *rdev) 957 { 958 unsigned i; 959 u32 tmp; 960 961 for (i = 0; i < rdev->usec_timeout; i++) { 962 tmp = RREG32(R_000E40_RBBM_STATUS); 963 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { 964 return 0; 965 } 966 udelay(1); 967 } 968 return -1; 969 } 970 971 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 972 { 973 int r; 974 975 r = radeon_ring_lock(rdev, ring, 2); 976 if (r) { 977 return; 978 } 979 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); 980 radeon_ring_write(ring, 981 RADEON_ISYNC_ANY2D_IDLE3D | 982 RADEON_ISYNC_ANY3D_IDLE2D | 983 RADEON_ISYNC_WAIT_IDLEGUI | 984 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 985 radeon_ring_unlock_commit(rdev, ring); 986 } 987 988 989 /* Load the microcode for the CP */ 990 static int r100_cp_init_microcode(struct radeon_device *rdev) 991 { 992 const char *fw_name = NULL; 993 int err; 994 995 DRM_DEBUG_KMS("\n"); 996 997 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || 998 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || 999 (rdev->family == CHIP_RS200)) { 1000 DRM_INFO("Loading R100 Microcode\n"); 1001 fw_name = FIRMWARE_R100; 1002 } else if ((rdev->family == CHIP_R200) || 1003 (rdev->family == CHIP_RV250) || 1004 (rdev->family == CHIP_RV280) || 1005 (rdev->family == CHIP_RS300)) { 1006 DRM_INFO("Loading R200 Microcode\n"); 1007 fw_name = FIRMWARE_R200; 1008 } else if ((rdev->family == CHIP_R300) || 1009 (rdev->family == CHIP_R350) || 1010 (rdev->family == CHIP_RV350) || 1011 (rdev->family == CHIP_RV380) || 1012 (rdev->family == CHIP_RS400) || 1013 (rdev->family == CHIP_RS480)) { 1014 DRM_INFO("Loading R300 Microcode\n"); 1015 fw_name = FIRMWARE_R300; 1016 } else if ((rdev->family == CHIP_R420) || 1017 (rdev->family == CHIP_R423) || 1018 (rdev->family == CHIP_RV410)) { 1019 DRM_INFO("Loading R400 Microcode\n"); 1020 fw_name = FIRMWARE_R420; 1021 } else if ((rdev->family == CHIP_RS690) || 1022 (rdev->family == CHIP_RS740)) { 1023 DRM_INFO("Loading RS690/RS740 Microcode\n"); 1024 fw_name = FIRMWARE_RS690; 1025 } else if (rdev->family == CHIP_RS600) { 1026 DRM_INFO("Loading RS600 Microcode\n"); 1027 fw_name = FIRMWARE_RS600; 1028 } else if ((rdev->family == CHIP_RV515) || 1029 (rdev->family == CHIP_R520) || 1030 (rdev->family == CHIP_RV530) || 1031 (rdev->family == CHIP_R580) || 1032 (rdev->family == CHIP_RV560) || 1033 (rdev->family == CHIP_RV570)) { 1034 DRM_INFO("Loading R500 Microcode\n"); 1035 fw_name = FIRMWARE_R520; 1036 } 1037 1038 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); 1039 if (err) { 1040 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", 1041 fw_name); 1042 } else if (rdev->me_fw->size % 8) { 1043 printk(KERN_ERR 1044 "radeon_cp: Bogus length %zu in firmware \"%s\"\n", 1045 rdev->me_fw->size, fw_name); 1046 err = -EINVAL; 1047 release_firmware(rdev->me_fw); 1048 rdev->me_fw = NULL; 1049 } 1050 return err; 1051 } 1052 1053 static void r100_cp_load_microcode(struct radeon_device *rdev) 1054 { 1055 const __be32 *fw_data; 1056 int i, size; 1057 1058 if (r100_gui_wait_for_idle(rdev)) { 1059 printk(KERN_WARNING "Failed to wait GUI idle while " 1060 "programming pipes. Bad things might happen.\n"); 1061 } 1062 1063 if (rdev->me_fw) { 1064 size = rdev->me_fw->size / 4; 1065 fw_data = (const __be32 *)&rdev->me_fw->data[0]; 1066 WREG32(RADEON_CP_ME_RAM_ADDR, 0); 1067 for (i = 0; i < size; i += 2) { 1068 WREG32(RADEON_CP_ME_RAM_DATAH, 1069 be32_to_cpup(&fw_data[i])); 1070 WREG32(RADEON_CP_ME_RAM_DATAL, 1071 be32_to_cpup(&fw_data[i + 1])); 1072 } 1073 } 1074 } 1075 1076 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) 1077 { 1078 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1079 unsigned rb_bufsz; 1080 unsigned rb_blksz; 1081 unsigned max_fetch; 1082 unsigned pre_write_timer; 1083 unsigned pre_write_limit; 1084 unsigned indirect2_start; 1085 unsigned indirect1_start; 1086 uint32_t tmp; 1087 int r; 1088 1089 if (r100_debugfs_cp_init(rdev)) { 1090 DRM_ERROR("Failed to register debugfs file for CP !\n"); 1091 } 1092 if (!rdev->me_fw) { 1093 r = r100_cp_init_microcode(rdev); 1094 if (r) { 1095 DRM_ERROR("Failed to load firmware!\n"); 1096 return r; 1097 } 1098 } 1099 1100 /* Align ring size */ 1101 rb_bufsz = order_base_2(ring_size / 8); 1102 ring_size = (1 << (rb_bufsz + 1)) * 4; 1103 r100_cp_load_microcode(rdev); 1104 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET, 1105 RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR, 1106 RADEON_CP_PACKET2); 1107 if (r) { 1108 return r; 1109 } 1110 /* Each time the cp read 1024 bytes (16 dword/quadword) update 1111 * the rptr copy in system ram */ 1112 rb_blksz = 9; 1113 /* cp will read 128bytes at a time (4 dwords) */ 1114 max_fetch = 1; 1115 ring->align_mask = 16 - 1; 1116 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ 1117 pre_write_timer = 64; 1118 /* Force CP_RB_WPTR write if written more than one time before the 1119 * delay expire 1120 */ 1121 pre_write_limit = 0; 1122 /* Setup the cp cache like this (cache size is 96 dwords) : 1123 * RING 0 to 15 1124 * INDIRECT1 16 to 79 1125 * INDIRECT2 80 to 95 1126 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1127 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) 1128 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1129 * Idea being that most of the gpu cmd will be through indirect1 buffer 1130 * so it gets the bigger cache. 1131 */ 1132 indirect2_start = 80; 1133 indirect1_start = 16; 1134 /* cp setup */ 1135 WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); 1136 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | 1137 REG_SET(RADEON_RB_BLKSZ, rb_blksz) | 1138 REG_SET(RADEON_MAX_FETCH, max_fetch)); 1139 #ifdef __BIG_ENDIAN 1140 tmp |= RADEON_BUF_SWAP_32BIT; 1141 #endif 1142 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); 1143 1144 /* Set ring address */ 1145 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr); 1146 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr); 1147 /* Force read & write ptr to 0 */ 1148 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); 1149 WREG32(RADEON_CP_RB_RPTR_WR, 0); 1150 ring->wptr = 0; 1151 WREG32(RADEON_CP_RB_WPTR, ring->wptr); 1152 1153 /* set the wb address whether it's enabled or not */ 1154 WREG32(R_00070C_CP_RB_RPTR_ADDR, 1155 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); 1156 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); 1157 1158 if (rdev->wb.enabled) 1159 WREG32(R_000770_SCRATCH_UMSK, 0xff); 1160 else { 1161 tmp |= RADEON_RB_NO_UPDATE; 1162 WREG32(R_000770_SCRATCH_UMSK, 0); 1163 } 1164 1165 WREG32(RADEON_CP_RB_CNTL, tmp); 1166 udelay(10); 1167 ring->rptr = RREG32(RADEON_CP_RB_RPTR); 1168 /* Set cp mode to bus mastering & enable cp*/ 1169 WREG32(RADEON_CP_CSQ_MODE, 1170 REG_SET(RADEON_INDIRECT2_START, indirect2_start) | 1171 REG_SET(RADEON_INDIRECT1_START, indirect1_start)); 1172 WREG32(RADEON_CP_RB_WPTR_DELAY, 0); 1173 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); 1174 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); 1175 1176 /* at this point everything should be setup correctly to enable master */ 1177 pci_set_master(rdev->pdev); 1178 1179 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1180 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 1181 if (r) { 1182 DRM_ERROR("radeon: cp isn't working (%d).\n", r); 1183 return r; 1184 } 1185 ring->ready = true; 1186 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 1187 1188 if (!ring->rptr_save_reg /* not resuming from suspend */ 1189 && radeon_ring_supports_scratch_reg(rdev, ring)) { 1190 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 1191 if (r) { 1192 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 1193 ring->rptr_save_reg = 0; 1194 } 1195 } 1196 return 0; 1197 } 1198 1199 void r100_cp_fini(struct radeon_device *rdev) 1200 { 1201 if (r100_cp_wait_for_idle(rdev)) { 1202 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); 1203 } 1204 /* Disable ring */ 1205 r100_cp_disable(rdev); 1206 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg); 1207 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1208 DRM_INFO("radeon: cp finalized\n"); 1209 } 1210 1211 void r100_cp_disable(struct radeon_device *rdev) 1212 { 1213 /* Disable ring */ 1214 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1215 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1216 WREG32(RADEON_CP_CSQ_MODE, 0); 1217 WREG32(RADEON_CP_CSQ_CNTL, 0); 1218 WREG32(R_000770_SCRATCH_UMSK, 0); 1219 if (r100_gui_wait_for_idle(rdev)) { 1220 printk(KERN_WARNING "Failed to wait GUI idle while " 1221 "programming pipes. Bad things might happen.\n"); 1222 } 1223 } 1224 1225 /* 1226 * CS functions 1227 */ 1228 int r100_reloc_pitch_offset(struct radeon_cs_parser *p, 1229 struct radeon_cs_packet *pkt, 1230 unsigned idx, 1231 unsigned reg) 1232 { 1233 int r; 1234 u32 tile_flags = 0; 1235 u32 tmp; 1236 struct radeon_cs_reloc *reloc; 1237 u32 value; 1238 1239 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1240 if (r) { 1241 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1242 idx, reg); 1243 radeon_cs_dump_packet(p, pkt); 1244 return r; 1245 } 1246 1247 value = radeon_get_ib_value(p, idx); 1248 tmp = value & 0x003fffff; 1249 tmp += (((u32)reloc->lobj.gpu_offset) >> 10); 1250 1251 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1252 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1253 tile_flags |= RADEON_DST_TILE_MACRO; 1254 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { 1255 if (reg == RADEON_SRC_PITCH_OFFSET) { 1256 DRM_ERROR("Cannot src blit from microtiled surface\n"); 1257 radeon_cs_dump_packet(p, pkt); 1258 return -EINVAL; 1259 } 1260 tile_flags |= RADEON_DST_TILE_MICRO; 1261 } 1262 1263 tmp |= tile_flags; 1264 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp; 1265 } else 1266 p->ib.ptr[idx] = (value & 0xffc00000) | tmp; 1267 return 0; 1268 } 1269 1270 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, 1271 struct radeon_cs_packet *pkt, 1272 int idx) 1273 { 1274 unsigned c, i; 1275 struct radeon_cs_reloc *reloc; 1276 struct r100_cs_track *track; 1277 int r = 0; 1278 volatile uint32_t *ib; 1279 u32 idx_value; 1280 1281 ib = p->ib.ptr; 1282 track = (struct r100_cs_track *)p->track; 1283 c = radeon_get_ib_value(p, idx++) & 0x1F; 1284 if (c > 16) { 1285 DRM_ERROR("Only 16 vertex buffers are allowed %d\n", 1286 pkt->opcode); 1287 radeon_cs_dump_packet(p, pkt); 1288 return -EINVAL; 1289 } 1290 track->num_arrays = c; 1291 for (i = 0; i < (c - 1); i+=2, idx+=3) { 1292 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1293 if (r) { 1294 DRM_ERROR("No reloc for packet3 %d\n", 1295 pkt->opcode); 1296 radeon_cs_dump_packet(p, pkt); 1297 return r; 1298 } 1299 idx_value = radeon_get_ib_value(p, idx); 1300 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 1301 1302 track->arrays[i + 0].esize = idx_value >> 8; 1303 track->arrays[i + 0].robj = reloc->robj; 1304 track->arrays[i + 0].esize &= 0x7F; 1305 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1306 if (r) { 1307 DRM_ERROR("No reloc for packet3 %d\n", 1308 pkt->opcode); 1309 radeon_cs_dump_packet(p, pkt); 1310 return r; 1311 } 1312 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset); 1313 track->arrays[i + 1].robj = reloc->robj; 1314 track->arrays[i + 1].esize = idx_value >> 24; 1315 track->arrays[i + 1].esize &= 0x7F; 1316 } 1317 if (c & 1) { 1318 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1319 if (r) { 1320 DRM_ERROR("No reloc for packet3 %d\n", 1321 pkt->opcode); 1322 radeon_cs_dump_packet(p, pkt); 1323 return r; 1324 } 1325 idx_value = radeon_get_ib_value(p, idx); 1326 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 1327 track->arrays[i + 0].robj = reloc->robj; 1328 track->arrays[i + 0].esize = idx_value >> 8; 1329 track->arrays[i + 0].esize &= 0x7F; 1330 } 1331 return r; 1332 } 1333 1334 int r100_cs_parse_packet0(struct radeon_cs_parser *p, 1335 struct radeon_cs_packet *pkt, 1336 const unsigned *auth, unsigned n, 1337 radeon_packet0_check_t check) 1338 { 1339 unsigned reg; 1340 unsigned i, j, m; 1341 unsigned idx; 1342 int r; 1343 1344 idx = pkt->idx + 1; 1345 reg = pkt->reg; 1346 /* Check that register fall into register range 1347 * determined by the number of entry (n) in the 1348 * safe register bitmap. 1349 */ 1350 if (pkt->one_reg_wr) { 1351 if ((reg >> 7) > n) { 1352 return -EINVAL; 1353 } 1354 } else { 1355 if (((reg + (pkt->count << 2)) >> 7) > n) { 1356 return -EINVAL; 1357 } 1358 } 1359 for (i = 0; i <= pkt->count; i++, idx++) { 1360 j = (reg >> 7); 1361 m = 1 << ((reg >> 2) & 31); 1362 if (auth[j] & m) { 1363 r = check(p, pkt, idx, reg); 1364 if (r) { 1365 return r; 1366 } 1367 } 1368 if (pkt->one_reg_wr) { 1369 if (!(auth[j] & m)) { 1370 break; 1371 } 1372 } else { 1373 reg += 4; 1374 } 1375 } 1376 return 0; 1377 } 1378 1379 /** 1380 * r100_cs_packet_next_vline() - parse userspace VLINE packet 1381 * @parser: parser structure holding parsing context. 1382 * 1383 * Userspace sends a special sequence for VLINE waits. 1384 * PACKET0 - VLINE_START_END + value 1385 * PACKET0 - WAIT_UNTIL +_value 1386 * RELOC (P3) - crtc_id in reloc. 1387 * 1388 * This function parses this and relocates the VLINE START END 1389 * and WAIT UNTIL packets to the correct crtc. 1390 * It also detects a switched off crtc and nulls out the 1391 * wait in that case. 1392 */ 1393 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) 1394 { 1395 struct drm_mode_object *obj; 1396 struct drm_crtc *crtc; 1397 struct radeon_crtc *radeon_crtc; 1398 struct radeon_cs_packet p3reloc, waitreloc; 1399 int crtc_id; 1400 int r; 1401 uint32_t header, h_idx, reg; 1402 volatile uint32_t *ib; 1403 1404 ib = p->ib.ptr; 1405 1406 /* parse the wait until */ 1407 r = radeon_cs_packet_parse(p, &waitreloc, p->idx); 1408 if (r) 1409 return r; 1410 1411 /* check its a wait until and only 1 count */ 1412 if (waitreloc.reg != RADEON_WAIT_UNTIL || 1413 waitreloc.count != 0) { 1414 DRM_ERROR("vline wait had illegal wait until segment\n"); 1415 return -EINVAL; 1416 } 1417 1418 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { 1419 DRM_ERROR("vline wait had illegal wait until\n"); 1420 return -EINVAL; 1421 } 1422 1423 /* jump over the NOP */ 1424 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); 1425 if (r) 1426 return r; 1427 1428 h_idx = p->idx - 2; 1429 p->idx += waitreloc.count + 2; 1430 p->idx += p3reloc.count + 2; 1431 1432 header = radeon_get_ib_value(p, h_idx); 1433 crtc_id = radeon_get_ib_value(p, h_idx + 5); 1434 reg = R100_CP_PACKET0_GET_REG(header); 1435 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); 1436 if (!obj) { 1437 DRM_ERROR("cannot find crtc %d\n", crtc_id); 1438 return -ENOENT; 1439 } 1440 crtc = obj_to_crtc(obj); 1441 radeon_crtc = to_radeon_crtc(crtc); 1442 crtc_id = radeon_crtc->crtc_id; 1443 1444 if (!crtc->enabled) { 1445 /* if the CRTC isn't enabled - we need to nop out the wait until */ 1446 ib[h_idx + 2] = PACKET2(0); 1447 ib[h_idx + 3] = PACKET2(0); 1448 } else if (crtc_id == 1) { 1449 switch (reg) { 1450 case AVIVO_D1MODE_VLINE_START_END: 1451 header &= ~R300_CP_PACKET0_REG_MASK; 1452 header |= AVIVO_D2MODE_VLINE_START_END >> 2; 1453 break; 1454 case RADEON_CRTC_GUI_TRIG_VLINE: 1455 header &= ~R300_CP_PACKET0_REG_MASK; 1456 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; 1457 break; 1458 default: 1459 DRM_ERROR("unknown crtc reloc\n"); 1460 return -EINVAL; 1461 } 1462 ib[h_idx] = header; 1463 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; 1464 } 1465 1466 return 0; 1467 } 1468 1469 static int r100_get_vtx_size(uint32_t vtx_fmt) 1470 { 1471 int vtx_size; 1472 vtx_size = 2; 1473 /* ordered according to bits in spec */ 1474 if (vtx_fmt & RADEON_SE_VTX_FMT_W0) 1475 vtx_size++; 1476 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) 1477 vtx_size += 3; 1478 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) 1479 vtx_size++; 1480 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) 1481 vtx_size++; 1482 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) 1483 vtx_size += 3; 1484 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) 1485 vtx_size++; 1486 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) 1487 vtx_size++; 1488 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) 1489 vtx_size += 2; 1490 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) 1491 vtx_size += 2; 1492 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) 1493 vtx_size++; 1494 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) 1495 vtx_size += 2; 1496 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) 1497 vtx_size++; 1498 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) 1499 vtx_size += 2; 1500 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) 1501 vtx_size++; 1502 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) 1503 vtx_size++; 1504 /* blend weight */ 1505 if (vtx_fmt & (0x7 << 15)) 1506 vtx_size += (vtx_fmt >> 15) & 0x7; 1507 if (vtx_fmt & RADEON_SE_VTX_FMT_N0) 1508 vtx_size += 3; 1509 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) 1510 vtx_size += 2; 1511 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) 1512 vtx_size++; 1513 if (vtx_fmt & RADEON_SE_VTX_FMT_W1) 1514 vtx_size++; 1515 if (vtx_fmt & RADEON_SE_VTX_FMT_N1) 1516 vtx_size++; 1517 if (vtx_fmt & RADEON_SE_VTX_FMT_Z) 1518 vtx_size++; 1519 return vtx_size; 1520 } 1521 1522 static int r100_packet0_check(struct radeon_cs_parser *p, 1523 struct radeon_cs_packet *pkt, 1524 unsigned idx, unsigned reg) 1525 { 1526 struct radeon_cs_reloc *reloc; 1527 struct r100_cs_track *track; 1528 volatile uint32_t *ib; 1529 uint32_t tmp; 1530 int r; 1531 int i, face; 1532 u32 tile_flags = 0; 1533 u32 idx_value; 1534 1535 ib = p->ib.ptr; 1536 track = (struct r100_cs_track *)p->track; 1537 1538 idx_value = radeon_get_ib_value(p, idx); 1539 1540 switch (reg) { 1541 case RADEON_CRTC_GUI_TRIG_VLINE: 1542 r = r100_cs_packet_parse_vline(p); 1543 if (r) { 1544 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1545 idx, reg); 1546 radeon_cs_dump_packet(p, pkt); 1547 return r; 1548 } 1549 break; 1550 /* FIXME: only allow PACKET3 blit? easier to check for out of 1551 * range access */ 1552 case RADEON_DST_PITCH_OFFSET: 1553 case RADEON_SRC_PITCH_OFFSET: 1554 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 1555 if (r) 1556 return r; 1557 break; 1558 case RADEON_RB3D_DEPTHOFFSET: 1559 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1560 if (r) { 1561 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1562 idx, reg); 1563 radeon_cs_dump_packet(p, pkt); 1564 return r; 1565 } 1566 track->zb.robj = reloc->robj; 1567 track->zb.offset = idx_value; 1568 track->zb_dirty = true; 1569 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1570 break; 1571 case RADEON_RB3D_COLOROFFSET: 1572 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1573 if (r) { 1574 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1575 idx, reg); 1576 radeon_cs_dump_packet(p, pkt); 1577 return r; 1578 } 1579 track->cb[0].robj = reloc->robj; 1580 track->cb[0].offset = idx_value; 1581 track->cb_dirty = true; 1582 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1583 break; 1584 case RADEON_PP_TXOFFSET_0: 1585 case RADEON_PP_TXOFFSET_1: 1586 case RADEON_PP_TXOFFSET_2: 1587 i = (reg - RADEON_PP_TXOFFSET_0) / 24; 1588 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1589 if (r) { 1590 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1591 idx, reg); 1592 radeon_cs_dump_packet(p, pkt); 1593 return r; 1594 } 1595 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1596 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1597 tile_flags |= RADEON_TXO_MACRO_TILE; 1598 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 1599 tile_flags |= RADEON_TXO_MICRO_TILE_X2; 1600 1601 tmp = idx_value & ~(0x7 << 2); 1602 tmp |= tile_flags; 1603 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset); 1604 } else 1605 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1606 track->textures[i].robj = reloc->robj; 1607 track->tex_dirty = true; 1608 break; 1609 case RADEON_PP_CUBIC_OFFSET_T0_0: 1610 case RADEON_PP_CUBIC_OFFSET_T0_1: 1611 case RADEON_PP_CUBIC_OFFSET_T0_2: 1612 case RADEON_PP_CUBIC_OFFSET_T0_3: 1613 case RADEON_PP_CUBIC_OFFSET_T0_4: 1614 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; 1615 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1616 if (r) { 1617 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1618 idx, reg); 1619 radeon_cs_dump_packet(p, pkt); 1620 return r; 1621 } 1622 track->textures[0].cube_info[i].offset = idx_value; 1623 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1624 track->textures[0].cube_info[i].robj = reloc->robj; 1625 track->tex_dirty = true; 1626 break; 1627 case RADEON_PP_CUBIC_OFFSET_T1_0: 1628 case RADEON_PP_CUBIC_OFFSET_T1_1: 1629 case RADEON_PP_CUBIC_OFFSET_T1_2: 1630 case RADEON_PP_CUBIC_OFFSET_T1_3: 1631 case RADEON_PP_CUBIC_OFFSET_T1_4: 1632 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; 1633 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1634 if (r) { 1635 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1636 idx, reg); 1637 radeon_cs_dump_packet(p, pkt); 1638 return r; 1639 } 1640 track->textures[1].cube_info[i].offset = idx_value; 1641 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1642 track->textures[1].cube_info[i].robj = reloc->robj; 1643 track->tex_dirty = true; 1644 break; 1645 case RADEON_PP_CUBIC_OFFSET_T2_0: 1646 case RADEON_PP_CUBIC_OFFSET_T2_1: 1647 case RADEON_PP_CUBIC_OFFSET_T2_2: 1648 case RADEON_PP_CUBIC_OFFSET_T2_3: 1649 case RADEON_PP_CUBIC_OFFSET_T2_4: 1650 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; 1651 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1652 if (r) { 1653 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1654 idx, reg); 1655 radeon_cs_dump_packet(p, pkt); 1656 return r; 1657 } 1658 track->textures[2].cube_info[i].offset = idx_value; 1659 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1660 track->textures[2].cube_info[i].robj = reloc->robj; 1661 track->tex_dirty = true; 1662 break; 1663 case RADEON_RE_WIDTH_HEIGHT: 1664 track->maxy = ((idx_value >> 16) & 0x7FF); 1665 track->cb_dirty = true; 1666 track->zb_dirty = true; 1667 break; 1668 case RADEON_RB3D_COLORPITCH: 1669 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1670 if (r) { 1671 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1672 idx, reg); 1673 radeon_cs_dump_packet(p, pkt); 1674 return r; 1675 } 1676 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1677 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1678 tile_flags |= RADEON_COLOR_TILE_ENABLE; 1679 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 1680 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; 1681 1682 tmp = idx_value & ~(0x7 << 16); 1683 tmp |= tile_flags; 1684 ib[idx] = tmp; 1685 } else 1686 ib[idx] = idx_value; 1687 1688 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; 1689 track->cb_dirty = true; 1690 break; 1691 case RADEON_RB3D_DEPTHPITCH: 1692 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; 1693 track->zb_dirty = true; 1694 break; 1695 case RADEON_RB3D_CNTL: 1696 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { 1697 case 7: 1698 case 8: 1699 case 9: 1700 case 11: 1701 case 12: 1702 track->cb[0].cpp = 1; 1703 break; 1704 case 3: 1705 case 4: 1706 case 15: 1707 track->cb[0].cpp = 2; 1708 break; 1709 case 6: 1710 track->cb[0].cpp = 4; 1711 break; 1712 default: 1713 DRM_ERROR("Invalid color buffer format (%d) !\n", 1714 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); 1715 return -EINVAL; 1716 } 1717 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); 1718 track->cb_dirty = true; 1719 track->zb_dirty = true; 1720 break; 1721 case RADEON_RB3D_ZSTENCILCNTL: 1722 switch (idx_value & 0xf) { 1723 case 0: 1724 track->zb.cpp = 2; 1725 break; 1726 case 2: 1727 case 3: 1728 case 4: 1729 case 5: 1730 case 9: 1731 case 11: 1732 track->zb.cpp = 4; 1733 break; 1734 default: 1735 break; 1736 } 1737 track->zb_dirty = true; 1738 break; 1739 case RADEON_RB3D_ZPASS_ADDR: 1740 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1741 if (r) { 1742 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1743 idx, reg); 1744 radeon_cs_dump_packet(p, pkt); 1745 return r; 1746 } 1747 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1748 break; 1749 case RADEON_PP_CNTL: 1750 { 1751 uint32_t temp = idx_value >> 4; 1752 for (i = 0; i < track->num_texture; i++) 1753 track->textures[i].enabled = !!(temp & (1 << i)); 1754 track->tex_dirty = true; 1755 } 1756 break; 1757 case RADEON_SE_VF_CNTL: 1758 track->vap_vf_cntl = idx_value; 1759 break; 1760 case RADEON_SE_VTX_FMT: 1761 track->vtx_size = r100_get_vtx_size(idx_value); 1762 break; 1763 case RADEON_PP_TEX_SIZE_0: 1764 case RADEON_PP_TEX_SIZE_1: 1765 case RADEON_PP_TEX_SIZE_2: 1766 i = (reg - RADEON_PP_TEX_SIZE_0) / 8; 1767 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; 1768 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; 1769 track->tex_dirty = true; 1770 break; 1771 case RADEON_PP_TEX_PITCH_0: 1772 case RADEON_PP_TEX_PITCH_1: 1773 case RADEON_PP_TEX_PITCH_2: 1774 i = (reg - RADEON_PP_TEX_PITCH_0) / 8; 1775 track->textures[i].pitch = idx_value + 32; 1776 track->tex_dirty = true; 1777 break; 1778 case RADEON_PP_TXFILTER_0: 1779 case RADEON_PP_TXFILTER_1: 1780 case RADEON_PP_TXFILTER_2: 1781 i = (reg - RADEON_PP_TXFILTER_0) / 24; 1782 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) 1783 >> RADEON_MAX_MIP_LEVEL_SHIFT); 1784 tmp = (idx_value >> 23) & 0x7; 1785 if (tmp == 2 || tmp == 6) 1786 track->textures[i].roundup_w = false; 1787 tmp = (idx_value >> 27) & 0x7; 1788 if (tmp == 2 || tmp == 6) 1789 track->textures[i].roundup_h = false; 1790 track->tex_dirty = true; 1791 break; 1792 case RADEON_PP_TXFORMAT_0: 1793 case RADEON_PP_TXFORMAT_1: 1794 case RADEON_PP_TXFORMAT_2: 1795 i = (reg - RADEON_PP_TXFORMAT_0) / 24; 1796 if (idx_value & RADEON_TXFORMAT_NON_POWER2) { 1797 track->textures[i].use_pitch = 1; 1798 } else { 1799 track->textures[i].use_pitch = 0; 1800 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); 1801 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); 1802 } 1803 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) 1804 track->textures[i].tex_coord_type = 2; 1805 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { 1806 case RADEON_TXFORMAT_I8: 1807 case RADEON_TXFORMAT_RGB332: 1808 case RADEON_TXFORMAT_Y8: 1809 track->textures[i].cpp = 1; 1810 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1811 break; 1812 case RADEON_TXFORMAT_AI88: 1813 case RADEON_TXFORMAT_ARGB1555: 1814 case RADEON_TXFORMAT_RGB565: 1815 case RADEON_TXFORMAT_ARGB4444: 1816 case RADEON_TXFORMAT_VYUY422: 1817 case RADEON_TXFORMAT_YVYU422: 1818 case RADEON_TXFORMAT_SHADOW16: 1819 case RADEON_TXFORMAT_LDUDV655: 1820 case RADEON_TXFORMAT_DUDV88: 1821 track->textures[i].cpp = 2; 1822 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1823 break; 1824 case RADEON_TXFORMAT_ARGB8888: 1825 case RADEON_TXFORMAT_RGBA8888: 1826 case RADEON_TXFORMAT_SHADOW32: 1827 case RADEON_TXFORMAT_LDUDUV8888: 1828 track->textures[i].cpp = 4; 1829 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1830 break; 1831 case RADEON_TXFORMAT_DXT1: 1832 track->textures[i].cpp = 1; 1833 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 1834 break; 1835 case RADEON_TXFORMAT_DXT23: 1836 case RADEON_TXFORMAT_DXT45: 1837 track->textures[i].cpp = 1; 1838 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 1839 break; 1840 } 1841 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); 1842 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); 1843 track->tex_dirty = true; 1844 break; 1845 case RADEON_PP_CUBIC_FACES_0: 1846 case RADEON_PP_CUBIC_FACES_1: 1847 case RADEON_PP_CUBIC_FACES_2: 1848 tmp = idx_value; 1849 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; 1850 for (face = 0; face < 4; face++) { 1851 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); 1852 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); 1853 } 1854 track->tex_dirty = true; 1855 break; 1856 default: 1857 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", 1858 reg, idx); 1859 return -EINVAL; 1860 } 1861 return 0; 1862 } 1863 1864 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 1865 struct radeon_cs_packet *pkt, 1866 struct radeon_bo *robj) 1867 { 1868 unsigned idx; 1869 u32 value; 1870 idx = pkt->idx + 1; 1871 value = radeon_get_ib_value(p, idx + 2); 1872 if ((value + 1) > radeon_bo_size(robj)) { 1873 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " 1874 "(need %u have %lu) !\n", 1875 value + 1, 1876 radeon_bo_size(robj)); 1877 return -EINVAL; 1878 } 1879 return 0; 1880 } 1881 1882 static int r100_packet3_check(struct radeon_cs_parser *p, 1883 struct radeon_cs_packet *pkt) 1884 { 1885 struct radeon_cs_reloc *reloc; 1886 struct r100_cs_track *track; 1887 unsigned idx; 1888 volatile uint32_t *ib; 1889 int r; 1890 1891 ib = p->ib.ptr; 1892 idx = pkt->idx + 1; 1893 track = (struct r100_cs_track *)p->track; 1894 switch (pkt->opcode) { 1895 case PACKET3_3D_LOAD_VBPNTR: 1896 r = r100_packet3_load_vbpntr(p, pkt, idx); 1897 if (r) 1898 return r; 1899 break; 1900 case PACKET3_INDX_BUFFER: 1901 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1902 if (r) { 1903 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1904 radeon_cs_dump_packet(p, pkt); 1905 return r; 1906 } 1907 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset); 1908 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1909 if (r) { 1910 return r; 1911 } 1912 break; 1913 case 0x23: 1914 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ 1915 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1916 if (r) { 1917 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1918 radeon_cs_dump_packet(p, pkt); 1919 return r; 1920 } 1921 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset); 1922 track->num_arrays = 1; 1923 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); 1924 1925 track->arrays[0].robj = reloc->robj; 1926 track->arrays[0].esize = track->vtx_size; 1927 1928 track->max_indx = radeon_get_ib_value(p, idx+1); 1929 1930 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); 1931 track->immd_dwords = pkt->count - 1; 1932 r = r100_cs_track_check(p->rdev, track); 1933 if (r) 1934 return r; 1935 break; 1936 case PACKET3_3D_DRAW_IMMD: 1937 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1938 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1939 return -EINVAL; 1940 } 1941 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); 1942 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1943 track->immd_dwords = pkt->count - 1; 1944 r = r100_cs_track_check(p->rdev, track); 1945 if (r) 1946 return r; 1947 break; 1948 /* triggers drawing using in-packet vertex data */ 1949 case PACKET3_3D_DRAW_IMMD_2: 1950 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1951 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1952 return -EINVAL; 1953 } 1954 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1955 track->immd_dwords = pkt->count; 1956 r = r100_cs_track_check(p->rdev, track); 1957 if (r) 1958 return r; 1959 break; 1960 /* triggers drawing using in-packet vertex data */ 1961 case PACKET3_3D_DRAW_VBUF_2: 1962 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1963 r = r100_cs_track_check(p->rdev, track); 1964 if (r) 1965 return r; 1966 break; 1967 /* triggers drawing of vertex buffers setup elsewhere */ 1968 case PACKET3_3D_DRAW_INDX_2: 1969 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1970 r = r100_cs_track_check(p->rdev, track); 1971 if (r) 1972 return r; 1973 break; 1974 /* triggers drawing using indices to vertex buffer */ 1975 case PACKET3_3D_DRAW_VBUF: 1976 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1977 r = r100_cs_track_check(p->rdev, track); 1978 if (r) 1979 return r; 1980 break; 1981 /* triggers drawing of vertex buffers setup elsewhere */ 1982 case PACKET3_3D_DRAW_INDX: 1983 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1984 r = r100_cs_track_check(p->rdev, track); 1985 if (r) 1986 return r; 1987 break; 1988 /* triggers drawing using indices to vertex buffer */ 1989 case PACKET3_3D_CLEAR_HIZ: 1990 case PACKET3_3D_CLEAR_ZMASK: 1991 if (p->rdev->hyperz_filp != p->filp) 1992 return -EINVAL; 1993 break; 1994 case PACKET3_NOP: 1995 break; 1996 default: 1997 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 1998 return -EINVAL; 1999 } 2000 return 0; 2001 } 2002 2003 int r100_cs_parse(struct radeon_cs_parser *p) 2004 { 2005 struct radeon_cs_packet pkt; 2006 struct r100_cs_track *track; 2007 int r; 2008 2009 track = kzalloc(sizeof(*track), GFP_KERNEL); 2010 if (!track) 2011 return -ENOMEM; 2012 r100_cs_track_clear(p->rdev, track); 2013 p->track = track; 2014 do { 2015 r = radeon_cs_packet_parse(p, &pkt, p->idx); 2016 if (r) { 2017 return r; 2018 } 2019 p->idx += pkt.count + 2; 2020 switch (pkt.type) { 2021 case RADEON_PACKET_TYPE0: 2022 if (p->rdev->family >= CHIP_R200) 2023 r = r100_cs_parse_packet0(p, &pkt, 2024 p->rdev->config.r100.reg_safe_bm, 2025 p->rdev->config.r100.reg_safe_bm_size, 2026 &r200_packet0_check); 2027 else 2028 r = r100_cs_parse_packet0(p, &pkt, 2029 p->rdev->config.r100.reg_safe_bm, 2030 p->rdev->config.r100.reg_safe_bm_size, 2031 &r100_packet0_check); 2032 break; 2033 case RADEON_PACKET_TYPE2: 2034 break; 2035 case RADEON_PACKET_TYPE3: 2036 r = r100_packet3_check(p, &pkt); 2037 break; 2038 default: 2039 DRM_ERROR("Unknown packet type %d !\n", 2040 pkt.type); 2041 return -EINVAL; 2042 } 2043 if (r) 2044 return r; 2045 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 2046 return 0; 2047 } 2048 2049 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t) 2050 { 2051 DRM_ERROR("pitch %d\n", t->pitch); 2052 DRM_ERROR("use_pitch %d\n", t->use_pitch); 2053 DRM_ERROR("width %d\n", t->width); 2054 DRM_ERROR("width_11 %d\n", t->width_11); 2055 DRM_ERROR("height %d\n", t->height); 2056 DRM_ERROR("height_11 %d\n", t->height_11); 2057 DRM_ERROR("num levels %d\n", t->num_levels); 2058 DRM_ERROR("depth %d\n", t->txdepth); 2059 DRM_ERROR("bpp %d\n", t->cpp); 2060 DRM_ERROR("coordinate type %d\n", t->tex_coord_type); 2061 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); 2062 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); 2063 DRM_ERROR("compress format %d\n", t->compress_format); 2064 } 2065 2066 static int r100_track_compress_size(int compress_format, int w, int h) 2067 { 2068 int block_width, block_height, block_bytes; 2069 int wblocks, hblocks; 2070 int min_wblocks; 2071 int sz; 2072 2073 block_width = 4; 2074 block_height = 4; 2075 2076 switch (compress_format) { 2077 case R100_TRACK_COMP_DXT1: 2078 block_bytes = 8; 2079 min_wblocks = 4; 2080 break; 2081 default: 2082 case R100_TRACK_COMP_DXT35: 2083 block_bytes = 16; 2084 min_wblocks = 2; 2085 break; 2086 } 2087 2088 hblocks = (h + block_height - 1) / block_height; 2089 wblocks = (w + block_width - 1) / block_width; 2090 if (wblocks < min_wblocks) 2091 wblocks = min_wblocks; 2092 sz = wblocks * hblocks * block_bytes; 2093 return sz; 2094 } 2095 2096 static int r100_cs_track_cube(struct radeon_device *rdev, 2097 struct r100_cs_track *track, unsigned idx) 2098 { 2099 unsigned face, w, h; 2100 struct radeon_bo *cube_robj; 2101 unsigned long size; 2102 unsigned compress_format = track->textures[idx].compress_format; 2103 2104 for (face = 0; face < 5; face++) { 2105 cube_robj = track->textures[idx].cube_info[face].robj; 2106 w = track->textures[idx].cube_info[face].width; 2107 h = track->textures[idx].cube_info[face].height; 2108 2109 if (compress_format) { 2110 size = r100_track_compress_size(compress_format, w, h); 2111 } else 2112 size = w * h; 2113 size *= track->textures[idx].cpp; 2114 2115 size += track->textures[idx].cube_info[face].offset; 2116 2117 if (size > radeon_bo_size(cube_robj)) { 2118 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", 2119 size, radeon_bo_size(cube_robj)); 2120 r100_cs_track_texture_print(&track->textures[idx]); 2121 return -1; 2122 } 2123 } 2124 return 0; 2125 } 2126 2127 static int r100_cs_track_texture_check(struct radeon_device *rdev, 2128 struct r100_cs_track *track) 2129 { 2130 struct radeon_bo *robj; 2131 unsigned long size; 2132 unsigned u, i, w, h, d; 2133 int ret; 2134 2135 for (u = 0; u < track->num_texture; u++) { 2136 if (!track->textures[u].enabled) 2137 continue; 2138 if (track->textures[u].lookup_disable) 2139 continue; 2140 robj = track->textures[u].robj; 2141 if (robj == NULL) { 2142 DRM_ERROR("No texture bound to unit %u\n", u); 2143 return -EINVAL; 2144 } 2145 size = 0; 2146 for (i = 0; i <= track->textures[u].num_levels; i++) { 2147 if (track->textures[u].use_pitch) { 2148 if (rdev->family < CHIP_R300) 2149 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); 2150 else 2151 w = track->textures[u].pitch / (1 << i); 2152 } else { 2153 w = track->textures[u].width; 2154 if (rdev->family >= CHIP_RV515) 2155 w |= track->textures[u].width_11; 2156 w = w / (1 << i); 2157 if (track->textures[u].roundup_w) 2158 w = roundup_pow_of_two(w); 2159 } 2160 h = track->textures[u].height; 2161 if (rdev->family >= CHIP_RV515) 2162 h |= track->textures[u].height_11; 2163 h = h / (1 << i); 2164 if (track->textures[u].roundup_h) 2165 h = roundup_pow_of_two(h); 2166 if (track->textures[u].tex_coord_type == 1) { 2167 d = (1 << track->textures[u].txdepth) / (1 << i); 2168 if (!d) 2169 d = 1; 2170 } else { 2171 d = 1; 2172 } 2173 if (track->textures[u].compress_format) { 2174 2175 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d; 2176 /* compressed textures are block based */ 2177 } else 2178 size += w * h * d; 2179 } 2180 size *= track->textures[u].cpp; 2181 2182 switch (track->textures[u].tex_coord_type) { 2183 case 0: 2184 case 1: 2185 break; 2186 case 2: 2187 if (track->separate_cube) { 2188 ret = r100_cs_track_cube(rdev, track, u); 2189 if (ret) 2190 return ret; 2191 } else 2192 size *= 6; 2193 break; 2194 default: 2195 DRM_ERROR("Invalid texture coordinate type %u for unit " 2196 "%u\n", track->textures[u].tex_coord_type, u); 2197 return -EINVAL; 2198 } 2199 if (size > radeon_bo_size(robj)) { 2200 DRM_ERROR("Texture of unit %u needs %lu bytes but is " 2201 "%lu\n", u, size, radeon_bo_size(robj)); 2202 r100_cs_track_texture_print(&track->textures[u]); 2203 return -EINVAL; 2204 } 2205 } 2206 return 0; 2207 } 2208 2209 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) 2210 { 2211 unsigned i; 2212 unsigned long size; 2213 unsigned prim_walk; 2214 unsigned nverts; 2215 unsigned num_cb = track->cb_dirty ? track->num_cb : 0; 2216 2217 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask && 2218 !track->blend_read_enable) 2219 num_cb = 0; 2220 2221 for (i = 0; i < num_cb; i++) { 2222 if (track->cb[i].robj == NULL) { 2223 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); 2224 return -EINVAL; 2225 } 2226 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; 2227 size += track->cb[i].offset; 2228 if (size > radeon_bo_size(track->cb[i].robj)) { 2229 DRM_ERROR("[drm] Buffer too small for color buffer %d " 2230 "(need %lu have %lu) !\n", i, size, 2231 radeon_bo_size(track->cb[i].robj)); 2232 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", 2233 i, track->cb[i].pitch, track->cb[i].cpp, 2234 track->cb[i].offset, track->maxy); 2235 return -EINVAL; 2236 } 2237 } 2238 track->cb_dirty = false; 2239 2240 if (track->zb_dirty && track->z_enabled) { 2241 if (track->zb.robj == NULL) { 2242 DRM_ERROR("[drm] No buffer for z buffer !\n"); 2243 return -EINVAL; 2244 } 2245 size = track->zb.pitch * track->zb.cpp * track->maxy; 2246 size += track->zb.offset; 2247 if (size > radeon_bo_size(track->zb.robj)) { 2248 DRM_ERROR("[drm] Buffer too small for z buffer " 2249 "(need %lu have %lu) !\n", size, 2250 radeon_bo_size(track->zb.robj)); 2251 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", 2252 track->zb.pitch, track->zb.cpp, 2253 track->zb.offset, track->maxy); 2254 return -EINVAL; 2255 } 2256 } 2257 track->zb_dirty = false; 2258 2259 if (track->aa_dirty && track->aaresolve) { 2260 if (track->aa.robj == NULL) { 2261 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i); 2262 return -EINVAL; 2263 } 2264 /* I believe the format comes from colorbuffer0. */ 2265 size = track->aa.pitch * track->cb[0].cpp * track->maxy; 2266 size += track->aa.offset; 2267 if (size > radeon_bo_size(track->aa.robj)) { 2268 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d " 2269 "(need %lu have %lu) !\n", i, size, 2270 radeon_bo_size(track->aa.robj)); 2271 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n", 2272 i, track->aa.pitch, track->cb[0].cpp, 2273 track->aa.offset, track->maxy); 2274 return -EINVAL; 2275 } 2276 } 2277 track->aa_dirty = false; 2278 2279 prim_walk = (track->vap_vf_cntl >> 4) & 0x3; 2280 if (track->vap_vf_cntl & (1 << 14)) { 2281 nverts = track->vap_alt_nverts; 2282 } else { 2283 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; 2284 } 2285 switch (prim_walk) { 2286 case 1: 2287 for (i = 0; i < track->num_arrays; i++) { 2288 size = track->arrays[i].esize * track->max_indx * 4; 2289 if (track->arrays[i].robj == NULL) { 2290 DRM_ERROR("(PW %u) Vertex array %u no buffer " 2291 "bound\n", prim_walk, i); 2292 return -EINVAL; 2293 } 2294 if (size > radeon_bo_size(track->arrays[i].robj)) { 2295 dev_err(rdev->dev, "(PW %u) Vertex array %u " 2296 "need %lu dwords have %lu dwords\n", 2297 prim_walk, i, size >> 2, 2298 radeon_bo_size(track->arrays[i].robj) 2299 >> 2); 2300 DRM_ERROR("Max indices %u\n", track->max_indx); 2301 return -EINVAL; 2302 } 2303 } 2304 break; 2305 case 2: 2306 for (i = 0; i < track->num_arrays; i++) { 2307 size = track->arrays[i].esize * (nverts - 1) * 4; 2308 if (track->arrays[i].robj == NULL) { 2309 DRM_ERROR("(PW %u) Vertex array %u no buffer " 2310 "bound\n", prim_walk, i); 2311 return -EINVAL; 2312 } 2313 if (size > radeon_bo_size(track->arrays[i].robj)) { 2314 dev_err(rdev->dev, "(PW %u) Vertex array %u " 2315 "need %lu dwords have %lu dwords\n", 2316 prim_walk, i, size >> 2, 2317 radeon_bo_size(track->arrays[i].robj) 2318 >> 2); 2319 return -EINVAL; 2320 } 2321 } 2322 break; 2323 case 3: 2324 size = track->vtx_size * nverts; 2325 if (size != track->immd_dwords) { 2326 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", 2327 track->immd_dwords, size); 2328 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", 2329 nverts, track->vtx_size); 2330 return -EINVAL; 2331 } 2332 break; 2333 default: 2334 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", 2335 prim_walk); 2336 return -EINVAL; 2337 } 2338 2339 if (track->tex_dirty) { 2340 track->tex_dirty = false; 2341 return r100_cs_track_texture_check(rdev, track); 2342 } 2343 return 0; 2344 } 2345 2346 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) 2347 { 2348 unsigned i, face; 2349 2350 track->cb_dirty = true; 2351 track->zb_dirty = true; 2352 track->tex_dirty = true; 2353 track->aa_dirty = true; 2354 2355 if (rdev->family < CHIP_R300) { 2356 track->num_cb = 1; 2357 if (rdev->family <= CHIP_RS200) 2358 track->num_texture = 3; 2359 else 2360 track->num_texture = 6; 2361 track->maxy = 2048; 2362 track->separate_cube = 1; 2363 } else { 2364 track->num_cb = 4; 2365 track->num_texture = 16; 2366 track->maxy = 4096; 2367 track->separate_cube = 0; 2368 track->aaresolve = false; 2369 track->aa.robj = NULL; 2370 } 2371 2372 for (i = 0; i < track->num_cb; i++) { 2373 track->cb[i].robj = NULL; 2374 track->cb[i].pitch = 8192; 2375 track->cb[i].cpp = 16; 2376 track->cb[i].offset = 0; 2377 } 2378 track->z_enabled = true; 2379 track->zb.robj = NULL; 2380 track->zb.pitch = 8192; 2381 track->zb.cpp = 4; 2382 track->zb.offset = 0; 2383 track->vtx_size = 0x7F; 2384 track->immd_dwords = 0xFFFFFFFFUL; 2385 track->num_arrays = 11; 2386 track->max_indx = 0x00FFFFFFUL; 2387 for (i = 0; i < track->num_arrays; i++) { 2388 track->arrays[i].robj = NULL; 2389 track->arrays[i].esize = 0x7F; 2390 } 2391 for (i = 0; i < track->num_texture; i++) { 2392 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 2393 track->textures[i].pitch = 16536; 2394 track->textures[i].width = 16536; 2395 track->textures[i].height = 16536; 2396 track->textures[i].width_11 = 1 << 11; 2397 track->textures[i].height_11 = 1 << 11; 2398 track->textures[i].num_levels = 12; 2399 if (rdev->family <= CHIP_RS200) { 2400 track->textures[i].tex_coord_type = 0; 2401 track->textures[i].txdepth = 0; 2402 } else { 2403 track->textures[i].txdepth = 16; 2404 track->textures[i].tex_coord_type = 1; 2405 } 2406 track->textures[i].cpp = 64; 2407 track->textures[i].robj = NULL; 2408 /* CS IB emission code makes sure texture unit are disabled */ 2409 track->textures[i].enabled = false; 2410 track->textures[i].lookup_disable = false; 2411 track->textures[i].roundup_w = true; 2412 track->textures[i].roundup_h = true; 2413 if (track->separate_cube) 2414 for (face = 0; face < 5; face++) { 2415 track->textures[i].cube_info[face].robj = NULL; 2416 track->textures[i].cube_info[face].width = 16536; 2417 track->textures[i].cube_info[face].height = 16536; 2418 track->textures[i].cube_info[face].offset = 0; 2419 } 2420 } 2421 } 2422 2423 /* 2424 * Global GPU functions 2425 */ 2426 static void r100_errata(struct radeon_device *rdev) 2427 { 2428 rdev->pll_errata = 0; 2429 2430 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { 2431 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; 2432 } 2433 2434 if (rdev->family == CHIP_RV100 || 2435 rdev->family == CHIP_RS100 || 2436 rdev->family == CHIP_RS200) { 2437 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; 2438 } 2439 } 2440 2441 static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) 2442 { 2443 unsigned i; 2444 uint32_t tmp; 2445 2446 for (i = 0; i < rdev->usec_timeout; i++) { 2447 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; 2448 if (tmp >= n) { 2449 return 0; 2450 } 2451 DRM_UDELAY(1); 2452 } 2453 return -1; 2454 } 2455 2456 int r100_gui_wait_for_idle(struct radeon_device *rdev) 2457 { 2458 unsigned i; 2459 uint32_t tmp; 2460 2461 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { 2462 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !" 2463 " Bad things might happen.\n"); 2464 } 2465 for (i = 0; i < rdev->usec_timeout; i++) { 2466 tmp = RREG32(RADEON_RBBM_STATUS); 2467 if (!(tmp & RADEON_RBBM_ACTIVE)) { 2468 return 0; 2469 } 2470 DRM_UDELAY(1); 2471 } 2472 return -1; 2473 } 2474 2475 int r100_mc_wait_for_idle(struct radeon_device *rdev) 2476 { 2477 unsigned i; 2478 uint32_t tmp; 2479 2480 for (i = 0; i < rdev->usec_timeout; i++) { 2481 /* read MC_STATUS */ 2482 tmp = RREG32(RADEON_MC_STATUS); 2483 if (tmp & RADEON_MC_IDLE) { 2484 return 0; 2485 } 2486 DRM_UDELAY(1); 2487 } 2488 return -1; 2489 } 2490 2491 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 2492 { 2493 u32 rbbm_status; 2494 2495 rbbm_status = RREG32(R_000E40_RBBM_STATUS); 2496 if (!G_000E40_GUI_ACTIVE(rbbm_status)) { 2497 radeon_ring_lockup_update(ring); 2498 return false; 2499 } 2500 /* force CP activities */ 2501 radeon_ring_force_activity(rdev, ring); 2502 return radeon_ring_test_lockup(rdev, ring); 2503 } 2504 2505 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 2506 void r100_enable_bm(struct radeon_device *rdev) 2507 { 2508 uint32_t tmp; 2509 /* Enable bus mastering */ 2510 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 2511 WREG32(RADEON_BUS_CNTL, tmp); 2512 } 2513 2514 void r100_bm_disable(struct radeon_device *rdev) 2515 { 2516 u32 tmp; 2517 2518 /* disable bus mastering */ 2519 tmp = RREG32(R_000030_BUS_CNTL); 2520 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044); 2521 mdelay(1); 2522 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042); 2523 mdelay(1); 2524 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); 2525 tmp = RREG32(RADEON_BUS_CNTL); 2526 mdelay(1); 2527 pci_clear_master(rdev->pdev); 2528 mdelay(1); 2529 } 2530 2531 int r100_asic_reset(struct radeon_device *rdev) 2532 { 2533 struct r100_mc_save save; 2534 u32 status, tmp; 2535 int ret = 0; 2536 2537 status = RREG32(R_000E40_RBBM_STATUS); 2538 if (!G_000E40_GUI_ACTIVE(status)) { 2539 return 0; 2540 } 2541 r100_mc_stop(rdev, &save); 2542 status = RREG32(R_000E40_RBBM_STATUS); 2543 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2544 /* stop CP */ 2545 WREG32(RADEON_CP_CSQ_CNTL, 0); 2546 tmp = RREG32(RADEON_CP_RB_CNTL); 2547 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 2548 WREG32(RADEON_CP_RB_RPTR_WR, 0); 2549 WREG32(RADEON_CP_RB_WPTR, 0); 2550 WREG32(RADEON_CP_RB_CNTL, tmp); 2551 /* save PCI state */ 2552 pci_save_state(rdev->pdev); 2553 /* disable bus mastering */ 2554 r100_bm_disable(rdev); 2555 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) | 2556 S_0000F0_SOFT_RESET_RE(1) | 2557 S_0000F0_SOFT_RESET_PP(1) | 2558 S_0000F0_SOFT_RESET_RB(1)); 2559 RREG32(R_0000F0_RBBM_SOFT_RESET); 2560 mdelay(500); 2561 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2562 mdelay(1); 2563 status = RREG32(R_000E40_RBBM_STATUS); 2564 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2565 /* reset CP */ 2566 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 2567 RREG32(R_0000F0_RBBM_SOFT_RESET); 2568 mdelay(500); 2569 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2570 mdelay(1); 2571 status = RREG32(R_000E40_RBBM_STATUS); 2572 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2573 /* restore PCI & busmastering */ 2574 pci_restore_state(rdev->pdev); 2575 r100_enable_bm(rdev); 2576 /* Check if GPU is idle */ 2577 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) || 2578 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) { 2579 dev_err(rdev->dev, "failed to reset GPU\n"); 2580 ret = -1; 2581 } else 2582 dev_info(rdev->dev, "GPU reset succeed\n"); 2583 r100_mc_resume(rdev, &save); 2584 return ret; 2585 } 2586 2587 void r100_set_common_regs(struct radeon_device *rdev) 2588 { 2589 struct drm_device *dev = rdev->ddev; 2590 bool force_dac2 = false; 2591 u32 tmp; 2592 2593 /* set these so they don't interfere with anything */ 2594 WREG32(RADEON_OV0_SCALE_CNTL, 0); 2595 WREG32(RADEON_SUBPIC_CNTL, 0); 2596 WREG32(RADEON_VIPH_CONTROL, 0); 2597 WREG32(RADEON_I2C_CNTL_1, 0); 2598 WREG32(RADEON_DVI_I2C_CNTL_1, 0); 2599 WREG32(RADEON_CAP0_TRIG_CNTL, 0); 2600 WREG32(RADEON_CAP1_TRIG_CNTL, 0); 2601 2602 /* always set up dac2 on rn50 and some rv100 as lots 2603 * of servers seem to wire it up to a VGA port but 2604 * don't report it in the bios connector 2605 * table. 2606 */ 2607 switch (dev->pdev->device) { 2608 /* RN50 */ 2609 case 0x515e: 2610 case 0x5969: 2611 force_dac2 = true; 2612 break; 2613 /* RV100*/ 2614 case 0x5159: 2615 case 0x515a: 2616 /* DELL triple head servers */ 2617 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) && 2618 ((dev->pdev->subsystem_device == 0x016c) || 2619 (dev->pdev->subsystem_device == 0x016d) || 2620 (dev->pdev->subsystem_device == 0x016e) || 2621 (dev->pdev->subsystem_device == 0x016f) || 2622 (dev->pdev->subsystem_device == 0x0170) || 2623 (dev->pdev->subsystem_device == 0x017d) || 2624 (dev->pdev->subsystem_device == 0x017e) || 2625 (dev->pdev->subsystem_device == 0x0183) || 2626 (dev->pdev->subsystem_device == 0x018a) || 2627 (dev->pdev->subsystem_device == 0x019a))) 2628 force_dac2 = true; 2629 break; 2630 } 2631 2632 if (force_dac2) { 2633 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 2634 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 2635 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 2636 2637 /* For CRT on DAC2, don't turn it on if BIOS didn't 2638 enable it, even it's detected. 2639 */ 2640 2641 /* force it to crtc0 */ 2642 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; 2643 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; 2644 disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 2645 2646 /* set up the TV DAC */ 2647 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL | 2648 RADEON_TV_DAC_STD_MASK | 2649 RADEON_TV_DAC_RDACPD | 2650 RADEON_TV_DAC_GDACPD | 2651 RADEON_TV_DAC_BDACPD | 2652 RADEON_TV_DAC_BGADJ_MASK | 2653 RADEON_TV_DAC_DACADJ_MASK); 2654 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | 2655 RADEON_TV_DAC_NHOLD | 2656 RADEON_TV_DAC_STD_PS2 | 2657 (0x58 << 16)); 2658 2659 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 2660 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 2661 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 2662 } 2663 2664 /* switch PM block to ACPI mode */ 2665 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); 2666 tmp &= ~RADEON_PM_MODE_SEL; 2667 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); 2668 2669 } 2670 2671 /* 2672 * VRAM info 2673 */ 2674 static void r100_vram_get_type(struct radeon_device *rdev) 2675 { 2676 uint32_t tmp; 2677 2678 rdev->mc.vram_is_ddr = false; 2679 if (rdev->flags & RADEON_IS_IGP) 2680 rdev->mc.vram_is_ddr = true; 2681 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) 2682 rdev->mc.vram_is_ddr = true; 2683 if ((rdev->family == CHIP_RV100) || 2684 (rdev->family == CHIP_RS100) || 2685 (rdev->family == CHIP_RS200)) { 2686 tmp = RREG32(RADEON_MEM_CNTL); 2687 if (tmp & RV100_HALF_MODE) { 2688 rdev->mc.vram_width = 32; 2689 } else { 2690 rdev->mc.vram_width = 64; 2691 } 2692 if (rdev->flags & RADEON_SINGLE_CRTC) { 2693 rdev->mc.vram_width /= 4; 2694 rdev->mc.vram_is_ddr = true; 2695 } 2696 } else if (rdev->family <= CHIP_RV280) { 2697 tmp = RREG32(RADEON_MEM_CNTL); 2698 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { 2699 rdev->mc.vram_width = 128; 2700 } else { 2701 rdev->mc.vram_width = 64; 2702 } 2703 } else { 2704 /* newer IGPs */ 2705 rdev->mc.vram_width = 128; 2706 } 2707 } 2708 2709 static u32 r100_get_accessible_vram(struct radeon_device *rdev) 2710 { 2711 u32 aper_size; 2712 u8 byte; 2713 2714 aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2715 2716 /* Set HDP_APER_CNTL only on cards that are known not to be broken, 2717 * that is has the 2nd generation multifunction PCI interface 2718 */ 2719 if (rdev->family == CHIP_RV280 || 2720 rdev->family >= CHIP_RV350) { 2721 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, 2722 ~RADEON_HDP_APER_CNTL); 2723 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); 2724 return aper_size * 2; 2725 } 2726 2727 /* Older cards have all sorts of funny issues to deal with. First 2728 * check if it's a multifunction card by reading the PCI config 2729 * header type... Limit those to one aperture size 2730 */ 2731 pci_read_config_byte(rdev->pdev, 0xe, &byte); 2732 if (byte & 0x80) { 2733 DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); 2734 DRM_INFO("Limiting VRAM to one aperture\n"); 2735 return aper_size; 2736 } 2737 2738 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS 2739 * have set it up. We don't write this as it's broken on some ASICs but 2740 * we expect the BIOS to have done the right thing (might be too optimistic...) 2741 */ 2742 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) 2743 return aper_size * 2; 2744 return aper_size; 2745 } 2746 2747 void r100_vram_init_sizes(struct radeon_device *rdev) 2748 { 2749 u64 config_aper_size; 2750 2751 /* work out accessible VRAM */ 2752 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 2753 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 2754 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); 2755 /* FIXME we don't use the second aperture yet when we could use it */ 2756 if (rdev->mc.visible_vram_size > rdev->mc.aper_size) 2757 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2758 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2759 if (rdev->flags & RADEON_IS_IGP) { 2760 uint32_t tom; 2761 /* read NB_TOM to get the amount of ram stolen for the GPU */ 2762 tom = RREG32(RADEON_NB_TOM); 2763 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); 2764 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2765 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2766 } else { 2767 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 2768 /* Some production boards of m6 will report 0 2769 * if it's 8 MB 2770 */ 2771 if (rdev->mc.real_vram_size == 0) { 2772 rdev->mc.real_vram_size = 8192 * 1024; 2773 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2774 } 2775 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 2776 * Novell bug 204882 + along with lots of ubuntu ones 2777 */ 2778 if (rdev->mc.aper_size > config_aper_size) 2779 config_aper_size = rdev->mc.aper_size; 2780 2781 if (config_aper_size > rdev->mc.real_vram_size) 2782 rdev->mc.mc_vram_size = config_aper_size; 2783 else 2784 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2785 } 2786 } 2787 2788 void r100_vga_set_state(struct radeon_device *rdev, bool state) 2789 { 2790 uint32_t temp; 2791 2792 temp = RREG32(RADEON_CONFIG_CNTL); 2793 if (state == false) { 2794 temp &= ~RADEON_CFG_VGA_RAM_EN; 2795 temp |= RADEON_CFG_VGA_IO_DIS; 2796 } else { 2797 temp &= ~RADEON_CFG_VGA_IO_DIS; 2798 } 2799 WREG32(RADEON_CONFIG_CNTL, temp); 2800 } 2801 2802 static void r100_mc_init(struct radeon_device *rdev) 2803 { 2804 u64 base; 2805 2806 r100_vram_get_type(rdev); 2807 r100_vram_init_sizes(rdev); 2808 base = rdev->mc.aper_base; 2809 if (rdev->flags & RADEON_IS_IGP) 2810 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 2811 radeon_vram_location(rdev, &rdev->mc, base); 2812 rdev->mc.gtt_base_align = 0; 2813 if (!(rdev->flags & RADEON_IS_AGP)) 2814 radeon_gtt_location(rdev, &rdev->mc); 2815 radeon_update_bandwidth_info(rdev); 2816 } 2817 2818 2819 /* 2820 * Indirect registers accessor 2821 */ 2822 void r100_pll_errata_after_index(struct radeon_device *rdev) 2823 { 2824 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) { 2825 (void)RREG32(RADEON_CLOCK_CNTL_DATA); 2826 (void)RREG32(RADEON_CRTC_GEN_CNTL); 2827 } 2828 } 2829 2830 static void r100_pll_errata_after_data(struct radeon_device *rdev) 2831 { 2832 /* This workarounds is necessary on RV100, RS100 and RS200 chips 2833 * or the chip could hang on a subsequent access 2834 */ 2835 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { 2836 mdelay(5); 2837 } 2838 2839 /* This function is required to workaround a hardware bug in some (all?) 2840 * revisions of the R300. This workaround should be called after every 2841 * CLOCK_CNTL_INDEX register access. If not, register reads afterward 2842 * may not be correct. 2843 */ 2844 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { 2845 uint32_t save, tmp; 2846 2847 save = RREG32(RADEON_CLOCK_CNTL_INDEX); 2848 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2849 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); 2850 tmp = RREG32(RADEON_CLOCK_CNTL_DATA); 2851 WREG32(RADEON_CLOCK_CNTL_INDEX, save); 2852 } 2853 } 2854 2855 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) 2856 { 2857 unsigned long flags; 2858 uint32_t data; 2859 2860 spin_lock_irqsave(&rdev->pll_idx_lock, flags); 2861 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); 2862 r100_pll_errata_after_index(rdev); 2863 data = RREG32(RADEON_CLOCK_CNTL_DATA); 2864 r100_pll_errata_after_data(rdev); 2865 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); 2866 return data; 2867 } 2868 2869 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2870 { 2871 unsigned long flags; 2872 2873 spin_lock_irqsave(&rdev->pll_idx_lock, flags); 2874 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); 2875 r100_pll_errata_after_index(rdev); 2876 WREG32(RADEON_CLOCK_CNTL_DATA, v); 2877 r100_pll_errata_after_data(rdev); 2878 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); 2879 } 2880 2881 static void r100_set_safe_registers(struct radeon_device *rdev) 2882 { 2883 if (ASIC_IS_RN50(rdev)) { 2884 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; 2885 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); 2886 } else if (rdev->family < CHIP_R200) { 2887 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; 2888 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); 2889 } else { 2890 r200_set_safe_registers(rdev); 2891 } 2892 } 2893 2894 /* 2895 * Debugfs info 2896 */ 2897 #if defined(CONFIG_DEBUG_FS) 2898 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data) 2899 { 2900 struct drm_info_node *node = (struct drm_info_node *) m->private; 2901 struct drm_device *dev = node->minor->dev; 2902 struct radeon_device *rdev = dev->dev_private; 2903 uint32_t reg, value; 2904 unsigned i; 2905 2906 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); 2907 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); 2908 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2909 for (i = 0; i < 64; i++) { 2910 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); 2911 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; 2912 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); 2913 value = RREG32(RADEON_RBBM_CMDFIFO_DATA); 2914 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); 2915 } 2916 return 0; 2917 } 2918 2919 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data) 2920 { 2921 struct drm_info_node *node = (struct drm_info_node *) m->private; 2922 struct drm_device *dev = node->minor->dev; 2923 struct radeon_device *rdev = dev->dev_private; 2924 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2925 uint32_t rdp, wdp; 2926 unsigned count, i, j; 2927 2928 radeon_ring_free_size(rdev, ring); 2929 rdp = RREG32(RADEON_CP_RB_RPTR); 2930 wdp = RREG32(RADEON_CP_RB_WPTR); 2931 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask; 2932 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2933 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); 2934 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); 2935 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); 2936 seq_printf(m, "%u dwords in ring\n", count); 2937 if (ring->ready) { 2938 for (j = 0; j <= count; j++) { 2939 i = (rdp + j) & ring->ptr_mask; 2940 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); 2941 } 2942 } 2943 return 0; 2944 } 2945 2946 2947 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data) 2948 { 2949 struct drm_info_node *node = (struct drm_info_node *) m->private; 2950 struct drm_device *dev = node->minor->dev; 2951 struct radeon_device *rdev = dev->dev_private; 2952 uint32_t csq_stat, csq2_stat, tmp; 2953 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; 2954 unsigned i; 2955 2956 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2957 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); 2958 csq_stat = RREG32(RADEON_CP_CSQ_STAT); 2959 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); 2960 r_rptr = (csq_stat >> 0) & 0x3ff; 2961 r_wptr = (csq_stat >> 10) & 0x3ff; 2962 ib1_rptr = (csq_stat >> 20) & 0x3ff; 2963 ib1_wptr = (csq2_stat >> 0) & 0x3ff; 2964 ib2_rptr = (csq2_stat >> 10) & 0x3ff; 2965 ib2_wptr = (csq2_stat >> 20) & 0x3ff; 2966 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); 2967 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); 2968 seq_printf(m, "Ring rptr %u\n", r_rptr); 2969 seq_printf(m, "Ring wptr %u\n", r_wptr); 2970 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); 2971 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); 2972 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); 2973 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); 2974 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms 2975 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ 2976 seq_printf(m, "Ring fifo:\n"); 2977 for (i = 0; i < 256; i++) { 2978 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2979 tmp = RREG32(RADEON_CP_CSQ_DATA); 2980 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); 2981 } 2982 seq_printf(m, "Indirect1 fifo:\n"); 2983 for (i = 256; i <= 512; i++) { 2984 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2985 tmp = RREG32(RADEON_CP_CSQ_DATA); 2986 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); 2987 } 2988 seq_printf(m, "Indirect2 fifo:\n"); 2989 for (i = 640; i < ib1_wptr; i++) { 2990 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2991 tmp = RREG32(RADEON_CP_CSQ_DATA); 2992 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); 2993 } 2994 return 0; 2995 } 2996 2997 static int r100_debugfs_mc_info(struct seq_file *m, void *data) 2998 { 2999 struct drm_info_node *node = (struct drm_info_node *) m->private; 3000 struct drm_device *dev = node->minor->dev; 3001 struct radeon_device *rdev = dev->dev_private; 3002 uint32_t tmp; 3003 3004 tmp = RREG32(RADEON_CONFIG_MEMSIZE); 3005 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); 3006 tmp = RREG32(RADEON_MC_FB_LOCATION); 3007 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); 3008 tmp = RREG32(RADEON_BUS_CNTL); 3009 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 3010 tmp = RREG32(RADEON_MC_AGP_LOCATION); 3011 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 3012 tmp = RREG32(RADEON_AGP_BASE); 3013 seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 3014 tmp = RREG32(RADEON_HOST_PATH_CNTL); 3015 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 3016 tmp = RREG32(0x01D0); 3017 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); 3018 tmp = RREG32(RADEON_AIC_LO_ADDR); 3019 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); 3020 tmp = RREG32(RADEON_AIC_HI_ADDR); 3021 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); 3022 tmp = RREG32(0x01E4); 3023 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); 3024 return 0; 3025 } 3026 3027 static struct drm_info_list r100_debugfs_rbbm_list[] = { 3028 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL}, 3029 }; 3030 3031 static struct drm_info_list r100_debugfs_cp_list[] = { 3032 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL}, 3033 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL}, 3034 }; 3035 3036 static struct drm_info_list r100_debugfs_mc_info_list[] = { 3037 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL}, 3038 }; 3039 #endif 3040 3041 int r100_debugfs_rbbm_init(struct radeon_device *rdev) 3042 { 3043 #if defined(CONFIG_DEBUG_FS) 3044 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1); 3045 #else 3046 return 0; 3047 #endif 3048 } 3049 3050 int r100_debugfs_cp_init(struct radeon_device *rdev) 3051 { 3052 #if defined(CONFIG_DEBUG_FS) 3053 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2); 3054 #else 3055 return 0; 3056 #endif 3057 } 3058 3059 int r100_debugfs_mc_info_init(struct radeon_device *rdev) 3060 { 3061 #if defined(CONFIG_DEBUG_FS) 3062 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1); 3063 #else 3064 return 0; 3065 #endif 3066 } 3067 3068 int r100_set_surface_reg(struct radeon_device *rdev, int reg, 3069 uint32_t tiling_flags, uint32_t pitch, 3070 uint32_t offset, uint32_t obj_size) 3071 { 3072 int surf_index = reg * 16; 3073 int flags = 0; 3074 3075 if (rdev->family <= CHIP_RS200) { 3076 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3077 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3078 flags |= RADEON_SURF_TILE_COLOR_BOTH; 3079 if (tiling_flags & RADEON_TILING_MACRO) 3080 flags |= RADEON_SURF_TILE_COLOR_MACRO; 3081 /* setting pitch to 0 disables tiling */ 3082 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3083 == 0) 3084 pitch = 0; 3085 } else if (rdev->family <= CHIP_RV280) { 3086 if (tiling_flags & (RADEON_TILING_MACRO)) 3087 flags |= R200_SURF_TILE_COLOR_MACRO; 3088 if (tiling_flags & RADEON_TILING_MICRO) 3089 flags |= R200_SURF_TILE_COLOR_MICRO; 3090 } else { 3091 if (tiling_flags & RADEON_TILING_MACRO) 3092 flags |= R300_SURF_TILE_MACRO; 3093 if (tiling_flags & RADEON_TILING_MICRO) 3094 flags |= R300_SURF_TILE_MICRO; 3095 } 3096 3097 if (tiling_flags & RADEON_TILING_SWAP_16BIT) 3098 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; 3099 if (tiling_flags & RADEON_TILING_SWAP_32BIT) 3100 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; 3101 3102 /* r100/r200 divide by 16 */ 3103 if (rdev->family < CHIP_R300) 3104 flags |= pitch / 16; 3105 else 3106 flags |= pitch / 8; 3107 3108 3109 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); 3110 WREG32(RADEON_SURFACE0_INFO + surf_index, flags); 3111 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); 3112 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); 3113 return 0; 3114 } 3115 3116 void r100_clear_surface_reg(struct radeon_device *rdev, int reg) 3117 { 3118 int surf_index = reg * 16; 3119 WREG32(RADEON_SURFACE0_INFO + surf_index, 0); 3120 } 3121 3122 void r100_bandwidth_update(struct radeon_device *rdev) 3123 { 3124 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; 3125 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; 3126 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; 3127 uint32_t temp, data, mem_trcd, mem_trp, mem_tras; 3128 fixed20_12 memtcas_ff[8] = { 3129 dfixed_init(1), 3130 dfixed_init(2), 3131 dfixed_init(3), 3132 dfixed_init(0), 3133 dfixed_init_half(1), 3134 dfixed_init_half(2), 3135 dfixed_init(0), 3136 }; 3137 fixed20_12 memtcas_rs480_ff[8] = { 3138 dfixed_init(0), 3139 dfixed_init(1), 3140 dfixed_init(2), 3141 dfixed_init(3), 3142 dfixed_init(0), 3143 dfixed_init_half(1), 3144 dfixed_init_half(2), 3145 dfixed_init_half(3), 3146 }; 3147 fixed20_12 memtcas2_ff[8] = { 3148 dfixed_init(0), 3149 dfixed_init(1), 3150 dfixed_init(2), 3151 dfixed_init(3), 3152 dfixed_init(4), 3153 dfixed_init(5), 3154 dfixed_init(6), 3155 dfixed_init(7), 3156 }; 3157 fixed20_12 memtrbs[8] = { 3158 dfixed_init(1), 3159 dfixed_init_half(1), 3160 dfixed_init(2), 3161 dfixed_init_half(2), 3162 dfixed_init(3), 3163 dfixed_init_half(3), 3164 dfixed_init(4), 3165 dfixed_init_half(4) 3166 }; 3167 fixed20_12 memtrbs_r4xx[8] = { 3168 dfixed_init(4), 3169 dfixed_init(5), 3170 dfixed_init(6), 3171 dfixed_init(7), 3172 dfixed_init(8), 3173 dfixed_init(9), 3174 dfixed_init(10), 3175 dfixed_init(11) 3176 }; 3177 fixed20_12 min_mem_eff; 3178 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; 3179 fixed20_12 cur_latency_mclk, cur_latency_sclk; 3180 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate, 3181 disp_drain_rate2, read_return_rate; 3182 fixed20_12 time_disp1_drop_priority; 3183 int c; 3184 int cur_size = 16; /* in octawords */ 3185 int critical_point = 0, critical_point2; 3186 /* uint32_t read_return_rate, time_disp1_drop_priority; */ 3187 int stop_req, max_stop_req; 3188 struct drm_display_mode *mode1 = NULL; 3189 struct drm_display_mode *mode2 = NULL; 3190 uint32_t pixel_bytes1 = 0; 3191 uint32_t pixel_bytes2 = 0; 3192 3193 radeon_update_display_priority(rdev); 3194 3195 if (rdev->mode_info.crtcs[0]->base.enabled) { 3196 mode1 = &rdev->mode_info.crtcs[0]->base.mode; 3197 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8; 3198 } 3199 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3200 if (rdev->mode_info.crtcs[1]->base.enabled) { 3201 mode2 = &rdev->mode_info.crtcs[1]->base.mode; 3202 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8; 3203 } 3204 } 3205 3206 min_mem_eff.full = dfixed_const_8(0); 3207 /* get modes */ 3208 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { 3209 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); 3210 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); 3211 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); 3212 /* check crtc enables */ 3213 if (mode2) 3214 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); 3215 if (mode1) 3216 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); 3217 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); 3218 } 3219 3220 /* 3221 * determine is there is enough bw for current mode 3222 */ 3223 sclk_ff = rdev->pm.sclk; 3224 mclk_ff = rdev->pm.mclk; 3225 3226 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); 3227 temp_ff.full = dfixed_const(temp); 3228 mem_bw.full = dfixed_mul(mclk_ff, temp_ff); 3229 3230 pix_clk.full = 0; 3231 pix_clk2.full = 0; 3232 peak_disp_bw.full = 0; 3233 if (mode1) { 3234 temp_ff.full = dfixed_const(1000); 3235 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ 3236 pix_clk.full = dfixed_div(pix_clk, temp_ff); 3237 temp_ff.full = dfixed_const(pixel_bytes1); 3238 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); 3239 } 3240 if (mode2) { 3241 temp_ff.full = dfixed_const(1000); 3242 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ 3243 pix_clk2.full = dfixed_div(pix_clk2, temp_ff); 3244 temp_ff.full = dfixed_const(pixel_bytes2); 3245 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); 3246 } 3247 3248 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); 3249 if (peak_disp_bw.full >= mem_bw.full) { 3250 DRM_ERROR("You may not have enough display bandwidth for current mode\n" 3251 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); 3252 } 3253 3254 /* Get values from the EXT_MEM_CNTL register...converting its contents. */ 3255 temp = RREG32(RADEON_MEM_TIMING_CNTL); 3256 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ 3257 mem_trcd = ((temp >> 2) & 0x3) + 1; 3258 mem_trp = ((temp & 0x3)) + 1; 3259 mem_tras = ((temp & 0x70) >> 4) + 1; 3260 } else if (rdev->family == CHIP_R300 || 3261 rdev->family == CHIP_R350) { /* r300, r350 */ 3262 mem_trcd = (temp & 0x7) + 1; 3263 mem_trp = ((temp >> 8) & 0x7) + 1; 3264 mem_tras = ((temp >> 11) & 0xf) + 4; 3265 } else if (rdev->family == CHIP_RV350 || 3266 rdev->family <= CHIP_RV380) { 3267 /* rv3x0 */ 3268 mem_trcd = (temp & 0x7) + 3; 3269 mem_trp = ((temp >> 8) & 0x7) + 3; 3270 mem_tras = ((temp >> 11) & 0xf) + 6; 3271 } else if (rdev->family == CHIP_R420 || 3272 rdev->family == CHIP_R423 || 3273 rdev->family == CHIP_RV410) { 3274 /* r4xx */ 3275 mem_trcd = (temp & 0xf) + 3; 3276 if (mem_trcd > 15) 3277 mem_trcd = 15; 3278 mem_trp = ((temp >> 8) & 0xf) + 3; 3279 if (mem_trp > 15) 3280 mem_trp = 15; 3281 mem_tras = ((temp >> 12) & 0x1f) + 6; 3282 if (mem_tras > 31) 3283 mem_tras = 31; 3284 } else { /* RV200, R200 */ 3285 mem_trcd = (temp & 0x7) + 1; 3286 mem_trp = ((temp >> 8) & 0x7) + 1; 3287 mem_tras = ((temp >> 12) & 0xf) + 4; 3288 } 3289 /* convert to FF */ 3290 trcd_ff.full = dfixed_const(mem_trcd); 3291 trp_ff.full = dfixed_const(mem_trp); 3292 tras_ff.full = dfixed_const(mem_tras); 3293 3294 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ 3295 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3296 data = (temp & (7 << 20)) >> 20; 3297 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { 3298 if (rdev->family == CHIP_RS480) /* don't think rs400 */ 3299 tcas_ff = memtcas_rs480_ff[data]; 3300 else 3301 tcas_ff = memtcas_ff[data]; 3302 } else 3303 tcas_ff = memtcas2_ff[data]; 3304 3305 if (rdev->family == CHIP_RS400 || 3306 rdev->family == CHIP_RS480) { 3307 /* extra cas latency stored in bits 23-25 0-4 clocks */ 3308 data = (temp >> 23) & 0x7; 3309 if (data < 5) 3310 tcas_ff.full += dfixed_const(data); 3311 } 3312 3313 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { 3314 /* on the R300, Tcas is included in Trbs. 3315 */ 3316 temp = RREG32(RADEON_MEM_CNTL); 3317 data = (R300_MEM_NUM_CHANNELS_MASK & temp); 3318 if (data == 1) { 3319 if (R300_MEM_USE_CD_CH_ONLY & temp) { 3320 temp = RREG32(R300_MC_IND_INDEX); 3321 temp &= ~R300_MC_IND_ADDR_MASK; 3322 temp |= R300_MC_READ_CNTL_CD_mcind; 3323 WREG32(R300_MC_IND_INDEX, temp); 3324 temp = RREG32(R300_MC_IND_DATA); 3325 data = (R300_MEM_RBS_POSITION_C_MASK & temp); 3326 } else { 3327 temp = RREG32(R300_MC_READ_CNTL_AB); 3328 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 3329 } 3330 } else { 3331 temp = RREG32(R300_MC_READ_CNTL_AB); 3332 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 3333 } 3334 if (rdev->family == CHIP_RV410 || 3335 rdev->family == CHIP_R420 || 3336 rdev->family == CHIP_R423) 3337 trbs_ff = memtrbs_r4xx[data]; 3338 else 3339 trbs_ff = memtrbs[data]; 3340 tcas_ff.full += trbs_ff.full; 3341 } 3342 3343 sclk_eff_ff.full = sclk_ff.full; 3344 3345 if (rdev->flags & RADEON_IS_AGP) { 3346 fixed20_12 agpmode_ff; 3347 agpmode_ff.full = dfixed_const(radeon_agpmode); 3348 temp_ff.full = dfixed_const_666(16); 3349 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); 3350 } 3351 /* TODO PCIE lanes may affect this - agpmode == 16?? */ 3352 3353 if (ASIC_IS_R300(rdev)) { 3354 sclk_delay_ff.full = dfixed_const(250); 3355 } else { 3356 if ((rdev->family == CHIP_RV100) || 3357 rdev->flags & RADEON_IS_IGP) { 3358 if (rdev->mc.vram_is_ddr) 3359 sclk_delay_ff.full = dfixed_const(41); 3360 else 3361 sclk_delay_ff.full = dfixed_const(33); 3362 } else { 3363 if (rdev->mc.vram_width == 128) 3364 sclk_delay_ff.full = dfixed_const(57); 3365 else 3366 sclk_delay_ff.full = dfixed_const(41); 3367 } 3368 } 3369 3370 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff); 3371 3372 if (rdev->mc.vram_is_ddr) { 3373 if (rdev->mc.vram_width == 32) { 3374 k1.full = dfixed_const(40); 3375 c = 3; 3376 } else { 3377 k1.full = dfixed_const(20); 3378 c = 1; 3379 } 3380 } else { 3381 k1.full = dfixed_const(40); 3382 c = 3; 3383 } 3384 3385 temp_ff.full = dfixed_const(2); 3386 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); 3387 temp_ff.full = dfixed_const(c); 3388 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); 3389 temp_ff.full = dfixed_const(4); 3390 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); 3391 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); 3392 mc_latency_mclk.full += k1.full; 3393 3394 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff); 3395 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff); 3396 3397 /* 3398 HW cursor time assuming worst case of full size colour cursor. 3399 */ 3400 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); 3401 temp_ff.full += trcd_ff.full; 3402 if (temp_ff.full < tras_ff.full) 3403 temp_ff.full = tras_ff.full; 3404 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff); 3405 3406 temp_ff.full = dfixed_const(cur_size); 3407 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff); 3408 /* 3409 Find the total latency for the display data. 3410 */ 3411 disp_latency_overhead.full = dfixed_const(8); 3412 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff); 3413 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; 3414 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; 3415 3416 if (mc_latency_mclk.full > mc_latency_sclk.full) 3417 disp_latency.full = mc_latency_mclk.full; 3418 else 3419 disp_latency.full = mc_latency_sclk.full; 3420 3421 /* setup Max GRPH_STOP_REQ default value */ 3422 if (ASIC_IS_RV100(rdev)) 3423 max_stop_req = 0x5c; 3424 else 3425 max_stop_req = 0x7c; 3426 3427 if (mode1) { 3428 /* CRTC1 3429 Set GRPH_BUFFER_CNTL register using h/w defined optimal values. 3430 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] 3431 */ 3432 stop_req = mode1->hdisplay * pixel_bytes1 / 16; 3433 3434 if (stop_req > max_stop_req) 3435 stop_req = max_stop_req; 3436 3437 /* 3438 Find the drain rate of the display buffer. 3439 */ 3440 temp_ff.full = dfixed_const((16/pixel_bytes1)); 3441 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); 3442 3443 /* 3444 Find the critical point of the display buffer. 3445 */ 3446 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); 3447 crit_point_ff.full += dfixed_const_half(0); 3448 3449 critical_point = dfixed_trunc(crit_point_ff); 3450 3451 if (rdev->disp_priority == 2) { 3452 critical_point = 0; 3453 } 3454 3455 /* 3456 The critical point should never be above max_stop_req-4. Setting 3457 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. 3458 */ 3459 if (max_stop_req - critical_point < 4) 3460 critical_point = 0; 3461 3462 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { 3463 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ 3464 critical_point = 0x10; 3465 } 3466 3467 temp = RREG32(RADEON_GRPH_BUFFER_CNTL); 3468 temp &= ~(RADEON_GRPH_STOP_REQ_MASK); 3469 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3470 temp &= ~(RADEON_GRPH_START_REQ_MASK); 3471 if ((rdev->family == CHIP_R350) && 3472 (stop_req > 0x15)) { 3473 stop_req -= 0x10; 3474 } 3475 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3476 temp |= RADEON_GRPH_BUFFER_SIZE; 3477 temp &= ~(RADEON_GRPH_CRITICAL_CNTL | 3478 RADEON_GRPH_CRITICAL_AT_SOF | 3479 RADEON_GRPH_STOP_CNTL); 3480 /* 3481 Write the result into the register. 3482 */ 3483 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3484 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3485 3486 #if 0 3487 if ((rdev->family == CHIP_RS400) || 3488 (rdev->family == CHIP_RS480)) { 3489 /* attempt to program RS400 disp regs correctly ??? */ 3490 temp = RREG32(RS400_DISP1_REG_CNTL); 3491 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | 3492 RS400_DISP1_STOP_REQ_LEVEL_MASK); 3493 WREG32(RS400_DISP1_REQ_CNTL1, (temp | 3494 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3495 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3496 temp = RREG32(RS400_DMIF_MEM_CNTL1); 3497 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | 3498 RS400_DISP1_CRITICAL_POINT_STOP_MASK); 3499 WREG32(RS400_DMIF_MEM_CNTL1, (temp | 3500 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | 3501 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); 3502 } 3503 #endif 3504 3505 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n", 3506 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ 3507 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); 3508 } 3509 3510 if (mode2) { 3511 u32 grph2_cntl; 3512 stop_req = mode2->hdisplay * pixel_bytes2 / 16; 3513 3514 if (stop_req > max_stop_req) 3515 stop_req = max_stop_req; 3516 3517 /* 3518 Find the drain rate of the display buffer. 3519 */ 3520 temp_ff.full = dfixed_const((16/pixel_bytes2)); 3521 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff); 3522 3523 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); 3524 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); 3525 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3526 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); 3527 if ((rdev->family == CHIP_R350) && 3528 (stop_req > 0x15)) { 3529 stop_req -= 0x10; 3530 } 3531 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3532 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; 3533 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | 3534 RADEON_GRPH_CRITICAL_AT_SOF | 3535 RADEON_GRPH_STOP_CNTL); 3536 3537 if ((rdev->family == CHIP_RS100) || 3538 (rdev->family == CHIP_RS200)) 3539 critical_point2 = 0; 3540 else { 3541 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; 3542 temp_ff.full = dfixed_const(temp); 3543 temp_ff.full = dfixed_mul(mclk_ff, temp_ff); 3544 if (sclk_ff.full < temp_ff.full) 3545 temp_ff.full = sclk_ff.full; 3546 3547 read_return_rate.full = temp_ff.full; 3548 3549 if (mode1) { 3550 temp_ff.full = read_return_rate.full - disp_drain_rate.full; 3551 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff); 3552 } else { 3553 time_disp1_drop_priority.full = 0; 3554 } 3555 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; 3556 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2); 3557 crit_point_ff.full += dfixed_const_half(0); 3558 3559 critical_point2 = dfixed_trunc(crit_point_ff); 3560 3561 if (rdev->disp_priority == 2) { 3562 critical_point2 = 0; 3563 } 3564 3565 if (max_stop_req - critical_point2 < 4) 3566 critical_point2 = 0; 3567 3568 } 3569 3570 if (critical_point2 == 0 && rdev->family == CHIP_R300) { 3571 /* some R300 cards have problem with this set to 0 */ 3572 critical_point2 = 0x10; 3573 } 3574 3575 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3576 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3577 3578 if ((rdev->family == CHIP_RS400) || 3579 (rdev->family == CHIP_RS480)) { 3580 #if 0 3581 /* attempt to program RS400 disp2 regs correctly ??? */ 3582 temp = RREG32(RS400_DISP2_REQ_CNTL1); 3583 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | 3584 RS400_DISP2_STOP_REQ_LEVEL_MASK); 3585 WREG32(RS400_DISP2_REQ_CNTL1, (temp | 3586 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3587 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3588 temp = RREG32(RS400_DISP2_REQ_CNTL2); 3589 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | 3590 RS400_DISP2_CRITICAL_POINT_STOP_MASK); 3591 WREG32(RS400_DISP2_REQ_CNTL2, (temp | 3592 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | 3593 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); 3594 #endif 3595 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); 3596 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); 3597 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); 3598 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); 3599 } 3600 3601 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n", 3602 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); 3603 } 3604 } 3605 3606 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 3607 { 3608 uint32_t scratch; 3609 uint32_t tmp = 0; 3610 unsigned i; 3611 int r; 3612 3613 r = radeon_scratch_get(rdev, &scratch); 3614 if (r) { 3615 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 3616 return r; 3617 } 3618 WREG32(scratch, 0xCAFEDEAD); 3619 r = radeon_ring_lock(rdev, ring, 2); 3620 if (r) { 3621 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 3622 radeon_scratch_free(rdev, scratch); 3623 return r; 3624 } 3625 radeon_ring_write(ring, PACKET0(scratch, 0)); 3626 radeon_ring_write(ring, 0xDEADBEEF); 3627 radeon_ring_unlock_commit(rdev, ring); 3628 for (i = 0; i < rdev->usec_timeout; i++) { 3629 tmp = RREG32(scratch); 3630 if (tmp == 0xDEADBEEF) { 3631 break; 3632 } 3633 DRM_UDELAY(1); 3634 } 3635 if (i < rdev->usec_timeout) { 3636 DRM_INFO("ring test succeeded in %d usecs\n", i); 3637 } else { 3638 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", 3639 scratch, tmp); 3640 r = -EINVAL; 3641 } 3642 radeon_scratch_free(rdev, scratch); 3643 return r; 3644 } 3645 3646 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3647 { 3648 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3649 3650 if (ring->rptr_save_reg) { 3651 u32 next_rptr = ring->wptr + 2 + 3; 3652 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0)); 3653 radeon_ring_write(ring, next_rptr); 3654 } 3655 3656 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1)); 3657 radeon_ring_write(ring, ib->gpu_addr); 3658 radeon_ring_write(ring, ib->length_dw); 3659 } 3660 3661 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3662 { 3663 struct radeon_ib ib; 3664 uint32_t scratch; 3665 uint32_t tmp = 0; 3666 unsigned i; 3667 int r; 3668 3669 r = radeon_scratch_get(rdev, &scratch); 3670 if (r) { 3671 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3672 return r; 3673 } 3674 WREG32(scratch, 0xCAFEDEAD); 3675 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256); 3676 if (r) { 3677 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3678 goto free_scratch; 3679 } 3680 ib.ptr[0] = PACKET0(scratch, 0); 3681 ib.ptr[1] = 0xDEADBEEF; 3682 ib.ptr[2] = PACKET2(0); 3683 ib.ptr[3] = PACKET2(0); 3684 ib.ptr[4] = PACKET2(0); 3685 ib.ptr[5] = PACKET2(0); 3686 ib.ptr[6] = PACKET2(0); 3687 ib.ptr[7] = PACKET2(0); 3688 ib.length_dw = 8; 3689 r = radeon_ib_schedule(rdev, &ib, NULL); 3690 if (r) { 3691 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3692 goto free_ib; 3693 } 3694 r = radeon_fence_wait(ib.fence, false); 3695 if (r) { 3696 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3697 goto free_ib; 3698 } 3699 for (i = 0; i < rdev->usec_timeout; i++) { 3700 tmp = RREG32(scratch); 3701 if (tmp == 0xDEADBEEF) { 3702 break; 3703 } 3704 DRM_UDELAY(1); 3705 } 3706 if (i < rdev->usec_timeout) { 3707 DRM_INFO("ib test succeeded in %u usecs\n", i); 3708 } else { 3709 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3710 scratch, tmp); 3711 r = -EINVAL; 3712 } 3713 free_ib: 3714 radeon_ib_free(rdev, &ib); 3715 free_scratch: 3716 radeon_scratch_free(rdev, scratch); 3717 return r; 3718 } 3719 3720 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) 3721 { 3722 /* Shutdown CP we shouldn't need to do that but better be safe than 3723 * sorry 3724 */ 3725 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 3726 WREG32(R_000740_CP_CSQ_CNTL, 0); 3727 3728 /* Save few CRTC registers */ 3729 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); 3730 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); 3731 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); 3732 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); 3733 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3734 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); 3735 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); 3736 } 3737 3738 /* Disable VGA aperture access */ 3739 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); 3740 /* Disable cursor, overlay, crtc */ 3741 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); 3742 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | 3743 S_000054_CRTC_DISPLAY_DIS(1)); 3744 WREG32(R_000050_CRTC_GEN_CNTL, 3745 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | 3746 S_000050_CRTC_DISP_REQ_EN_B(1)); 3747 WREG32(R_000420_OV0_SCALE_CNTL, 3748 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); 3749 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); 3750 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3751 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | 3752 S_000360_CUR2_LOCK(1)); 3753 WREG32(R_0003F8_CRTC2_GEN_CNTL, 3754 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | 3755 S_0003F8_CRTC2_DISPLAY_DIS(1) | 3756 S_0003F8_CRTC2_DISP_REQ_EN_B(1)); 3757 WREG32(R_000360_CUR2_OFFSET, 3758 C_000360_CUR2_LOCK & save->CUR2_OFFSET); 3759 } 3760 } 3761 3762 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) 3763 { 3764 /* Update base address for crtc */ 3765 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3766 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3767 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3768 } 3769 /* Restore CRTC registers */ 3770 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); 3771 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); 3772 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); 3773 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3774 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); 3775 } 3776 } 3777 3778 void r100_vga_render_disable(struct radeon_device *rdev) 3779 { 3780 u32 tmp; 3781 3782 tmp = RREG8(R_0003C2_GENMO_WT); 3783 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); 3784 } 3785 3786 static void r100_debugfs(struct radeon_device *rdev) 3787 { 3788 int r; 3789 3790 r = r100_debugfs_mc_info_init(rdev); 3791 if (r) 3792 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n"); 3793 } 3794 3795 static void r100_mc_program(struct radeon_device *rdev) 3796 { 3797 struct r100_mc_save save; 3798 3799 /* Stops all mc clients */ 3800 r100_mc_stop(rdev, &save); 3801 if (rdev->flags & RADEON_IS_AGP) { 3802 WREG32(R_00014C_MC_AGP_LOCATION, 3803 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 3804 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 3805 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 3806 if (rdev->family > CHIP_RV200) 3807 WREG32(R_00015C_AGP_BASE_2, 3808 upper_32_bits(rdev->mc.agp_base) & 0xff); 3809 } else { 3810 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 3811 WREG32(R_000170_AGP_BASE, 0); 3812 if (rdev->family > CHIP_RV200) 3813 WREG32(R_00015C_AGP_BASE_2, 0); 3814 } 3815 /* Wait for mc idle */ 3816 if (r100_mc_wait_for_idle(rdev)) 3817 dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); 3818 /* Program MC, should be a 32bits limited address space */ 3819 WREG32(R_000148_MC_FB_LOCATION, 3820 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 3821 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 3822 r100_mc_resume(rdev, &save); 3823 } 3824 3825 static void r100_clock_startup(struct radeon_device *rdev) 3826 { 3827 u32 tmp; 3828 3829 if (radeon_dynclks != -1 && radeon_dynclks) 3830 radeon_legacy_set_clock_gating(rdev, 1); 3831 /* We need to force on some of the block */ 3832 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 3833 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 3834 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) 3835 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); 3836 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 3837 } 3838 3839 static int r100_startup(struct radeon_device *rdev) 3840 { 3841 int r; 3842 3843 /* set common regs */ 3844 r100_set_common_regs(rdev); 3845 /* program mc */ 3846 r100_mc_program(rdev); 3847 /* Resume clock */ 3848 r100_clock_startup(rdev); 3849 /* Initialize GART (initialize after TTM so we can allocate 3850 * memory through TTM but finalize after TTM) */ 3851 r100_enable_bm(rdev); 3852 if (rdev->flags & RADEON_IS_PCI) { 3853 r = r100_pci_gart_enable(rdev); 3854 if (r) 3855 return r; 3856 } 3857 3858 /* allocate wb buffer */ 3859 r = radeon_wb_init(rdev); 3860 if (r) 3861 return r; 3862 3863 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 3864 if (r) { 3865 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 3866 return r; 3867 } 3868 3869 /* Enable IRQ */ 3870 if (!rdev->irq.installed) { 3871 r = radeon_irq_kms_init(rdev); 3872 if (r) 3873 return r; 3874 } 3875 3876 r100_irq_set(rdev); 3877 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 3878 /* 1M ring buffer */ 3879 r = r100_cp_init(rdev, 1024 * 1024); 3880 if (r) { 3881 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 3882 return r; 3883 } 3884 3885 r = radeon_ib_pool_init(rdev); 3886 if (r) { 3887 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 3888 return r; 3889 } 3890 3891 return 0; 3892 } 3893 3894 int r100_resume(struct radeon_device *rdev) 3895 { 3896 int r; 3897 3898 /* Make sur GART are not working */ 3899 if (rdev->flags & RADEON_IS_PCI) 3900 r100_pci_gart_disable(rdev); 3901 /* Resume clock before doing reset */ 3902 r100_clock_startup(rdev); 3903 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 3904 if (radeon_asic_reset(rdev)) { 3905 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 3906 RREG32(R_000E40_RBBM_STATUS), 3907 RREG32(R_0007C0_CP_STAT)); 3908 } 3909 /* post */ 3910 radeon_combios_asic_init(rdev->ddev); 3911 /* Resume clock after posting */ 3912 r100_clock_startup(rdev); 3913 /* Initialize surface registers */ 3914 radeon_surface_init(rdev); 3915 3916 rdev->accel_working = true; 3917 r = r100_startup(rdev); 3918 if (r) { 3919 rdev->accel_working = false; 3920 } 3921 return r; 3922 } 3923 3924 int r100_suspend(struct radeon_device *rdev) 3925 { 3926 r100_cp_disable(rdev); 3927 radeon_wb_disable(rdev); 3928 r100_irq_disable(rdev); 3929 if (rdev->flags & RADEON_IS_PCI) 3930 r100_pci_gart_disable(rdev); 3931 return 0; 3932 } 3933 3934 void r100_fini(struct radeon_device *rdev) 3935 { 3936 r100_cp_fini(rdev); 3937 radeon_wb_fini(rdev); 3938 radeon_ib_pool_fini(rdev); 3939 radeon_gem_fini(rdev); 3940 if (rdev->flags & RADEON_IS_PCI) 3941 r100_pci_gart_fini(rdev); 3942 radeon_agp_fini(rdev); 3943 radeon_irq_kms_fini(rdev); 3944 radeon_fence_driver_fini(rdev); 3945 radeon_bo_fini(rdev); 3946 radeon_atombios_fini(rdev); 3947 kfree(rdev->bios); 3948 rdev->bios = NULL; 3949 } 3950 3951 /* 3952 * Due to how kexec works, it can leave the hw fully initialised when it 3953 * boots the new kernel. However doing our init sequence with the CP and 3954 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup 3955 * do some quick sanity checks and restore sane values to avoid this 3956 * problem. 3957 */ 3958 void r100_restore_sanity(struct radeon_device *rdev) 3959 { 3960 u32 tmp; 3961 3962 tmp = RREG32(RADEON_CP_CSQ_CNTL); 3963 if (tmp) { 3964 WREG32(RADEON_CP_CSQ_CNTL, 0); 3965 } 3966 tmp = RREG32(RADEON_CP_RB_CNTL); 3967 if (tmp) { 3968 WREG32(RADEON_CP_RB_CNTL, 0); 3969 } 3970 tmp = RREG32(RADEON_SCRATCH_UMSK); 3971 if (tmp) { 3972 WREG32(RADEON_SCRATCH_UMSK, 0); 3973 } 3974 } 3975 3976 int r100_init(struct radeon_device *rdev) 3977 { 3978 int r; 3979 3980 /* Register debugfs file specific to this group of asics */ 3981 r100_debugfs(rdev); 3982 /* Disable VGA */ 3983 r100_vga_render_disable(rdev); 3984 /* Initialize scratch registers */ 3985 radeon_scratch_init(rdev); 3986 /* Initialize surface registers */ 3987 radeon_surface_init(rdev); 3988 /* sanity check some register to avoid hangs like after kexec */ 3989 r100_restore_sanity(rdev); 3990 /* TODO: disable VGA need to use VGA request */ 3991 /* BIOS*/ 3992 if (!radeon_get_bios(rdev)) { 3993 if (ASIC_IS_AVIVO(rdev)) 3994 return -EINVAL; 3995 } 3996 if (rdev->is_atom_bios) { 3997 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 3998 return -EINVAL; 3999 } else { 4000 r = radeon_combios_init(rdev); 4001 if (r) 4002 return r; 4003 } 4004 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 4005 if (radeon_asic_reset(rdev)) { 4006 dev_warn(rdev->dev, 4007 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 4008 RREG32(R_000E40_RBBM_STATUS), 4009 RREG32(R_0007C0_CP_STAT)); 4010 } 4011 /* check if cards are posted or not */ 4012 if (radeon_boot_test_post_card(rdev) == false) 4013 return -EINVAL; 4014 /* Set asic errata */ 4015 r100_errata(rdev); 4016 /* Initialize clocks */ 4017 radeon_get_clock_info(rdev->ddev); 4018 /* initialize AGP */ 4019 if (rdev->flags & RADEON_IS_AGP) { 4020 r = radeon_agp_init(rdev); 4021 if (r) { 4022 radeon_agp_disable(rdev); 4023 } 4024 } 4025 /* initialize VRAM */ 4026 r100_mc_init(rdev); 4027 /* Fence driver */ 4028 r = radeon_fence_driver_init(rdev); 4029 if (r) 4030 return r; 4031 /* Memory manager */ 4032 r = radeon_bo_init(rdev); 4033 if (r) 4034 return r; 4035 if (rdev->flags & RADEON_IS_PCI) { 4036 r = r100_pci_gart_init(rdev); 4037 if (r) 4038 return r; 4039 } 4040 r100_set_safe_registers(rdev); 4041 4042 rdev->accel_working = true; 4043 r = r100_startup(rdev); 4044 if (r) { 4045 /* Somethings want wront with the accel init stop accel */ 4046 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 4047 r100_cp_fini(rdev); 4048 radeon_wb_fini(rdev); 4049 radeon_ib_pool_fini(rdev); 4050 radeon_irq_kms_fini(rdev); 4051 if (rdev->flags & RADEON_IS_PCI) 4052 r100_pci_gart_fini(rdev); 4053 rdev->accel_working = false; 4054 } 4055 return 0; 4056 } 4057 4058 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 4059 bool always_indirect) 4060 { 4061 if (reg < rdev->rmmio_size && !always_indirect) 4062 return readl(((void __iomem *)rdev->rmmio) + reg); 4063 else { 4064 unsigned long flags; 4065 uint32_t ret; 4066 4067 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 4068 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 4069 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 4070 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 4071 4072 return ret; 4073 } 4074 } 4075 4076 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 4077 bool always_indirect) 4078 { 4079 if (reg < rdev->rmmio_size && !always_indirect) 4080 writel(v, ((void __iomem *)rdev->rmmio) + reg); 4081 else { 4082 unsigned long flags; 4083 4084 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 4085 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 4086 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 4087 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 4088 } 4089 } 4090 4091 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) 4092 { 4093 if (reg < rdev->rio_mem_size) 4094 return ioread32(rdev->rio_mem + reg); 4095 else { 4096 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); 4097 return ioread32(rdev->rio_mem + RADEON_MM_DATA); 4098 } 4099 } 4100 4101 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) 4102 { 4103 if (reg < rdev->rio_mem_size) 4104 iowrite32(v, rdev->rio_mem + reg); 4105 else { 4106 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); 4107 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); 4108 } 4109 } 4110