1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2008 Advanced Micro Devices, Inc. 3771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 4771fe6b9SJerome Glisse * Copyright 2009 Jerome Glisse. 5771fe6b9SJerome Glisse * 6771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 7771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 8771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 9771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 11771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 12771fe6b9SJerome Glisse * 13771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 14771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 15771fe6b9SJerome Glisse * 16771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 23771fe6b9SJerome Glisse * 24771fe6b9SJerome Glisse * Authors: Dave Airlie 25771fe6b9SJerome Glisse * Alex Deucher 26771fe6b9SJerome Glisse * Jerome Glisse 27771fe6b9SJerome Glisse */ 28c182615fSSam Ravnborg 2970967ab9SBen Hutchings #include <linux/firmware.h> 30e0cd3608SPaul Gortmaker #include <linux/module.h> 312ef79416SThomas Zimmermann #include <linux/pci.h> 322ef79416SThomas Zimmermann #include <linux/seq_file.h> 332ef79416SThomas Zimmermann #include <linux/slab.h> 3470967ab9SBen Hutchings 35c182615fSSam Ravnborg #include <drm/drm_device.h> 36c182615fSSam Ravnborg #include <drm/drm_file.h> 37c182615fSSam Ravnborg #include <drm/drm_fourcc.h> 38c182615fSSam Ravnborg #include <drm/drm_vblank.h> 39c182615fSSam Ravnborg #include <drm/radeon_drm.h> 40c182615fSSam Ravnborg 41c182615fSSam Ravnborg #include "atom.h" 42551ebd83SDave Airlie #include "r100_reg_safe.h" 43c182615fSSam Ravnborg #include "r100d.h" 44c182615fSSam Ravnborg #include "radeon.h" 45c182615fSSam Ravnborg #include "radeon_asic.h" 46c182615fSSam Ravnborg #include "radeon_reg.h" 47551ebd83SDave Airlie #include "rn50_reg_safe.h" 48c182615fSSam Ravnborg #include "rs100d.h" 49c182615fSSam Ravnborg #include "rv200d.h" 50c182615fSSam Ravnborg #include "rv250d.h" 51551ebd83SDave Airlie 5270967ab9SBen Hutchings /* Firmware Names */ 5370967ab9SBen Hutchings #define FIRMWARE_R100 "radeon/R100_cp.bin" 5470967ab9SBen Hutchings #define FIRMWARE_R200 "radeon/R200_cp.bin" 5570967ab9SBen Hutchings #define FIRMWARE_R300 "radeon/R300_cp.bin" 5670967ab9SBen Hutchings #define FIRMWARE_R420 "radeon/R420_cp.bin" 5770967ab9SBen Hutchings #define FIRMWARE_RS690 "radeon/RS690_cp.bin" 5870967ab9SBen Hutchings #define FIRMWARE_RS600 "radeon/RS600_cp.bin" 5970967ab9SBen Hutchings #define FIRMWARE_R520 "radeon/R520_cp.bin" 6070967ab9SBen Hutchings 6170967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_R100); 6270967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_R200); 6370967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_R300); 6470967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_R420); 6570967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_RS690); 6670967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_RS600); 6770967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_R520); 68771fe6b9SJerome Glisse 69551ebd83SDave Airlie #include "r100_track.h" 70551ebd83SDave Airlie 7148ef779fSAlex Deucher /* This files gather functions specifics to: 7248ef779fSAlex Deucher * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 7348ef779fSAlex Deucher * and others in some cases. 7448ef779fSAlex Deucher */ 7548ef779fSAlex Deucher 762b48b968SAlex Deucher static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc) 772b48b968SAlex Deucher { 782b48b968SAlex Deucher if (crtc == 0) { 792b48b968SAlex Deucher if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) 802b48b968SAlex Deucher return true; 812b48b968SAlex Deucher else 822b48b968SAlex Deucher return false; 832b48b968SAlex Deucher } else { 842b48b968SAlex Deucher if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) 852b48b968SAlex Deucher return true; 862b48b968SAlex Deucher else 872b48b968SAlex Deucher return false; 882b48b968SAlex Deucher } 892b48b968SAlex Deucher } 902b48b968SAlex Deucher 912b48b968SAlex Deucher static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc) 922b48b968SAlex Deucher { 932b48b968SAlex Deucher u32 vline1, vline2; 942b48b968SAlex Deucher 952b48b968SAlex Deucher if (crtc == 0) { 962b48b968SAlex Deucher vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 972b48b968SAlex Deucher vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 982b48b968SAlex Deucher } else { 992b48b968SAlex Deucher vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1002b48b968SAlex Deucher vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1012b48b968SAlex Deucher } 1022b48b968SAlex Deucher if (vline1 != vline2) 1032b48b968SAlex Deucher return true; 1042b48b968SAlex Deucher else 1052b48b968SAlex Deucher return false; 1062b48b968SAlex Deucher } 1072b48b968SAlex Deucher 10848ef779fSAlex Deucher /** 10948ef779fSAlex Deucher * r100_wait_for_vblank - vblank wait asic callback. 11048ef779fSAlex Deucher * 11148ef779fSAlex Deucher * @rdev: radeon_device pointer 11248ef779fSAlex Deucher * @crtc: crtc to wait for vblank on 11348ef779fSAlex Deucher * 11448ef779fSAlex Deucher * Wait for vblank on the requested crtc (r1xx-r4xx). 11548ef779fSAlex Deucher */ 1163ae19b75SAlex Deucher void r100_wait_for_vblank(struct radeon_device *rdev, int crtc) 1173ae19b75SAlex Deucher { 1182b48b968SAlex Deucher unsigned i = 0; 1193ae19b75SAlex Deucher 12094f768fdSAlex Deucher if (crtc >= rdev->num_crtc) 12194f768fdSAlex Deucher return; 12294f768fdSAlex Deucher 12394f768fdSAlex Deucher if (crtc == 0) { 1242b48b968SAlex Deucher if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN)) 1252b48b968SAlex Deucher return; 1263ae19b75SAlex Deucher } else { 1272b48b968SAlex Deucher if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN)) 1282b48b968SAlex Deucher return; 1293ae19b75SAlex Deucher } 1302b48b968SAlex Deucher 1312b48b968SAlex Deucher /* depending on when we hit vblank, we may be close to active; if so, 1322b48b968SAlex Deucher * wait for another frame. 1332b48b968SAlex Deucher */ 1342b48b968SAlex Deucher while (r100_is_in_vblank(rdev, crtc)) { 1352b48b968SAlex Deucher if (i++ % 100 == 0) { 1362b48b968SAlex Deucher if (!r100_is_counter_moving(rdev, crtc)) 1373ae19b75SAlex Deucher break; 1383ae19b75SAlex Deucher } 1393ae19b75SAlex Deucher } 1402b48b968SAlex Deucher 1412b48b968SAlex Deucher while (!r100_is_in_vblank(rdev, crtc)) { 1422b48b968SAlex Deucher if (i++ % 100 == 0) { 1432b48b968SAlex Deucher if (!r100_is_counter_moving(rdev, crtc)) 1442b48b968SAlex Deucher break; 1452b48b968SAlex Deucher } 1463ae19b75SAlex Deucher } 1473ae19b75SAlex Deucher } 1483ae19b75SAlex Deucher 14948ef779fSAlex Deucher /** 15048ef779fSAlex Deucher * r100_page_flip - pageflip callback. 15148ef779fSAlex Deucher * 15248ef779fSAlex Deucher * @rdev: radeon_device pointer 15348ef779fSAlex Deucher * @crtc_id: crtc to cleanup pageflip on 15448ef779fSAlex Deucher * @crtc_base: new address of the crtc (GPU MC address) 1550d8357c2SLee Jones * @async: asynchronous flip 15648ef779fSAlex Deucher * 15748ef779fSAlex Deucher * Does the actual pageflip (r1xx-r4xx). 15848ef779fSAlex Deucher * During vblank we take the crtc lock and wait for the update_pending 15948ef779fSAlex Deucher * bit to go high, when it does, we release the lock, and allow the 16048ef779fSAlex Deucher * double buffered update to take place. 16148ef779fSAlex Deucher */ 162c63dd758SMichel Dänzer void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async) 1636f34be50SAlex Deucher { 1646f34be50SAlex Deucher struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 165*c841e552SZhenneng Li uint32_t crtc_pitch, pitch_pixels; 166*c841e552SZhenneng Li struct drm_framebuffer *fb = radeon_crtc->base.primary->fb; 1676f34be50SAlex Deucher u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; 168f6496479SAlex Deucher int i; 1696f34be50SAlex Deucher 1706f34be50SAlex Deucher /* Lock the graphics update lock */ 1716f34be50SAlex Deucher /* update the scanout addresses */ 1726f34be50SAlex Deucher WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 1736f34be50SAlex Deucher 174*c841e552SZhenneng Li /* update pitch */ 175*c841e552SZhenneng Li pitch_pixels = fb->pitches[0] / fb->format->cpp[0]; 176*c841e552SZhenneng Li crtc_pitch = DIV_ROUND_UP(pitch_pixels * fb->format->cpp[0] * 8, 177*c841e552SZhenneng Li fb->format->cpp[0] * 8 * 8); 178*c841e552SZhenneng Li crtc_pitch |= crtc_pitch << 16; 179*c841e552SZhenneng Li WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); 180*c841e552SZhenneng Li 181acb32506SAlex Deucher /* Wait for update_pending to go high. */ 182f6496479SAlex Deucher for (i = 0; i < rdev->usec_timeout; i++) { 183f6496479SAlex Deucher if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) 184f6496479SAlex Deucher break; 185f6496479SAlex Deucher udelay(1); 186f6496479SAlex Deucher } 187acb32506SAlex Deucher DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 1886f34be50SAlex Deucher 1896f34be50SAlex Deucher /* Unlock the lock, so double-buffering can take place inside vblank */ 1906f34be50SAlex Deucher tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK; 1916f34be50SAlex Deucher WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 1926f34be50SAlex Deucher 193157fa14dSChristian König } 194157fa14dSChristian König 195157fa14dSChristian König /** 196157fa14dSChristian König * r100_page_flip_pending - check if page flip is still pending 197157fa14dSChristian König * 198157fa14dSChristian König * @rdev: radeon_device pointer 199157fa14dSChristian König * @crtc_id: crtc to check 200157fa14dSChristian König * 201157fa14dSChristian König * Check if the last pagefilp is still pending (r1xx-r4xx). 202157fa14dSChristian König * Returns the current update pending status. 203157fa14dSChristian König */ 204157fa14dSChristian König bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id) 205157fa14dSChristian König { 206157fa14dSChristian König struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 207157fa14dSChristian König 2086f34be50SAlex Deucher /* Return current update_pending status: */ 209157fa14dSChristian König return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & 210157fa14dSChristian König RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET); 2116f34be50SAlex Deucher } 2126f34be50SAlex Deucher 21348ef779fSAlex Deucher /** 21448ef779fSAlex Deucher * r100_pm_get_dynpm_state - look up dynpm power state callback. 21548ef779fSAlex Deucher * 21648ef779fSAlex Deucher * @rdev: radeon_device pointer 21748ef779fSAlex Deucher * 21848ef779fSAlex Deucher * Look up the optimal power state based on the 21948ef779fSAlex Deucher * current state of the GPU (r1xx-r5xx). 22048ef779fSAlex Deucher * Used for dynpm only. 22148ef779fSAlex Deucher */ 222ce8f5370SAlex Deucher void r100_pm_get_dynpm_state(struct radeon_device *rdev) 223a48b9b4eSAlex Deucher { 224a48b9b4eSAlex Deucher int i; 225ce8f5370SAlex Deucher rdev->pm.dynpm_can_upclock = true; 226ce8f5370SAlex Deucher rdev->pm.dynpm_can_downclock = true; 227a48b9b4eSAlex Deucher 228ce8f5370SAlex Deucher switch (rdev->pm.dynpm_planned_action) { 229ce8f5370SAlex Deucher case DYNPM_ACTION_MINIMUM: 230a48b9b4eSAlex Deucher rdev->pm.requested_power_state_index = 0; 231ce8f5370SAlex Deucher rdev->pm.dynpm_can_downclock = false; 232a48b9b4eSAlex Deucher break; 233ce8f5370SAlex Deucher case DYNPM_ACTION_DOWNCLOCK: 234a48b9b4eSAlex Deucher if (rdev->pm.current_power_state_index == 0) { 235a48b9b4eSAlex Deucher rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 236ce8f5370SAlex Deucher rdev->pm.dynpm_can_downclock = false; 237a48b9b4eSAlex Deucher } else { 238a48b9b4eSAlex Deucher if (rdev->pm.active_crtc_count > 1) { 239a48b9b4eSAlex Deucher for (i = 0; i < rdev->pm.num_power_states; i++) { 240d7311171SAlex Deucher if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 241a48b9b4eSAlex Deucher continue; 242a48b9b4eSAlex Deucher else if (i >= rdev->pm.current_power_state_index) { 243a48b9b4eSAlex Deucher rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 244a48b9b4eSAlex Deucher break; 245a48b9b4eSAlex Deucher } else { 246a48b9b4eSAlex Deucher rdev->pm.requested_power_state_index = i; 247a48b9b4eSAlex Deucher break; 248a48b9b4eSAlex Deucher } 249a48b9b4eSAlex Deucher } 250a48b9b4eSAlex Deucher } else 251a48b9b4eSAlex Deucher rdev->pm.requested_power_state_index = 252a48b9b4eSAlex Deucher rdev->pm.current_power_state_index - 1; 253a48b9b4eSAlex Deucher } 254d7311171SAlex Deucher /* don't use the power state if crtcs are active and no display flag is set */ 255d7311171SAlex Deucher if ((rdev->pm.active_crtc_count > 0) && 256d7311171SAlex Deucher (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & 257d7311171SAlex Deucher RADEON_PM_MODE_NO_DISPLAY)) { 258d7311171SAlex Deucher rdev->pm.requested_power_state_index++; 259d7311171SAlex Deucher } 260a48b9b4eSAlex Deucher break; 261ce8f5370SAlex Deucher case DYNPM_ACTION_UPCLOCK: 262a48b9b4eSAlex Deucher if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 263a48b9b4eSAlex Deucher rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 264ce8f5370SAlex Deucher rdev->pm.dynpm_can_upclock = false; 265a48b9b4eSAlex Deucher } else { 266a48b9b4eSAlex Deucher if (rdev->pm.active_crtc_count > 1) { 267a48b9b4eSAlex Deucher for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 268d7311171SAlex Deucher if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 269a48b9b4eSAlex Deucher continue; 270a48b9b4eSAlex Deucher else if (i <= rdev->pm.current_power_state_index) { 271a48b9b4eSAlex Deucher rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 272a48b9b4eSAlex Deucher break; 273a48b9b4eSAlex Deucher } else { 274a48b9b4eSAlex Deucher rdev->pm.requested_power_state_index = i; 275a48b9b4eSAlex Deucher break; 276a48b9b4eSAlex Deucher } 277a48b9b4eSAlex Deucher } 278a48b9b4eSAlex Deucher } else 279a48b9b4eSAlex Deucher rdev->pm.requested_power_state_index = 280a48b9b4eSAlex Deucher rdev->pm.current_power_state_index + 1; 281a48b9b4eSAlex Deucher } 282a48b9b4eSAlex Deucher break; 283ce8f5370SAlex Deucher case DYNPM_ACTION_DEFAULT: 28458e21dffSAlex Deucher rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 285ce8f5370SAlex Deucher rdev->pm.dynpm_can_upclock = false; 28658e21dffSAlex Deucher break; 287ce8f5370SAlex Deucher case DYNPM_ACTION_NONE: 288a48b9b4eSAlex Deucher default: 289a48b9b4eSAlex Deucher DRM_ERROR("Requested mode for not defined action\n"); 290a48b9b4eSAlex Deucher return; 291a48b9b4eSAlex Deucher } 292a48b9b4eSAlex Deucher /* only one clock mode per power state */ 293a48b9b4eSAlex Deucher rdev->pm.requested_clock_mode_index = 0; 294a48b9b4eSAlex Deucher 295d9fdaafbSDave Airlie DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 296a48b9b4eSAlex Deucher rdev->pm.power_state[rdev->pm.requested_power_state_index]. 297a48b9b4eSAlex Deucher clock_info[rdev->pm.requested_clock_mode_index].sclk, 298a48b9b4eSAlex Deucher rdev->pm.power_state[rdev->pm.requested_power_state_index]. 299a48b9b4eSAlex Deucher clock_info[rdev->pm.requested_clock_mode_index].mclk, 300a48b9b4eSAlex Deucher rdev->pm.power_state[rdev->pm.requested_power_state_index]. 30179daedc9SAlex Deucher pcie_lanes); 302a48b9b4eSAlex Deucher } 303a48b9b4eSAlex Deucher 30448ef779fSAlex Deucher /** 30548ef779fSAlex Deucher * r100_pm_init_profile - Initialize power profiles callback. 30648ef779fSAlex Deucher * 30748ef779fSAlex Deucher * @rdev: radeon_device pointer 30848ef779fSAlex Deucher * 30948ef779fSAlex Deucher * Initialize the power states used in profile mode 31048ef779fSAlex Deucher * (r1xx-r3xx). 31148ef779fSAlex Deucher * Used for profile mode only. 31248ef779fSAlex Deucher */ 313ce8f5370SAlex Deucher void r100_pm_init_profile(struct radeon_device *rdev) 314bae6b562SAlex Deucher { 315ce8f5370SAlex Deucher /* default */ 316ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 317ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 318ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 319ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 320ce8f5370SAlex Deucher /* low sh */ 321ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 322ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 323ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 324ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 325c9e75b21SAlex Deucher /* mid sh */ 326c9e75b21SAlex Deucher rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 327c9e75b21SAlex Deucher rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 328c9e75b21SAlex Deucher rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 329c9e75b21SAlex Deucher rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 330ce8f5370SAlex Deucher /* high sh */ 331ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 332ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 333ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 334ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 335ce8f5370SAlex Deucher /* low mh */ 336ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 337ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 338ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 339ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 340c9e75b21SAlex Deucher /* mid mh */ 341c9e75b21SAlex Deucher rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 342c9e75b21SAlex Deucher rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 343c9e75b21SAlex Deucher rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 344c9e75b21SAlex Deucher rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 345ce8f5370SAlex Deucher /* high mh */ 346ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 347ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 348ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 349ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 350bae6b562SAlex Deucher } 351bae6b562SAlex Deucher 35248ef779fSAlex Deucher /** 35348ef779fSAlex Deucher * r100_pm_misc - set additional pm hw parameters callback. 35448ef779fSAlex Deucher * 35548ef779fSAlex Deucher * @rdev: radeon_device pointer 35648ef779fSAlex Deucher * 35748ef779fSAlex Deucher * Set non-clock parameters associated with a power state 35848ef779fSAlex Deucher * (voltage, pcie lanes, etc.) (r1xx-r4xx). 35948ef779fSAlex Deucher */ 36049e02b73SAlex Deucher void r100_pm_misc(struct radeon_device *rdev) 36149e02b73SAlex Deucher { 36249e02b73SAlex Deucher int requested_index = rdev->pm.requested_power_state_index; 36349e02b73SAlex Deucher struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 36449e02b73SAlex Deucher struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 36549e02b73SAlex Deucher u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl; 36649e02b73SAlex Deucher 36749e02b73SAlex Deucher if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { 36849e02b73SAlex Deucher if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { 36949e02b73SAlex Deucher tmp = RREG32(voltage->gpio.reg); 37049e02b73SAlex Deucher if (voltage->active_high) 37149e02b73SAlex Deucher tmp |= voltage->gpio.mask; 37249e02b73SAlex Deucher else 37349e02b73SAlex Deucher tmp &= ~(voltage->gpio.mask); 37449e02b73SAlex Deucher WREG32(voltage->gpio.reg, tmp); 37549e02b73SAlex Deucher if (voltage->delay) 37649e02b73SAlex Deucher udelay(voltage->delay); 37749e02b73SAlex Deucher } else { 37849e02b73SAlex Deucher tmp = RREG32(voltage->gpio.reg); 37949e02b73SAlex Deucher if (voltage->active_high) 38049e02b73SAlex Deucher tmp &= ~voltage->gpio.mask; 38149e02b73SAlex Deucher else 38249e02b73SAlex Deucher tmp |= voltage->gpio.mask; 38349e02b73SAlex Deucher WREG32(voltage->gpio.reg, tmp); 38449e02b73SAlex Deucher if (voltage->delay) 38549e02b73SAlex Deucher udelay(voltage->delay); 38649e02b73SAlex Deucher } 38749e02b73SAlex Deucher } 38849e02b73SAlex Deucher 38949e02b73SAlex Deucher sclk_cntl = RREG32_PLL(SCLK_CNTL); 39049e02b73SAlex Deucher sclk_cntl2 = RREG32_PLL(SCLK_CNTL2); 39149e02b73SAlex Deucher sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3); 39249e02b73SAlex Deucher sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL); 39349e02b73SAlex Deucher sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3); 39449e02b73SAlex Deucher if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { 39549e02b73SAlex Deucher sclk_more_cntl |= REDUCED_SPEED_SCLK_EN; 39649e02b73SAlex Deucher if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE) 39749e02b73SAlex Deucher sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE; 39849e02b73SAlex Deucher else 39949e02b73SAlex Deucher sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE; 40049e02b73SAlex Deucher if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) 40149e02b73SAlex Deucher sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0); 40249e02b73SAlex Deucher else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) 40349e02b73SAlex Deucher sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2); 40449e02b73SAlex Deucher } else 40549e02b73SAlex Deucher sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN; 40649e02b73SAlex Deucher 40749e02b73SAlex Deucher if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { 40849e02b73SAlex Deucher sclk_more_cntl |= IO_CG_VOLTAGE_DROP; 40949e02b73SAlex Deucher if (voltage->delay) { 41049e02b73SAlex Deucher sclk_more_cntl |= VOLTAGE_DROP_SYNC; 41149e02b73SAlex Deucher switch (voltage->delay) { 41249e02b73SAlex Deucher case 33: 41349e02b73SAlex Deucher sclk_more_cntl |= VOLTAGE_DELAY_SEL(0); 41449e02b73SAlex Deucher break; 41549e02b73SAlex Deucher case 66: 41649e02b73SAlex Deucher sclk_more_cntl |= VOLTAGE_DELAY_SEL(1); 41749e02b73SAlex Deucher break; 41849e02b73SAlex Deucher case 99: 41949e02b73SAlex Deucher sclk_more_cntl |= VOLTAGE_DELAY_SEL(2); 42049e02b73SAlex Deucher break; 42149e02b73SAlex Deucher case 132: 42249e02b73SAlex Deucher sclk_more_cntl |= VOLTAGE_DELAY_SEL(3); 42349e02b73SAlex Deucher break; 42449e02b73SAlex Deucher } 42549e02b73SAlex Deucher } else 42649e02b73SAlex Deucher sclk_more_cntl &= ~VOLTAGE_DROP_SYNC; 42749e02b73SAlex Deucher } else 42849e02b73SAlex Deucher sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP; 42949e02b73SAlex Deucher 43049e02b73SAlex Deucher if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) 43149e02b73SAlex Deucher sclk_cntl &= ~FORCE_HDP; 43249e02b73SAlex Deucher else 43349e02b73SAlex Deucher sclk_cntl |= FORCE_HDP; 43449e02b73SAlex Deucher 43549e02b73SAlex Deucher WREG32_PLL(SCLK_CNTL, sclk_cntl); 43649e02b73SAlex Deucher WREG32_PLL(SCLK_CNTL2, sclk_cntl2); 43749e02b73SAlex Deucher WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl); 43849e02b73SAlex Deucher 43949e02b73SAlex Deucher /* set pcie lanes */ 44049e02b73SAlex Deucher if ((rdev->flags & RADEON_IS_PCIE) && 44149e02b73SAlex Deucher !(rdev->flags & RADEON_IS_IGP) && 442798bcf73SAlex Deucher rdev->asic->pm.set_pcie_lanes && 44349e02b73SAlex Deucher (ps->pcie_lanes != 44449e02b73SAlex Deucher rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { 44549e02b73SAlex Deucher radeon_set_pcie_lanes(rdev, 44649e02b73SAlex Deucher ps->pcie_lanes); 447d9fdaafbSDave Airlie DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes); 44849e02b73SAlex Deucher } 44949e02b73SAlex Deucher } 45049e02b73SAlex Deucher 45148ef779fSAlex Deucher /** 45248ef779fSAlex Deucher * r100_pm_prepare - pre-power state change callback. 45348ef779fSAlex Deucher * 45448ef779fSAlex Deucher * @rdev: radeon_device pointer 45548ef779fSAlex Deucher * 45648ef779fSAlex Deucher * Prepare for a power state change (r1xx-r4xx). 45748ef779fSAlex Deucher */ 45849e02b73SAlex Deucher void r100_pm_prepare(struct radeon_device *rdev) 45949e02b73SAlex Deucher { 46049e02b73SAlex Deucher struct drm_device *ddev = rdev->ddev; 46149e02b73SAlex Deucher struct drm_crtc *crtc; 46249e02b73SAlex Deucher struct radeon_crtc *radeon_crtc; 46349e02b73SAlex Deucher u32 tmp; 46449e02b73SAlex Deucher 46549e02b73SAlex Deucher /* disable any active CRTCs */ 46649e02b73SAlex Deucher list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 46749e02b73SAlex Deucher radeon_crtc = to_radeon_crtc(crtc); 46849e02b73SAlex Deucher if (radeon_crtc->enabled) { 46949e02b73SAlex Deucher if (radeon_crtc->crtc_id) { 47049e02b73SAlex Deucher tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 47149e02b73SAlex Deucher tmp |= RADEON_CRTC2_DISP_REQ_EN_B; 47249e02b73SAlex Deucher WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 47349e02b73SAlex Deucher } else { 47449e02b73SAlex Deucher tmp = RREG32(RADEON_CRTC_GEN_CNTL); 47549e02b73SAlex Deucher tmp |= RADEON_CRTC_DISP_REQ_EN_B; 47649e02b73SAlex Deucher WREG32(RADEON_CRTC_GEN_CNTL, tmp); 47749e02b73SAlex Deucher } 47849e02b73SAlex Deucher } 47949e02b73SAlex Deucher } 48049e02b73SAlex Deucher } 48149e02b73SAlex Deucher 48248ef779fSAlex Deucher /** 48348ef779fSAlex Deucher * r100_pm_finish - post-power state change callback. 48448ef779fSAlex Deucher * 48548ef779fSAlex Deucher * @rdev: radeon_device pointer 48648ef779fSAlex Deucher * 48748ef779fSAlex Deucher * Clean up after a power state change (r1xx-r4xx). 48848ef779fSAlex Deucher */ 48949e02b73SAlex Deucher void r100_pm_finish(struct radeon_device *rdev) 49049e02b73SAlex Deucher { 49149e02b73SAlex Deucher struct drm_device *ddev = rdev->ddev; 49249e02b73SAlex Deucher struct drm_crtc *crtc; 49349e02b73SAlex Deucher struct radeon_crtc *radeon_crtc; 49449e02b73SAlex Deucher u32 tmp; 49549e02b73SAlex Deucher 49649e02b73SAlex Deucher /* enable any active CRTCs */ 49749e02b73SAlex Deucher list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 49849e02b73SAlex Deucher radeon_crtc = to_radeon_crtc(crtc); 49949e02b73SAlex Deucher if (radeon_crtc->enabled) { 50049e02b73SAlex Deucher if (radeon_crtc->crtc_id) { 50149e02b73SAlex Deucher tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 50249e02b73SAlex Deucher tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B; 50349e02b73SAlex Deucher WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 50449e02b73SAlex Deucher } else { 50549e02b73SAlex Deucher tmp = RREG32(RADEON_CRTC_GEN_CNTL); 50649e02b73SAlex Deucher tmp &= ~RADEON_CRTC_DISP_REQ_EN_B; 50749e02b73SAlex Deucher WREG32(RADEON_CRTC_GEN_CNTL, tmp); 50849e02b73SAlex Deucher } 50949e02b73SAlex Deucher } 51049e02b73SAlex Deucher } 51149e02b73SAlex Deucher } 51249e02b73SAlex Deucher 51348ef779fSAlex Deucher /** 51448ef779fSAlex Deucher * r100_gui_idle - gui idle callback. 51548ef779fSAlex Deucher * 51648ef779fSAlex Deucher * @rdev: radeon_device pointer 51748ef779fSAlex Deucher * 51848ef779fSAlex Deucher * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx). 51948ef779fSAlex Deucher * Returns true if idle, false if not. 52048ef779fSAlex Deucher */ 521def9ba9cSAlex Deucher bool r100_gui_idle(struct radeon_device *rdev) 522def9ba9cSAlex Deucher { 523def9ba9cSAlex Deucher if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) 524def9ba9cSAlex Deucher return false; 525def9ba9cSAlex Deucher else 526def9ba9cSAlex Deucher return true; 527def9ba9cSAlex Deucher } 528def9ba9cSAlex Deucher 52905a05c50SAlex Deucher /* hpd for digital panel detect/disconnect */ 53048ef779fSAlex Deucher /** 53148ef779fSAlex Deucher * r100_hpd_sense - hpd sense callback. 53248ef779fSAlex Deucher * 53348ef779fSAlex Deucher * @rdev: radeon_device pointer 53448ef779fSAlex Deucher * @hpd: hpd (hotplug detect) pin 53548ef779fSAlex Deucher * 53648ef779fSAlex Deucher * Checks if a digital monitor is connected (r1xx-r4xx). 53748ef779fSAlex Deucher * Returns true if connected, false if not connected. 53848ef779fSAlex Deucher */ 53905a05c50SAlex Deucher bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 54005a05c50SAlex Deucher { 54105a05c50SAlex Deucher bool connected = false; 54205a05c50SAlex Deucher 54305a05c50SAlex Deucher switch (hpd) { 54405a05c50SAlex Deucher case RADEON_HPD_1: 54505a05c50SAlex Deucher if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) 54605a05c50SAlex Deucher connected = true; 54705a05c50SAlex Deucher break; 54805a05c50SAlex Deucher case RADEON_HPD_2: 54905a05c50SAlex Deucher if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) 55005a05c50SAlex Deucher connected = true; 55105a05c50SAlex Deucher break; 55205a05c50SAlex Deucher default: 55305a05c50SAlex Deucher break; 55405a05c50SAlex Deucher } 55505a05c50SAlex Deucher return connected; 55605a05c50SAlex Deucher } 55705a05c50SAlex Deucher 55848ef779fSAlex Deucher /** 55948ef779fSAlex Deucher * r100_hpd_set_polarity - hpd set polarity callback. 56048ef779fSAlex Deucher * 56148ef779fSAlex Deucher * @rdev: radeon_device pointer 56248ef779fSAlex Deucher * @hpd: hpd (hotplug detect) pin 56348ef779fSAlex Deucher * 56448ef779fSAlex Deucher * Set the polarity of the hpd pin (r1xx-r4xx). 56548ef779fSAlex Deucher */ 56605a05c50SAlex Deucher void r100_hpd_set_polarity(struct radeon_device *rdev, 56705a05c50SAlex Deucher enum radeon_hpd_id hpd) 56805a05c50SAlex Deucher { 56905a05c50SAlex Deucher u32 tmp; 57005a05c50SAlex Deucher bool connected = r100_hpd_sense(rdev, hpd); 57105a05c50SAlex Deucher 57205a05c50SAlex Deucher switch (hpd) { 57305a05c50SAlex Deucher case RADEON_HPD_1: 57405a05c50SAlex Deucher tmp = RREG32(RADEON_FP_GEN_CNTL); 57505a05c50SAlex Deucher if (connected) 57605a05c50SAlex Deucher tmp &= ~RADEON_FP_DETECT_INT_POL; 57705a05c50SAlex Deucher else 57805a05c50SAlex Deucher tmp |= RADEON_FP_DETECT_INT_POL; 57905a05c50SAlex Deucher WREG32(RADEON_FP_GEN_CNTL, tmp); 58005a05c50SAlex Deucher break; 58105a05c50SAlex Deucher case RADEON_HPD_2: 58205a05c50SAlex Deucher tmp = RREG32(RADEON_FP2_GEN_CNTL); 58305a05c50SAlex Deucher if (connected) 58405a05c50SAlex Deucher tmp &= ~RADEON_FP2_DETECT_INT_POL; 58505a05c50SAlex Deucher else 58605a05c50SAlex Deucher tmp |= RADEON_FP2_DETECT_INT_POL; 58705a05c50SAlex Deucher WREG32(RADEON_FP2_GEN_CNTL, tmp); 58805a05c50SAlex Deucher break; 58905a05c50SAlex Deucher default: 59005a05c50SAlex Deucher break; 59105a05c50SAlex Deucher } 59205a05c50SAlex Deucher } 59305a05c50SAlex Deucher 59448ef779fSAlex Deucher /** 59548ef779fSAlex Deucher * r100_hpd_init - hpd setup callback. 59648ef779fSAlex Deucher * 59748ef779fSAlex Deucher * @rdev: radeon_device pointer 59848ef779fSAlex Deucher * 59948ef779fSAlex Deucher * Setup the hpd pins used by the card (r1xx-r4xx). 60048ef779fSAlex Deucher * Set the polarity, and enable the hpd interrupts. 60148ef779fSAlex Deucher */ 60205a05c50SAlex Deucher void r100_hpd_init(struct radeon_device *rdev) 60305a05c50SAlex Deucher { 60405a05c50SAlex Deucher struct drm_device *dev = rdev->ddev; 60505a05c50SAlex Deucher struct drm_connector *connector; 606fb98257aSChristian Koenig unsigned enable = 0; 60705a05c50SAlex Deucher 60805a05c50SAlex Deucher list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 60905a05c50SAlex Deucher struct radeon_connector *radeon_connector = to_radeon_connector(connector); 610b2c0cbd6SNicolai Stange if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 611fb98257aSChristian Koenig enable |= 1 << radeon_connector->hpd.hpd; 61264912e99SAlex Deucher radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 61305a05c50SAlex Deucher } 614fb98257aSChristian Koenig radeon_irq_kms_enable_hpd(rdev, enable); 61505a05c50SAlex Deucher } 61605a05c50SAlex Deucher 61748ef779fSAlex Deucher /** 61848ef779fSAlex Deucher * r100_hpd_fini - hpd tear down callback. 61948ef779fSAlex Deucher * 62048ef779fSAlex Deucher * @rdev: radeon_device pointer 62148ef779fSAlex Deucher * 62248ef779fSAlex Deucher * Tear down the hpd pins used by the card (r1xx-r4xx). 62348ef779fSAlex Deucher * Disable the hpd interrupts. 62448ef779fSAlex Deucher */ 62505a05c50SAlex Deucher void r100_hpd_fini(struct radeon_device *rdev) 62605a05c50SAlex Deucher { 62705a05c50SAlex Deucher struct drm_device *dev = rdev->ddev; 62805a05c50SAlex Deucher struct drm_connector *connector; 629fb98257aSChristian Koenig unsigned disable = 0; 63005a05c50SAlex Deucher 63105a05c50SAlex Deucher list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 63205a05c50SAlex Deucher struct radeon_connector *radeon_connector = to_radeon_connector(connector); 633b2c0cbd6SNicolai Stange if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 634fb98257aSChristian Koenig disable |= 1 << radeon_connector->hpd.hpd; 63505a05c50SAlex Deucher } 636fb98257aSChristian Koenig radeon_irq_kms_disable_hpd(rdev, disable); 63705a05c50SAlex Deucher } 63805a05c50SAlex Deucher 639771fe6b9SJerome Glisse /* 640771fe6b9SJerome Glisse * PCI GART 641771fe6b9SJerome Glisse */ 642771fe6b9SJerome Glisse void r100_pci_gart_tlb_flush(struct radeon_device *rdev) 643771fe6b9SJerome Glisse { 644771fe6b9SJerome Glisse /* TODO: can we do somethings here ? */ 645771fe6b9SJerome Glisse /* It seems hw only cache one entry so we should discard this 646771fe6b9SJerome Glisse * entry otherwise if first GPU GART read hit this entry it 647771fe6b9SJerome Glisse * could end up in wrong address. */ 648771fe6b9SJerome Glisse } 649771fe6b9SJerome Glisse 6504aac0473SJerome Glisse int r100_pci_gart_init(struct radeon_device *rdev) 6514aac0473SJerome Glisse { 6524aac0473SJerome Glisse int r; 6534aac0473SJerome Glisse 654c9a1be96SJerome Glisse if (rdev->gart.ptr) { 655fce7d61bSJoe Perches WARN(1, "R100 PCI GART already initialized\n"); 6564aac0473SJerome Glisse return 0; 6574aac0473SJerome Glisse } 6584aac0473SJerome Glisse /* Initialize common gart structure */ 6594aac0473SJerome Glisse r = radeon_gart_init(rdev); 6604aac0473SJerome Glisse if (r) 6614aac0473SJerome Glisse return r; 6624aac0473SJerome Glisse rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 663c5b3b850SAlex Deucher rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 664cb658906SMichel Dänzer rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; 665c5b3b850SAlex Deucher rdev->asic->gart.set_page = &r100_pci_gart_set_page; 6664aac0473SJerome Glisse return radeon_gart_table_ram_alloc(rdev); 6674aac0473SJerome Glisse } 6684aac0473SJerome Glisse 669771fe6b9SJerome Glisse int r100_pci_gart_enable(struct radeon_device *rdev) 670771fe6b9SJerome Glisse { 671771fe6b9SJerome Glisse uint32_t tmp; 672771fe6b9SJerome Glisse 673771fe6b9SJerome Glisse /* discard memory request outside of configured range */ 674771fe6b9SJerome Glisse tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 675771fe6b9SJerome Glisse WREG32(RADEON_AIC_CNTL, tmp); 676771fe6b9SJerome Glisse /* set address range for PCI address translate */ 677d594e46aSJerome Glisse WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); 678d594e46aSJerome Glisse WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); 679771fe6b9SJerome Glisse /* set PCI GART page-table base address */ 680771fe6b9SJerome Glisse WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); 681771fe6b9SJerome Glisse tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; 682771fe6b9SJerome Glisse WREG32(RADEON_AIC_CNTL, tmp); 683771fe6b9SJerome Glisse r100_pci_gart_tlb_flush(rdev); 68443caf451SMichel Dänzer DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n", 685fcf4de5aSTormod Volden (unsigned)(rdev->mc.gtt_size >> 20), 686fcf4de5aSTormod Volden (unsigned long long)rdev->gart.table_addr); 687771fe6b9SJerome Glisse rdev->gart.ready = true; 688771fe6b9SJerome Glisse return 0; 689771fe6b9SJerome Glisse } 690771fe6b9SJerome Glisse 691771fe6b9SJerome Glisse void r100_pci_gart_disable(struct radeon_device *rdev) 692771fe6b9SJerome Glisse { 693771fe6b9SJerome Glisse uint32_t tmp; 694771fe6b9SJerome Glisse 695771fe6b9SJerome Glisse /* discard memory request outside of configured range */ 696771fe6b9SJerome Glisse tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 697771fe6b9SJerome Glisse WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); 698771fe6b9SJerome Glisse WREG32(RADEON_AIC_LO_ADDR, 0); 699771fe6b9SJerome Glisse WREG32(RADEON_AIC_HI_ADDR, 0); 700771fe6b9SJerome Glisse } 701771fe6b9SJerome Glisse 702cb658906SMichel Dänzer uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags) 703cb658906SMichel Dänzer { 704cb658906SMichel Dänzer return addr; 705cb658906SMichel Dänzer } 706cb658906SMichel Dänzer 7077f90fc96SChristian König void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i, 708cb658906SMichel Dänzer uint64_t entry) 709771fe6b9SJerome Glisse { 710c9a1be96SJerome Glisse u32 *gtt = rdev->gart.ptr; 711cb658906SMichel Dänzer gtt[i] = cpu_to_le32(lower_32_bits(entry)); 712771fe6b9SJerome Glisse } 713771fe6b9SJerome Glisse 7144aac0473SJerome Glisse void r100_pci_gart_fini(struct radeon_device *rdev) 715771fe6b9SJerome Glisse { 716f9274562SJerome Glisse radeon_gart_fini(rdev); 717771fe6b9SJerome Glisse r100_pci_gart_disable(rdev); 7184aac0473SJerome Glisse radeon_gart_table_ram_free(rdev); 719771fe6b9SJerome Glisse } 720771fe6b9SJerome Glisse 7217ed220d7SMichel Dänzer int r100_irq_set(struct radeon_device *rdev) 7227ed220d7SMichel Dänzer { 7237ed220d7SMichel Dänzer uint32_t tmp = 0; 7247ed220d7SMichel Dänzer 725003e69f9SJerome Glisse if (!rdev->irq.installed) { 726fce7d61bSJoe Perches WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 727003e69f9SJerome Glisse WREG32(R_000040_GEN_INT_CNTL, 0); 728003e69f9SJerome Glisse return -EINVAL; 729003e69f9SJerome Glisse } 730736fc37fSChristian Koenig if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 7317ed220d7SMichel Dänzer tmp |= RADEON_SW_INT_ENABLE; 7327ed220d7SMichel Dänzer } 7336f34be50SAlex Deucher if (rdev->irq.crtc_vblank_int[0] || 734736fc37fSChristian Koenig atomic_read(&rdev->irq.pflip[0])) { 7357ed220d7SMichel Dänzer tmp |= RADEON_CRTC_VBLANK_MASK; 7367ed220d7SMichel Dänzer } 7376f34be50SAlex Deucher if (rdev->irq.crtc_vblank_int[1] || 738736fc37fSChristian Koenig atomic_read(&rdev->irq.pflip[1])) { 7397ed220d7SMichel Dänzer tmp |= RADEON_CRTC2_VBLANK_MASK; 7407ed220d7SMichel Dänzer } 74105a05c50SAlex Deucher if (rdev->irq.hpd[0]) { 74205a05c50SAlex Deucher tmp |= RADEON_FP_DETECT_MASK; 74305a05c50SAlex Deucher } 74405a05c50SAlex Deucher if (rdev->irq.hpd[1]) { 74505a05c50SAlex Deucher tmp |= RADEON_FP2_DETECT_MASK; 74605a05c50SAlex Deucher } 7477ed220d7SMichel Dänzer WREG32(RADEON_GEN_INT_CNTL, tmp); 748f957063fSAlex Deucher 749f957063fSAlex Deucher /* read back to post the write */ 750f957063fSAlex Deucher RREG32(RADEON_GEN_INT_CNTL); 751f957063fSAlex Deucher 7527ed220d7SMichel Dänzer return 0; 7537ed220d7SMichel Dänzer } 7547ed220d7SMichel Dänzer 7559f022ddfSJerome Glisse void r100_irq_disable(struct radeon_device *rdev) 7569f022ddfSJerome Glisse { 7579f022ddfSJerome Glisse u32 tmp; 7589f022ddfSJerome Glisse 7599f022ddfSJerome Glisse WREG32(R_000040_GEN_INT_CNTL, 0); 7609f022ddfSJerome Glisse /* Wait and acknowledge irq */ 7619f022ddfSJerome Glisse mdelay(1); 7629f022ddfSJerome Glisse tmp = RREG32(R_000044_GEN_INT_STATUS); 7639f022ddfSJerome Glisse WREG32(R_000044_GEN_INT_STATUS, tmp); 7649f022ddfSJerome Glisse } 7659f022ddfSJerome Glisse 766cbdd4501SAndi Kleen static uint32_t r100_irq_ack(struct radeon_device *rdev) 7677ed220d7SMichel Dänzer { 7687ed220d7SMichel Dänzer uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); 76905a05c50SAlex Deucher uint32_t irq_mask = RADEON_SW_INT_TEST | 77005a05c50SAlex Deucher RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | 77105a05c50SAlex Deucher RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; 7727ed220d7SMichel Dänzer 7737ed220d7SMichel Dänzer if (irqs) { 7747ed220d7SMichel Dänzer WREG32(RADEON_GEN_INT_STATUS, irqs); 7757ed220d7SMichel Dänzer } 7767ed220d7SMichel Dänzer return irqs & irq_mask; 7777ed220d7SMichel Dänzer } 7787ed220d7SMichel Dänzer 7797ed220d7SMichel Dänzer int r100_irq_process(struct radeon_device *rdev) 7807ed220d7SMichel Dänzer { 7813e5cb98dSAlex Deucher uint32_t status, msi_rearm; 782d4877cf2SAlex Deucher bool queue_hotplug = false; 7837ed220d7SMichel Dänzer 7847ed220d7SMichel Dänzer status = r100_irq_ack(rdev); 7857ed220d7SMichel Dänzer if (!status) { 7867ed220d7SMichel Dänzer return IRQ_NONE; 7877ed220d7SMichel Dänzer } 788a513c184SJerome Glisse if (rdev->shutdown) { 789a513c184SJerome Glisse return IRQ_NONE; 790a513c184SJerome Glisse } 7917ed220d7SMichel Dänzer while (status) { 7927ed220d7SMichel Dänzer /* SW interrupt */ 7937ed220d7SMichel Dänzer if (status & RADEON_SW_INT_TEST) { 7947465280cSAlex Deucher radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 7957ed220d7SMichel Dänzer } 7967ed220d7SMichel Dänzer /* Vertical blank interrupts */ 7977ed220d7SMichel Dänzer if (status & RADEON_CRTC_VBLANK_STAT) { 7986f34be50SAlex Deucher if (rdev->irq.crtc_vblank_int[0]) { 7997ed220d7SMichel Dänzer drm_handle_vblank(rdev->ddev, 0); 800839461d3SRafał Miłecki rdev->pm.vblank_sync = true; 80173a6d3fcSRafał Miłecki wake_up(&rdev->irq.vblank_queue); 8027ed220d7SMichel Dänzer } 803736fc37fSChristian Koenig if (atomic_read(&rdev->irq.pflip[0])) 8041a0e7918SChristian König radeon_crtc_handle_vblank(rdev, 0); 8056f34be50SAlex Deucher } 8067ed220d7SMichel Dänzer if (status & RADEON_CRTC2_VBLANK_STAT) { 8076f34be50SAlex Deucher if (rdev->irq.crtc_vblank_int[1]) { 8087ed220d7SMichel Dänzer drm_handle_vblank(rdev->ddev, 1); 809839461d3SRafał Miłecki rdev->pm.vblank_sync = true; 81073a6d3fcSRafał Miłecki wake_up(&rdev->irq.vblank_queue); 8117ed220d7SMichel Dänzer } 812736fc37fSChristian Koenig if (atomic_read(&rdev->irq.pflip[1])) 8131a0e7918SChristian König radeon_crtc_handle_vblank(rdev, 1); 8146f34be50SAlex Deucher } 81505a05c50SAlex Deucher if (status & RADEON_FP_DETECT_STAT) { 816d4877cf2SAlex Deucher queue_hotplug = true; 817d4877cf2SAlex Deucher DRM_DEBUG("HPD1\n"); 81805a05c50SAlex Deucher } 81905a05c50SAlex Deucher if (status & RADEON_FP2_DETECT_STAT) { 820d4877cf2SAlex Deucher queue_hotplug = true; 821d4877cf2SAlex Deucher DRM_DEBUG("HPD2\n"); 82205a05c50SAlex Deucher } 8237ed220d7SMichel Dänzer status = r100_irq_ack(rdev); 8247ed220d7SMichel Dänzer } 825d4877cf2SAlex Deucher if (queue_hotplug) 826cb5d4166SLyude schedule_delayed_work(&rdev->hotplug_work, 0); 8273e5cb98dSAlex Deucher if (rdev->msi_enabled) { 8283e5cb98dSAlex Deucher switch (rdev->family) { 8293e5cb98dSAlex Deucher case CHIP_RS400: 8303e5cb98dSAlex Deucher case CHIP_RS480: 8313e5cb98dSAlex Deucher msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; 8323e5cb98dSAlex Deucher WREG32(RADEON_AIC_CNTL, msi_rearm); 8333e5cb98dSAlex Deucher WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); 8343e5cb98dSAlex Deucher break; 8353e5cb98dSAlex Deucher default: 836b7f5b7deSAlex Deucher WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); 8373e5cb98dSAlex Deucher break; 8383e5cb98dSAlex Deucher } 8393e5cb98dSAlex Deucher } 8407ed220d7SMichel Dänzer return IRQ_HANDLED; 8417ed220d7SMichel Dänzer } 8427ed220d7SMichel Dänzer 8437ed220d7SMichel Dänzer u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) 8447ed220d7SMichel Dänzer { 8457ed220d7SMichel Dänzer if (crtc == 0) 8467ed220d7SMichel Dänzer return RREG32(RADEON_CRTC_CRNT_FRAME); 8477ed220d7SMichel Dänzer else 8487ed220d7SMichel Dänzer return RREG32(RADEON_CRTC2_CRNT_FRAME); 8497ed220d7SMichel Dänzer } 8507ed220d7SMichel Dänzer 851897eba82SMichel Dänzer /** 852897eba82SMichel Dänzer * r100_ring_hdp_flush - flush Host Data Path via the ring buffer 8530d8357c2SLee Jones * @rdev: radeon device structure 8540d8357c2SLee Jones * @ring: ring buffer struct for emitting packets 855897eba82SMichel Dänzer */ 856897eba82SMichel Dänzer static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring) 857897eba82SMichel Dänzer { 858897eba82SMichel Dänzer radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 859897eba82SMichel Dänzer radeon_ring_write(ring, rdev->config.r100.hdp_cntl | 860897eba82SMichel Dänzer RADEON_HDP_READ_BUFFER_INVALIDATE); 861897eba82SMichel Dänzer radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 862897eba82SMichel Dänzer radeon_ring_write(ring, rdev->config.r100.hdp_cntl); 863897eba82SMichel Dänzer } 864897eba82SMichel Dänzer 8659e5b2af7SPauli Nieminen /* Who ever call radeon_fence_emit should call ring_lock and ask 8669e5b2af7SPauli Nieminen * for enough space (today caller are ib schedule and buffer move) */ 867771fe6b9SJerome Glisse void r100_fence_ring_emit(struct radeon_device *rdev, 868771fe6b9SJerome Glisse struct radeon_fence *fence) 869771fe6b9SJerome Glisse { 870e32eb50dSChristian König struct radeon_ring *ring = &rdev->ring[fence->ring]; 8717b1f2485SChristian König 8729e5b2af7SPauli Nieminen /* We have to make sure that caches are flushed before 8739e5b2af7SPauli Nieminen * CPU might read something from VRAM. */ 874e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); 875e32eb50dSChristian König radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL); 876e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); 877e32eb50dSChristian König radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL); 878771fe6b9SJerome Glisse /* Wait until IDLE & CLEAN */ 879e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 880e32eb50dSChristian König radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 88172a9987eSMichel Dänzer r100_ring_hdp_flush(rdev, ring); 882771fe6b9SJerome Glisse /* Emit fence sequence & fire IRQ */ 883e32eb50dSChristian König radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); 884e32eb50dSChristian König radeon_ring_write(ring, fence->seq); 885e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); 886e32eb50dSChristian König radeon_ring_write(ring, RADEON_SW_INT_FIRE); 887771fe6b9SJerome Glisse } 888771fe6b9SJerome Glisse 8891654b817SChristian König bool r100_semaphore_ring_emit(struct radeon_device *rdev, 890e32eb50dSChristian König struct radeon_ring *ring, 89115d3332fSChristian König struct radeon_semaphore *semaphore, 8927b1f2485SChristian König bool emit_wait) 89315d3332fSChristian König { 89415d3332fSChristian König /* Unused on older asics, since we don't have semaphores or multiple rings */ 89515d3332fSChristian König BUG(); 8961654b817SChristian König return false; 89715d3332fSChristian König } 89815d3332fSChristian König 89957d20a43SChristian König struct radeon_fence *r100_copy_blit(struct radeon_device *rdev, 900771fe6b9SJerome Glisse uint64_t src_offset, 901771fe6b9SJerome Glisse uint64_t dst_offset, 902003cefe0SAlex Deucher unsigned num_gpu_pages, 90352791eeeSChristian König struct dma_resv *resv) 904771fe6b9SJerome Glisse { 905e32eb50dSChristian König struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 90657d20a43SChristian König struct radeon_fence *fence; 907771fe6b9SJerome Glisse uint32_t cur_pages; 908003cefe0SAlex Deucher uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE; 909771fe6b9SJerome Glisse uint32_t pitch; 910771fe6b9SJerome Glisse uint32_t stride_pixels; 911771fe6b9SJerome Glisse unsigned ndw; 912771fe6b9SJerome Glisse int num_loops; 913771fe6b9SJerome Glisse int r = 0; 914771fe6b9SJerome Glisse 915771fe6b9SJerome Glisse /* radeon limited to 16k stride */ 916771fe6b9SJerome Glisse stride_bytes &= 0x3fff; 917771fe6b9SJerome Glisse /* radeon pitch is /64 */ 918771fe6b9SJerome Glisse pitch = stride_bytes / 64; 919771fe6b9SJerome Glisse stride_pixels = stride_bytes / 4; 920003cefe0SAlex Deucher num_loops = DIV_ROUND_UP(num_gpu_pages, 8191); 921771fe6b9SJerome Glisse 922771fe6b9SJerome Glisse /* Ask for enough room for blit + flush + fence */ 923771fe6b9SJerome Glisse ndw = 64 + (10 * num_loops); 924e32eb50dSChristian König r = radeon_ring_lock(rdev, ring, ndw); 925771fe6b9SJerome Glisse if (r) { 926771fe6b9SJerome Glisse DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); 92757d20a43SChristian König return ERR_PTR(-EINVAL); 928771fe6b9SJerome Glisse } 929003cefe0SAlex Deucher while (num_gpu_pages > 0) { 930003cefe0SAlex Deucher cur_pages = num_gpu_pages; 931771fe6b9SJerome Glisse if (cur_pages > 8191) { 932771fe6b9SJerome Glisse cur_pages = 8191; 933771fe6b9SJerome Glisse } 934003cefe0SAlex Deucher num_gpu_pages -= cur_pages; 935771fe6b9SJerome Glisse 936771fe6b9SJerome Glisse /* pages are in Y direction - height 937771fe6b9SJerome Glisse page width in X direction - width */ 938e32eb50dSChristian König radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8)); 939e32eb50dSChristian König radeon_ring_write(ring, 940771fe6b9SJerome Glisse RADEON_GMC_SRC_PITCH_OFFSET_CNTL | 941771fe6b9SJerome Glisse RADEON_GMC_DST_PITCH_OFFSET_CNTL | 942771fe6b9SJerome Glisse RADEON_GMC_SRC_CLIPPING | 943771fe6b9SJerome Glisse RADEON_GMC_DST_CLIPPING | 944771fe6b9SJerome Glisse RADEON_GMC_BRUSH_NONE | 945771fe6b9SJerome Glisse (RADEON_COLOR_FORMAT_ARGB8888 << 8) | 946771fe6b9SJerome Glisse RADEON_GMC_SRC_DATATYPE_COLOR | 947771fe6b9SJerome Glisse RADEON_ROP3_S | 948771fe6b9SJerome Glisse RADEON_DP_SRC_SOURCE_MEMORY | 949771fe6b9SJerome Glisse RADEON_GMC_CLR_CMP_CNTL_DIS | 950771fe6b9SJerome Glisse RADEON_GMC_WR_MSK_DIS); 951e32eb50dSChristian König radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10)); 952e32eb50dSChristian König radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10)); 953e32eb50dSChristian König radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); 954e32eb50dSChristian König radeon_ring_write(ring, 0); 955e32eb50dSChristian König radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); 956e32eb50dSChristian König radeon_ring_write(ring, num_gpu_pages); 957e32eb50dSChristian König radeon_ring_write(ring, num_gpu_pages); 958e32eb50dSChristian König radeon_ring_write(ring, cur_pages | (stride_pixels << 16)); 959771fe6b9SJerome Glisse } 960e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); 961e32eb50dSChristian König radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL); 962e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 963e32eb50dSChristian König radeon_ring_write(ring, 964771fe6b9SJerome Glisse RADEON_WAIT_2D_IDLECLEAN | 965771fe6b9SJerome Glisse RADEON_WAIT_HOST_IDLECLEAN | 966771fe6b9SJerome Glisse RADEON_WAIT_DMA_GUI_IDLE); 96757d20a43SChristian König r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX); 96857d20a43SChristian König if (r) { 96957d20a43SChristian König radeon_ring_unlock_undo(rdev, ring); 97057d20a43SChristian König return ERR_PTR(r); 971771fe6b9SJerome Glisse } 9721538a9e0SMichel Dänzer radeon_ring_unlock_commit(rdev, ring, false); 97357d20a43SChristian König return fence; 974771fe6b9SJerome Glisse } 975771fe6b9SJerome Glisse 97645600232SJerome Glisse static int r100_cp_wait_for_idle(struct radeon_device *rdev) 97745600232SJerome Glisse { 97845600232SJerome Glisse unsigned i; 97945600232SJerome Glisse u32 tmp; 98045600232SJerome Glisse 98145600232SJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 98245600232SJerome Glisse tmp = RREG32(R_000E40_RBBM_STATUS); 98345600232SJerome Glisse if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { 98445600232SJerome Glisse return 0; 98545600232SJerome Glisse } 98645600232SJerome Glisse udelay(1); 98745600232SJerome Glisse } 98845600232SJerome Glisse return -1; 98945600232SJerome Glisse } 99045600232SJerome Glisse 991f712812eSAlex Deucher void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 992771fe6b9SJerome Glisse { 993771fe6b9SJerome Glisse int r; 994771fe6b9SJerome Glisse 995e32eb50dSChristian König r = radeon_ring_lock(rdev, ring, 2); 996771fe6b9SJerome Glisse if (r) { 997771fe6b9SJerome Glisse return; 998771fe6b9SJerome Glisse } 999e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); 1000e32eb50dSChristian König radeon_ring_write(ring, 1001771fe6b9SJerome Glisse RADEON_ISYNC_ANY2D_IDLE3D | 1002771fe6b9SJerome Glisse RADEON_ISYNC_ANY3D_IDLE2D | 1003771fe6b9SJerome Glisse RADEON_ISYNC_WAIT_IDLEGUI | 1004771fe6b9SJerome Glisse RADEON_ISYNC_CPSCRATCH_IDLEGUI); 10051538a9e0SMichel Dänzer radeon_ring_unlock_commit(rdev, ring, false); 1006771fe6b9SJerome Glisse } 1007771fe6b9SJerome Glisse 100870967ab9SBen Hutchings 100970967ab9SBen Hutchings /* Load the microcode for the CP */ 101070967ab9SBen Hutchings static int r100_cp_init_microcode(struct radeon_device *rdev) 1011771fe6b9SJerome Glisse { 101270967ab9SBen Hutchings const char *fw_name = NULL; 101370967ab9SBen Hutchings int err; 1014771fe6b9SJerome Glisse 1015d9fdaafbSDave Airlie DRM_DEBUG_KMS("\n"); 101670967ab9SBen Hutchings 1017771fe6b9SJerome Glisse if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || 1018771fe6b9SJerome Glisse (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || 1019771fe6b9SJerome Glisse (rdev->family == CHIP_RS200)) { 1020771fe6b9SJerome Glisse DRM_INFO("Loading R100 Microcode\n"); 102170967ab9SBen Hutchings fw_name = FIRMWARE_R100; 1022771fe6b9SJerome Glisse } else if ((rdev->family == CHIP_R200) || 1023771fe6b9SJerome Glisse (rdev->family == CHIP_RV250) || 1024771fe6b9SJerome Glisse (rdev->family == CHIP_RV280) || 1025771fe6b9SJerome Glisse (rdev->family == CHIP_RS300)) { 1026771fe6b9SJerome Glisse DRM_INFO("Loading R200 Microcode\n"); 102770967ab9SBen Hutchings fw_name = FIRMWARE_R200; 1028771fe6b9SJerome Glisse } else if ((rdev->family == CHIP_R300) || 1029771fe6b9SJerome Glisse (rdev->family == CHIP_R350) || 1030771fe6b9SJerome Glisse (rdev->family == CHIP_RV350) || 1031771fe6b9SJerome Glisse (rdev->family == CHIP_RV380) || 1032771fe6b9SJerome Glisse (rdev->family == CHIP_RS400) || 1033771fe6b9SJerome Glisse (rdev->family == CHIP_RS480)) { 1034771fe6b9SJerome Glisse DRM_INFO("Loading R300 Microcode\n"); 103570967ab9SBen Hutchings fw_name = FIRMWARE_R300; 1036771fe6b9SJerome Glisse } else if ((rdev->family == CHIP_R420) || 1037771fe6b9SJerome Glisse (rdev->family == CHIP_R423) || 1038771fe6b9SJerome Glisse (rdev->family == CHIP_RV410)) { 1039771fe6b9SJerome Glisse DRM_INFO("Loading R400 Microcode\n"); 104070967ab9SBen Hutchings fw_name = FIRMWARE_R420; 1041771fe6b9SJerome Glisse } else if ((rdev->family == CHIP_RS690) || 1042771fe6b9SJerome Glisse (rdev->family == CHIP_RS740)) { 1043771fe6b9SJerome Glisse DRM_INFO("Loading RS690/RS740 Microcode\n"); 104470967ab9SBen Hutchings fw_name = FIRMWARE_RS690; 1045771fe6b9SJerome Glisse } else if (rdev->family == CHIP_RS600) { 1046771fe6b9SJerome Glisse DRM_INFO("Loading RS600 Microcode\n"); 104770967ab9SBen Hutchings fw_name = FIRMWARE_RS600; 1048771fe6b9SJerome Glisse } else if ((rdev->family == CHIP_RV515) || 1049771fe6b9SJerome Glisse (rdev->family == CHIP_R520) || 1050771fe6b9SJerome Glisse (rdev->family == CHIP_RV530) || 1051771fe6b9SJerome Glisse (rdev->family == CHIP_R580) || 1052771fe6b9SJerome Glisse (rdev->family == CHIP_RV560) || 1053771fe6b9SJerome Glisse (rdev->family == CHIP_RV570)) { 1054771fe6b9SJerome Glisse DRM_INFO("Loading R500 Microcode\n"); 105570967ab9SBen Hutchings fw_name = FIRMWARE_R520; 105670967ab9SBen Hutchings } 105770967ab9SBen Hutchings 10580a168933SJerome Glisse err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); 105970967ab9SBen Hutchings if (err) { 10607ca85295SJoe Perches pr_err("radeon_cp: Failed to load firmware \"%s\"\n", fw_name); 10613ce0a23dSJerome Glisse } else if (rdev->me_fw->size % 8) { 10627ca85295SJoe Perches pr_err("radeon_cp: Bogus length %zu in firmware \"%s\"\n", 10633ce0a23dSJerome Glisse rdev->me_fw->size, fw_name); 106470967ab9SBen Hutchings err = -EINVAL; 10653ce0a23dSJerome Glisse release_firmware(rdev->me_fw); 10663ce0a23dSJerome Glisse rdev->me_fw = NULL; 106770967ab9SBen Hutchings } 106870967ab9SBen Hutchings return err; 106970967ab9SBen Hutchings } 1070d4550907SJerome Glisse 1071ea31bf69SAlex Deucher u32 r100_gfx_get_rptr(struct radeon_device *rdev, 1072ea31bf69SAlex Deucher struct radeon_ring *ring) 1073ea31bf69SAlex Deucher { 1074ea31bf69SAlex Deucher u32 rptr; 1075ea31bf69SAlex Deucher 1076ea31bf69SAlex Deucher if (rdev->wb.enabled) 1077ea31bf69SAlex Deucher rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); 1078ea31bf69SAlex Deucher else 1079ea31bf69SAlex Deucher rptr = RREG32(RADEON_CP_RB_RPTR); 1080ea31bf69SAlex Deucher 1081ea31bf69SAlex Deucher return rptr; 1082ea31bf69SAlex Deucher } 1083ea31bf69SAlex Deucher 1084ea31bf69SAlex Deucher u32 r100_gfx_get_wptr(struct radeon_device *rdev, 1085ea31bf69SAlex Deucher struct radeon_ring *ring) 1086ea31bf69SAlex Deucher { 10870003b8d2SMasahiro Yamada return RREG32(RADEON_CP_RB_WPTR); 1088ea31bf69SAlex Deucher } 1089ea31bf69SAlex Deucher 1090ea31bf69SAlex Deucher void r100_gfx_set_wptr(struct radeon_device *rdev, 1091ea31bf69SAlex Deucher struct radeon_ring *ring) 1092ea31bf69SAlex Deucher { 1093ea31bf69SAlex Deucher WREG32(RADEON_CP_RB_WPTR, ring->wptr); 1094ea31bf69SAlex Deucher (void)RREG32(RADEON_CP_RB_WPTR); 1095ea31bf69SAlex Deucher } 1096ea31bf69SAlex Deucher 109770967ab9SBen Hutchings static void r100_cp_load_microcode(struct radeon_device *rdev) 109870967ab9SBen Hutchings { 109970967ab9SBen Hutchings const __be32 *fw_data; 110070967ab9SBen Hutchings int i, size; 110170967ab9SBen Hutchings 110270967ab9SBen Hutchings if (r100_gui_wait_for_idle(rdev)) { 11037ca85295SJoe Perches pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 110470967ab9SBen Hutchings } 110570967ab9SBen Hutchings 11063ce0a23dSJerome Glisse if (rdev->me_fw) { 11073ce0a23dSJerome Glisse size = rdev->me_fw->size / 4; 11083ce0a23dSJerome Glisse fw_data = (const __be32 *)&rdev->me_fw->data[0]; 110970967ab9SBen Hutchings WREG32(RADEON_CP_ME_RAM_ADDR, 0); 111070967ab9SBen Hutchings for (i = 0; i < size; i += 2) { 111170967ab9SBen Hutchings WREG32(RADEON_CP_ME_RAM_DATAH, 111270967ab9SBen Hutchings be32_to_cpup(&fw_data[i])); 111370967ab9SBen Hutchings WREG32(RADEON_CP_ME_RAM_DATAL, 111470967ab9SBen Hutchings be32_to_cpup(&fw_data[i + 1])); 1115771fe6b9SJerome Glisse } 1116771fe6b9SJerome Glisse } 1117771fe6b9SJerome Glisse } 1118771fe6b9SJerome Glisse 1119771fe6b9SJerome Glisse int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) 1120771fe6b9SJerome Glisse { 1121e32eb50dSChristian König struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1122771fe6b9SJerome Glisse unsigned rb_bufsz; 1123771fe6b9SJerome Glisse unsigned rb_blksz; 1124771fe6b9SJerome Glisse unsigned max_fetch; 1125771fe6b9SJerome Glisse unsigned pre_write_timer; 1126771fe6b9SJerome Glisse unsigned pre_write_limit; 1127771fe6b9SJerome Glisse unsigned indirect2_start; 1128771fe6b9SJerome Glisse unsigned indirect1_start; 1129771fe6b9SJerome Glisse uint32_t tmp; 1130771fe6b9SJerome Glisse int r; 1131771fe6b9SJerome Glisse 11325b54d679SNirmoy Das r100_debugfs_cp_init(rdev); 11333ce0a23dSJerome Glisse if (!rdev->me_fw) { 113470967ab9SBen Hutchings r = r100_cp_init_microcode(rdev); 113570967ab9SBen Hutchings if (r) { 113670967ab9SBen Hutchings DRM_ERROR("Failed to load firmware!\n"); 113770967ab9SBen Hutchings return r; 113870967ab9SBen Hutchings } 113970967ab9SBen Hutchings } 114070967ab9SBen Hutchings 1141771fe6b9SJerome Glisse /* Align ring size */ 1142b72a8925SDaniel Vetter rb_bufsz = order_base_2(ring_size / 8); 1143771fe6b9SJerome Glisse ring_size = (1 << (rb_bufsz + 1)) * 4; 1144771fe6b9SJerome Glisse r100_cp_load_microcode(rdev); 1145e32eb50dSChristian König r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET, 11462e1e6dadSChristian König RADEON_CP_PACKET2); 1147771fe6b9SJerome Glisse if (r) { 1148771fe6b9SJerome Glisse return r; 1149771fe6b9SJerome Glisse } 1150771fe6b9SJerome Glisse /* Each time the cp read 1024 bytes (16 dword/quadword) update 1151771fe6b9SJerome Glisse * the rptr copy in system ram */ 1152771fe6b9SJerome Glisse rb_blksz = 9; 1153771fe6b9SJerome Glisse /* cp will read 128bytes at a time (4 dwords) */ 1154771fe6b9SJerome Glisse max_fetch = 1; 1155e32eb50dSChristian König ring->align_mask = 16 - 1; 1156771fe6b9SJerome Glisse /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ 1157771fe6b9SJerome Glisse pre_write_timer = 64; 1158771fe6b9SJerome Glisse /* Force CP_RB_WPTR write if written more than one time before the 1159771fe6b9SJerome Glisse * delay expire 1160771fe6b9SJerome Glisse */ 1161771fe6b9SJerome Glisse pre_write_limit = 0; 1162771fe6b9SJerome Glisse /* Setup the cp cache like this (cache size is 96 dwords) : 1163771fe6b9SJerome Glisse * RING 0 to 15 1164771fe6b9SJerome Glisse * INDIRECT1 16 to 79 1165771fe6b9SJerome Glisse * INDIRECT2 80 to 95 1166771fe6b9SJerome Glisse * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1167771fe6b9SJerome Glisse * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) 1168771fe6b9SJerome Glisse * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1169771fe6b9SJerome Glisse * Idea being that most of the gpu cmd will be through indirect1 buffer 1170771fe6b9SJerome Glisse * so it gets the bigger cache. 1171771fe6b9SJerome Glisse */ 1172771fe6b9SJerome Glisse indirect2_start = 80; 1173771fe6b9SJerome Glisse indirect1_start = 16; 1174771fe6b9SJerome Glisse /* cp setup */ 1175771fe6b9SJerome Glisse WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); 1176d6f28938SAlex Deucher tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | 1177771fe6b9SJerome Glisse REG_SET(RADEON_RB_BLKSZ, rb_blksz) | 1178724c80e1SAlex Deucher REG_SET(RADEON_MAX_FETCH, max_fetch)); 1179d6f28938SAlex Deucher #ifdef __BIG_ENDIAN 1180d6f28938SAlex Deucher tmp |= RADEON_BUF_SWAP_32BIT; 1181d6f28938SAlex Deucher #endif 1182724c80e1SAlex Deucher WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); 1183d6f28938SAlex Deucher 1184771fe6b9SJerome Glisse /* Set ring address */ 1185e32eb50dSChristian König DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr); 1186e32eb50dSChristian König WREG32(RADEON_CP_RB_BASE, ring->gpu_addr); 1187771fe6b9SJerome Glisse /* Force read & write ptr to 0 */ 1188724c80e1SAlex Deucher WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); 1189771fe6b9SJerome Glisse WREG32(RADEON_CP_RB_RPTR_WR, 0); 1190e32eb50dSChristian König ring->wptr = 0; 1191e32eb50dSChristian König WREG32(RADEON_CP_RB_WPTR, ring->wptr); 1192724c80e1SAlex Deucher 1193724c80e1SAlex Deucher /* set the wb address whether it's enabled or not */ 1194724c80e1SAlex Deucher WREG32(R_00070C_CP_RB_RPTR_ADDR, 1195724c80e1SAlex Deucher S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); 1196724c80e1SAlex Deucher WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); 1197724c80e1SAlex Deucher 1198724c80e1SAlex Deucher if (rdev->wb.enabled) 1199724c80e1SAlex Deucher WREG32(R_000770_SCRATCH_UMSK, 0xff); 1200724c80e1SAlex Deucher else { 1201724c80e1SAlex Deucher tmp |= RADEON_RB_NO_UPDATE; 1202724c80e1SAlex Deucher WREG32(R_000770_SCRATCH_UMSK, 0); 1203724c80e1SAlex Deucher } 1204724c80e1SAlex Deucher 1205771fe6b9SJerome Glisse WREG32(RADEON_CP_RB_CNTL, tmp); 1206771fe6b9SJerome Glisse udelay(10); 1207771fe6b9SJerome Glisse /* Set cp mode to bus mastering & enable cp*/ 1208771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_MODE, 1209771fe6b9SJerome Glisse REG_SET(RADEON_INDIRECT2_START, indirect2_start) | 1210771fe6b9SJerome Glisse REG_SET(RADEON_INDIRECT1_START, indirect1_start)); 1211d75ee3beSAlex Deucher WREG32(RADEON_CP_RB_WPTR_DELAY, 0); 1212d75ee3beSAlex Deucher WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); 1213771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); 12142099810fSDave Airlie 12152099810fSDave Airlie /* at this point everything should be setup correctly to enable master */ 12162099810fSDave Airlie pci_set_master(rdev->pdev); 12172099810fSDave Airlie 1218f712812eSAlex Deucher radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1219f712812eSAlex Deucher r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 1220771fe6b9SJerome Glisse if (r) { 1221771fe6b9SJerome Glisse DRM_ERROR("radeon: cp isn't working (%d).\n", r); 1222771fe6b9SJerome Glisse return r; 1223771fe6b9SJerome Glisse } 1224e32eb50dSChristian König ring->ready = true; 122553595338SDave Airlie radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 1226c7eff978SAlex Deucher 122716c58081SSimon Kitching if (!ring->rptr_save_reg /* not resuming from suspend */ 122816c58081SSimon Kitching && radeon_ring_supports_scratch_reg(rdev, ring)) { 1229c7eff978SAlex Deucher r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 1230c7eff978SAlex Deucher if (r) { 1231c7eff978SAlex Deucher DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 1232c7eff978SAlex Deucher ring->rptr_save_reg = 0; 1233c7eff978SAlex Deucher } 1234c7eff978SAlex Deucher } 1235771fe6b9SJerome Glisse return 0; 1236771fe6b9SJerome Glisse } 1237771fe6b9SJerome Glisse 1238771fe6b9SJerome Glisse void r100_cp_fini(struct radeon_device *rdev) 1239771fe6b9SJerome Glisse { 124045600232SJerome Glisse if (r100_cp_wait_for_idle(rdev)) { 124145600232SJerome Glisse DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); 124245600232SJerome Glisse } 1243771fe6b9SJerome Glisse /* Disable ring */ 1244a18d7ea1SJerome Glisse r100_cp_disable(rdev); 1245c7eff978SAlex Deucher radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg); 1246e32eb50dSChristian König radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1247771fe6b9SJerome Glisse DRM_INFO("radeon: cp finalized\n"); 1248771fe6b9SJerome Glisse } 1249771fe6b9SJerome Glisse 1250771fe6b9SJerome Glisse void r100_cp_disable(struct radeon_device *rdev) 1251771fe6b9SJerome Glisse { 1252771fe6b9SJerome Glisse /* Disable ring */ 125353595338SDave Airlie radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1254e32eb50dSChristian König rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1255771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_MODE, 0); 1256771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_CNTL, 0); 1257724c80e1SAlex Deucher WREG32(R_000770_SCRATCH_UMSK, 0); 1258771fe6b9SJerome Glisse if (r100_gui_wait_for_idle(rdev)) { 12597ca85295SJoe Perches pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 1260771fe6b9SJerome Glisse } 1261771fe6b9SJerome Glisse } 1262771fe6b9SJerome Glisse 1263771fe6b9SJerome Glisse /* 1264771fe6b9SJerome Glisse * CS functions 1265771fe6b9SJerome Glisse */ 12660242f74dSAlex Deucher int r100_reloc_pitch_offset(struct radeon_cs_parser *p, 12670242f74dSAlex Deucher struct radeon_cs_packet *pkt, 12680242f74dSAlex Deucher unsigned idx, 12690242f74dSAlex Deucher unsigned reg) 12700242f74dSAlex Deucher { 12710242f74dSAlex Deucher int r; 12720242f74dSAlex Deucher u32 tile_flags = 0; 12730242f74dSAlex Deucher u32 tmp; 12741d0c0942SChristian König struct radeon_bo_list *reloc; 12750242f74dSAlex Deucher u32 value; 12760242f74dSAlex Deucher 1277012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 12780242f74dSAlex Deucher if (r) { 12790242f74dSAlex Deucher DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 12800242f74dSAlex Deucher idx, reg); 1281c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 12820242f74dSAlex Deucher return r; 12830242f74dSAlex Deucher } 12840242f74dSAlex Deucher 12850242f74dSAlex Deucher value = radeon_get_ib_value(p, idx); 12860242f74dSAlex Deucher tmp = value & 0x003fffff; 1287df0af440SChristian König tmp += (((u32)reloc->gpu_offset) >> 10); 12880242f74dSAlex Deucher 12890242f74dSAlex Deucher if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1290df0af440SChristian König if (reloc->tiling_flags & RADEON_TILING_MACRO) 12910242f74dSAlex Deucher tile_flags |= RADEON_DST_TILE_MACRO; 1292df0af440SChristian König if (reloc->tiling_flags & RADEON_TILING_MICRO) { 12930242f74dSAlex Deucher if (reg == RADEON_SRC_PITCH_OFFSET) { 12940242f74dSAlex Deucher DRM_ERROR("Cannot src blit from microtiled surface\n"); 1295c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 12960242f74dSAlex Deucher return -EINVAL; 12970242f74dSAlex Deucher } 12980242f74dSAlex Deucher tile_flags |= RADEON_DST_TILE_MICRO; 12990242f74dSAlex Deucher } 13000242f74dSAlex Deucher 13010242f74dSAlex Deucher tmp |= tile_flags; 13020242f74dSAlex Deucher p->ib.ptr[idx] = (value & 0x3fc00000) | tmp; 13030242f74dSAlex Deucher } else 13040242f74dSAlex Deucher p->ib.ptr[idx] = (value & 0xffc00000) | tmp; 13050242f74dSAlex Deucher return 0; 13060242f74dSAlex Deucher } 13070242f74dSAlex Deucher 13080242f74dSAlex Deucher int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, 13090242f74dSAlex Deucher struct radeon_cs_packet *pkt, 13100242f74dSAlex Deucher int idx) 13110242f74dSAlex Deucher { 13120242f74dSAlex Deucher unsigned c, i; 13131d0c0942SChristian König struct radeon_bo_list *reloc; 13140242f74dSAlex Deucher struct r100_cs_track *track; 13150242f74dSAlex Deucher int r = 0; 13160242f74dSAlex Deucher volatile uint32_t *ib; 13170242f74dSAlex Deucher u32 idx_value; 13180242f74dSAlex Deucher 13190242f74dSAlex Deucher ib = p->ib.ptr; 13200242f74dSAlex Deucher track = (struct r100_cs_track *)p->track; 13210242f74dSAlex Deucher c = radeon_get_ib_value(p, idx++) & 0x1F; 13220242f74dSAlex Deucher if (c > 16) { 13230242f74dSAlex Deucher DRM_ERROR("Only 16 vertex buffers are allowed %d\n", 13240242f74dSAlex Deucher pkt->opcode); 1325c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 13260242f74dSAlex Deucher return -EINVAL; 13270242f74dSAlex Deucher } 13280242f74dSAlex Deucher track->num_arrays = c; 13290242f74dSAlex Deucher for (i = 0; i < (c - 1); i+=2, idx+=3) { 1330012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 13310242f74dSAlex Deucher if (r) { 13320242f74dSAlex Deucher DRM_ERROR("No reloc for packet3 %d\n", 13330242f74dSAlex Deucher pkt->opcode); 1334c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 13350242f74dSAlex Deucher return r; 13360242f74dSAlex Deucher } 13370242f74dSAlex Deucher idx_value = radeon_get_ib_value(p, idx); 1338df0af440SChristian König ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); 13390242f74dSAlex Deucher 13400242f74dSAlex Deucher track->arrays[i + 0].esize = idx_value >> 8; 13410242f74dSAlex Deucher track->arrays[i + 0].robj = reloc->robj; 13420242f74dSAlex Deucher track->arrays[i + 0].esize &= 0x7F; 1343012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 13440242f74dSAlex Deucher if (r) { 13450242f74dSAlex Deucher DRM_ERROR("No reloc for packet3 %d\n", 13460242f74dSAlex Deucher pkt->opcode); 1347c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 13480242f74dSAlex Deucher return r; 13490242f74dSAlex Deucher } 1350df0af440SChristian König ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset); 13510242f74dSAlex Deucher track->arrays[i + 1].robj = reloc->robj; 13520242f74dSAlex Deucher track->arrays[i + 1].esize = idx_value >> 24; 13530242f74dSAlex Deucher track->arrays[i + 1].esize &= 0x7F; 13540242f74dSAlex Deucher } 13550242f74dSAlex Deucher if (c & 1) { 1356012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 13570242f74dSAlex Deucher if (r) { 13580242f74dSAlex Deucher DRM_ERROR("No reloc for packet3 %d\n", 13590242f74dSAlex Deucher pkt->opcode); 1360c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 13610242f74dSAlex Deucher return r; 13620242f74dSAlex Deucher } 13630242f74dSAlex Deucher idx_value = radeon_get_ib_value(p, idx); 1364df0af440SChristian König ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); 13650242f74dSAlex Deucher track->arrays[i + 0].robj = reloc->robj; 13660242f74dSAlex Deucher track->arrays[i + 0].esize = idx_value >> 8; 13670242f74dSAlex Deucher track->arrays[i + 0].esize &= 0x7F; 13680242f74dSAlex Deucher } 13690242f74dSAlex Deucher return r; 13700242f74dSAlex Deucher } 13710242f74dSAlex Deucher 1372771fe6b9SJerome Glisse int r100_cs_parse_packet0(struct radeon_cs_parser *p, 1373771fe6b9SJerome Glisse struct radeon_cs_packet *pkt, 1374068a117cSJerome Glisse const unsigned *auth, unsigned n, 1375771fe6b9SJerome Glisse radeon_packet0_check_t check) 1376771fe6b9SJerome Glisse { 1377771fe6b9SJerome Glisse unsigned reg; 1378771fe6b9SJerome Glisse unsigned i, j, m; 1379771fe6b9SJerome Glisse unsigned idx; 1380771fe6b9SJerome Glisse int r; 1381771fe6b9SJerome Glisse 1382771fe6b9SJerome Glisse idx = pkt->idx + 1; 1383771fe6b9SJerome Glisse reg = pkt->reg; 1384068a117cSJerome Glisse /* Check that register fall into register range 1385068a117cSJerome Glisse * determined by the number of entry (n) in the 1386068a117cSJerome Glisse * safe register bitmap. 1387068a117cSJerome Glisse */ 1388771fe6b9SJerome Glisse if (pkt->one_reg_wr) { 1389771fe6b9SJerome Glisse if ((reg >> 7) > n) { 1390771fe6b9SJerome Glisse return -EINVAL; 1391771fe6b9SJerome Glisse } 1392771fe6b9SJerome Glisse } else { 1393771fe6b9SJerome Glisse if (((reg + (pkt->count << 2)) >> 7) > n) { 1394771fe6b9SJerome Glisse return -EINVAL; 1395771fe6b9SJerome Glisse } 1396771fe6b9SJerome Glisse } 1397771fe6b9SJerome Glisse for (i = 0; i <= pkt->count; i++, idx++) { 1398771fe6b9SJerome Glisse j = (reg >> 7); 1399771fe6b9SJerome Glisse m = 1 << ((reg >> 2) & 31); 1400771fe6b9SJerome Glisse if (auth[j] & m) { 1401771fe6b9SJerome Glisse r = check(p, pkt, idx, reg); 1402771fe6b9SJerome Glisse if (r) { 1403771fe6b9SJerome Glisse return r; 1404771fe6b9SJerome Glisse } 1405771fe6b9SJerome Glisse } 1406771fe6b9SJerome Glisse if (pkt->one_reg_wr) { 1407771fe6b9SJerome Glisse if (!(auth[j] & m)) { 1408771fe6b9SJerome Glisse break; 1409771fe6b9SJerome Glisse } 1410771fe6b9SJerome Glisse } else { 1411771fe6b9SJerome Glisse reg += 4; 1412771fe6b9SJerome Glisse } 1413771fe6b9SJerome Glisse } 1414771fe6b9SJerome Glisse return 0; 1415771fe6b9SJerome Glisse } 1416771fe6b9SJerome Glisse 1417771fe6b9SJerome Glisse /** 1418463e2989SLee Jones * r100_cs_packet_parse_vline() - parse userspace VLINE packet 14190d8357c2SLee Jones * @p: parser structure holding parsing context. 1420531369e6SDave Airlie * 1421531369e6SDave Airlie * Userspace sends a special sequence for VLINE waits. 1422531369e6SDave Airlie * PACKET0 - VLINE_START_END + value 1423531369e6SDave Airlie * PACKET0 - WAIT_UNTIL +_value 1424531369e6SDave Airlie * RELOC (P3) - crtc_id in reloc. 1425531369e6SDave Airlie * 1426531369e6SDave Airlie * This function parses this and relocates the VLINE START END 1427531369e6SDave Airlie * and WAIT UNTIL packets to the correct crtc. 1428531369e6SDave Airlie * It also detects a switched off crtc and nulls out the 1429531369e6SDave Airlie * wait in that case. 1430531369e6SDave Airlie */ 1431531369e6SDave Airlie int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) 1432531369e6SDave Airlie { 1433531369e6SDave Airlie struct drm_crtc *crtc; 1434531369e6SDave Airlie struct radeon_crtc *radeon_crtc; 1435531369e6SDave Airlie struct radeon_cs_packet p3reloc, waitreloc; 1436531369e6SDave Airlie int crtc_id; 1437531369e6SDave Airlie int r; 1438531369e6SDave Airlie uint32_t header, h_idx, reg; 1439513bcb46SDave Airlie volatile uint32_t *ib; 1440531369e6SDave Airlie 1441f2e39221SJerome Glisse ib = p->ib.ptr; 1442531369e6SDave Airlie 1443531369e6SDave Airlie /* parse the wait until */ 1444c38f34b5SIlija Hadzic r = radeon_cs_packet_parse(p, &waitreloc, p->idx); 1445531369e6SDave Airlie if (r) 1446531369e6SDave Airlie return r; 1447531369e6SDave Airlie 1448531369e6SDave Airlie /* check its a wait until and only 1 count */ 1449531369e6SDave Airlie if (waitreloc.reg != RADEON_WAIT_UNTIL || 1450531369e6SDave Airlie waitreloc.count != 0) { 1451531369e6SDave Airlie DRM_ERROR("vline wait had illegal wait until segment\n"); 1452a3a88a66SPaul Bolle return -EINVAL; 1453531369e6SDave Airlie } 1454531369e6SDave Airlie 1455513bcb46SDave Airlie if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { 1456531369e6SDave Airlie DRM_ERROR("vline wait had illegal wait until\n"); 1457a3a88a66SPaul Bolle return -EINVAL; 1458531369e6SDave Airlie } 1459531369e6SDave Airlie 1460531369e6SDave Airlie /* jump over the NOP */ 1461c38f34b5SIlija Hadzic r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); 1462531369e6SDave Airlie if (r) 1463531369e6SDave Airlie return r; 1464531369e6SDave Airlie 1465531369e6SDave Airlie h_idx = p->idx - 2; 146690ebd065SAlex Deucher p->idx += waitreloc.count + 2; 146790ebd065SAlex Deucher p->idx += p3reloc.count + 2; 1468531369e6SDave Airlie 1469513bcb46SDave Airlie header = radeon_get_ib_value(p, h_idx); 1470513bcb46SDave Airlie crtc_id = radeon_get_ib_value(p, h_idx + 5); 14714e872ae2SIlija Hadzic reg = R100_CP_PACKET0_GET_REG(header); 1472418da172SKeith Packard crtc = drm_crtc_find(p->rdev->ddev, p->filp, crtc_id); 1473b957f457SRob Clark if (!crtc) { 1474531369e6SDave Airlie DRM_ERROR("cannot find crtc %d\n", crtc_id); 147510e10d34SVille Syrjälä return -ENOENT; 1476531369e6SDave Airlie } 1477531369e6SDave Airlie radeon_crtc = to_radeon_crtc(crtc); 1478531369e6SDave Airlie crtc_id = radeon_crtc->crtc_id; 1479531369e6SDave Airlie 1480531369e6SDave Airlie if (!crtc->enabled) { 1481531369e6SDave Airlie /* if the CRTC isn't enabled - we need to nop out the wait until */ 1482513bcb46SDave Airlie ib[h_idx + 2] = PACKET2(0); 1483513bcb46SDave Airlie ib[h_idx + 3] = PACKET2(0); 1484531369e6SDave Airlie } else if (crtc_id == 1) { 1485531369e6SDave Airlie switch (reg) { 1486531369e6SDave Airlie case AVIVO_D1MODE_VLINE_START_END: 148790ebd065SAlex Deucher header &= ~R300_CP_PACKET0_REG_MASK; 1488531369e6SDave Airlie header |= AVIVO_D2MODE_VLINE_START_END >> 2; 1489531369e6SDave Airlie break; 1490531369e6SDave Airlie case RADEON_CRTC_GUI_TRIG_VLINE: 149190ebd065SAlex Deucher header &= ~R300_CP_PACKET0_REG_MASK; 1492531369e6SDave Airlie header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; 1493531369e6SDave Airlie break; 1494531369e6SDave Airlie default: 1495531369e6SDave Airlie DRM_ERROR("unknown crtc reloc\n"); 1496a3a88a66SPaul Bolle return -EINVAL; 1497531369e6SDave Airlie } 1498513bcb46SDave Airlie ib[h_idx] = header; 1499513bcb46SDave Airlie ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; 1500531369e6SDave Airlie } 1501a3a88a66SPaul Bolle 1502a3a88a66SPaul Bolle return 0; 1503531369e6SDave Airlie } 1504531369e6SDave Airlie 1505551ebd83SDave Airlie static int r100_get_vtx_size(uint32_t vtx_fmt) 1506551ebd83SDave Airlie { 1507551ebd83SDave Airlie int vtx_size; 1508551ebd83SDave Airlie vtx_size = 2; 1509551ebd83SDave Airlie /* ordered according to bits in spec */ 1510551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_W0) 1511551ebd83SDave Airlie vtx_size++; 1512551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) 1513551ebd83SDave Airlie vtx_size += 3; 1514551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) 1515551ebd83SDave Airlie vtx_size++; 1516551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) 1517551ebd83SDave Airlie vtx_size++; 1518551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) 1519551ebd83SDave Airlie vtx_size += 3; 1520551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) 1521551ebd83SDave Airlie vtx_size++; 1522551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) 1523551ebd83SDave Airlie vtx_size++; 1524551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) 1525551ebd83SDave Airlie vtx_size += 2; 1526551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) 1527551ebd83SDave Airlie vtx_size += 2; 1528551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) 1529551ebd83SDave Airlie vtx_size++; 1530551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) 1531551ebd83SDave Airlie vtx_size += 2; 1532551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) 1533551ebd83SDave Airlie vtx_size++; 1534551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) 1535551ebd83SDave Airlie vtx_size += 2; 1536551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) 1537551ebd83SDave Airlie vtx_size++; 1538551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) 1539551ebd83SDave Airlie vtx_size++; 1540551ebd83SDave Airlie /* blend weight */ 1541551ebd83SDave Airlie if (vtx_fmt & (0x7 << 15)) 1542551ebd83SDave Airlie vtx_size += (vtx_fmt >> 15) & 0x7; 1543551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_N0) 1544551ebd83SDave Airlie vtx_size += 3; 1545551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) 1546551ebd83SDave Airlie vtx_size += 2; 1547551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) 1548551ebd83SDave Airlie vtx_size++; 1549551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_W1) 1550551ebd83SDave Airlie vtx_size++; 1551551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_N1) 1552551ebd83SDave Airlie vtx_size++; 1553551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_Z) 1554551ebd83SDave Airlie vtx_size++; 1555551ebd83SDave Airlie return vtx_size; 1556551ebd83SDave Airlie } 1557551ebd83SDave Airlie 1558771fe6b9SJerome Glisse static int r100_packet0_check(struct radeon_cs_parser *p, 1559551ebd83SDave Airlie struct radeon_cs_packet *pkt, 1560551ebd83SDave Airlie unsigned idx, unsigned reg) 1561771fe6b9SJerome Glisse { 15621d0c0942SChristian König struct radeon_bo_list *reloc; 1563551ebd83SDave Airlie struct r100_cs_track *track; 1564771fe6b9SJerome Glisse volatile uint32_t *ib; 1565771fe6b9SJerome Glisse uint32_t tmp; 1566771fe6b9SJerome Glisse int r; 1567551ebd83SDave Airlie int i, face; 1568e024e110SDave Airlie u32 tile_flags = 0; 1569513bcb46SDave Airlie u32 idx_value; 1570771fe6b9SJerome Glisse 1571f2e39221SJerome Glisse ib = p->ib.ptr; 1572551ebd83SDave Airlie track = (struct r100_cs_track *)p->track; 1573551ebd83SDave Airlie 1574513bcb46SDave Airlie idx_value = radeon_get_ib_value(p, idx); 1575513bcb46SDave Airlie 1576771fe6b9SJerome Glisse switch (reg) { 1577531369e6SDave Airlie case RADEON_CRTC_GUI_TRIG_VLINE: 1578531369e6SDave Airlie r = r100_cs_packet_parse_vline(p); 1579531369e6SDave Airlie if (r) { 1580531369e6SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1581531369e6SDave Airlie idx, reg); 1582c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 1583531369e6SDave Airlie return r; 1584531369e6SDave Airlie } 1585531369e6SDave Airlie break; 1586771fe6b9SJerome Glisse /* FIXME: only allow PACKET3 blit? easier to check for out of 1587771fe6b9SJerome Glisse * range access */ 1588771fe6b9SJerome Glisse case RADEON_DST_PITCH_OFFSET: 1589771fe6b9SJerome Glisse case RADEON_SRC_PITCH_OFFSET: 1590551ebd83SDave Airlie r = r100_reloc_pitch_offset(p, pkt, idx, reg); 1591551ebd83SDave Airlie if (r) 1592551ebd83SDave Airlie return r; 1593551ebd83SDave Airlie break; 1594551ebd83SDave Airlie case RADEON_RB3D_DEPTHOFFSET: 1595012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1596771fe6b9SJerome Glisse if (r) { 1597771fe6b9SJerome Glisse DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1598771fe6b9SJerome Glisse idx, reg); 1599c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 1600771fe6b9SJerome Glisse return r; 1601771fe6b9SJerome Glisse } 1602551ebd83SDave Airlie track->zb.robj = reloc->robj; 1603513bcb46SDave Airlie track->zb.offset = idx_value; 160440b4a759SMarek Olšák track->zb_dirty = true; 1605df0af440SChristian König ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1606771fe6b9SJerome Glisse break; 1607771fe6b9SJerome Glisse case RADEON_RB3D_COLOROFFSET: 1608012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1609551ebd83SDave Airlie if (r) { 1610551ebd83SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1611551ebd83SDave Airlie idx, reg); 1612c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 1613551ebd83SDave Airlie return r; 1614551ebd83SDave Airlie } 1615551ebd83SDave Airlie track->cb[0].robj = reloc->robj; 1616513bcb46SDave Airlie track->cb[0].offset = idx_value; 161740b4a759SMarek Olšák track->cb_dirty = true; 1618df0af440SChristian König ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1619551ebd83SDave Airlie break; 1620771fe6b9SJerome Glisse case RADEON_PP_TXOFFSET_0: 1621771fe6b9SJerome Glisse case RADEON_PP_TXOFFSET_1: 1622771fe6b9SJerome Glisse case RADEON_PP_TXOFFSET_2: 1623551ebd83SDave Airlie i = (reg - RADEON_PP_TXOFFSET_0) / 24; 1624012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1625771fe6b9SJerome Glisse if (r) { 1626771fe6b9SJerome Glisse DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1627771fe6b9SJerome Glisse idx, reg); 1628c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 1629771fe6b9SJerome Glisse return r; 1630771fe6b9SJerome Glisse } 1631f2746f83SAlex Deucher if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1632df0af440SChristian König if (reloc->tiling_flags & RADEON_TILING_MACRO) 1633f2746f83SAlex Deucher tile_flags |= RADEON_TXO_MACRO_TILE; 1634df0af440SChristian König if (reloc->tiling_flags & RADEON_TILING_MICRO) 1635f2746f83SAlex Deucher tile_flags |= RADEON_TXO_MICRO_TILE_X2; 1636f2746f83SAlex Deucher 1637f2746f83SAlex Deucher tmp = idx_value & ~(0x7 << 2); 1638f2746f83SAlex Deucher tmp |= tile_flags; 1639df0af440SChristian König ib[idx] = tmp + ((u32)reloc->gpu_offset); 1640f2746f83SAlex Deucher } else 1641df0af440SChristian König ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1642551ebd83SDave Airlie track->textures[i].robj = reloc->robj; 164340b4a759SMarek Olšák track->tex_dirty = true; 1644771fe6b9SJerome Glisse break; 1645551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T0_0: 1646551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T0_1: 1647551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T0_2: 1648551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T0_3: 1649551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T0_4: 1650551ebd83SDave Airlie i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; 1651012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1652551ebd83SDave Airlie if (r) { 1653551ebd83SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1654551ebd83SDave Airlie idx, reg); 1655c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 1656551ebd83SDave Airlie return r; 1657551ebd83SDave Airlie } 1658513bcb46SDave Airlie track->textures[0].cube_info[i].offset = idx_value; 1659df0af440SChristian König ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1660551ebd83SDave Airlie track->textures[0].cube_info[i].robj = reloc->robj; 166140b4a759SMarek Olšák track->tex_dirty = true; 1662551ebd83SDave Airlie break; 1663551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T1_0: 1664551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T1_1: 1665551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T1_2: 1666551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T1_3: 1667551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T1_4: 1668551ebd83SDave Airlie i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; 1669012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1670551ebd83SDave Airlie if (r) { 1671551ebd83SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1672551ebd83SDave Airlie idx, reg); 1673c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 1674551ebd83SDave Airlie return r; 1675551ebd83SDave Airlie } 1676513bcb46SDave Airlie track->textures[1].cube_info[i].offset = idx_value; 1677df0af440SChristian König ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1678551ebd83SDave Airlie track->textures[1].cube_info[i].robj = reloc->robj; 167940b4a759SMarek Olšák track->tex_dirty = true; 1680551ebd83SDave Airlie break; 1681551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T2_0: 1682551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T2_1: 1683551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T2_2: 1684551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T2_3: 1685551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T2_4: 1686551ebd83SDave Airlie i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; 1687012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1688551ebd83SDave Airlie if (r) { 1689551ebd83SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1690551ebd83SDave Airlie idx, reg); 1691c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 1692551ebd83SDave Airlie return r; 1693551ebd83SDave Airlie } 1694513bcb46SDave Airlie track->textures[2].cube_info[i].offset = idx_value; 1695df0af440SChristian König ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1696551ebd83SDave Airlie track->textures[2].cube_info[i].robj = reloc->robj; 169740b4a759SMarek Olšák track->tex_dirty = true; 1698551ebd83SDave Airlie break; 1699551ebd83SDave Airlie case RADEON_RE_WIDTH_HEIGHT: 1700513bcb46SDave Airlie track->maxy = ((idx_value >> 16) & 0x7FF); 170140b4a759SMarek Olšák track->cb_dirty = true; 170240b4a759SMarek Olšák track->zb_dirty = true; 1703551ebd83SDave Airlie break; 1704e024e110SDave Airlie case RADEON_RB3D_COLORPITCH: 1705012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1706e024e110SDave Airlie if (r) { 1707e024e110SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1708e024e110SDave Airlie idx, reg); 1709c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 1710e024e110SDave Airlie return r; 1711e024e110SDave Airlie } 1712c9068eb2SAlex Deucher if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1713df0af440SChristian König if (reloc->tiling_flags & RADEON_TILING_MACRO) 1714e024e110SDave Airlie tile_flags |= RADEON_COLOR_TILE_ENABLE; 1715df0af440SChristian König if (reloc->tiling_flags & RADEON_TILING_MICRO) 1716e024e110SDave Airlie tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; 1717e024e110SDave Airlie 1718513bcb46SDave Airlie tmp = idx_value & ~(0x7 << 16); 1719e024e110SDave Airlie tmp |= tile_flags; 1720e024e110SDave Airlie ib[idx] = tmp; 1721c9068eb2SAlex Deucher } else 1722c9068eb2SAlex Deucher ib[idx] = idx_value; 1723551ebd83SDave Airlie 1724513bcb46SDave Airlie track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; 172540b4a759SMarek Olšák track->cb_dirty = true; 1726551ebd83SDave Airlie break; 1727551ebd83SDave Airlie case RADEON_RB3D_DEPTHPITCH: 1728513bcb46SDave Airlie track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; 172940b4a759SMarek Olšák track->zb_dirty = true; 1730551ebd83SDave Airlie break; 1731551ebd83SDave Airlie case RADEON_RB3D_CNTL: 1732513bcb46SDave Airlie switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { 1733551ebd83SDave Airlie case 7: 1734551ebd83SDave Airlie case 8: 1735551ebd83SDave Airlie case 9: 1736551ebd83SDave Airlie case 11: 1737551ebd83SDave Airlie case 12: 1738551ebd83SDave Airlie track->cb[0].cpp = 1; 1739551ebd83SDave Airlie break; 1740551ebd83SDave Airlie case 3: 1741551ebd83SDave Airlie case 4: 1742551ebd83SDave Airlie case 15: 1743551ebd83SDave Airlie track->cb[0].cpp = 2; 1744551ebd83SDave Airlie break; 1745551ebd83SDave Airlie case 6: 1746551ebd83SDave Airlie track->cb[0].cpp = 4; 1747551ebd83SDave Airlie break; 1748551ebd83SDave Airlie default: 1749551ebd83SDave Airlie DRM_ERROR("Invalid color buffer format (%d) !\n", 1750513bcb46SDave Airlie ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); 1751551ebd83SDave Airlie return -EINVAL; 1752551ebd83SDave Airlie } 1753513bcb46SDave Airlie track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); 175440b4a759SMarek Olšák track->cb_dirty = true; 175540b4a759SMarek Olšák track->zb_dirty = true; 1756551ebd83SDave Airlie break; 1757551ebd83SDave Airlie case RADEON_RB3D_ZSTENCILCNTL: 1758513bcb46SDave Airlie switch (idx_value & 0xf) { 1759551ebd83SDave Airlie case 0: 1760551ebd83SDave Airlie track->zb.cpp = 2; 1761551ebd83SDave Airlie break; 1762551ebd83SDave Airlie case 2: 1763551ebd83SDave Airlie case 3: 1764551ebd83SDave Airlie case 4: 1765551ebd83SDave Airlie case 5: 1766551ebd83SDave Airlie case 9: 1767551ebd83SDave Airlie case 11: 1768551ebd83SDave Airlie track->zb.cpp = 4; 1769551ebd83SDave Airlie break; 1770551ebd83SDave Airlie default: 1771551ebd83SDave Airlie break; 1772551ebd83SDave Airlie } 177340b4a759SMarek Olšák track->zb_dirty = true; 1774e024e110SDave Airlie break; 177517782d99SDave Airlie case RADEON_RB3D_ZPASS_ADDR: 1776012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 177717782d99SDave Airlie if (r) { 177817782d99SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 177917782d99SDave Airlie idx, reg); 1780c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 178117782d99SDave Airlie return r; 178217782d99SDave Airlie } 1783df0af440SChristian König ib[idx] = idx_value + ((u32)reloc->gpu_offset); 178417782d99SDave Airlie break; 1785551ebd83SDave Airlie case RADEON_PP_CNTL: 1786551ebd83SDave Airlie { 1787513bcb46SDave Airlie uint32_t temp = idx_value >> 4; 1788551ebd83SDave Airlie for (i = 0; i < track->num_texture; i++) 1789551ebd83SDave Airlie track->textures[i].enabled = !!(temp & (1 << i)); 179040b4a759SMarek Olšák track->tex_dirty = true; 1791551ebd83SDave Airlie } 1792551ebd83SDave Airlie break; 1793551ebd83SDave Airlie case RADEON_SE_VF_CNTL: 1794513bcb46SDave Airlie track->vap_vf_cntl = idx_value; 1795551ebd83SDave Airlie break; 1796551ebd83SDave Airlie case RADEON_SE_VTX_FMT: 1797513bcb46SDave Airlie track->vtx_size = r100_get_vtx_size(idx_value); 1798551ebd83SDave Airlie break; 1799551ebd83SDave Airlie case RADEON_PP_TEX_SIZE_0: 1800551ebd83SDave Airlie case RADEON_PP_TEX_SIZE_1: 1801551ebd83SDave Airlie case RADEON_PP_TEX_SIZE_2: 1802551ebd83SDave Airlie i = (reg - RADEON_PP_TEX_SIZE_0) / 8; 1803513bcb46SDave Airlie track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; 1804513bcb46SDave Airlie track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; 180540b4a759SMarek Olšák track->tex_dirty = true; 1806551ebd83SDave Airlie break; 1807551ebd83SDave Airlie case RADEON_PP_TEX_PITCH_0: 1808551ebd83SDave Airlie case RADEON_PP_TEX_PITCH_1: 1809551ebd83SDave Airlie case RADEON_PP_TEX_PITCH_2: 1810551ebd83SDave Airlie i = (reg - RADEON_PP_TEX_PITCH_0) / 8; 1811513bcb46SDave Airlie track->textures[i].pitch = idx_value + 32; 181240b4a759SMarek Olšák track->tex_dirty = true; 1813551ebd83SDave Airlie break; 1814551ebd83SDave Airlie case RADEON_PP_TXFILTER_0: 1815551ebd83SDave Airlie case RADEON_PP_TXFILTER_1: 1816551ebd83SDave Airlie case RADEON_PP_TXFILTER_2: 1817551ebd83SDave Airlie i = (reg - RADEON_PP_TXFILTER_0) / 24; 1818513bcb46SDave Airlie track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) 1819551ebd83SDave Airlie >> RADEON_MAX_MIP_LEVEL_SHIFT); 1820513bcb46SDave Airlie tmp = (idx_value >> 23) & 0x7; 1821551ebd83SDave Airlie if (tmp == 2 || tmp == 6) 1822551ebd83SDave Airlie track->textures[i].roundup_w = false; 1823513bcb46SDave Airlie tmp = (idx_value >> 27) & 0x7; 1824551ebd83SDave Airlie if (tmp == 2 || tmp == 6) 1825551ebd83SDave Airlie track->textures[i].roundup_h = false; 182640b4a759SMarek Olšák track->tex_dirty = true; 1827551ebd83SDave Airlie break; 1828551ebd83SDave Airlie case RADEON_PP_TXFORMAT_0: 1829551ebd83SDave Airlie case RADEON_PP_TXFORMAT_1: 1830551ebd83SDave Airlie case RADEON_PP_TXFORMAT_2: 1831551ebd83SDave Airlie i = (reg - RADEON_PP_TXFORMAT_0) / 24; 1832513bcb46SDave Airlie if (idx_value & RADEON_TXFORMAT_NON_POWER2) { 18337bf2f607Szhengbin track->textures[i].use_pitch = true; 1834551ebd83SDave Airlie } else { 18357bf2f607Szhengbin track->textures[i].use_pitch = false; 1836008037d4SAlex Deucher track->textures[i].width = 1 << ((idx_value & RADEON_TXFORMAT_WIDTH_MASK) >> RADEON_TXFORMAT_WIDTH_SHIFT); 1837008037d4SAlex Deucher track->textures[i].height = 1 << ((idx_value & RADEON_TXFORMAT_HEIGHT_MASK) >> RADEON_TXFORMAT_HEIGHT_SHIFT); 1838551ebd83SDave Airlie } 1839513bcb46SDave Airlie if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) 1840551ebd83SDave Airlie track->textures[i].tex_coord_type = 2; 1841513bcb46SDave Airlie switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { 1842551ebd83SDave Airlie case RADEON_TXFORMAT_I8: 1843551ebd83SDave Airlie case RADEON_TXFORMAT_RGB332: 1844551ebd83SDave Airlie case RADEON_TXFORMAT_Y8: 1845551ebd83SDave Airlie track->textures[i].cpp = 1; 1846f9da52d5SRoland Scheidegger track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1847551ebd83SDave Airlie break; 1848551ebd83SDave Airlie case RADEON_TXFORMAT_AI88: 1849551ebd83SDave Airlie case RADEON_TXFORMAT_ARGB1555: 1850551ebd83SDave Airlie case RADEON_TXFORMAT_RGB565: 1851551ebd83SDave Airlie case RADEON_TXFORMAT_ARGB4444: 1852551ebd83SDave Airlie case RADEON_TXFORMAT_VYUY422: 1853551ebd83SDave Airlie case RADEON_TXFORMAT_YVYU422: 1854551ebd83SDave Airlie case RADEON_TXFORMAT_SHADOW16: 1855551ebd83SDave Airlie case RADEON_TXFORMAT_LDUDV655: 1856551ebd83SDave Airlie case RADEON_TXFORMAT_DUDV88: 1857551ebd83SDave Airlie track->textures[i].cpp = 2; 1858f9da52d5SRoland Scheidegger track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1859551ebd83SDave Airlie break; 1860551ebd83SDave Airlie case RADEON_TXFORMAT_ARGB8888: 1861551ebd83SDave Airlie case RADEON_TXFORMAT_RGBA8888: 1862551ebd83SDave Airlie case RADEON_TXFORMAT_SHADOW32: 1863551ebd83SDave Airlie case RADEON_TXFORMAT_LDUDUV8888: 1864551ebd83SDave Airlie track->textures[i].cpp = 4; 1865f9da52d5SRoland Scheidegger track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1866551ebd83SDave Airlie break; 1867d785d78bSDave Airlie case RADEON_TXFORMAT_DXT1: 1868d785d78bSDave Airlie track->textures[i].cpp = 1; 1869d785d78bSDave Airlie track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 1870d785d78bSDave Airlie break; 1871d785d78bSDave Airlie case RADEON_TXFORMAT_DXT23: 1872d785d78bSDave Airlie case RADEON_TXFORMAT_DXT45: 1873d785d78bSDave Airlie track->textures[i].cpp = 1; 1874d785d78bSDave Airlie track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 1875d785d78bSDave Airlie break; 1876551ebd83SDave Airlie } 1877513bcb46SDave Airlie track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); 1878513bcb46SDave Airlie track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); 187940b4a759SMarek Olšák track->tex_dirty = true; 1880551ebd83SDave Airlie break; 1881551ebd83SDave Airlie case RADEON_PP_CUBIC_FACES_0: 1882551ebd83SDave Airlie case RADEON_PP_CUBIC_FACES_1: 1883551ebd83SDave Airlie case RADEON_PP_CUBIC_FACES_2: 1884513bcb46SDave Airlie tmp = idx_value; 1885551ebd83SDave Airlie i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; 1886551ebd83SDave Airlie for (face = 0; face < 4; face++) { 1887551ebd83SDave Airlie track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); 1888551ebd83SDave Airlie track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); 1889551ebd83SDave Airlie } 189040b4a759SMarek Olšák track->tex_dirty = true; 1891551ebd83SDave Airlie break; 1892771fe6b9SJerome Glisse default: 18937ca85295SJoe Perches pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx); 1894551ebd83SDave Airlie return -EINVAL; 1895771fe6b9SJerome Glisse } 1896771fe6b9SJerome Glisse return 0; 1897771fe6b9SJerome Glisse } 1898771fe6b9SJerome Glisse 1899068a117cSJerome Glisse int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 1900068a117cSJerome Glisse struct radeon_cs_packet *pkt, 19014c788679SJerome Glisse struct radeon_bo *robj) 1902068a117cSJerome Glisse { 1903068a117cSJerome Glisse unsigned idx; 1904513bcb46SDave Airlie u32 value; 1905068a117cSJerome Glisse idx = pkt->idx + 1; 1906513bcb46SDave Airlie value = radeon_get_ib_value(p, idx + 2); 19074c788679SJerome Glisse if ((value + 1) > radeon_bo_size(robj)) { 1908068a117cSJerome Glisse DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " 1909068a117cSJerome Glisse "(need %u have %lu) !\n", 1910513bcb46SDave Airlie value + 1, 19114c788679SJerome Glisse radeon_bo_size(robj)); 1912068a117cSJerome Glisse return -EINVAL; 1913068a117cSJerome Glisse } 1914068a117cSJerome Glisse return 0; 1915068a117cSJerome Glisse } 1916068a117cSJerome Glisse 1917771fe6b9SJerome Glisse static int r100_packet3_check(struct radeon_cs_parser *p, 1918771fe6b9SJerome Glisse struct radeon_cs_packet *pkt) 1919771fe6b9SJerome Glisse { 19201d0c0942SChristian König struct radeon_bo_list *reloc; 1921551ebd83SDave Airlie struct r100_cs_track *track; 1922771fe6b9SJerome Glisse unsigned idx; 1923771fe6b9SJerome Glisse volatile uint32_t *ib; 1924771fe6b9SJerome Glisse int r; 1925771fe6b9SJerome Glisse 1926f2e39221SJerome Glisse ib = p->ib.ptr; 1927771fe6b9SJerome Glisse idx = pkt->idx + 1; 1928551ebd83SDave Airlie track = (struct r100_cs_track *)p->track; 1929771fe6b9SJerome Glisse switch (pkt->opcode) { 1930771fe6b9SJerome Glisse case PACKET3_3D_LOAD_VBPNTR: 1931513bcb46SDave Airlie r = r100_packet3_load_vbpntr(p, pkt, idx); 1932513bcb46SDave Airlie if (r) 1933771fe6b9SJerome Glisse return r; 1934771fe6b9SJerome Glisse break; 1935771fe6b9SJerome Glisse case PACKET3_INDX_BUFFER: 1936012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1937771fe6b9SJerome Glisse if (r) { 1938771fe6b9SJerome Glisse DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1939c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 1940771fe6b9SJerome Glisse return r; 1941771fe6b9SJerome Glisse } 1942df0af440SChristian König ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset); 1943068a117cSJerome Glisse r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1944068a117cSJerome Glisse if (r) { 1945068a117cSJerome Glisse return r; 1946068a117cSJerome Glisse } 1947771fe6b9SJerome Glisse break; 1948771fe6b9SJerome Glisse case 0x23: 1949771fe6b9SJerome Glisse /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ 1950012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1951771fe6b9SJerome Glisse if (r) { 1952771fe6b9SJerome Glisse DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1953c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 1954771fe6b9SJerome Glisse return r; 1955771fe6b9SJerome Glisse } 1956df0af440SChristian König ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset); 1957551ebd83SDave Airlie track->num_arrays = 1; 1958513bcb46SDave Airlie track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); 1959551ebd83SDave Airlie 1960551ebd83SDave Airlie track->arrays[0].robj = reloc->robj; 1961551ebd83SDave Airlie track->arrays[0].esize = track->vtx_size; 1962551ebd83SDave Airlie 1963513bcb46SDave Airlie track->max_indx = radeon_get_ib_value(p, idx+1); 1964551ebd83SDave Airlie 1965513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); 1966551ebd83SDave Airlie track->immd_dwords = pkt->count - 1; 1967551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track); 1968551ebd83SDave Airlie if (r) 1969551ebd83SDave Airlie return r; 1970771fe6b9SJerome Glisse break; 1971771fe6b9SJerome Glisse case PACKET3_3D_DRAW_IMMD: 1972513bcb46SDave Airlie if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1973551ebd83SDave Airlie DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1974551ebd83SDave Airlie return -EINVAL; 1975551ebd83SDave Airlie } 1976cf57fc7aSAlex Deucher track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); 1977513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1978551ebd83SDave Airlie track->immd_dwords = pkt->count - 1; 1979551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track); 1980551ebd83SDave Airlie if (r) 1981551ebd83SDave Airlie return r; 1982551ebd83SDave Airlie break; 1983771fe6b9SJerome Glisse /* triggers drawing using in-packet vertex data */ 1984771fe6b9SJerome Glisse case PACKET3_3D_DRAW_IMMD_2: 1985513bcb46SDave Airlie if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1986551ebd83SDave Airlie DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1987551ebd83SDave Airlie return -EINVAL; 1988551ebd83SDave Airlie } 1989513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1990551ebd83SDave Airlie track->immd_dwords = pkt->count; 1991551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track); 1992551ebd83SDave Airlie if (r) 1993551ebd83SDave Airlie return r; 1994551ebd83SDave Airlie break; 1995771fe6b9SJerome Glisse /* triggers drawing using in-packet vertex data */ 1996771fe6b9SJerome Glisse case PACKET3_3D_DRAW_VBUF_2: 1997513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1998551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track); 1999551ebd83SDave Airlie if (r) 2000551ebd83SDave Airlie return r; 2001551ebd83SDave Airlie break; 2002771fe6b9SJerome Glisse /* triggers drawing of vertex buffers setup elsewhere */ 2003771fe6b9SJerome Glisse case PACKET3_3D_DRAW_INDX_2: 2004513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx); 2005551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track); 2006551ebd83SDave Airlie if (r) 2007551ebd83SDave Airlie return r; 2008551ebd83SDave Airlie break; 2009771fe6b9SJerome Glisse /* triggers drawing using indices to vertex buffer */ 2010771fe6b9SJerome Glisse case PACKET3_3D_DRAW_VBUF: 2011513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 2012551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track); 2013551ebd83SDave Airlie if (r) 2014551ebd83SDave Airlie return r; 2015551ebd83SDave Airlie break; 2016771fe6b9SJerome Glisse /* triggers drawing of vertex buffers setup elsewhere */ 2017771fe6b9SJerome Glisse case PACKET3_3D_DRAW_INDX: 2018513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 2019551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track); 2020551ebd83SDave Airlie if (r) 2021551ebd83SDave Airlie return r; 2022551ebd83SDave Airlie break; 2023771fe6b9SJerome Glisse /* triggers drawing using indices to vertex buffer */ 2024ab9e1f59SDave Airlie case PACKET3_3D_CLEAR_HIZ: 2025ab9e1f59SDave Airlie case PACKET3_3D_CLEAR_ZMASK: 2026ab9e1f59SDave Airlie if (p->rdev->hyperz_filp != p->filp) 2027ab9e1f59SDave Airlie return -EINVAL; 2028ab9e1f59SDave Airlie break; 2029771fe6b9SJerome Glisse case PACKET3_NOP: 2030771fe6b9SJerome Glisse break; 2031771fe6b9SJerome Glisse default: 2032771fe6b9SJerome Glisse DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 2033771fe6b9SJerome Glisse return -EINVAL; 2034771fe6b9SJerome Glisse } 2035771fe6b9SJerome Glisse return 0; 2036771fe6b9SJerome Glisse } 2037771fe6b9SJerome Glisse 2038771fe6b9SJerome Glisse int r100_cs_parse(struct radeon_cs_parser *p) 2039771fe6b9SJerome Glisse { 2040771fe6b9SJerome Glisse struct radeon_cs_packet pkt; 20419f022ddfSJerome Glisse struct r100_cs_track *track; 2042771fe6b9SJerome Glisse int r; 2043771fe6b9SJerome Glisse 20449f022ddfSJerome Glisse track = kzalloc(sizeof(*track), GFP_KERNEL); 2045ce067913SDan Carpenter if (!track) 2046ce067913SDan Carpenter return -ENOMEM; 20479f022ddfSJerome Glisse r100_cs_track_clear(p->rdev, track); 20489f022ddfSJerome Glisse p->track = track; 2049771fe6b9SJerome Glisse do { 2050c38f34b5SIlija Hadzic r = radeon_cs_packet_parse(p, &pkt, p->idx); 2051771fe6b9SJerome Glisse if (r) { 2052771fe6b9SJerome Glisse return r; 2053771fe6b9SJerome Glisse } 2054771fe6b9SJerome Glisse p->idx += pkt.count + 2; 2055771fe6b9SJerome Glisse switch (pkt.type) { 20564e872ae2SIlija Hadzic case RADEON_PACKET_TYPE0: 2057551ebd83SDave Airlie if (p->rdev->family >= CHIP_R200) 2058551ebd83SDave Airlie r = r100_cs_parse_packet0(p, &pkt, 2059551ebd83SDave Airlie p->rdev->config.r100.reg_safe_bm, 2060551ebd83SDave Airlie p->rdev->config.r100.reg_safe_bm_size, 2061551ebd83SDave Airlie &r200_packet0_check); 2062551ebd83SDave Airlie else 2063551ebd83SDave Airlie r = r100_cs_parse_packet0(p, &pkt, 2064551ebd83SDave Airlie p->rdev->config.r100.reg_safe_bm, 2065551ebd83SDave Airlie p->rdev->config.r100.reg_safe_bm_size, 2066551ebd83SDave Airlie &r100_packet0_check); 2067771fe6b9SJerome Glisse break; 20684e872ae2SIlija Hadzic case RADEON_PACKET_TYPE2: 2069771fe6b9SJerome Glisse break; 20704e872ae2SIlija Hadzic case RADEON_PACKET_TYPE3: 2071771fe6b9SJerome Glisse r = r100_packet3_check(p, &pkt); 2072771fe6b9SJerome Glisse break; 2073771fe6b9SJerome Glisse default: 2074771fe6b9SJerome Glisse DRM_ERROR("Unknown packet type %d !\n", 2075771fe6b9SJerome Glisse pkt.type); 2076771fe6b9SJerome Glisse return -EINVAL; 2077771fe6b9SJerome Glisse } 207866b3543eSIlija Hadzic if (r) 2079771fe6b9SJerome Glisse return r; 20806d2d13ddSChristian König } while (p->idx < p->chunk_ib->length_dw); 2081771fe6b9SJerome Glisse return 0; 2082771fe6b9SJerome Glisse } 2083771fe6b9SJerome Glisse 20840242f74dSAlex Deucher static void r100_cs_track_texture_print(struct r100_cs_track_texture *t) 20850242f74dSAlex Deucher { 20860242f74dSAlex Deucher DRM_ERROR("pitch %d\n", t->pitch); 20870242f74dSAlex Deucher DRM_ERROR("use_pitch %d\n", t->use_pitch); 20880242f74dSAlex Deucher DRM_ERROR("width %d\n", t->width); 20890242f74dSAlex Deucher DRM_ERROR("width_11 %d\n", t->width_11); 20900242f74dSAlex Deucher DRM_ERROR("height %d\n", t->height); 20910242f74dSAlex Deucher DRM_ERROR("height_11 %d\n", t->height_11); 20920242f74dSAlex Deucher DRM_ERROR("num levels %d\n", t->num_levels); 20930242f74dSAlex Deucher DRM_ERROR("depth %d\n", t->txdepth); 20940242f74dSAlex Deucher DRM_ERROR("bpp %d\n", t->cpp); 20950242f74dSAlex Deucher DRM_ERROR("coordinate type %d\n", t->tex_coord_type); 20960242f74dSAlex Deucher DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); 20970242f74dSAlex Deucher DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); 20980242f74dSAlex Deucher DRM_ERROR("compress format %d\n", t->compress_format); 20990242f74dSAlex Deucher } 21000242f74dSAlex Deucher 21010242f74dSAlex Deucher static int r100_track_compress_size(int compress_format, int w, int h) 21020242f74dSAlex Deucher { 21030242f74dSAlex Deucher int block_width, block_height, block_bytes; 21040242f74dSAlex Deucher int wblocks, hblocks; 21050242f74dSAlex Deucher int min_wblocks; 21060242f74dSAlex Deucher int sz; 21070242f74dSAlex Deucher 21080242f74dSAlex Deucher block_width = 4; 21090242f74dSAlex Deucher block_height = 4; 21100242f74dSAlex Deucher 21110242f74dSAlex Deucher switch (compress_format) { 21120242f74dSAlex Deucher case R100_TRACK_COMP_DXT1: 21130242f74dSAlex Deucher block_bytes = 8; 21140242f74dSAlex Deucher min_wblocks = 4; 21150242f74dSAlex Deucher break; 21160242f74dSAlex Deucher default: 21170242f74dSAlex Deucher case R100_TRACK_COMP_DXT35: 21180242f74dSAlex Deucher block_bytes = 16; 21190242f74dSAlex Deucher min_wblocks = 2; 21200242f74dSAlex Deucher break; 21210242f74dSAlex Deucher } 21220242f74dSAlex Deucher 21230242f74dSAlex Deucher hblocks = (h + block_height - 1) / block_height; 21240242f74dSAlex Deucher wblocks = (w + block_width - 1) / block_width; 21250242f74dSAlex Deucher if (wblocks < min_wblocks) 21260242f74dSAlex Deucher wblocks = min_wblocks; 21270242f74dSAlex Deucher sz = wblocks * hblocks * block_bytes; 21280242f74dSAlex Deucher return sz; 21290242f74dSAlex Deucher } 21300242f74dSAlex Deucher 21310242f74dSAlex Deucher static int r100_cs_track_cube(struct radeon_device *rdev, 21320242f74dSAlex Deucher struct r100_cs_track *track, unsigned idx) 21330242f74dSAlex Deucher { 21340242f74dSAlex Deucher unsigned face, w, h; 21350242f74dSAlex Deucher struct radeon_bo *cube_robj; 21360242f74dSAlex Deucher unsigned long size; 21370242f74dSAlex Deucher unsigned compress_format = track->textures[idx].compress_format; 21380242f74dSAlex Deucher 21390242f74dSAlex Deucher for (face = 0; face < 5; face++) { 21400242f74dSAlex Deucher cube_robj = track->textures[idx].cube_info[face].robj; 21410242f74dSAlex Deucher w = track->textures[idx].cube_info[face].width; 21420242f74dSAlex Deucher h = track->textures[idx].cube_info[face].height; 21430242f74dSAlex Deucher 21440242f74dSAlex Deucher if (compress_format) { 21450242f74dSAlex Deucher size = r100_track_compress_size(compress_format, w, h); 21460242f74dSAlex Deucher } else 21470242f74dSAlex Deucher size = w * h; 21480242f74dSAlex Deucher size *= track->textures[idx].cpp; 21490242f74dSAlex Deucher 21500242f74dSAlex Deucher size += track->textures[idx].cube_info[face].offset; 21510242f74dSAlex Deucher 21520242f74dSAlex Deucher if (size > radeon_bo_size(cube_robj)) { 21530242f74dSAlex Deucher DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", 21540242f74dSAlex Deucher size, radeon_bo_size(cube_robj)); 21550242f74dSAlex Deucher r100_cs_track_texture_print(&track->textures[idx]); 21560242f74dSAlex Deucher return -1; 21570242f74dSAlex Deucher } 21580242f74dSAlex Deucher } 21590242f74dSAlex Deucher return 0; 21600242f74dSAlex Deucher } 21610242f74dSAlex Deucher 21620242f74dSAlex Deucher static int r100_cs_track_texture_check(struct radeon_device *rdev, 21630242f74dSAlex Deucher struct r100_cs_track *track) 21640242f74dSAlex Deucher { 21650242f74dSAlex Deucher struct radeon_bo *robj; 21660242f74dSAlex Deucher unsigned long size; 21670242f74dSAlex Deucher unsigned u, i, w, h, d; 21680242f74dSAlex Deucher int ret; 21690242f74dSAlex Deucher 21700242f74dSAlex Deucher for (u = 0; u < track->num_texture; u++) { 21710242f74dSAlex Deucher if (!track->textures[u].enabled) 21720242f74dSAlex Deucher continue; 21730242f74dSAlex Deucher if (track->textures[u].lookup_disable) 21740242f74dSAlex Deucher continue; 21750242f74dSAlex Deucher robj = track->textures[u].robj; 21760242f74dSAlex Deucher if (robj == NULL) { 21770242f74dSAlex Deucher DRM_ERROR("No texture bound to unit %u\n", u); 21780242f74dSAlex Deucher return -EINVAL; 21790242f74dSAlex Deucher } 21800242f74dSAlex Deucher size = 0; 21810242f74dSAlex Deucher for (i = 0; i <= track->textures[u].num_levels; i++) { 21820242f74dSAlex Deucher if (track->textures[u].use_pitch) { 21830242f74dSAlex Deucher if (rdev->family < CHIP_R300) 21840242f74dSAlex Deucher w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); 21850242f74dSAlex Deucher else 21860242f74dSAlex Deucher w = track->textures[u].pitch / (1 << i); 21870242f74dSAlex Deucher } else { 21880242f74dSAlex Deucher w = track->textures[u].width; 21890242f74dSAlex Deucher if (rdev->family >= CHIP_RV515) 21900242f74dSAlex Deucher w |= track->textures[u].width_11; 21910242f74dSAlex Deucher w = w / (1 << i); 21920242f74dSAlex Deucher if (track->textures[u].roundup_w) 21930242f74dSAlex Deucher w = roundup_pow_of_two(w); 21940242f74dSAlex Deucher } 21950242f74dSAlex Deucher h = track->textures[u].height; 21960242f74dSAlex Deucher if (rdev->family >= CHIP_RV515) 21970242f74dSAlex Deucher h |= track->textures[u].height_11; 21980242f74dSAlex Deucher h = h / (1 << i); 21990242f74dSAlex Deucher if (track->textures[u].roundup_h) 22000242f74dSAlex Deucher h = roundup_pow_of_two(h); 22010242f74dSAlex Deucher if (track->textures[u].tex_coord_type == 1) { 22020242f74dSAlex Deucher d = (1 << track->textures[u].txdepth) / (1 << i); 22030242f74dSAlex Deucher if (!d) 22040242f74dSAlex Deucher d = 1; 22050242f74dSAlex Deucher } else { 22060242f74dSAlex Deucher d = 1; 22070242f74dSAlex Deucher } 22080242f74dSAlex Deucher if (track->textures[u].compress_format) { 22090242f74dSAlex Deucher 22100242f74dSAlex Deucher size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d; 22110242f74dSAlex Deucher /* compressed textures are block based */ 22120242f74dSAlex Deucher } else 22130242f74dSAlex Deucher size += w * h * d; 22140242f74dSAlex Deucher } 22150242f74dSAlex Deucher size *= track->textures[u].cpp; 22160242f74dSAlex Deucher 22170242f74dSAlex Deucher switch (track->textures[u].tex_coord_type) { 22180242f74dSAlex Deucher case 0: 22190242f74dSAlex Deucher case 1: 22200242f74dSAlex Deucher break; 22210242f74dSAlex Deucher case 2: 22220242f74dSAlex Deucher if (track->separate_cube) { 22230242f74dSAlex Deucher ret = r100_cs_track_cube(rdev, track, u); 22240242f74dSAlex Deucher if (ret) 22250242f74dSAlex Deucher return ret; 22260242f74dSAlex Deucher } else 22270242f74dSAlex Deucher size *= 6; 22280242f74dSAlex Deucher break; 22290242f74dSAlex Deucher default: 22300242f74dSAlex Deucher DRM_ERROR("Invalid texture coordinate type %u for unit " 22310242f74dSAlex Deucher "%u\n", track->textures[u].tex_coord_type, u); 22320242f74dSAlex Deucher return -EINVAL; 22330242f74dSAlex Deucher } 22340242f74dSAlex Deucher if (size > radeon_bo_size(robj)) { 22350242f74dSAlex Deucher DRM_ERROR("Texture of unit %u needs %lu bytes but is " 22360242f74dSAlex Deucher "%lu\n", u, size, radeon_bo_size(robj)); 22370242f74dSAlex Deucher r100_cs_track_texture_print(&track->textures[u]); 22380242f74dSAlex Deucher return -EINVAL; 22390242f74dSAlex Deucher } 22400242f74dSAlex Deucher } 22410242f74dSAlex Deucher return 0; 22420242f74dSAlex Deucher } 22430242f74dSAlex Deucher 22440242f74dSAlex Deucher int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) 22450242f74dSAlex Deucher { 22460242f74dSAlex Deucher unsigned i; 22470242f74dSAlex Deucher unsigned long size; 22480242f74dSAlex Deucher unsigned prim_walk; 22490242f74dSAlex Deucher unsigned nverts; 22500242f74dSAlex Deucher unsigned num_cb = track->cb_dirty ? track->num_cb : 0; 22510242f74dSAlex Deucher 22520242f74dSAlex Deucher if (num_cb && !track->zb_cb_clear && !track->color_channel_mask && 22530242f74dSAlex Deucher !track->blend_read_enable) 22540242f74dSAlex Deucher num_cb = 0; 22550242f74dSAlex Deucher 22560242f74dSAlex Deucher for (i = 0; i < num_cb; i++) { 22570242f74dSAlex Deucher if (track->cb[i].robj == NULL) { 22580242f74dSAlex Deucher DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); 22590242f74dSAlex Deucher return -EINVAL; 22600242f74dSAlex Deucher } 22610242f74dSAlex Deucher size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; 22620242f74dSAlex Deucher size += track->cb[i].offset; 22630242f74dSAlex Deucher if (size > radeon_bo_size(track->cb[i].robj)) { 22640242f74dSAlex Deucher DRM_ERROR("[drm] Buffer too small for color buffer %d " 22650242f74dSAlex Deucher "(need %lu have %lu) !\n", i, size, 22660242f74dSAlex Deucher radeon_bo_size(track->cb[i].robj)); 22670242f74dSAlex Deucher DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", 22680242f74dSAlex Deucher i, track->cb[i].pitch, track->cb[i].cpp, 22690242f74dSAlex Deucher track->cb[i].offset, track->maxy); 22700242f74dSAlex Deucher return -EINVAL; 22710242f74dSAlex Deucher } 22720242f74dSAlex Deucher } 22730242f74dSAlex Deucher track->cb_dirty = false; 22740242f74dSAlex Deucher 22750242f74dSAlex Deucher if (track->zb_dirty && track->z_enabled) { 22760242f74dSAlex Deucher if (track->zb.robj == NULL) { 22770242f74dSAlex Deucher DRM_ERROR("[drm] No buffer for z buffer !\n"); 22780242f74dSAlex Deucher return -EINVAL; 22790242f74dSAlex Deucher } 22800242f74dSAlex Deucher size = track->zb.pitch * track->zb.cpp * track->maxy; 22810242f74dSAlex Deucher size += track->zb.offset; 22820242f74dSAlex Deucher if (size > radeon_bo_size(track->zb.robj)) { 22830242f74dSAlex Deucher DRM_ERROR("[drm] Buffer too small for z buffer " 22840242f74dSAlex Deucher "(need %lu have %lu) !\n", size, 22850242f74dSAlex Deucher radeon_bo_size(track->zb.robj)); 22860242f74dSAlex Deucher DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", 22870242f74dSAlex Deucher track->zb.pitch, track->zb.cpp, 22880242f74dSAlex Deucher track->zb.offset, track->maxy); 22890242f74dSAlex Deucher return -EINVAL; 22900242f74dSAlex Deucher } 22910242f74dSAlex Deucher } 22920242f74dSAlex Deucher track->zb_dirty = false; 22930242f74dSAlex Deucher 22940242f74dSAlex Deucher if (track->aa_dirty && track->aaresolve) { 22950242f74dSAlex Deucher if (track->aa.robj == NULL) { 22960242f74dSAlex Deucher DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i); 22970242f74dSAlex Deucher return -EINVAL; 22980242f74dSAlex Deucher } 22990242f74dSAlex Deucher /* I believe the format comes from colorbuffer0. */ 23000242f74dSAlex Deucher size = track->aa.pitch * track->cb[0].cpp * track->maxy; 23010242f74dSAlex Deucher size += track->aa.offset; 23020242f74dSAlex Deucher if (size > radeon_bo_size(track->aa.robj)) { 23030242f74dSAlex Deucher DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d " 23040242f74dSAlex Deucher "(need %lu have %lu) !\n", i, size, 23050242f74dSAlex Deucher radeon_bo_size(track->aa.robj)); 23060242f74dSAlex Deucher DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n", 23070242f74dSAlex Deucher i, track->aa.pitch, track->cb[0].cpp, 23080242f74dSAlex Deucher track->aa.offset, track->maxy); 23090242f74dSAlex Deucher return -EINVAL; 23100242f74dSAlex Deucher } 23110242f74dSAlex Deucher } 23120242f74dSAlex Deucher track->aa_dirty = false; 23130242f74dSAlex Deucher 23140242f74dSAlex Deucher prim_walk = (track->vap_vf_cntl >> 4) & 0x3; 23150242f74dSAlex Deucher if (track->vap_vf_cntl & (1 << 14)) { 23160242f74dSAlex Deucher nverts = track->vap_alt_nverts; 23170242f74dSAlex Deucher } else { 23180242f74dSAlex Deucher nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; 23190242f74dSAlex Deucher } 23200242f74dSAlex Deucher switch (prim_walk) { 23210242f74dSAlex Deucher case 1: 23220242f74dSAlex Deucher for (i = 0; i < track->num_arrays; i++) { 23230242f74dSAlex Deucher size = track->arrays[i].esize * track->max_indx * 4; 23240242f74dSAlex Deucher if (track->arrays[i].robj == NULL) { 23250242f74dSAlex Deucher DRM_ERROR("(PW %u) Vertex array %u no buffer " 23260242f74dSAlex Deucher "bound\n", prim_walk, i); 23270242f74dSAlex Deucher return -EINVAL; 23280242f74dSAlex Deucher } 23290242f74dSAlex Deucher if (size > radeon_bo_size(track->arrays[i].robj)) { 23300242f74dSAlex Deucher dev_err(rdev->dev, "(PW %u) Vertex array %u " 23310242f74dSAlex Deucher "need %lu dwords have %lu dwords\n", 23320242f74dSAlex Deucher prim_walk, i, size >> 2, 23330242f74dSAlex Deucher radeon_bo_size(track->arrays[i].robj) 23340242f74dSAlex Deucher >> 2); 23350242f74dSAlex Deucher DRM_ERROR("Max indices %u\n", track->max_indx); 23360242f74dSAlex Deucher return -EINVAL; 23370242f74dSAlex Deucher } 23380242f74dSAlex Deucher } 23390242f74dSAlex Deucher break; 23400242f74dSAlex Deucher case 2: 23410242f74dSAlex Deucher for (i = 0; i < track->num_arrays; i++) { 23420242f74dSAlex Deucher size = track->arrays[i].esize * (nverts - 1) * 4; 23430242f74dSAlex Deucher if (track->arrays[i].robj == NULL) { 23440242f74dSAlex Deucher DRM_ERROR("(PW %u) Vertex array %u no buffer " 23450242f74dSAlex Deucher "bound\n", prim_walk, i); 23460242f74dSAlex Deucher return -EINVAL; 23470242f74dSAlex Deucher } 23480242f74dSAlex Deucher if (size > radeon_bo_size(track->arrays[i].robj)) { 23490242f74dSAlex Deucher dev_err(rdev->dev, "(PW %u) Vertex array %u " 23500242f74dSAlex Deucher "need %lu dwords have %lu dwords\n", 23510242f74dSAlex Deucher prim_walk, i, size >> 2, 23520242f74dSAlex Deucher radeon_bo_size(track->arrays[i].robj) 23530242f74dSAlex Deucher >> 2); 23540242f74dSAlex Deucher return -EINVAL; 23550242f74dSAlex Deucher } 23560242f74dSAlex Deucher } 23570242f74dSAlex Deucher break; 23580242f74dSAlex Deucher case 3: 23590242f74dSAlex Deucher size = track->vtx_size * nverts; 23600242f74dSAlex Deucher if (size != track->immd_dwords) { 23610242f74dSAlex Deucher DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", 23620242f74dSAlex Deucher track->immd_dwords, size); 23630242f74dSAlex Deucher DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", 23640242f74dSAlex Deucher nverts, track->vtx_size); 23650242f74dSAlex Deucher return -EINVAL; 23660242f74dSAlex Deucher } 23670242f74dSAlex Deucher break; 23680242f74dSAlex Deucher default: 23690242f74dSAlex Deucher DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", 23700242f74dSAlex Deucher prim_walk); 23710242f74dSAlex Deucher return -EINVAL; 23720242f74dSAlex Deucher } 23730242f74dSAlex Deucher 23740242f74dSAlex Deucher if (track->tex_dirty) { 23750242f74dSAlex Deucher track->tex_dirty = false; 23760242f74dSAlex Deucher return r100_cs_track_texture_check(rdev, track); 23770242f74dSAlex Deucher } 23780242f74dSAlex Deucher return 0; 23790242f74dSAlex Deucher } 23800242f74dSAlex Deucher 23810242f74dSAlex Deucher void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) 23820242f74dSAlex Deucher { 23830242f74dSAlex Deucher unsigned i, face; 23840242f74dSAlex Deucher 23850242f74dSAlex Deucher track->cb_dirty = true; 23860242f74dSAlex Deucher track->zb_dirty = true; 23870242f74dSAlex Deucher track->tex_dirty = true; 23880242f74dSAlex Deucher track->aa_dirty = true; 23890242f74dSAlex Deucher 23900242f74dSAlex Deucher if (rdev->family < CHIP_R300) { 23910242f74dSAlex Deucher track->num_cb = 1; 23920242f74dSAlex Deucher if (rdev->family <= CHIP_RS200) 23930242f74dSAlex Deucher track->num_texture = 3; 23940242f74dSAlex Deucher else 23950242f74dSAlex Deucher track->num_texture = 6; 23960242f74dSAlex Deucher track->maxy = 2048; 23977bf2f607Szhengbin track->separate_cube = true; 23980242f74dSAlex Deucher } else { 23990242f74dSAlex Deucher track->num_cb = 4; 24000242f74dSAlex Deucher track->num_texture = 16; 24010242f74dSAlex Deucher track->maxy = 4096; 24027bf2f607Szhengbin track->separate_cube = false; 24030242f74dSAlex Deucher track->aaresolve = false; 24040242f74dSAlex Deucher track->aa.robj = NULL; 24050242f74dSAlex Deucher } 24060242f74dSAlex Deucher 24070242f74dSAlex Deucher for (i = 0; i < track->num_cb; i++) { 24080242f74dSAlex Deucher track->cb[i].robj = NULL; 24090242f74dSAlex Deucher track->cb[i].pitch = 8192; 24100242f74dSAlex Deucher track->cb[i].cpp = 16; 24110242f74dSAlex Deucher track->cb[i].offset = 0; 24120242f74dSAlex Deucher } 24130242f74dSAlex Deucher track->z_enabled = true; 24140242f74dSAlex Deucher track->zb.robj = NULL; 24150242f74dSAlex Deucher track->zb.pitch = 8192; 24160242f74dSAlex Deucher track->zb.cpp = 4; 24170242f74dSAlex Deucher track->zb.offset = 0; 24180242f74dSAlex Deucher track->vtx_size = 0x7F; 24190242f74dSAlex Deucher track->immd_dwords = 0xFFFFFFFFUL; 24200242f74dSAlex Deucher track->num_arrays = 11; 24210242f74dSAlex Deucher track->max_indx = 0x00FFFFFFUL; 24220242f74dSAlex Deucher for (i = 0; i < track->num_arrays; i++) { 24230242f74dSAlex Deucher track->arrays[i].robj = NULL; 24240242f74dSAlex Deucher track->arrays[i].esize = 0x7F; 24250242f74dSAlex Deucher } 24260242f74dSAlex Deucher for (i = 0; i < track->num_texture; i++) { 24270242f74dSAlex Deucher track->textures[i].compress_format = R100_TRACK_COMP_NONE; 24280242f74dSAlex Deucher track->textures[i].pitch = 16536; 24290242f74dSAlex Deucher track->textures[i].width = 16536; 24300242f74dSAlex Deucher track->textures[i].height = 16536; 24310242f74dSAlex Deucher track->textures[i].width_11 = 1 << 11; 24320242f74dSAlex Deucher track->textures[i].height_11 = 1 << 11; 24330242f74dSAlex Deucher track->textures[i].num_levels = 12; 24340242f74dSAlex Deucher if (rdev->family <= CHIP_RS200) { 24350242f74dSAlex Deucher track->textures[i].tex_coord_type = 0; 24360242f74dSAlex Deucher track->textures[i].txdepth = 0; 24370242f74dSAlex Deucher } else { 24380242f74dSAlex Deucher track->textures[i].txdepth = 16; 24390242f74dSAlex Deucher track->textures[i].tex_coord_type = 1; 24400242f74dSAlex Deucher } 24410242f74dSAlex Deucher track->textures[i].cpp = 64; 24420242f74dSAlex Deucher track->textures[i].robj = NULL; 24430242f74dSAlex Deucher /* CS IB emission code makes sure texture unit are disabled */ 24440242f74dSAlex Deucher track->textures[i].enabled = false; 24450242f74dSAlex Deucher track->textures[i].lookup_disable = false; 24460242f74dSAlex Deucher track->textures[i].roundup_w = true; 24470242f74dSAlex Deucher track->textures[i].roundup_h = true; 24480242f74dSAlex Deucher if (track->separate_cube) 24490242f74dSAlex Deucher for (face = 0; face < 5; face++) { 24500242f74dSAlex Deucher track->textures[i].cube_info[face].robj = NULL; 24510242f74dSAlex Deucher track->textures[i].cube_info[face].width = 16536; 24520242f74dSAlex Deucher track->textures[i].cube_info[face].height = 16536; 24530242f74dSAlex Deucher track->textures[i].cube_info[face].offset = 0; 24540242f74dSAlex Deucher } 24550242f74dSAlex Deucher } 24560242f74dSAlex Deucher } 2457771fe6b9SJerome Glisse 2458771fe6b9SJerome Glisse /* 2459771fe6b9SJerome Glisse * Global GPU functions 2460771fe6b9SJerome Glisse */ 24611109ca09SLauri Kasanen static void r100_errata(struct radeon_device *rdev) 2462771fe6b9SJerome Glisse { 2463771fe6b9SJerome Glisse rdev->pll_errata = 0; 2464771fe6b9SJerome Glisse 2465771fe6b9SJerome Glisse if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { 2466771fe6b9SJerome Glisse rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; 2467771fe6b9SJerome Glisse } 2468771fe6b9SJerome Glisse 2469771fe6b9SJerome Glisse if (rdev->family == CHIP_RV100 || 2470771fe6b9SJerome Glisse rdev->family == CHIP_RS100 || 2471771fe6b9SJerome Glisse rdev->family == CHIP_RS200) { 2472771fe6b9SJerome Glisse rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; 2473771fe6b9SJerome Glisse } 2474771fe6b9SJerome Glisse } 2475771fe6b9SJerome Glisse 24761109ca09SLauri Kasanen static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) 2477771fe6b9SJerome Glisse { 2478771fe6b9SJerome Glisse unsigned i; 2479771fe6b9SJerome Glisse uint32_t tmp; 2480771fe6b9SJerome Glisse 2481771fe6b9SJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 2482771fe6b9SJerome Glisse tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; 2483771fe6b9SJerome Glisse if (tmp >= n) { 2484771fe6b9SJerome Glisse return 0; 2485771fe6b9SJerome Glisse } 24860e1a351dSSam Ravnborg udelay(1); 2487771fe6b9SJerome Glisse } 2488771fe6b9SJerome Glisse return -1; 2489771fe6b9SJerome Glisse } 2490771fe6b9SJerome Glisse 2491771fe6b9SJerome Glisse int r100_gui_wait_for_idle(struct radeon_device *rdev) 2492771fe6b9SJerome Glisse { 2493771fe6b9SJerome Glisse unsigned i; 2494771fe6b9SJerome Glisse uint32_t tmp; 2495771fe6b9SJerome Glisse 2496771fe6b9SJerome Glisse if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { 24977ca85295SJoe Perches pr_warn("radeon: wait for empty RBBM fifo failed! Bad things might happen.\n"); 2498771fe6b9SJerome Glisse } 2499771fe6b9SJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 2500771fe6b9SJerome Glisse tmp = RREG32(RADEON_RBBM_STATUS); 25014612dc97SAlex Deucher if (!(tmp & RADEON_RBBM_ACTIVE)) { 2502771fe6b9SJerome Glisse return 0; 2503771fe6b9SJerome Glisse } 25040e1a351dSSam Ravnborg udelay(1); 2505771fe6b9SJerome Glisse } 2506771fe6b9SJerome Glisse return -1; 2507771fe6b9SJerome Glisse } 2508771fe6b9SJerome Glisse 2509771fe6b9SJerome Glisse int r100_mc_wait_for_idle(struct radeon_device *rdev) 2510771fe6b9SJerome Glisse { 2511771fe6b9SJerome Glisse unsigned i; 2512771fe6b9SJerome Glisse uint32_t tmp; 2513771fe6b9SJerome Glisse 2514771fe6b9SJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 2515771fe6b9SJerome Glisse /* read MC_STATUS */ 25164612dc97SAlex Deucher tmp = RREG32(RADEON_MC_STATUS); 25174612dc97SAlex Deucher if (tmp & RADEON_MC_IDLE) { 2518771fe6b9SJerome Glisse return 0; 2519771fe6b9SJerome Glisse } 25200e1a351dSSam Ravnborg udelay(1); 2521771fe6b9SJerome Glisse } 2522771fe6b9SJerome Glisse return -1; 2523771fe6b9SJerome Glisse } 2524771fe6b9SJerome Glisse 2525e32eb50dSChristian König bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 2526771fe6b9SJerome Glisse { 2527225758d8SJerome Glisse u32 rbbm_status; 2528771fe6b9SJerome Glisse 2529225758d8SJerome Glisse rbbm_status = RREG32(R_000E40_RBBM_STATUS); 2530225758d8SJerome Glisse if (!G_000E40_GUI_ACTIVE(rbbm_status)) { 2531ff212f25SChristian König radeon_ring_lockup_update(rdev, ring); 2532225758d8SJerome Glisse return false; 2533225758d8SJerome Glisse } 2534069211e5SChristian König return radeon_ring_test_lockup(rdev, ring); 2535225758d8SJerome Glisse } 2536225758d8SJerome Glisse 253774da01dcSAlex Deucher /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 253874da01dcSAlex Deucher void r100_enable_bm(struct radeon_device *rdev) 253974da01dcSAlex Deucher { 254074da01dcSAlex Deucher uint32_t tmp; 254174da01dcSAlex Deucher /* Enable bus mastering */ 254274da01dcSAlex Deucher tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 254374da01dcSAlex Deucher WREG32(RADEON_BUS_CNTL, tmp); 254474da01dcSAlex Deucher } 254574da01dcSAlex Deucher 254690aca4d2SJerome Glisse void r100_bm_disable(struct radeon_device *rdev) 254790aca4d2SJerome Glisse { 254890aca4d2SJerome Glisse u32 tmp; 254990aca4d2SJerome Glisse 255090aca4d2SJerome Glisse /* disable bus mastering */ 255190aca4d2SJerome Glisse tmp = RREG32(R_000030_BUS_CNTL); 255290aca4d2SJerome Glisse WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044); 2553771fe6b9SJerome Glisse mdelay(1); 255490aca4d2SJerome Glisse WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042); 255590aca4d2SJerome Glisse mdelay(1); 255690aca4d2SJerome Glisse WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); 255790aca4d2SJerome Glisse tmp = RREG32(RADEON_BUS_CNTL); 255890aca4d2SJerome Glisse mdelay(1); 2559642ce525SMichel Dänzer pci_clear_master(rdev->pdev); 256090aca4d2SJerome Glisse mdelay(1); 256190aca4d2SJerome Glisse } 256290aca4d2SJerome Glisse 256371fe2899SJérome Glisse int r100_asic_reset(struct radeon_device *rdev, bool hard) 2564771fe6b9SJerome Glisse { 256590aca4d2SJerome Glisse struct r100_mc_save save; 256690aca4d2SJerome Glisse u32 status, tmp; 256725b2ec5bSAlex Deucher int ret = 0; 2568771fe6b9SJerome Glisse 256990aca4d2SJerome Glisse status = RREG32(R_000E40_RBBM_STATUS); 257090aca4d2SJerome Glisse if (!G_000E40_GUI_ACTIVE(status)) { 2571771fe6b9SJerome Glisse return 0; 2572771fe6b9SJerome Glisse } 257325b2ec5bSAlex Deucher r100_mc_stop(rdev, &save); 257490aca4d2SJerome Glisse status = RREG32(R_000E40_RBBM_STATUS); 257590aca4d2SJerome Glisse dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 257690aca4d2SJerome Glisse /* stop CP */ 257790aca4d2SJerome Glisse WREG32(RADEON_CP_CSQ_CNTL, 0); 257890aca4d2SJerome Glisse tmp = RREG32(RADEON_CP_RB_CNTL); 257990aca4d2SJerome Glisse WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 258090aca4d2SJerome Glisse WREG32(RADEON_CP_RB_RPTR_WR, 0); 258190aca4d2SJerome Glisse WREG32(RADEON_CP_RB_WPTR, 0); 258290aca4d2SJerome Glisse WREG32(RADEON_CP_RB_CNTL, tmp); 258390aca4d2SJerome Glisse /* save PCI state */ 258490aca4d2SJerome Glisse pci_save_state(rdev->pdev); 258590aca4d2SJerome Glisse /* disable bus mastering */ 258690aca4d2SJerome Glisse r100_bm_disable(rdev); 258790aca4d2SJerome Glisse WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) | 258890aca4d2SJerome Glisse S_0000F0_SOFT_RESET_RE(1) | 258990aca4d2SJerome Glisse S_0000F0_SOFT_RESET_PP(1) | 259090aca4d2SJerome Glisse S_0000F0_SOFT_RESET_RB(1)); 259190aca4d2SJerome Glisse RREG32(R_0000F0_RBBM_SOFT_RESET); 259290aca4d2SJerome Glisse mdelay(500); 259390aca4d2SJerome Glisse WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 259490aca4d2SJerome Glisse mdelay(1); 259590aca4d2SJerome Glisse status = RREG32(R_000E40_RBBM_STATUS); 259690aca4d2SJerome Glisse dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2597771fe6b9SJerome Glisse /* reset CP */ 259890aca4d2SJerome Glisse WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 259990aca4d2SJerome Glisse RREG32(R_0000F0_RBBM_SOFT_RESET); 260090aca4d2SJerome Glisse mdelay(500); 260190aca4d2SJerome Glisse WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 260290aca4d2SJerome Glisse mdelay(1); 260390aca4d2SJerome Glisse status = RREG32(R_000E40_RBBM_STATUS); 260490aca4d2SJerome Glisse dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 260590aca4d2SJerome Glisse /* restore PCI & busmastering */ 260690aca4d2SJerome Glisse pci_restore_state(rdev->pdev); 260790aca4d2SJerome Glisse r100_enable_bm(rdev); 2608771fe6b9SJerome Glisse /* Check if GPU is idle */ 260990aca4d2SJerome Glisse if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) || 261090aca4d2SJerome Glisse G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) { 261190aca4d2SJerome Glisse dev_err(rdev->dev, "failed to reset GPU\n"); 261225b2ec5bSAlex Deucher ret = -1; 261325b2ec5bSAlex Deucher } else 261490aca4d2SJerome Glisse dev_info(rdev->dev, "GPU reset succeed\n"); 261525b2ec5bSAlex Deucher r100_mc_resume(rdev, &save); 261625b2ec5bSAlex Deucher return ret; 2617771fe6b9SJerome Glisse } 2618771fe6b9SJerome Glisse 261992cde00cSAlex Deucher void r100_set_common_regs(struct radeon_device *rdev) 262092cde00cSAlex Deucher { 26212739d49cSAlex Deucher bool force_dac2 = false; 2622d668046cSDave Airlie u32 tmp; 26232739d49cSAlex Deucher 262492cde00cSAlex Deucher /* set these so they don't interfere with anything */ 262592cde00cSAlex Deucher WREG32(RADEON_OV0_SCALE_CNTL, 0); 262692cde00cSAlex Deucher WREG32(RADEON_SUBPIC_CNTL, 0); 262792cde00cSAlex Deucher WREG32(RADEON_VIPH_CONTROL, 0); 262892cde00cSAlex Deucher WREG32(RADEON_I2C_CNTL_1, 0); 262992cde00cSAlex Deucher WREG32(RADEON_DVI_I2C_CNTL_1, 0); 263092cde00cSAlex Deucher WREG32(RADEON_CAP0_TRIG_CNTL, 0); 263192cde00cSAlex Deucher WREG32(RADEON_CAP1_TRIG_CNTL, 0); 26322739d49cSAlex Deucher 26332739d49cSAlex Deucher /* always set up dac2 on rn50 and some rv100 as lots 26342739d49cSAlex Deucher * of servers seem to wire it up to a VGA port but 26352739d49cSAlex Deucher * don't report it in the bios connector 26362739d49cSAlex Deucher * table. 26372739d49cSAlex Deucher */ 2638d86a4126SThomas Zimmermann switch (rdev->pdev->device) { 26392739d49cSAlex Deucher /* RN50 */ 26402739d49cSAlex Deucher case 0x515e: 26412739d49cSAlex Deucher case 0x5969: 26422739d49cSAlex Deucher force_dac2 = true; 26432739d49cSAlex Deucher break; 26442739d49cSAlex Deucher /* RV100*/ 26452739d49cSAlex Deucher case 0x5159: 26462739d49cSAlex Deucher case 0x515a: 26472739d49cSAlex Deucher /* DELL triple head servers */ 2648d86a4126SThomas Zimmermann if ((rdev->pdev->subsystem_vendor == 0x1028 /* DELL */) && 2649d86a4126SThomas Zimmermann ((rdev->pdev->subsystem_device == 0x016c) || 2650d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x016d) || 2651d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x016e) || 2652d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x016f) || 2653d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x0170) || 2654d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x017d) || 2655d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x017e) || 2656d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x0183) || 2657d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x018a) || 2658d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x019a))) 26592739d49cSAlex Deucher force_dac2 = true; 26602739d49cSAlex Deucher break; 26612739d49cSAlex Deucher } 26622739d49cSAlex Deucher 26632739d49cSAlex Deucher if (force_dac2) { 26642739d49cSAlex Deucher u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 26652739d49cSAlex Deucher u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 26662739d49cSAlex Deucher u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 26672739d49cSAlex Deucher 26682739d49cSAlex Deucher /* For CRT on DAC2, don't turn it on if BIOS didn't 26692739d49cSAlex Deucher enable it, even it's detected. 26702739d49cSAlex Deucher */ 26712739d49cSAlex Deucher 26722739d49cSAlex Deucher /* force it to crtc0 */ 26732739d49cSAlex Deucher dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; 26742739d49cSAlex Deucher dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; 26752739d49cSAlex Deucher disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 26762739d49cSAlex Deucher 26772739d49cSAlex Deucher /* set up the TV DAC */ 26782739d49cSAlex Deucher tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL | 26792739d49cSAlex Deucher RADEON_TV_DAC_STD_MASK | 26802739d49cSAlex Deucher RADEON_TV_DAC_RDACPD | 26812739d49cSAlex Deucher RADEON_TV_DAC_GDACPD | 26822739d49cSAlex Deucher RADEON_TV_DAC_BDACPD | 26832739d49cSAlex Deucher RADEON_TV_DAC_BGADJ_MASK | 26842739d49cSAlex Deucher RADEON_TV_DAC_DACADJ_MASK); 26852739d49cSAlex Deucher tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | 26862739d49cSAlex Deucher RADEON_TV_DAC_NHOLD | 26872739d49cSAlex Deucher RADEON_TV_DAC_STD_PS2 | 26882739d49cSAlex Deucher (0x58 << 16)); 26892739d49cSAlex Deucher 26902739d49cSAlex Deucher WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 26912739d49cSAlex Deucher WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 26922739d49cSAlex Deucher WREG32(RADEON_DAC_CNTL2, dac2_cntl); 26932739d49cSAlex Deucher } 2694d668046cSDave Airlie 2695d668046cSDave Airlie /* switch PM block to ACPI mode */ 2696d668046cSDave Airlie tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); 2697d668046cSDave Airlie tmp &= ~RADEON_PM_MODE_SEL; 2698d668046cSDave Airlie WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); 2699d668046cSDave Airlie 270092cde00cSAlex Deucher } 2701771fe6b9SJerome Glisse 2702771fe6b9SJerome Glisse /* 2703771fe6b9SJerome Glisse * VRAM info 2704771fe6b9SJerome Glisse */ 2705771fe6b9SJerome Glisse static void r100_vram_get_type(struct radeon_device *rdev) 2706771fe6b9SJerome Glisse { 2707771fe6b9SJerome Glisse uint32_t tmp; 2708771fe6b9SJerome Glisse 2709771fe6b9SJerome Glisse rdev->mc.vram_is_ddr = false; 2710771fe6b9SJerome Glisse if (rdev->flags & RADEON_IS_IGP) 2711771fe6b9SJerome Glisse rdev->mc.vram_is_ddr = true; 2712771fe6b9SJerome Glisse else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) 2713771fe6b9SJerome Glisse rdev->mc.vram_is_ddr = true; 2714771fe6b9SJerome Glisse if ((rdev->family == CHIP_RV100) || 2715771fe6b9SJerome Glisse (rdev->family == CHIP_RS100) || 2716771fe6b9SJerome Glisse (rdev->family == CHIP_RS200)) { 2717771fe6b9SJerome Glisse tmp = RREG32(RADEON_MEM_CNTL); 2718771fe6b9SJerome Glisse if (tmp & RV100_HALF_MODE) { 2719771fe6b9SJerome Glisse rdev->mc.vram_width = 32; 2720771fe6b9SJerome Glisse } else { 2721771fe6b9SJerome Glisse rdev->mc.vram_width = 64; 2722771fe6b9SJerome Glisse } 2723771fe6b9SJerome Glisse if (rdev->flags & RADEON_SINGLE_CRTC) { 2724771fe6b9SJerome Glisse rdev->mc.vram_width /= 4; 2725771fe6b9SJerome Glisse rdev->mc.vram_is_ddr = true; 2726771fe6b9SJerome Glisse } 2727771fe6b9SJerome Glisse } else if (rdev->family <= CHIP_RV280) { 2728771fe6b9SJerome Glisse tmp = RREG32(RADEON_MEM_CNTL); 2729771fe6b9SJerome Glisse if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { 2730771fe6b9SJerome Glisse rdev->mc.vram_width = 128; 2731771fe6b9SJerome Glisse } else { 2732771fe6b9SJerome Glisse rdev->mc.vram_width = 64; 2733771fe6b9SJerome Glisse } 2734771fe6b9SJerome Glisse } else { 2735771fe6b9SJerome Glisse /* newer IGPs */ 2736771fe6b9SJerome Glisse rdev->mc.vram_width = 128; 2737771fe6b9SJerome Glisse } 2738771fe6b9SJerome Glisse } 2739771fe6b9SJerome Glisse 27402a0f8918SDave Airlie static u32 r100_get_accessible_vram(struct radeon_device *rdev) 2741771fe6b9SJerome Glisse { 27422a0f8918SDave Airlie u32 aper_size; 27432a0f8918SDave Airlie u8 byte; 27442a0f8918SDave Airlie 27452a0f8918SDave Airlie aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 27462a0f8918SDave Airlie 27472a0f8918SDave Airlie /* Set HDP_APER_CNTL only on cards that are known not to be broken, 27482a0f8918SDave Airlie * that is has the 2nd generation multifunction PCI interface 27492a0f8918SDave Airlie */ 27502a0f8918SDave Airlie if (rdev->family == CHIP_RV280 || 27512a0f8918SDave Airlie rdev->family >= CHIP_RV350) { 27522a0f8918SDave Airlie WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, 27532a0f8918SDave Airlie ~RADEON_HDP_APER_CNTL); 27542a0f8918SDave Airlie DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); 27552a0f8918SDave Airlie return aper_size * 2; 27562a0f8918SDave Airlie } 27572a0f8918SDave Airlie 27582a0f8918SDave Airlie /* Older cards have all sorts of funny issues to deal with. First 27592a0f8918SDave Airlie * check if it's a multifunction card by reading the PCI config 27602a0f8918SDave Airlie * header type... Limit those to one aperture size 27612a0f8918SDave Airlie */ 27622a0f8918SDave Airlie pci_read_config_byte(rdev->pdev, 0xe, &byte); 27632a0f8918SDave Airlie if (byte & 0x80) { 27642a0f8918SDave Airlie DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); 27652a0f8918SDave Airlie DRM_INFO("Limiting VRAM to one aperture\n"); 27662a0f8918SDave Airlie return aper_size; 27672a0f8918SDave Airlie } 27682a0f8918SDave Airlie 27692a0f8918SDave Airlie /* Single function older card. We read HDP_APER_CNTL to see how the BIOS 27702a0f8918SDave Airlie * have set it up. We don't write this as it's broken on some ASICs but 27712a0f8918SDave Airlie * we expect the BIOS to have done the right thing (might be too optimistic...) 27722a0f8918SDave Airlie */ 27732a0f8918SDave Airlie if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) 27742a0f8918SDave Airlie return aper_size * 2; 27752a0f8918SDave Airlie return aper_size; 27762a0f8918SDave Airlie } 27772a0f8918SDave Airlie 27782a0f8918SDave Airlie void r100_vram_init_sizes(struct radeon_device *rdev) 27792a0f8918SDave Airlie { 27802a0f8918SDave Airlie u64 config_aper_size; 27812a0f8918SDave Airlie 2782d594e46aSJerome Glisse /* work out accessible VRAM */ 278301d73a69SJordan Crouse rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 278401d73a69SJordan Crouse rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 278551e5fcd3SJerome Glisse rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); 278651e5fcd3SJerome Glisse /* FIXME we don't use the second aperture yet when we could use it */ 278751e5fcd3SJerome Glisse if (rdev->mc.visible_vram_size > rdev->mc.aper_size) 278851e5fcd3SJerome Glisse rdev->mc.visible_vram_size = rdev->mc.aper_size; 27892a0f8918SDave Airlie config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2790771fe6b9SJerome Glisse if (rdev->flags & RADEON_IS_IGP) { 2791771fe6b9SJerome Glisse uint32_t tom; 2792771fe6b9SJerome Glisse /* read NB_TOM to get the amount of ram stolen for the GPU */ 2793771fe6b9SJerome Glisse tom = RREG32(RADEON_NB_TOM); 27947a50f01aSDave Airlie rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); 27957a50f01aSDave Airlie WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 27967a50f01aSDave Airlie rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2797771fe6b9SJerome Glisse } else { 27987a50f01aSDave Airlie rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 2799771fe6b9SJerome Glisse /* Some production boards of m6 will report 0 2800771fe6b9SJerome Glisse * if it's 8 MB 2801771fe6b9SJerome Glisse */ 28027a50f01aSDave Airlie if (rdev->mc.real_vram_size == 0) { 28037a50f01aSDave Airlie rdev->mc.real_vram_size = 8192 * 1024; 28047a50f01aSDave Airlie WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2805771fe6b9SJerome Glisse } 28062a0f8918SDave Airlie /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 2807d594e46aSJerome Glisse * Novell bug 204882 + along with lots of ubuntu ones 2808d594e46aSJerome Glisse */ 2809b7d8cce5SAlex Deucher if (rdev->mc.aper_size > config_aper_size) 2810b7d8cce5SAlex Deucher config_aper_size = rdev->mc.aper_size; 2811b7d8cce5SAlex Deucher 28127a50f01aSDave Airlie if (config_aper_size > rdev->mc.real_vram_size) 28137a50f01aSDave Airlie rdev->mc.mc_vram_size = config_aper_size; 28147a50f01aSDave Airlie else 28157a50f01aSDave Airlie rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2816771fe6b9SJerome Glisse } 2817d594e46aSJerome Glisse } 28182a0f8918SDave Airlie 281928d52043SDave Airlie void r100_vga_set_state(struct radeon_device *rdev, bool state) 282028d52043SDave Airlie { 282128d52043SDave Airlie uint32_t temp; 282228d52043SDave Airlie 282328d52043SDave Airlie temp = RREG32(RADEON_CONFIG_CNTL); 2824fbd62354SWambui Karuga if (!state) { 2825d75ee3beSAlex Deucher temp &= ~RADEON_CFG_VGA_RAM_EN; 2826d75ee3beSAlex Deucher temp |= RADEON_CFG_VGA_IO_DIS; 282728d52043SDave Airlie } else { 2828d75ee3beSAlex Deucher temp &= ~RADEON_CFG_VGA_IO_DIS; 282928d52043SDave Airlie } 283028d52043SDave Airlie WREG32(RADEON_CONFIG_CNTL, temp); 283128d52043SDave Airlie } 283228d52043SDave Airlie 28331109ca09SLauri Kasanen static void r100_mc_init(struct radeon_device *rdev) 28342a0f8918SDave Airlie { 2835d594e46aSJerome Glisse u64 base; 28362a0f8918SDave Airlie 2837d594e46aSJerome Glisse r100_vram_get_type(rdev); 28382a0f8918SDave Airlie r100_vram_init_sizes(rdev); 2839d594e46aSJerome Glisse base = rdev->mc.aper_base; 2840d594e46aSJerome Glisse if (rdev->flags & RADEON_IS_IGP) 2841d594e46aSJerome Glisse base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 2842d594e46aSJerome Glisse radeon_vram_location(rdev, &rdev->mc, base); 28438d369bb1SAlex Deucher rdev->mc.gtt_base_align = 0; 2844d594e46aSJerome Glisse if (!(rdev->flags & RADEON_IS_AGP)) 2845d594e46aSJerome Glisse radeon_gtt_location(rdev, &rdev->mc); 2846f47299c5SAlex Deucher radeon_update_bandwidth_info(rdev); 2847771fe6b9SJerome Glisse } 2848771fe6b9SJerome Glisse 2849771fe6b9SJerome Glisse 2850771fe6b9SJerome Glisse /* 2851771fe6b9SJerome Glisse * Indirect registers accessor 2852771fe6b9SJerome Glisse */ 2853771fe6b9SJerome Glisse void r100_pll_errata_after_index(struct radeon_device *rdev) 2854771fe6b9SJerome Glisse { 28554ce9198eSAlex Deucher if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) { 2856771fe6b9SJerome Glisse (void)RREG32(RADEON_CLOCK_CNTL_DATA); 2857771fe6b9SJerome Glisse (void)RREG32(RADEON_CRTC_GEN_CNTL); 2858771fe6b9SJerome Glisse } 28594ce9198eSAlex Deucher } 2860771fe6b9SJerome Glisse 2861771fe6b9SJerome Glisse static void r100_pll_errata_after_data(struct radeon_device *rdev) 2862771fe6b9SJerome Glisse { 2863771fe6b9SJerome Glisse /* This workarounds is necessary on RV100, RS100 and RS200 chips 2864771fe6b9SJerome Glisse * or the chip could hang on a subsequent access 2865771fe6b9SJerome Glisse */ 2866771fe6b9SJerome Glisse if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { 28674de833c3SArnd Bergmann mdelay(5); 2868771fe6b9SJerome Glisse } 2869771fe6b9SJerome Glisse 2870771fe6b9SJerome Glisse /* This function is required to workaround a hardware bug in some (all?) 2871771fe6b9SJerome Glisse * revisions of the R300. This workaround should be called after every 2872771fe6b9SJerome Glisse * CLOCK_CNTL_INDEX register access. If not, register reads afterward 2873771fe6b9SJerome Glisse * may not be correct. 2874771fe6b9SJerome Glisse */ 2875771fe6b9SJerome Glisse if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { 2876771fe6b9SJerome Glisse uint32_t save, tmp; 2877771fe6b9SJerome Glisse 2878771fe6b9SJerome Glisse save = RREG32(RADEON_CLOCK_CNTL_INDEX); 2879771fe6b9SJerome Glisse tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2880771fe6b9SJerome Glisse WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); 2881771fe6b9SJerome Glisse tmp = RREG32(RADEON_CLOCK_CNTL_DATA); 2882771fe6b9SJerome Glisse WREG32(RADEON_CLOCK_CNTL_INDEX, save); 2883771fe6b9SJerome Glisse } 2884771fe6b9SJerome Glisse } 2885771fe6b9SJerome Glisse 2886771fe6b9SJerome Glisse uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) 2887771fe6b9SJerome Glisse { 28880a5b7b0bSAlex Deucher unsigned long flags; 2889771fe6b9SJerome Glisse uint32_t data; 2890771fe6b9SJerome Glisse 28910a5b7b0bSAlex Deucher spin_lock_irqsave(&rdev->pll_idx_lock, flags); 2892771fe6b9SJerome Glisse WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); 2893771fe6b9SJerome Glisse r100_pll_errata_after_index(rdev); 2894771fe6b9SJerome Glisse data = RREG32(RADEON_CLOCK_CNTL_DATA); 2895771fe6b9SJerome Glisse r100_pll_errata_after_data(rdev); 28960a5b7b0bSAlex Deucher spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); 2897771fe6b9SJerome Glisse return data; 2898771fe6b9SJerome Glisse } 2899771fe6b9SJerome Glisse 2900771fe6b9SJerome Glisse void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2901771fe6b9SJerome Glisse { 29020a5b7b0bSAlex Deucher unsigned long flags; 29030a5b7b0bSAlex Deucher 29040a5b7b0bSAlex Deucher spin_lock_irqsave(&rdev->pll_idx_lock, flags); 2905771fe6b9SJerome Glisse WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); 2906771fe6b9SJerome Glisse r100_pll_errata_after_index(rdev); 2907771fe6b9SJerome Glisse WREG32(RADEON_CLOCK_CNTL_DATA, v); 2908771fe6b9SJerome Glisse r100_pll_errata_after_data(rdev); 29090a5b7b0bSAlex Deucher spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); 2910771fe6b9SJerome Glisse } 2911771fe6b9SJerome Glisse 29121109ca09SLauri Kasanen static void r100_set_safe_registers(struct radeon_device *rdev) 2913068a117cSJerome Glisse { 2914551ebd83SDave Airlie if (ASIC_IS_RN50(rdev)) { 2915551ebd83SDave Airlie rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; 2916551ebd83SDave Airlie rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); 2917551ebd83SDave Airlie } else if (rdev->family < CHIP_R200) { 2918551ebd83SDave Airlie rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; 2919551ebd83SDave Airlie rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); 2920551ebd83SDave Airlie } else { 2921d4550907SJerome Glisse r200_set_safe_registers(rdev); 2922551ebd83SDave Airlie } 2923068a117cSJerome Glisse } 2924068a117cSJerome Glisse 2925771fe6b9SJerome Glisse /* 2926771fe6b9SJerome Glisse * Debugfs info 2927771fe6b9SJerome Glisse */ 2928771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS) 29295b54d679SNirmoy Das static int r100_debugfs_rbbm_info_show(struct seq_file *m, void *unused) 2930771fe6b9SJerome Glisse { 29315b54d679SNirmoy Das struct radeon_device *rdev = (struct radeon_device *)m->private; 2932771fe6b9SJerome Glisse uint32_t reg, value; 2933771fe6b9SJerome Glisse unsigned i; 2934771fe6b9SJerome Glisse 2935771fe6b9SJerome Glisse seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); 2936771fe6b9SJerome Glisse seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); 2937771fe6b9SJerome Glisse seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2938771fe6b9SJerome Glisse for (i = 0; i < 64; i++) { 2939771fe6b9SJerome Glisse WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); 2940771fe6b9SJerome Glisse reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; 2941771fe6b9SJerome Glisse WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); 2942771fe6b9SJerome Glisse value = RREG32(RADEON_RBBM_CMDFIFO_DATA); 2943771fe6b9SJerome Glisse seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); 2944771fe6b9SJerome Glisse } 2945771fe6b9SJerome Glisse return 0; 2946771fe6b9SJerome Glisse } 2947771fe6b9SJerome Glisse 29485b54d679SNirmoy Das static int r100_debugfs_cp_ring_info_show(struct seq_file *m, void *unused) 2949771fe6b9SJerome Glisse { 29505b54d679SNirmoy Das struct radeon_device *rdev = (struct radeon_device *)m->private; 2951e32eb50dSChristian König struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2952771fe6b9SJerome Glisse uint32_t rdp, wdp; 2953771fe6b9SJerome Glisse unsigned count, i, j; 2954771fe6b9SJerome Glisse 2955e32eb50dSChristian König radeon_ring_free_size(rdev, ring); 2956771fe6b9SJerome Glisse rdp = RREG32(RADEON_CP_RB_RPTR); 2957771fe6b9SJerome Glisse wdp = RREG32(RADEON_CP_RB_WPTR); 2958e32eb50dSChristian König count = (rdp + ring->ring_size - wdp) & ring->ptr_mask; 2959771fe6b9SJerome Glisse seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2960771fe6b9SJerome Glisse seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); 2961771fe6b9SJerome Glisse seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); 2962e32eb50dSChristian König seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); 2963771fe6b9SJerome Glisse seq_printf(m, "%u dwords in ring\n", count); 29640eb3448aSAlex Ivanov if (ring->ready) { 2965771fe6b9SJerome Glisse for (j = 0; j <= count; j++) { 2966e32eb50dSChristian König i = (rdp + j) & ring->ptr_mask; 2967e32eb50dSChristian König seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); 2968771fe6b9SJerome Glisse } 29690eb3448aSAlex Ivanov } 2970771fe6b9SJerome Glisse return 0; 2971771fe6b9SJerome Glisse } 2972771fe6b9SJerome Glisse 2973771fe6b9SJerome Glisse 29745b54d679SNirmoy Das static int r100_debugfs_cp_csq_fifo_show(struct seq_file *m, void *unused) 2975771fe6b9SJerome Glisse { 29765b54d679SNirmoy Das struct radeon_device *rdev = (struct radeon_device *)m->private; 2977771fe6b9SJerome Glisse uint32_t csq_stat, csq2_stat, tmp; 2978771fe6b9SJerome Glisse unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; 2979771fe6b9SJerome Glisse unsigned i; 2980771fe6b9SJerome Glisse 2981771fe6b9SJerome Glisse seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2982771fe6b9SJerome Glisse seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); 2983771fe6b9SJerome Glisse csq_stat = RREG32(RADEON_CP_CSQ_STAT); 2984771fe6b9SJerome Glisse csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); 2985771fe6b9SJerome Glisse r_rptr = (csq_stat >> 0) & 0x3ff; 2986771fe6b9SJerome Glisse r_wptr = (csq_stat >> 10) & 0x3ff; 2987771fe6b9SJerome Glisse ib1_rptr = (csq_stat >> 20) & 0x3ff; 2988771fe6b9SJerome Glisse ib1_wptr = (csq2_stat >> 0) & 0x3ff; 2989771fe6b9SJerome Glisse ib2_rptr = (csq2_stat >> 10) & 0x3ff; 2990771fe6b9SJerome Glisse ib2_wptr = (csq2_stat >> 20) & 0x3ff; 2991771fe6b9SJerome Glisse seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); 2992771fe6b9SJerome Glisse seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); 2993771fe6b9SJerome Glisse seq_printf(m, "Ring rptr %u\n", r_rptr); 2994771fe6b9SJerome Glisse seq_printf(m, "Ring wptr %u\n", r_wptr); 2995771fe6b9SJerome Glisse seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); 2996771fe6b9SJerome Glisse seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); 2997771fe6b9SJerome Glisse seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); 2998771fe6b9SJerome Glisse seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); 2999771fe6b9SJerome Glisse /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms 3000771fe6b9SJerome Glisse * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ 3001771fe6b9SJerome Glisse seq_printf(m, "Ring fifo:\n"); 3002771fe6b9SJerome Glisse for (i = 0; i < 256; i++) { 3003771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_ADDR, i << 2); 3004771fe6b9SJerome Glisse tmp = RREG32(RADEON_CP_CSQ_DATA); 3005771fe6b9SJerome Glisse seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); 3006771fe6b9SJerome Glisse } 3007771fe6b9SJerome Glisse seq_printf(m, "Indirect1 fifo:\n"); 3008771fe6b9SJerome Glisse for (i = 256; i <= 512; i++) { 3009771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_ADDR, i << 2); 3010771fe6b9SJerome Glisse tmp = RREG32(RADEON_CP_CSQ_DATA); 3011771fe6b9SJerome Glisse seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); 3012771fe6b9SJerome Glisse } 3013771fe6b9SJerome Glisse seq_printf(m, "Indirect2 fifo:\n"); 3014771fe6b9SJerome Glisse for (i = 640; i < ib1_wptr; i++) { 3015771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_ADDR, i << 2); 3016771fe6b9SJerome Glisse tmp = RREG32(RADEON_CP_CSQ_DATA); 3017771fe6b9SJerome Glisse seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); 3018771fe6b9SJerome Glisse } 3019771fe6b9SJerome Glisse return 0; 3020771fe6b9SJerome Glisse } 3021771fe6b9SJerome Glisse 30225b54d679SNirmoy Das static int r100_debugfs_mc_info_show(struct seq_file *m, void *unused) 3023771fe6b9SJerome Glisse { 30245b54d679SNirmoy Das struct radeon_device *rdev = (struct radeon_device *)m->private; 3025771fe6b9SJerome Glisse uint32_t tmp; 3026771fe6b9SJerome Glisse 3027771fe6b9SJerome Glisse tmp = RREG32(RADEON_CONFIG_MEMSIZE); 3028771fe6b9SJerome Glisse seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); 3029771fe6b9SJerome Glisse tmp = RREG32(RADEON_MC_FB_LOCATION); 3030771fe6b9SJerome Glisse seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); 3031771fe6b9SJerome Glisse tmp = RREG32(RADEON_BUS_CNTL); 3032771fe6b9SJerome Glisse seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 3033771fe6b9SJerome Glisse tmp = RREG32(RADEON_MC_AGP_LOCATION); 3034771fe6b9SJerome Glisse seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 3035771fe6b9SJerome Glisse tmp = RREG32(RADEON_AGP_BASE); 3036771fe6b9SJerome Glisse seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 3037771fe6b9SJerome Glisse tmp = RREG32(RADEON_HOST_PATH_CNTL); 3038771fe6b9SJerome Glisse seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 3039771fe6b9SJerome Glisse tmp = RREG32(0x01D0); 3040771fe6b9SJerome Glisse seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); 3041771fe6b9SJerome Glisse tmp = RREG32(RADEON_AIC_LO_ADDR); 3042771fe6b9SJerome Glisse seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); 3043771fe6b9SJerome Glisse tmp = RREG32(RADEON_AIC_HI_ADDR); 3044771fe6b9SJerome Glisse seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); 3045771fe6b9SJerome Glisse tmp = RREG32(0x01E4); 3046771fe6b9SJerome Glisse seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); 3047771fe6b9SJerome Glisse return 0; 3048771fe6b9SJerome Glisse } 3049771fe6b9SJerome Glisse 30505b54d679SNirmoy Das DEFINE_SHOW_ATTRIBUTE(r100_debugfs_rbbm_info); 30515b54d679SNirmoy Das DEFINE_SHOW_ATTRIBUTE(r100_debugfs_cp_ring_info); 30525b54d679SNirmoy Das DEFINE_SHOW_ATTRIBUTE(r100_debugfs_cp_csq_fifo); 30535b54d679SNirmoy Das DEFINE_SHOW_ATTRIBUTE(r100_debugfs_mc_info); 3054771fe6b9SJerome Glisse 3055771fe6b9SJerome Glisse #endif 3056771fe6b9SJerome Glisse 30575b54d679SNirmoy Das void r100_debugfs_rbbm_init(struct radeon_device *rdev) 3058771fe6b9SJerome Glisse { 3059771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS) 30605b54d679SNirmoy Das struct dentry *root = rdev->ddev->primary->debugfs_root; 30615b54d679SNirmoy Das 30625b54d679SNirmoy Das debugfs_create_file("r100_rbbm_info", 0444, root, rdev, 30635b54d679SNirmoy Das &r100_debugfs_rbbm_info_fops); 3064771fe6b9SJerome Glisse #endif 3065771fe6b9SJerome Glisse } 3066771fe6b9SJerome Glisse 30675b54d679SNirmoy Das void r100_debugfs_cp_init(struct radeon_device *rdev) 3068771fe6b9SJerome Glisse { 3069771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS) 30705b54d679SNirmoy Das struct dentry *root = rdev->ddev->primary->debugfs_root; 30715b54d679SNirmoy Das 30725b54d679SNirmoy Das debugfs_create_file("r100_cp_ring_info", 0444, root, rdev, 30735b54d679SNirmoy Das &r100_debugfs_cp_ring_info_fops); 30745b54d679SNirmoy Das debugfs_create_file("r100_cp_csq_fifo", 0444, root, rdev, 30755b54d679SNirmoy Das &r100_debugfs_cp_csq_fifo_fops); 3076771fe6b9SJerome Glisse #endif 3077771fe6b9SJerome Glisse } 3078771fe6b9SJerome Glisse 30795b54d679SNirmoy Das void r100_debugfs_mc_info_init(struct radeon_device *rdev) 3080771fe6b9SJerome Glisse { 3081771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS) 30825b54d679SNirmoy Das struct dentry *root = rdev->ddev->primary->debugfs_root; 30835b54d679SNirmoy Das 30845b54d679SNirmoy Das debugfs_create_file("r100_mc_info", 0444, root, rdev, 30855b54d679SNirmoy Das &r100_debugfs_mc_info_fops); 3086771fe6b9SJerome Glisse #endif 3087771fe6b9SJerome Glisse } 3088e024e110SDave Airlie 3089e024e110SDave Airlie int r100_set_surface_reg(struct radeon_device *rdev, int reg, 3090e024e110SDave Airlie uint32_t tiling_flags, uint32_t pitch, 3091e024e110SDave Airlie uint32_t offset, uint32_t obj_size) 3092e024e110SDave Airlie { 3093e024e110SDave Airlie int surf_index = reg * 16; 3094e024e110SDave Airlie int flags = 0; 3095e024e110SDave Airlie 3096e024e110SDave Airlie if (rdev->family <= CHIP_RS200) { 3097e024e110SDave Airlie if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3098e024e110SDave Airlie == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3099e024e110SDave Airlie flags |= RADEON_SURF_TILE_COLOR_BOTH; 3100e024e110SDave Airlie if (tiling_flags & RADEON_TILING_MACRO) 3101e024e110SDave Airlie flags |= RADEON_SURF_TILE_COLOR_MACRO; 310267d5ced5SAlex Deucher /* setting pitch to 0 disables tiling */ 310367d5ced5SAlex Deucher if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 310467d5ced5SAlex Deucher == 0) 310567d5ced5SAlex Deucher pitch = 0; 3106e024e110SDave Airlie } else if (rdev->family <= CHIP_RV280) { 3107e024e110SDave Airlie if (tiling_flags & (RADEON_TILING_MACRO)) 3108e024e110SDave Airlie flags |= R200_SURF_TILE_COLOR_MACRO; 3109e024e110SDave Airlie if (tiling_flags & RADEON_TILING_MICRO) 3110e024e110SDave Airlie flags |= R200_SURF_TILE_COLOR_MICRO; 3111e024e110SDave Airlie } else { 3112e024e110SDave Airlie if (tiling_flags & RADEON_TILING_MACRO) 3113e024e110SDave Airlie flags |= R300_SURF_TILE_MACRO; 3114e024e110SDave Airlie if (tiling_flags & RADEON_TILING_MICRO) 3115e024e110SDave Airlie flags |= R300_SURF_TILE_MICRO; 3116e024e110SDave Airlie } 3117e024e110SDave Airlie 3118c88f9f0cSMichel Dänzer if (tiling_flags & RADEON_TILING_SWAP_16BIT) 3119c88f9f0cSMichel Dänzer flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; 3120c88f9f0cSMichel Dänzer if (tiling_flags & RADEON_TILING_SWAP_32BIT) 3121c88f9f0cSMichel Dänzer flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; 3122c88f9f0cSMichel Dänzer 3123f5c5f040SDave Airlie /* r100/r200 divide by 16 */ 3124f5c5f040SDave Airlie if (rdev->family < CHIP_R300) 3125f5c5f040SDave Airlie flags |= pitch / 16; 3126f5c5f040SDave Airlie else 3127f5c5f040SDave Airlie flags |= pitch / 8; 3128f5c5f040SDave Airlie 3129f5c5f040SDave Airlie 3130d9fdaafbSDave Airlie DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); 3131e024e110SDave Airlie WREG32(RADEON_SURFACE0_INFO + surf_index, flags); 3132e024e110SDave Airlie WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); 3133e024e110SDave Airlie WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); 3134e024e110SDave Airlie return 0; 3135e024e110SDave Airlie } 3136e024e110SDave Airlie 3137e024e110SDave Airlie void r100_clear_surface_reg(struct radeon_device *rdev, int reg) 3138e024e110SDave Airlie { 3139e024e110SDave Airlie int surf_index = reg * 16; 3140e024e110SDave Airlie WREG32(RADEON_SURFACE0_INFO + surf_index, 0); 3141e024e110SDave Airlie } 3142c93bb85bSJerome Glisse 3143c93bb85bSJerome Glisse void r100_bandwidth_update(struct radeon_device *rdev) 3144c93bb85bSJerome Glisse { 3145c93bb85bSJerome Glisse fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; 3146c93bb85bSJerome Glisse fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; 31471ef897e4STim Gardner fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff; 31481ef897e4STim Gardner fixed20_12 crit_point_ff = {0}; 3149c93bb85bSJerome Glisse uint32_t temp, data, mem_trcd, mem_trp, mem_tras; 3150c93bb85bSJerome Glisse fixed20_12 memtcas_ff[8] = { 315168adac5eSBen Skeggs dfixed_init(1), 315268adac5eSBen Skeggs dfixed_init(2), 315368adac5eSBen Skeggs dfixed_init(3), 315468adac5eSBen Skeggs dfixed_init(0), 315568adac5eSBen Skeggs dfixed_init_half(1), 315668adac5eSBen Skeggs dfixed_init_half(2), 315768adac5eSBen Skeggs dfixed_init(0), 3158c93bb85bSJerome Glisse }; 3159c93bb85bSJerome Glisse fixed20_12 memtcas_rs480_ff[8] = { 316068adac5eSBen Skeggs dfixed_init(0), 316168adac5eSBen Skeggs dfixed_init(1), 316268adac5eSBen Skeggs dfixed_init(2), 316368adac5eSBen Skeggs dfixed_init(3), 316468adac5eSBen Skeggs dfixed_init(0), 316568adac5eSBen Skeggs dfixed_init_half(1), 316668adac5eSBen Skeggs dfixed_init_half(2), 316768adac5eSBen Skeggs dfixed_init_half(3), 3168c93bb85bSJerome Glisse }; 3169c93bb85bSJerome Glisse fixed20_12 memtcas2_ff[8] = { 317068adac5eSBen Skeggs dfixed_init(0), 317168adac5eSBen Skeggs dfixed_init(1), 317268adac5eSBen Skeggs dfixed_init(2), 317368adac5eSBen Skeggs dfixed_init(3), 317468adac5eSBen Skeggs dfixed_init(4), 317568adac5eSBen Skeggs dfixed_init(5), 317668adac5eSBen Skeggs dfixed_init(6), 317768adac5eSBen Skeggs dfixed_init(7), 3178c93bb85bSJerome Glisse }; 3179c93bb85bSJerome Glisse fixed20_12 memtrbs[8] = { 318068adac5eSBen Skeggs dfixed_init(1), 318168adac5eSBen Skeggs dfixed_init_half(1), 318268adac5eSBen Skeggs dfixed_init(2), 318368adac5eSBen Skeggs dfixed_init_half(2), 318468adac5eSBen Skeggs dfixed_init(3), 318568adac5eSBen Skeggs dfixed_init_half(3), 318668adac5eSBen Skeggs dfixed_init(4), 318768adac5eSBen Skeggs dfixed_init_half(4) 3188c93bb85bSJerome Glisse }; 3189c93bb85bSJerome Glisse fixed20_12 memtrbs_r4xx[8] = { 319068adac5eSBen Skeggs dfixed_init(4), 319168adac5eSBen Skeggs dfixed_init(5), 319268adac5eSBen Skeggs dfixed_init(6), 319368adac5eSBen Skeggs dfixed_init(7), 319468adac5eSBen Skeggs dfixed_init(8), 319568adac5eSBen Skeggs dfixed_init(9), 319668adac5eSBen Skeggs dfixed_init(10), 319768adac5eSBen Skeggs dfixed_init(11) 3198c93bb85bSJerome Glisse }; 3199c93bb85bSJerome Glisse fixed20_12 min_mem_eff; 3200c93bb85bSJerome Glisse fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; 3201c93bb85bSJerome Glisse fixed20_12 cur_latency_mclk, cur_latency_sclk; 32021ef897e4STim Gardner fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate = {0}, 3203c93bb85bSJerome Glisse disp_drain_rate2, read_return_rate; 3204c93bb85bSJerome Glisse fixed20_12 time_disp1_drop_priority; 3205c93bb85bSJerome Glisse int c; 3206c93bb85bSJerome Glisse int cur_size = 16; /* in octawords */ 3207c93bb85bSJerome Glisse int critical_point = 0, critical_point2; 3208c93bb85bSJerome Glisse /* uint32_t read_return_rate, time_disp1_drop_priority; */ 3209c93bb85bSJerome Glisse int stop_req, max_stop_req; 3210c93bb85bSJerome Glisse struct drm_display_mode *mode1 = NULL; 3211c93bb85bSJerome Glisse struct drm_display_mode *mode2 = NULL; 3212c93bb85bSJerome Glisse uint32_t pixel_bytes1 = 0; 3213c93bb85bSJerome Glisse uint32_t pixel_bytes2 = 0; 3214c93bb85bSJerome Glisse 32155b5561b3SMario Kleiner /* Guess line buffer size to be 8192 pixels */ 32165b5561b3SMario Kleiner u32 lb_size = 8192; 32175b5561b3SMario Kleiner 32188efe82caSAlex Deucher if (!rdev->mode_info.mode_config_initialized) 32198efe82caSAlex Deucher return; 32208efe82caSAlex Deucher 3221f46c0120SAlex Deucher radeon_update_display_priority(rdev); 3222f46c0120SAlex Deucher 3223c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[0]->base.enabled) { 3224489f3267SVille Syrjälä const struct drm_framebuffer *fb = 3225489f3267SVille Syrjälä rdev->mode_info.crtcs[0]->base.primary->fb; 3226489f3267SVille Syrjälä 3227c93bb85bSJerome Glisse mode1 = &rdev->mode_info.crtcs[0]->base.mode; 3228272725c7SVille Syrjälä pixel_bytes1 = fb->format->cpp[0]; 3229c93bb85bSJerome Glisse } 3230dfee5614SDave Airlie if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3231c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[1]->base.enabled) { 3232489f3267SVille Syrjälä const struct drm_framebuffer *fb = 3233489f3267SVille Syrjälä rdev->mode_info.crtcs[1]->base.primary->fb; 3234489f3267SVille Syrjälä 3235c93bb85bSJerome Glisse mode2 = &rdev->mode_info.crtcs[1]->base.mode; 3236272725c7SVille Syrjälä pixel_bytes2 = fb->format->cpp[0]; 3237c93bb85bSJerome Glisse } 3238dfee5614SDave Airlie } 3239c93bb85bSJerome Glisse 324068adac5eSBen Skeggs min_mem_eff.full = dfixed_const_8(0); 3241c93bb85bSJerome Glisse /* get modes */ 3242c93bb85bSJerome Glisse if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { 3243c93bb85bSJerome Glisse uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); 3244c93bb85bSJerome Glisse mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); 3245c93bb85bSJerome Glisse mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); 3246c93bb85bSJerome Glisse /* check crtc enables */ 3247c93bb85bSJerome Glisse if (mode2) 3248c93bb85bSJerome Glisse mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); 3249c93bb85bSJerome Glisse if (mode1) 3250c93bb85bSJerome Glisse mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); 3251c93bb85bSJerome Glisse WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); 3252c93bb85bSJerome Glisse } 3253c93bb85bSJerome Glisse 3254c93bb85bSJerome Glisse /* 3255c93bb85bSJerome Glisse * determine is there is enough bw for current mode 3256c93bb85bSJerome Glisse */ 3257f47299c5SAlex Deucher sclk_ff = rdev->pm.sclk; 3258f47299c5SAlex Deucher mclk_ff = rdev->pm.mclk; 3259c93bb85bSJerome Glisse 3260c93bb85bSJerome Glisse temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); 326168adac5eSBen Skeggs temp_ff.full = dfixed_const(temp); 326268adac5eSBen Skeggs mem_bw.full = dfixed_mul(mclk_ff, temp_ff); 3263c93bb85bSJerome Glisse 3264c93bb85bSJerome Glisse pix_clk.full = 0; 3265c93bb85bSJerome Glisse pix_clk2.full = 0; 3266c93bb85bSJerome Glisse peak_disp_bw.full = 0; 3267c93bb85bSJerome Glisse if (mode1) { 326868adac5eSBen Skeggs temp_ff.full = dfixed_const(1000); 326968adac5eSBen Skeggs pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ 327068adac5eSBen Skeggs pix_clk.full = dfixed_div(pix_clk, temp_ff); 327168adac5eSBen Skeggs temp_ff.full = dfixed_const(pixel_bytes1); 327268adac5eSBen Skeggs peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); 3273c93bb85bSJerome Glisse } 3274c93bb85bSJerome Glisse if (mode2) { 327568adac5eSBen Skeggs temp_ff.full = dfixed_const(1000); 327668adac5eSBen Skeggs pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ 327768adac5eSBen Skeggs pix_clk2.full = dfixed_div(pix_clk2, temp_ff); 327868adac5eSBen Skeggs temp_ff.full = dfixed_const(pixel_bytes2); 327968adac5eSBen Skeggs peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); 3280c93bb85bSJerome Glisse } 3281c93bb85bSJerome Glisse 328268adac5eSBen Skeggs mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); 3283c93bb85bSJerome Glisse if (peak_disp_bw.full >= mem_bw.full) { 3284c93bb85bSJerome Glisse DRM_ERROR("You may not have enough display bandwidth for current mode\n" 3285c93bb85bSJerome Glisse "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); 3286c93bb85bSJerome Glisse } 3287c93bb85bSJerome Glisse 3288c93bb85bSJerome Glisse /* Get values from the EXT_MEM_CNTL register...converting its contents. */ 3289c93bb85bSJerome Glisse temp = RREG32(RADEON_MEM_TIMING_CNTL); 3290c93bb85bSJerome Glisse if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ 3291c93bb85bSJerome Glisse mem_trcd = ((temp >> 2) & 0x3) + 1; 3292c93bb85bSJerome Glisse mem_trp = ((temp & 0x3)) + 1; 3293c93bb85bSJerome Glisse mem_tras = ((temp & 0x70) >> 4) + 1; 3294c93bb85bSJerome Glisse } else if (rdev->family == CHIP_R300 || 3295c93bb85bSJerome Glisse rdev->family == CHIP_R350) { /* r300, r350 */ 3296c93bb85bSJerome Glisse mem_trcd = (temp & 0x7) + 1; 3297c93bb85bSJerome Glisse mem_trp = ((temp >> 8) & 0x7) + 1; 3298c93bb85bSJerome Glisse mem_tras = ((temp >> 11) & 0xf) + 4; 3299c93bb85bSJerome Glisse } else if (rdev->family == CHIP_RV350 || 3300211eed65SAlex Deucher rdev->family == CHIP_RV380) { 3301c93bb85bSJerome Glisse /* rv3x0 */ 3302c93bb85bSJerome Glisse mem_trcd = (temp & 0x7) + 3; 3303c93bb85bSJerome Glisse mem_trp = ((temp >> 8) & 0x7) + 3; 3304c93bb85bSJerome Glisse mem_tras = ((temp >> 11) & 0xf) + 6; 3305c93bb85bSJerome Glisse } else if (rdev->family == CHIP_R420 || 3306c93bb85bSJerome Glisse rdev->family == CHIP_R423 || 3307c93bb85bSJerome Glisse rdev->family == CHIP_RV410) { 3308c93bb85bSJerome Glisse /* r4xx */ 3309c93bb85bSJerome Glisse mem_trcd = (temp & 0xf) + 3; 3310c93bb85bSJerome Glisse if (mem_trcd > 15) 3311c93bb85bSJerome Glisse mem_trcd = 15; 3312c93bb85bSJerome Glisse mem_trp = ((temp >> 8) & 0xf) + 3; 3313c93bb85bSJerome Glisse if (mem_trp > 15) 3314c93bb85bSJerome Glisse mem_trp = 15; 3315c93bb85bSJerome Glisse mem_tras = ((temp >> 12) & 0x1f) + 6; 3316c93bb85bSJerome Glisse if (mem_tras > 31) 3317c93bb85bSJerome Glisse mem_tras = 31; 3318c93bb85bSJerome Glisse } else { /* RV200, R200 */ 3319c93bb85bSJerome Glisse mem_trcd = (temp & 0x7) + 1; 3320c93bb85bSJerome Glisse mem_trp = ((temp >> 8) & 0x7) + 1; 3321c93bb85bSJerome Glisse mem_tras = ((temp >> 12) & 0xf) + 4; 3322c93bb85bSJerome Glisse } 3323c93bb85bSJerome Glisse /* convert to FF */ 332468adac5eSBen Skeggs trcd_ff.full = dfixed_const(mem_trcd); 332568adac5eSBen Skeggs trp_ff.full = dfixed_const(mem_trp); 332668adac5eSBen Skeggs tras_ff.full = dfixed_const(mem_tras); 3327c93bb85bSJerome Glisse 3328c93bb85bSJerome Glisse /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ 3329c93bb85bSJerome Glisse temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3330c93bb85bSJerome Glisse data = (temp & (7 << 20)) >> 20; 3331c93bb85bSJerome Glisse if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { 3332c93bb85bSJerome Glisse if (rdev->family == CHIP_RS480) /* don't think rs400 */ 3333c93bb85bSJerome Glisse tcas_ff = memtcas_rs480_ff[data]; 3334c93bb85bSJerome Glisse else 3335c93bb85bSJerome Glisse tcas_ff = memtcas_ff[data]; 3336c93bb85bSJerome Glisse } else 3337c93bb85bSJerome Glisse tcas_ff = memtcas2_ff[data]; 3338c93bb85bSJerome Glisse 3339c93bb85bSJerome Glisse if (rdev->family == CHIP_RS400 || 3340c93bb85bSJerome Glisse rdev->family == CHIP_RS480) { 3341c93bb85bSJerome Glisse /* extra cas latency stored in bits 23-25 0-4 clocks */ 3342c93bb85bSJerome Glisse data = (temp >> 23) & 0x7; 3343c93bb85bSJerome Glisse if (data < 5) 334468adac5eSBen Skeggs tcas_ff.full += dfixed_const(data); 3345c93bb85bSJerome Glisse } 3346c93bb85bSJerome Glisse 3347c93bb85bSJerome Glisse if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { 3348c93bb85bSJerome Glisse /* on the R300, Tcas is included in Trbs. 3349c93bb85bSJerome Glisse */ 3350c93bb85bSJerome Glisse temp = RREG32(RADEON_MEM_CNTL); 3351c93bb85bSJerome Glisse data = (R300_MEM_NUM_CHANNELS_MASK & temp); 3352c93bb85bSJerome Glisse if (data == 1) { 3353c93bb85bSJerome Glisse if (R300_MEM_USE_CD_CH_ONLY & temp) { 3354c93bb85bSJerome Glisse temp = RREG32(R300_MC_IND_INDEX); 3355c93bb85bSJerome Glisse temp &= ~R300_MC_IND_ADDR_MASK; 3356c93bb85bSJerome Glisse temp |= R300_MC_READ_CNTL_CD_mcind; 3357c93bb85bSJerome Glisse WREG32(R300_MC_IND_INDEX, temp); 3358c93bb85bSJerome Glisse temp = RREG32(R300_MC_IND_DATA); 3359c93bb85bSJerome Glisse data = (R300_MEM_RBS_POSITION_C_MASK & temp); 3360c93bb85bSJerome Glisse } else { 3361c93bb85bSJerome Glisse temp = RREG32(R300_MC_READ_CNTL_AB); 3362c93bb85bSJerome Glisse data = (R300_MEM_RBS_POSITION_A_MASK & temp); 3363c93bb85bSJerome Glisse } 3364c93bb85bSJerome Glisse } else { 3365c93bb85bSJerome Glisse temp = RREG32(R300_MC_READ_CNTL_AB); 3366c93bb85bSJerome Glisse data = (R300_MEM_RBS_POSITION_A_MASK & temp); 3367c93bb85bSJerome Glisse } 3368c93bb85bSJerome Glisse if (rdev->family == CHIP_RV410 || 3369c93bb85bSJerome Glisse rdev->family == CHIP_R420 || 3370c93bb85bSJerome Glisse rdev->family == CHIP_R423) 3371c93bb85bSJerome Glisse trbs_ff = memtrbs_r4xx[data]; 3372c93bb85bSJerome Glisse else 3373c93bb85bSJerome Glisse trbs_ff = memtrbs[data]; 3374c93bb85bSJerome Glisse tcas_ff.full += trbs_ff.full; 3375c93bb85bSJerome Glisse } 3376c93bb85bSJerome Glisse 3377c93bb85bSJerome Glisse sclk_eff_ff.full = sclk_ff.full; 3378c93bb85bSJerome Glisse 3379c93bb85bSJerome Glisse if (rdev->flags & RADEON_IS_AGP) { 3380c93bb85bSJerome Glisse fixed20_12 agpmode_ff; 338168adac5eSBen Skeggs agpmode_ff.full = dfixed_const(radeon_agpmode); 338268adac5eSBen Skeggs temp_ff.full = dfixed_const_666(16); 338368adac5eSBen Skeggs sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); 3384c93bb85bSJerome Glisse } 3385c93bb85bSJerome Glisse /* TODO PCIE lanes may affect this - agpmode == 16?? */ 3386c93bb85bSJerome Glisse 3387c93bb85bSJerome Glisse if (ASIC_IS_R300(rdev)) { 338868adac5eSBen Skeggs sclk_delay_ff.full = dfixed_const(250); 3389c93bb85bSJerome Glisse } else { 3390c93bb85bSJerome Glisse if ((rdev->family == CHIP_RV100) || 3391c93bb85bSJerome Glisse rdev->flags & RADEON_IS_IGP) { 3392c93bb85bSJerome Glisse if (rdev->mc.vram_is_ddr) 339368adac5eSBen Skeggs sclk_delay_ff.full = dfixed_const(41); 3394c93bb85bSJerome Glisse else 339568adac5eSBen Skeggs sclk_delay_ff.full = dfixed_const(33); 3396c93bb85bSJerome Glisse } else { 3397c93bb85bSJerome Glisse if (rdev->mc.vram_width == 128) 339868adac5eSBen Skeggs sclk_delay_ff.full = dfixed_const(57); 3399c93bb85bSJerome Glisse else 340068adac5eSBen Skeggs sclk_delay_ff.full = dfixed_const(41); 3401c93bb85bSJerome Glisse } 3402c93bb85bSJerome Glisse } 3403c93bb85bSJerome Glisse 340468adac5eSBen Skeggs mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff); 3405c93bb85bSJerome Glisse 3406c93bb85bSJerome Glisse if (rdev->mc.vram_is_ddr) { 3407c93bb85bSJerome Glisse if (rdev->mc.vram_width == 32) { 340868adac5eSBen Skeggs k1.full = dfixed_const(40); 3409c93bb85bSJerome Glisse c = 3; 3410c93bb85bSJerome Glisse } else { 341168adac5eSBen Skeggs k1.full = dfixed_const(20); 3412c93bb85bSJerome Glisse c = 1; 3413c93bb85bSJerome Glisse } 3414c93bb85bSJerome Glisse } else { 341568adac5eSBen Skeggs k1.full = dfixed_const(40); 3416c93bb85bSJerome Glisse c = 3; 3417c93bb85bSJerome Glisse } 3418c93bb85bSJerome Glisse 341968adac5eSBen Skeggs temp_ff.full = dfixed_const(2); 342068adac5eSBen Skeggs mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); 342168adac5eSBen Skeggs temp_ff.full = dfixed_const(c); 342268adac5eSBen Skeggs mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); 342368adac5eSBen Skeggs temp_ff.full = dfixed_const(4); 342468adac5eSBen Skeggs mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); 342568adac5eSBen Skeggs mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); 3426c93bb85bSJerome Glisse mc_latency_mclk.full += k1.full; 3427c93bb85bSJerome Glisse 342868adac5eSBen Skeggs mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff); 342968adac5eSBen Skeggs mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff); 3430c93bb85bSJerome Glisse 3431c93bb85bSJerome Glisse /* 3432c93bb85bSJerome Glisse HW cursor time assuming worst case of full size colour cursor. 3433c93bb85bSJerome Glisse */ 343468adac5eSBen Skeggs temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); 3435c93bb85bSJerome Glisse temp_ff.full += trcd_ff.full; 3436c93bb85bSJerome Glisse if (temp_ff.full < tras_ff.full) 3437c93bb85bSJerome Glisse temp_ff.full = tras_ff.full; 343868adac5eSBen Skeggs cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff); 3439c93bb85bSJerome Glisse 344068adac5eSBen Skeggs temp_ff.full = dfixed_const(cur_size); 344168adac5eSBen Skeggs cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff); 3442c93bb85bSJerome Glisse /* 3443c93bb85bSJerome Glisse Find the total latency for the display data. 3444c93bb85bSJerome Glisse */ 344568adac5eSBen Skeggs disp_latency_overhead.full = dfixed_const(8); 344668adac5eSBen Skeggs disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff); 3447c93bb85bSJerome Glisse mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; 3448c93bb85bSJerome Glisse mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; 3449c93bb85bSJerome Glisse 3450c93bb85bSJerome Glisse if (mc_latency_mclk.full > mc_latency_sclk.full) 3451c93bb85bSJerome Glisse disp_latency.full = mc_latency_mclk.full; 3452c93bb85bSJerome Glisse else 3453c93bb85bSJerome Glisse disp_latency.full = mc_latency_sclk.full; 3454c93bb85bSJerome Glisse 3455c93bb85bSJerome Glisse /* setup Max GRPH_STOP_REQ default value */ 3456c93bb85bSJerome Glisse if (ASIC_IS_RV100(rdev)) 3457c93bb85bSJerome Glisse max_stop_req = 0x5c; 3458c93bb85bSJerome Glisse else 3459c93bb85bSJerome Glisse max_stop_req = 0x7c; 3460c93bb85bSJerome Glisse 3461c93bb85bSJerome Glisse if (mode1) { 3462c93bb85bSJerome Glisse /* CRTC1 3463c93bb85bSJerome Glisse Set GRPH_BUFFER_CNTL register using h/w defined optimal values. 3464c93bb85bSJerome Glisse GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] 3465c93bb85bSJerome Glisse */ 3466c93bb85bSJerome Glisse stop_req = mode1->hdisplay * pixel_bytes1 / 16; 3467c93bb85bSJerome Glisse 3468c93bb85bSJerome Glisse if (stop_req > max_stop_req) 3469c93bb85bSJerome Glisse stop_req = max_stop_req; 3470c93bb85bSJerome Glisse 3471c93bb85bSJerome Glisse /* 3472c93bb85bSJerome Glisse Find the drain rate of the display buffer. 3473c93bb85bSJerome Glisse */ 347468adac5eSBen Skeggs temp_ff.full = dfixed_const((16/pixel_bytes1)); 347568adac5eSBen Skeggs disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); 3476c93bb85bSJerome Glisse 3477c93bb85bSJerome Glisse /* 3478c93bb85bSJerome Glisse Find the critical point of the display buffer. 3479c93bb85bSJerome Glisse */ 348068adac5eSBen Skeggs crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); 348168adac5eSBen Skeggs crit_point_ff.full += dfixed_const_half(0); 3482c93bb85bSJerome Glisse 348368adac5eSBen Skeggs critical_point = dfixed_trunc(crit_point_ff); 3484c93bb85bSJerome Glisse 3485c93bb85bSJerome Glisse if (rdev->disp_priority == 2) { 3486c93bb85bSJerome Glisse critical_point = 0; 3487c93bb85bSJerome Glisse } 3488c93bb85bSJerome Glisse 3489c93bb85bSJerome Glisse /* 3490c93bb85bSJerome Glisse The critical point should never be above max_stop_req-4. Setting 3491c93bb85bSJerome Glisse GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. 3492c93bb85bSJerome Glisse */ 3493c93bb85bSJerome Glisse if (max_stop_req - critical_point < 4) 3494c93bb85bSJerome Glisse critical_point = 0; 3495c93bb85bSJerome Glisse 3496c93bb85bSJerome Glisse if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { 3497c93bb85bSJerome Glisse /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ 3498c93bb85bSJerome Glisse critical_point = 0x10; 3499c93bb85bSJerome Glisse } 3500c93bb85bSJerome Glisse 3501c93bb85bSJerome Glisse temp = RREG32(RADEON_GRPH_BUFFER_CNTL); 3502c93bb85bSJerome Glisse temp &= ~(RADEON_GRPH_STOP_REQ_MASK); 3503c93bb85bSJerome Glisse temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3504c93bb85bSJerome Glisse temp &= ~(RADEON_GRPH_START_REQ_MASK); 3505c93bb85bSJerome Glisse if ((rdev->family == CHIP_R350) && 3506c93bb85bSJerome Glisse (stop_req > 0x15)) { 3507c93bb85bSJerome Glisse stop_req -= 0x10; 3508c93bb85bSJerome Glisse } 3509c93bb85bSJerome Glisse temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3510c93bb85bSJerome Glisse temp |= RADEON_GRPH_BUFFER_SIZE; 3511c93bb85bSJerome Glisse temp &= ~(RADEON_GRPH_CRITICAL_CNTL | 3512c93bb85bSJerome Glisse RADEON_GRPH_CRITICAL_AT_SOF | 3513c93bb85bSJerome Glisse RADEON_GRPH_STOP_CNTL); 3514c93bb85bSJerome Glisse /* 3515c93bb85bSJerome Glisse Write the result into the register. 3516c93bb85bSJerome Glisse */ 3517c93bb85bSJerome Glisse WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3518c93bb85bSJerome Glisse (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3519c93bb85bSJerome Glisse 3520c93bb85bSJerome Glisse #if 0 3521c93bb85bSJerome Glisse if ((rdev->family == CHIP_RS400) || 3522c93bb85bSJerome Glisse (rdev->family == CHIP_RS480)) { 3523c93bb85bSJerome Glisse /* attempt to program RS400 disp regs correctly ??? */ 3524c93bb85bSJerome Glisse temp = RREG32(RS400_DISP1_REG_CNTL); 3525c93bb85bSJerome Glisse temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | 3526c93bb85bSJerome Glisse RS400_DISP1_STOP_REQ_LEVEL_MASK); 3527c93bb85bSJerome Glisse WREG32(RS400_DISP1_REQ_CNTL1, (temp | 3528c93bb85bSJerome Glisse (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3529c93bb85bSJerome Glisse (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3530c93bb85bSJerome Glisse temp = RREG32(RS400_DMIF_MEM_CNTL1); 3531c93bb85bSJerome Glisse temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | 3532c93bb85bSJerome Glisse RS400_DISP1_CRITICAL_POINT_STOP_MASK); 3533c93bb85bSJerome Glisse WREG32(RS400_DMIF_MEM_CNTL1, (temp | 3534c93bb85bSJerome Glisse (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | 3535c93bb85bSJerome Glisse (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); 3536c93bb85bSJerome Glisse } 3537c93bb85bSJerome Glisse #endif 3538c93bb85bSJerome Glisse 3539d9fdaafbSDave Airlie DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n", 3540c93bb85bSJerome Glisse /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ 3541c93bb85bSJerome Glisse (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); 3542c93bb85bSJerome Glisse } 3543c93bb85bSJerome Glisse 3544c93bb85bSJerome Glisse if (mode2) { 3545c93bb85bSJerome Glisse u32 grph2_cntl; 3546c93bb85bSJerome Glisse stop_req = mode2->hdisplay * pixel_bytes2 / 16; 3547c93bb85bSJerome Glisse 3548c93bb85bSJerome Glisse if (stop_req > max_stop_req) 3549c93bb85bSJerome Glisse stop_req = max_stop_req; 3550c93bb85bSJerome Glisse 3551c93bb85bSJerome Glisse /* 3552c93bb85bSJerome Glisse Find the drain rate of the display buffer. 3553c93bb85bSJerome Glisse */ 355468adac5eSBen Skeggs temp_ff.full = dfixed_const((16/pixel_bytes2)); 355568adac5eSBen Skeggs disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff); 3556c93bb85bSJerome Glisse 3557c93bb85bSJerome Glisse grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); 3558c93bb85bSJerome Glisse grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); 3559c93bb85bSJerome Glisse grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3560c93bb85bSJerome Glisse grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); 3561c93bb85bSJerome Glisse if ((rdev->family == CHIP_R350) && 3562c93bb85bSJerome Glisse (stop_req > 0x15)) { 3563c93bb85bSJerome Glisse stop_req -= 0x10; 3564c93bb85bSJerome Glisse } 3565c93bb85bSJerome Glisse grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3566c93bb85bSJerome Glisse grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; 3567c93bb85bSJerome Glisse grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | 3568c93bb85bSJerome Glisse RADEON_GRPH_CRITICAL_AT_SOF | 3569c93bb85bSJerome Glisse RADEON_GRPH_STOP_CNTL); 3570c93bb85bSJerome Glisse 3571c93bb85bSJerome Glisse if ((rdev->family == CHIP_RS100) || 3572c93bb85bSJerome Glisse (rdev->family == CHIP_RS200)) 3573c93bb85bSJerome Glisse critical_point2 = 0; 3574c93bb85bSJerome Glisse else { 3575c93bb85bSJerome Glisse temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; 357668adac5eSBen Skeggs temp_ff.full = dfixed_const(temp); 357768adac5eSBen Skeggs temp_ff.full = dfixed_mul(mclk_ff, temp_ff); 3578c93bb85bSJerome Glisse if (sclk_ff.full < temp_ff.full) 3579c93bb85bSJerome Glisse temp_ff.full = sclk_ff.full; 3580c93bb85bSJerome Glisse 3581c93bb85bSJerome Glisse read_return_rate.full = temp_ff.full; 3582c93bb85bSJerome Glisse 3583c93bb85bSJerome Glisse if (mode1) { 3584c93bb85bSJerome Glisse temp_ff.full = read_return_rate.full - disp_drain_rate.full; 358568adac5eSBen Skeggs time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff); 3586c93bb85bSJerome Glisse } else { 3587c93bb85bSJerome Glisse time_disp1_drop_priority.full = 0; 3588c93bb85bSJerome Glisse } 3589c93bb85bSJerome Glisse crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; 359068adac5eSBen Skeggs crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2); 359168adac5eSBen Skeggs crit_point_ff.full += dfixed_const_half(0); 3592c93bb85bSJerome Glisse 359368adac5eSBen Skeggs critical_point2 = dfixed_trunc(crit_point_ff); 3594c93bb85bSJerome Glisse 3595c93bb85bSJerome Glisse if (rdev->disp_priority == 2) { 3596c93bb85bSJerome Glisse critical_point2 = 0; 3597c93bb85bSJerome Glisse } 3598c93bb85bSJerome Glisse 3599c93bb85bSJerome Glisse if (max_stop_req - critical_point2 < 4) 3600c93bb85bSJerome Glisse critical_point2 = 0; 3601c93bb85bSJerome Glisse 3602c93bb85bSJerome Glisse } 3603c93bb85bSJerome Glisse 3604c93bb85bSJerome Glisse if (critical_point2 == 0 && rdev->family == CHIP_R300) { 3605c93bb85bSJerome Glisse /* some R300 cards have problem with this set to 0 */ 3606c93bb85bSJerome Glisse critical_point2 = 0x10; 3607c93bb85bSJerome Glisse } 3608c93bb85bSJerome Glisse 3609c93bb85bSJerome Glisse WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3610c93bb85bSJerome Glisse (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3611c93bb85bSJerome Glisse 3612c93bb85bSJerome Glisse if ((rdev->family == CHIP_RS400) || 3613c93bb85bSJerome Glisse (rdev->family == CHIP_RS480)) { 3614c93bb85bSJerome Glisse #if 0 3615c93bb85bSJerome Glisse /* attempt to program RS400 disp2 regs correctly ??? */ 3616c93bb85bSJerome Glisse temp = RREG32(RS400_DISP2_REQ_CNTL1); 3617c93bb85bSJerome Glisse temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | 3618c93bb85bSJerome Glisse RS400_DISP2_STOP_REQ_LEVEL_MASK); 3619c93bb85bSJerome Glisse WREG32(RS400_DISP2_REQ_CNTL1, (temp | 3620c93bb85bSJerome Glisse (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3621c93bb85bSJerome Glisse (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3622c93bb85bSJerome Glisse temp = RREG32(RS400_DISP2_REQ_CNTL2); 3623c93bb85bSJerome Glisse temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | 3624c93bb85bSJerome Glisse RS400_DISP2_CRITICAL_POINT_STOP_MASK); 3625c93bb85bSJerome Glisse WREG32(RS400_DISP2_REQ_CNTL2, (temp | 3626c93bb85bSJerome Glisse (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | 3627c93bb85bSJerome Glisse (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); 3628c93bb85bSJerome Glisse #endif 3629c93bb85bSJerome Glisse WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); 3630c93bb85bSJerome Glisse WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); 3631c93bb85bSJerome Glisse WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); 3632c93bb85bSJerome Glisse WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); 3633c93bb85bSJerome Glisse } 3634c93bb85bSJerome Glisse 3635d9fdaafbSDave Airlie DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n", 3636c93bb85bSJerome Glisse (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); 3637c93bb85bSJerome Glisse } 36385b5561b3SMario Kleiner 36395b5561b3SMario Kleiner /* Save number of lines the linebuffer leads before the scanout */ 36405b5561b3SMario Kleiner if (mode1) 36415b5561b3SMario Kleiner rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); 36425b5561b3SMario Kleiner 36435b5561b3SMario Kleiner if (mode2) 36445b5561b3SMario Kleiner rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); 3645c93bb85bSJerome Glisse } 3646551ebd83SDave Airlie 3647e32eb50dSChristian König int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 36483ce0a23dSJerome Glisse { 36493ce0a23dSJerome Glisse uint32_t scratch; 36503ce0a23dSJerome Glisse uint32_t tmp = 0; 36513ce0a23dSJerome Glisse unsigned i; 36523ce0a23dSJerome Glisse int r; 36533ce0a23dSJerome Glisse 36543ce0a23dSJerome Glisse r = radeon_scratch_get(rdev, &scratch); 36553ce0a23dSJerome Glisse if (r) { 36563ce0a23dSJerome Glisse DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 36573ce0a23dSJerome Glisse return r; 36583ce0a23dSJerome Glisse } 36593ce0a23dSJerome Glisse WREG32(scratch, 0xCAFEDEAD); 3660e32eb50dSChristian König r = radeon_ring_lock(rdev, ring, 2); 36613ce0a23dSJerome Glisse if (r) { 36623ce0a23dSJerome Glisse DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 36633ce0a23dSJerome Glisse radeon_scratch_free(rdev, scratch); 36643ce0a23dSJerome Glisse return r; 36653ce0a23dSJerome Glisse } 3666e32eb50dSChristian König radeon_ring_write(ring, PACKET0(scratch, 0)); 3667e32eb50dSChristian König radeon_ring_write(ring, 0xDEADBEEF); 36681538a9e0SMichel Dänzer radeon_ring_unlock_commit(rdev, ring, false); 36693ce0a23dSJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 36703ce0a23dSJerome Glisse tmp = RREG32(scratch); 36713ce0a23dSJerome Glisse if (tmp == 0xDEADBEEF) { 36723ce0a23dSJerome Glisse break; 36733ce0a23dSJerome Glisse } 36740e1a351dSSam Ravnborg udelay(1); 36753ce0a23dSJerome Glisse } 36763ce0a23dSJerome Glisse if (i < rdev->usec_timeout) { 36773ce0a23dSJerome Glisse DRM_INFO("ring test succeeded in %d usecs\n", i); 36783ce0a23dSJerome Glisse } else { 3679369d7ec1SAlex Deucher DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", 36803ce0a23dSJerome Glisse scratch, tmp); 36813ce0a23dSJerome Glisse r = -EINVAL; 36823ce0a23dSJerome Glisse } 36833ce0a23dSJerome Glisse radeon_scratch_free(rdev, scratch); 36843ce0a23dSJerome Glisse return r; 36853ce0a23dSJerome Glisse } 36863ce0a23dSJerome Glisse 36873ce0a23dSJerome Glisse void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 36883ce0a23dSJerome Glisse { 3689e32eb50dSChristian König struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 36907b1f2485SChristian König 3691c7eff978SAlex Deucher if (ring->rptr_save_reg) { 3692c7eff978SAlex Deucher u32 next_rptr = ring->wptr + 2 + 3; 3693c7eff978SAlex Deucher radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0)); 3694c7eff978SAlex Deucher radeon_ring_write(ring, next_rptr); 3695c7eff978SAlex Deucher } 3696c7eff978SAlex Deucher 3697e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1)); 3698e32eb50dSChristian König radeon_ring_write(ring, ib->gpu_addr); 3699e32eb50dSChristian König radeon_ring_write(ring, ib->length_dw); 37003ce0a23dSJerome Glisse } 37013ce0a23dSJerome Glisse 3702f712812eSAlex Deucher int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 37033ce0a23dSJerome Glisse { 3704f2e39221SJerome Glisse struct radeon_ib ib; 37053ce0a23dSJerome Glisse uint32_t scratch; 37063ce0a23dSJerome Glisse uint32_t tmp = 0; 37073ce0a23dSJerome Glisse unsigned i; 37083ce0a23dSJerome Glisse int r; 37093ce0a23dSJerome Glisse 37103ce0a23dSJerome Glisse r = radeon_scratch_get(rdev, &scratch); 37113ce0a23dSJerome Glisse if (r) { 37123ce0a23dSJerome Glisse DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 37133ce0a23dSJerome Glisse return r; 37143ce0a23dSJerome Glisse } 37153ce0a23dSJerome Glisse WREG32(scratch, 0xCAFEDEAD); 37164bf3dd92SChristian König r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256); 37173ce0a23dSJerome Glisse if (r) { 3718af026c5bSMichel Dänzer DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3719af026c5bSMichel Dänzer goto free_scratch; 37203ce0a23dSJerome Glisse } 3721f2e39221SJerome Glisse ib.ptr[0] = PACKET0(scratch, 0); 3722f2e39221SJerome Glisse ib.ptr[1] = 0xDEADBEEF; 3723f2e39221SJerome Glisse ib.ptr[2] = PACKET2(0); 3724f2e39221SJerome Glisse ib.ptr[3] = PACKET2(0); 3725f2e39221SJerome Glisse ib.ptr[4] = PACKET2(0); 3726f2e39221SJerome Glisse ib.ptr[5] = PACKET2(0); 3727f2e39221SJerome Glisse ib.ptr[6] = PACKET2(0); 3728f2e39221SJerome Glisse ib.ptr[7] = PACKET2(0); 3729f2e39221SJerome Glisse ib.length_dw = 8; 37301538a9e0SMichel Dänzer r = radeon_ib_schedule(rdev, &ib, NULL, false); 37313ce0a23dSJerome Glisse if (r) { 3732af026c5bSMichel Dänzer DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3733af026c5bSMichel Dänzer goto free_ib; 37343ce0a23dSJerome Glisse } 373504db4cafSMatthew Dawson r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies( 373604db4cafSMatthew Dawson RADEON_USEC_IB_TEST_TIMEOUT)); 373704db4cafSMatthew Dawson if (r < 0) { 3738af026c5bSMichel Dänzer DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3739af026c5bSMichel Dänzer goto free_ib; 374004db4cafSMatthew Dawson } else if (r == 0) { 374104db4cafSMatthew Dawson DRM_ERROR("radeon: fence wait timed out.\n"); 374204db4cafSMatthew Dawson r = -ETIMEDOUT; 374304db4cafSMatthew Dawson goto free_ib; 37443ce0a23dSJerome Glisse } 374504db4cafSMatthew Dawson r = 0; 37463ce0a23dSJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 37473ce0a23dSJerome Glisse tmp = RREG32(scratch); 37483ce0a23dSJerome Glisse if (tmp == 0xDEADBEEF) { 37493ce0a23dSJerome Glisse break; 37503ce0a23dSJerome Glisse } 37510e1a351dSSam Ravnborg udelay(1); 37523ce0a23dSJerome Glisse } 37533ce0a23dSJerome Glisse if (i < rdev->usec_timeout) { 37543ce0a23dSJerome Glisse DRM_INFO("ib test succeeded in %u usecs\n", i); 37553ce0a23dSJerome Glisse } else { 375662f288cfSPaul Bolle DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 37573ce0a23dSJerome Glisse scratch, tmp); 37583ce0a23dSJerome Glisse r = -EINVAL; 37593ce0a23dSJerome Glisse } 3760af026c5bSMichel Dänzer free_ib: 37613ce0a23dSJerome Glisse radeon_ib_free(rdev, &ib); 3762af026c5bSMichel Dänzer free_scratch: 3763af026c5bSMichel Dänzer radeon_scratch_free(rdev, scratch); 37643ce0a23dSJerome Glisse return r; 37653ce0a23dSJerome Glisse } 37669f022ddfSJerome Glisse 37679f022ddfSJerome Glisse void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) 37689f022ddfSJerome Glisse { 37699f022ddfSJerome Glisse /* Shutdown CP we shouldn't need to do that but better be safe than 37709f022ddfSJerome Glisse * sorry 37719f022ddfSJerome Glisse */ 3772e32eb50dSChristian König rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 37739f022ddfSJerome Glisse WREG32(R_000740_CP_CSQ_CNTL, 0); 37749f022ddfSJerome Glisse 37759f022ddfSJerome Glisse /* Save few CRTC registers */ 3776ca6ffc64SJerome Glisse save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); 37779f022ddfSJerome Glisse save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); 37789f022ddfSJerome Glisse save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); 37799f022ddfSJerome Glisse save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); 37809f022ddfSJerome Glisse if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 37819f022ddfSJerome Glisse save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); 37829f022ddfSJerome Glisse save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); 37839f022ddfSJerome Glisse } 37849f022ddfSJerome Glisse 37859f022ddfSJerome Glisse /* Disable VGA aperture access */ 3786ca6ffc64SJerome Glisse WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); 37879f022ddfSJerome Glisse /* Disable cursor, overlay, crtc */ 37889f022ddfSJerome Glisse WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); 37899f022ddfSJerome Glisse WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | 37909f022ddfSJerome Glisse S_000054_CRTC_DISPLAY_DIS(1)); 37919f022ddfSJerome Glisse WREG32(R_000050_CRTC_GEN_CNTL, 37929f022ddfSJerome Glisse (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | 37939f022ddfSJerome Glisse S_000050_CRTC_DISP_REQ_EN_B(1)); 37949f022ddfSJerome Glisse WREG32(R_000420_OV0_SCALE_CNTL, 37959f022ddfSJerome Glisse C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); 37969f022ddfSJerome Glisse WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); 37979f022ddfSJerome Glisse if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 37989f022ddfSJerome Glisse WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | 37999f022ddfSJerome Glisse S_000360_CUR2_LOCK(1)); 38009f022ddfSJerome Glisse WREG32(R_0003F8_CRTC2_GEN_CNTL, 38019f022ddfSJerome Glisse (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | 38029f022ddfSJerome Glisse S_0003F8_CRTC2_DISPLAY_DIS(1) | 38039f022ddfSJerome Glisse S_0003F8_CRTC2_DISP_REQ_EN_B(1)); 38049f022ddfSJerome Glisse WREG32(R_000360_CUR2_OFFSET, 38059f022ddfSJerome Glisse C_000360_CUR2_LOCK & save->CUR2_OFFSET); 38069f022ddfSJerome Glisse } 38079f022ddfSJerome Glisse } 38089f022ddfSJerome Glisse 38099f022ddfSJerome Glisse void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) 38109f022ddfSJerome Glisse { 38119f022ddfSJerome Glisse /* Update base address for crtc */ 3812d594e46aSJerome Glisse WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 38139f022ddfSJerome Glisse if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3814d594e46aSJerome Glisse WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 38159f022ddfSJerome Glisse } 38169f022ddfSJerome Glisse /* Restore CRTC registers */ 3817ca6ffc64SJerome Glisse WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); 38189f022ddfSJerome Glisse WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); 38199f022ddfSJerome Glisse WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); 38209f022ddfSJerome Glisse if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 38219f022ddfSJerome Glisse WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); 38229f022ddfSJerome Glisse } 38239f022ddfSJerome Glisse } 3824ca6ffc64SJerome Glisse 3825ca6ffc64SJerome Glisse void r100_vga_render_disable(struct radeon_device *rdev) 3826ca6ffc64SJerome Glisse { 3827ca6ffc64SJerome Glisse u32 tmp; 3828ca6ffc64SJerome Glisse 3829ca6ffc64SJerome Glisse tmp = RREG8(R_0003C2_GENMO_WT); 3830ca6ffc64SJerome Glisse WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); 3831ca6ffc64SJerome Glisse } 3832d4550907SJerome Glisse 3833d4550907SJerome Glisse static void r100_mc_program(struct radeon_device *rdev) 3834d4550907SJerome Glisse { 3835d4550907SJerome Glisse struct r100_mc_save save; 3836d4550907SJerome Glisse 3837d4550907SJerome Glisse /* Stops all mc clients */ 3838d4550907SJerome Glisse r100_mc_stop(rdev, &save); 3839d4550907SJerome Glisse if (rdev->flags & RADEON_IS_AGP) { 3840d4550907SJerome Glisse WREG32(R_00014C_MC_AGP_LOCATION, 3841d4550907SJerome Glisse S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 3842d4550907SJerome Glisse S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 3843d4550907SJerome Glisse WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 3844d4550907SJerome Glisse if (rdev->family > CHIP_RV200) 3845d4550907SJerome Glisse WREG32(R_00015C_AGP_BASE_2, 3846d4550907SJerome Glisse upper_32_bits(rdev->mc.agp_base) & 0xff); 3847d4550907SJerome Glisse } else { 3848d4550907SJerome Glisse WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 3849d4550907SJerome Glisse WREG32(R_000170_AGP_BASE, 0); 3850d4550907SJerome Glisse if (rdev->family > CHIP_RV200) 3851d4550907SJerome Glisse WREG32(R_00015C_AGP_BASE_2, 0); 3852d4550907SJerome Glisse } 3853d4550907SJerome Glisse /* Wait for mc idle */ 3854d4550907SJerome Glisse if (r100_mc_wait_for_idle(rdev)) 3855d4550907SJerome Glisse dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); 3856d4550907SJerome Glisse /* Program MC, should be a 32bits limited address space */ 3857d4550907SJerome Glisse WREG32(R_000148_MC_FB_LOCATION, 3858d4550907SJerome Glisse S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 3859d4550907SJerome Glisse S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 3860d4550907SJerome Glisse r100_mc_resume(rdev, &save); 3861d4550907SJerome Glisse } 3862d4550907SJerome Glisse 38631109ca09SLauri Kasanen static void r100_clock_startup(struct radeon_device *rdev) 3864d4550907SJerome Glisse { 3865d4550907SJerome Glisse u32 tmp; 3866d4550907SJerome Glisse 3867d4550907SJerome Glisse if (radeon_dynclks != -1 && radeon_dynclks) 3868d4550907SJerome Glisse radeon_legacy_set_clock_gating(rdev, 1); 3869d4550907SJerome Glisse /* We need to force on some of the block */ 3870d4550907SJerome Glisse tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 3871d4550907SJerome Glisse tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 3872d4550907SJerome Glisse if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) 3873d4550907SJerome Glisse tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); 3874d4550907SJerome Glisse WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 3875d4550907SJerome Glisse } 3876d4550907SJerome Glisse 3877d4550907SJerome Glisse static int r100_startup(struct radeon_device *rdev) 3878d4550907SJerome Glisse { 3879d4550907SJerome Glisse int r; 3880d4550907SJerome Glisse 388192cde00cSAlex Deucher /* set common regs */ 388292cde00cSAlex Deucher r100_set_common_regs(rdev); 388392cde00cSAlex Deucher /* program mc */ 3884d4550907SJerome Glisse r100_mc_program(rdev); 3885d4550907SJerome Glisse /* Resume clock */ 3886d4550907SJerome Glisse r100_clock_startup(rdev); 3887d4550907SJerome Glisse /* Initialize GART (initialize after TTM so we can allocate 3888d4550907SJerome Glisse * memory through TTM but finalize after TTM) */ 388917e15b0cSDave Airlie r100_enable_bm(rdev); 3890d4550907SJerome Glisse if (rdev->flags & RADEON_IS_PCI) { 3891d4550907SJerome Glisse r = r100_pci_gart_enable(rdev); 3892d4550907SJerome Glisse if (r) 3893d4550907SJerome Glisse return r; 3894d4550907SJerome Glisse } 3895724c80e1SAlex Deucher 3896724c80e1SAlex Deucher /* allocate wb buffer */ 3897724c80e1SAlex Deucher r = radeon_wb_init(rdev); 3898724c80e1SAlex Deucher if (r) 3899724c80e1SAlex Deucher return r; 3900724c80e1SAlex Deucher 390130eb77f4SJerome Glisse r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 390230eb77f4SJerome Glisse if (r) { 390330eb77f4SJerome Glisse dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 390430eb77f4SJerome Glisse return r; 390530eb77f4SJerome Glisse } 390630eb77f4SJerome Glisse 3907d4550907SJerome Glisse /* Enable IRQ */ 3908e49f3959SAdis Hamzić if (!rdev->irq.installed) { 3909e49f3959SAdis Hamzić r = radeon_irq_kms_init(rdev); 3910e49f3959SAdis Hamzić if (r) 3911e49f3959SAdis Hamzić return r; 3912e49f3959SAdis Hamzić } 3913e49f3959SAdis Hamzić 3914d4550907SJerome Glisse r100_irq_set(rdev); 3915cafe6609SJerome Glisse rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 3916d4550907SJerome Glisse /* 1M ring buffer */ 3917d4550907SJerome Glisse r = r100_cp_init(rdev, 1024 * 1024); 3918d4550907SJerome Glisse if (r) { 3919ec4f2ac4SPaul Bolle dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 3920d4550907SJerome Glisse return r; 3921d4550907SJerome Glisse } 3922b15ba512SJerome Glisse 39232898c348SChristian König r = radeon_ib_pool_init(rdev); 39242898c348SChristian König if (r) { 39252898c348SChristian König dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 3926b15ba512SJerome Glisse return r; 39272898c348SChristian König } 3928b15ba512SJerome Glisse 3929d4550907SJerome Glisse return 0; 3930d4550907SJerome Glisse } 3931d4550907SJerome Glisse 3932d4550907SJerome Glisse int r100_resume(struct radeon_device *rdev) 3933d4550907SJerome Glisse { 39346b7746e8SJerome Glisse int r; 39356b7746e8SJerome Glisse 3936d4550907SJerome Glisse /* Make sur GART are not working */ 3937d4550907SJerome Glisse if (rdev->flags & RADEON_IS_PCI) 3938d4550907SJerome Glisse r100_pci_gart_disable(rdev); 3939d4550907SJerome Glisse /* Resume clock before doing reset */ 3940d4550907SJerome Glisse r100_clock_startup(rdev); 3941d4550907SJerome Glisse /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 3942a2d07b74SJerome Glisse if (radeon_asic_reset(rdev)) { 3943d4550907SJerome Glisse dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 3944d4550907SJerome Glisse RREG32(R_000E40_RBBM_STATUS), 3945d4550907SJerome Glisse RREG32(R_0007C0_CP_STAT)); 3946d4550907SJerome Glisse } 3947d4550907SJerome Glisse /* post */ 3948d4550907SJerome Glisse radeon_combios_asic_init(rdev->ddev); 3949d4550907SJerome Glisse /* Resume clock after posting */ 3950d4550907SJerome Glisse r100_clock_startup(rdev); 3951550e2d92SDave Airlie /* Initialize surface registers */ 3952550e2d92SDave Airlie radeon_surface_init(rdev); 3953b15ba512SJerome Glisse 3954b15ba512SJerome Glisse rdev->accel_working = true; 39556b7746e8SJerome Glisse r = r100_startup(rdev); 39566b7746e8SJerome Glisse if (r) { 39576b7746e8SJerome Glisse rdev->accel_working = false; 39586b7746e8SJerome Glisse } 39596b7746e8SJerome Glisse return r; 3960d4550907SJerome Glisse } 3961d4550907SJerome Glisse 3962d4550907SJerome Glisse int r100_suspend(struct radeon_device *rdev) 3963d4550907SJerome Glisse { 39646c7bcceaSAlex Deucher radeon_pm_suspend(rdev); 3965d4550907SJerome Glisse r100_cp_disable(rdev); 3966724c80e1SAlex Deucher radeon_wb_disable(rdev); 3967d4550907SJerome Glisse r100_irq_disable(rdev); 3968d4550907SJerome Glisse if (rdev->flags & RADEON_IS_PCI) 3969d4550907SJerome Glisse r100_pci_gart_disable(rdev); 3970d4550907SJerome Glisse return 0; 3971d4550907SJerome Glisse } 3972d4550907SJerome Glisse 3973d4550907SJerome Glisse void r100_fini(struct radeon_device *rdev) 3974d4550907SJerome Glisse { 39756c7bcceaSAlex Deucher radeon_pm_fini(rdev); 3976d4550907SJerome Glisse r100_cp_fini(rdev); 3977724c80e1SAlex Deucher radeon_wb_fini(rdev); 39782898c348SChristian König radeon_ib_pool_fini(rdev); 3979d4550907SJerome Glisse radeon_gem_fini(rdev); 3980d4550907SJerome Glisse if (rdev->flags & RADEON_IS_PCI) 3981d4550907SJerome Glisse r100_pci_gart_fini(rdev); 3982d0269ed8SJerome Glisse radeon_agp_fini(rdev); 3983d4550907SJerome Glisse radeon_irq_kms_fini(rdev); 3984d4550907SJerome Glisse radeon_fence_driver_fini(rdev); 39854c788679SJerome Glisse radeon_bo_fini(rdev); 3986d4550907SJerome Glisse radeon_atombios_fini(rdev); 3987d4550907SJerome Glisse kfree(rdev->bios); 3988d4550907SJerome Glisse rdev->bios = NULL; 3989d4550907SJerome Glisse } 3990d4550907SJerome Glisse 39914c712e6cSDave Airlie /* 39924c712e6cSDave Airlie * Due to how kexec works, it can leave the hw fully initialised when it 39934c712e6cSDave Airlie * boots the new kernel. However doing our init sequence with the CP and 39944c712e6cSDave Airlie * WB stuff setup causes GPU hangs on the RN50 at least. So at startup 39954c712e6cSDave Airlie * do some quick sanity checks and restore sane values to avoid this 39964c712e6cSDave Airlie * problem. 39974c712e6cSDave Airlie */ 39984c712e6cSDave Airlie void r100_restore_sanity(struct radeon_device *rdev) 39994c712e6cSDave Airlie { 40004c712e6cSDave Airlie u32 tmp; 40014c712e6cSDave Airlie 40024c712e6cSDave Airlie tmp = RREG32(RADEON_CP_CSQ_CNTL); 40034c712e6cSDave Airlie if (tmp) { 40044c712e6cSDave Airlie WREG32(RADEON_CP_CSQ_CNTL, 0); 40054c712e6cSDave Airlie } 40064c712e6cSDave Airlie tmp = RREG32(RADEON_CP_RB_CNTL); 40074c712e6cSDave Airlie if (tmp) { 40084c712e6cSDave Airlie WREG32(RADEON_CP_RB_CNTL, 0); 40094c712e6cSDave Airlie } 40104c712e6cSDave Airlie tmp = RREG32(RADEON_SCRATCH_UMSK); 40114c712e6cSDave Airlie if (tmp) { 40124c712e6cSDave Airlie WREG32(RADEON_SCRATCH_UMSK, 0); 40134c712e6cSDave Airlie } 40144c712e6cSDave Airlie } 40154c712e6cSDave Airlie 4016d4550907SJerome Glisse int r100_init(struct radeon_device *rdev) 4017d4550907SJerome Glisse { 4018d4550907SJerome Glisse int r; 4019d4550907SJerome Glisse 4020d4550907SJerome Glisse /* Register debugfs file specific to this group of asics */ 40215b54d679SNirmoy Das r100_debugfs_mc_info_init(rdev); 4022d4550907SJerome Glisse /* Disable VGA */ 4023d4550907SJerome Glisse r100_vga_render_disable(rdev); 4024d4550907SJerome Glisse /* Initialize scratch registers */ 4025d4550907SJerome Glisse radeon_scratch_init(rdev); 4026d4550907SJerome Glisse /* Initialize surface registers */ 4027d4550907SJerome Glisse radeon_surface_init(rdev); 40284c712e6cSDave Airlie /* sanity check some register to avoid hangs like after kexec */ 40294c712e6cSDave Airlie r100_restore_sanity(rdev); 4030d4550907SJerome Glisse /* TODO: disable VGA need to use VGA request */ 4031d4550907SJerome Glisse /* BIOS*/ 4032d4550907SJerome Glisse if (!radeon_get_bios(rdev)) { 4033d4550907SJerome Glisse if (ASIC_IS_AVIVO(rdev)) 4034d4550907SJerome Glisse return -EINVAL; 4035d4550907SJerome Glisse } 4036d4550907SJerome Glisse if (rdev->is_atom_bios) { 4037d4550907SJerome Glisse dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 4038d4550907SJerome Glisse return -EINVAL; 4039d4550907SJerome Glisse } else { 4040d4550907SJerome Glisse r = radeon_combios_init(rdev); 4041d4550907SJerome Glisse if (r) 4042d4550907SJerome Glisse return r; 4043d4550907SJerome Glisse } 4044d4550907SJerome Glisse /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 4045a2d07b74SJerome Glisse if (radeon_asic_reset(rdev)) { 4046d4550907SJerome Glisse dev_warn(rdev->dev, 4047d4550907SJerome Glisse "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 4048d4550907SJerome Glisse RREG32(R_000E40_RBBM_STATUS), 4049d4550907SJerome Glisse RREG32(R_0007C0_CP_STAT)); 4050d4550907SJerome Glisse } 4051d4550907SJerome Glisse /* check if cards are posted or not */ 405272542d77SDave Airlie if (radeon_boot_test_post_card(rdev) == false) 405372542d77SDave Airlie return -EINVAL; 4054d4550907SJerome Glisse /* Set asic errata */ 4055d4550907SJerome Glisse r100_errata(rdev); 4056d4550907SJerome Glisse /* Initialize clocks */ 4057d4550907SJerome Glisse radeon_get_clock_info(rdev->ddev); 4058d594e46aSJerome Glisse /* initialize AGP */ 4059d594e46aSJerome Glisse if (rdev->flags & RADEON_IS_AGP) { 4060d594e46aSJerome Glisse r = radeon_agp_init(rdev); 4061d594e46aSJerome Glisse if (r) { 4062d594e46aSJerome Glisse radeon_agp_disable(rdev); 4063d594e46aSJerome Glisse } 4064d594e46aSJerome Glisse } 4065d594e46aSJerome Glisse /* initialize VRAM */ 4066d594e46aSJerome Glisse r100_mc_init(rdev); 4067d4550907SJerome Glisse /* Fence driver */ 4068519424d7SBernard Zhao radeon_fence_driver_init(rdev); 4069d4550907SJerome Glisse /* Memory manager */ 40704c788679SJerome Glisse r = radeon_bo_init(rdev); 4071d4550907SJerome Glisse if (r) 4072d4550907SJerome Glisse return r; 4073d4550907SJerome Glisse if (rdev->flags & RADEON_IS_PCI) { 4074d4550907SJerome Glisse r = r100_pci_gart_init(rdev); 4075d4550907SJerome Glisse if (r) 4076d4550907SJerome Glisse return r; 4077d4550907SJerome Glisse } 4078d4550907SJerome Glisse r100_set_safe_registers(rdev); 4079b15ba512SJerome Glisse 40806c7bcceaSAlex Deucher /* Initialize power management */ 40816c7bcceaSAlex Deucher radeon_pm_init(rdev); 40826c7bcceaSAlex Deucher 4083d4550907SJerome Glisse rdev->accel_working = true; 4084d4550907SJerome Glisse r = r100_startup(rdev); 4085d4550907SJerome Glisse if (r) { 4086d4550907SJerome Glisse /* Somethings want wront with the accel init stop accel */ 4087d4550907SJerome Glisse dev_err(rdev->dev, "Disabling GPU acceleration\n"); 4088d4550907SJerome Glisse r100_cp_fini(rdev); 4089724c80e1SAlex Deucher radeon_wb_fini(rdev); 40902898c348SChristian König radeon_ib_pool_fini(rdev); 4091655efd3dSJerome Glisse radeon_irq_kms_fini(rdev); 4092d4550907SJerome Glisse if (rdev->flags & RADEON_IS_PCI) 4093d4550907SJerome Glisse r100_pci_gart_fini(rdev); 4094d4550907SJerome Glisse rdev->accel_working = false; 4095d4550907SJerome Glisse } 4096d4550907SJerome Glisse return 0; 4097d4550907SJerome Glisse } 40986fcbef7aSAndi Kleen 40999e5acbc2SDenys Vlasenko uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg) 41009e5acbc2SDenys Vlasenko { 41019e5acbc2SDenys Vlasenko unsigned long flags; 41029e5acbc2SDenys Vlasenko uint32_t ret; 41039e5acbc2SDenys Vlasenko 41049e5acbc2SDenys Vlasenko spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 41059e5acbc2SDenys Vlasenko writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 41069e5acbc2SDenys Vlasenko ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 41079e5acbc2SDenys Vlasenko spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 41089e5acbc2SDenys Vlasenko return ret; 41099e5acbc2SDenys Vlasenko } 41109e5acbc2SDenys Vlasenko 41119e5acbc2SDenys Vlasenko void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v) 41129e5acbc2SDenys Vlasenko { 41139e5acbc2SDenys Vlasenko unsigned long flags; 41149e5acbc2SDenys Vlasenko 41159e5acbc2SDenys Vlasenko spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 41169e5acbc2SDenys Vlasenko writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 41179e5acbc2SDenys Vlasenko writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 41189e5acbc2SDenys Vlasenko spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 41199e5acbc2SDenys Vlasenko } 41209e5acbc2SDenys Vlasenko 41216fcbef7aSAndi Kleen u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) 41226fcbef7aSAndi Kleen { 41236fcbef7aSAndi Kleen if (reg < rdev->rio_mem_size) 41246fcbef7aSAndi Kleen return ioread32(rdev->rio_mem + reg); 41256fcbef7aSAndi Kleen else { 41266fcbef7aSAndi Kleen iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); 41276fcbef7aSAndi Kleen return ioread32(rdev->rio_mem + RADEON_MM_DATA); 41286fcbef7aSAndi Kleen } 41296fcbef7aSAndi Kleen } 41306fcbef7aSAndi Kleen 41316fcbef7aSAndi Kleen void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) 41326fcbef7aSAndi Kleen { 41336fcbef7aSAndi Kleen if (reg < rdev->rio_mem_size) 41346fcbef7aSAndi Kleen iowrite32(v, rdev->rio_mem + reg); 41356fcbef7aSAndi Kleen else { 41366fcbef7aSAndi Kleen iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); 41376fcbef7aSAndi Kleen iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); 41386fcbef7aSAndi Kleen } 41396fcbef7aSAndi Kleen } 4140