1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef _PPTABLE_H 24 #define _PPTABLE_H 25 26 #pragma pack(push, 1) 27 28 typedef struct _ATOM_PPLIB_THERMALCONTROLLER 29 30 { 31 UCHAR ucType; // one of ATOM_PP_THERMALCONTROLLER_* 32 UCHAR ucI2cLine; // as interpreted by DAL I2C 33 UCHAR ucI2cAddress; 34 UCHAR ucFanParameters; // Fan Control Parameters. 35 UCHAR ucFanMinRPM; // Fan Minimum RPM (hundreds) -- for display purposes only. 36 UCHAR ucFanMaxRPM; // Fan Maximum RPM (hundreds) -- for display purposes only. 37 UCHAR ucReserved; // ---- 38 UCHAR ucFlags; // to be defined 39 } ATOM_PPLIB_THERMALCONTROLLER; 40 41 #define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f 42 #define ATOM_PP_FANPARAMETERS_NOFAN 0x80 // No fan is connected to this controller. 43 44 #define ATOM_PP_THERMALCONTROLLER_NONE 0 45 #define ATOM_PP_THERMALCONTROLLER_LM63 1 // Not used by PPLib 46 #define ATOM_PP_THERMALCONTROLLER_ADM1032 2 // Not used by PPLib 47 #define ATOM_PP_THERMALCONTROLLER_ADM1030 3 // Not used by PPLib 48 #define ATOM_PP_THERMALCONTROLLER_MUA6649 4 // Not used by PPLib 49 #define ATOM_PP_THERMALCONTROLLER_LM64 5 50 #define ATOM_PP_THERMALCONTROLLER_F75375 6 // Not used by PPLib 51 #define ATOM_PP_THERMALCONTROLLER_RV6xx 7 52 #define ATOM_PP_THERMALCONTROLLER_RV770 8 53 #define ATOM_PP_THERMALCONTROLLER_ADT7473 9 54 #define ATOM_PP_THERMALCONTROLLER_KONG 10 55 #define ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO 11 56 #define ATOM_PP_THERMALCONTROLLER_EVERGREEN 12 57 #define ATOM_PP_THERMALCONTROLLER_EMC2103 13 /* 0x0D */ // Only fan control will be implemented, do NOT show this in PPGen. 58 #define ATOM_PP_THERMALCONTROLLER_SUMO 14 /* 0x0E */ // Sumo type, used internally 59 #define ATOM_PP_THERMALCONTROLLER_NISLANDS 15 60 #define ATOM_PP_THERMALCONTROLLER_SISLANDS 16 61 #define ATOM_PP_THERMALCONTROLLER_LM96163 17 62 #define ATOM_PP_THERMALCONTROLLER_CISLANDS 18 63 #define ATOM_PP_THERMALCONTROLLER_KAVERI 19 64 65 66 // Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal. 67 // We probably should reserve the bit 0x80 for this use. 68 // To keep the number of these types low we should also use the same code for all ASICs (i.e. do not distinguish RV6xx and RV7xx Internal here). 69 // The driver can pick the correct internal controller based on the ASIC. 70 71 #define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 // ADT7473 Fan Control + Internal Thermal Controller 72 #define ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL 0x8D // EMC2103 Fan Control + Internal Thermal Controller 73 74 typedef struct _ATOM_PPLIB_STATE 75 { 76 UCHAR ucNonClockStateIndex; 77 UCHAR ucClockStateIndices[1]; // variable-sized 78 } ATOM_PPLIB_STATE; 79 80 81 typedef struct _ATOM_PPLIB_FANTABLE 82 { 83 UCHAR ucFanTableFormat; // Change this if the table format changes or version changes so that the other fields are not the same. 84 UCHAR ucTHyst; // Temperature hysteresis. Integer. 85 USHORT usTMin; // The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. 86 USHORT usTMed; // The middle temperature where we change slopes. 87 USHORT usTHigh; // The high point above TMed for adjusting the second slope. 88 USHORT usPWMMin; // The minimum PWM value in percent (0.01% increments). 89 USHORT usPWMMed; // The PWM value (in percent) at TMed. 90 USHORT usPWMHigh; // The PWM value at THigh. 91 } ATOM_PPLIB_FANTABLE; 92 93 typedef struct _ATOM_PPLIB_FANTABLE2 94 { 95 ATOM_PPLIB_FANTABLE basicTable; 96 USHORT usTMax; // The max temperature 97 } ATOM_PPLIB_FANTABLE2; 98 99 typedef struct _ATOM_PPLIB_EXTENDEDHEADER 100 { 101 USHORT usSize; 102 ULONG ulMaxEngineClock; // For Overdrive. 103 ULONG ulMaxMemoryClock; // For Overdrive. 104 // Add extra system parameters here, always adjust size to include all fields. 105 USHORT usVCETableOffset; //points to ATOM_PPLIB_VCE_Table 106 USHORT usUVDTableOffset; //points to ATOM_PPLIB_UVD_Table 107 USHORT usSAMUTableOffset; //points to ATOM_PPLIB_SAMU_Table 108 USHORT usPPMTableOffset; //points to ATOM_PPLIB_PPM_Table 109 USHORT usACPTableOffset; //points to ATOM_PPLIB_ACP_Table 110 USHORT usPowerTuneTableOffset; //points to ATOM_PPLIB_POWERTUNE_Table 111 } ATOM_PPLIB_EXTENDEDHEADER; 112 113 //// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps 114 #define ATOM_PP_PLATFORM_CAP_BACKBIAS 1 115 #define ATOM_PP_PLATFORM_CAP_POWERPLAY 2 116 #define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4 117 #define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8 118 #define ATOM_PP_PLATFORM_CAP_ASPM_L1 16 119 #define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32 120 #define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64 121 #define ATOM_PP_PLATFORM_CAP_STEPVDDC 128 122 #define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256 123 #define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512 124 #define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024 125 #define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048 126 #define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096 127 #define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition. 128 #define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). 129 #define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does the driver control VDDCI independently from VDDC. 130 #define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature. 131 #define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state. 132 #define ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE 0x00040000 // Does the driver supports new CAC voltage table. 133 #define ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY 0x00080000 // Does the driver supports revert GPIO5 polarity. 134 #define ATOM_PP_PLATFORM_CAP_OUTPUT_THERMAL2GPIO17 0x00100000 // Does the driver supports thermal2GPIO17. 135 #define ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE 0x00200000 // Does the driver supports VR HOT GPIO Configurable. 136 #define ATOM_PP_PLATFORM_CAP_TEMP_INVERSION 0x00400000 // Does the driver supports Temp Inversion feature. 137 #define ATOM_PP_PLATFORM_CAP_EVV 0x00800000 138 139 typedef struct _ATOM_PPLIB_POWERPLAYTABLE 140 { 141 ATOM_COMMON_TABLE_HEADER sHeader; 142 143 UCHAR ucDataRevision; 144 145 UCHAR ucNumStates; 146 UCHAR ucStateEntrySize; 147 UCHAR ucClockInfoSize; 148 UCHAR ucNonClockSize; 149 150 // offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures 151 USHORT usStateArrayOffset; 152 153 // offset from start of this table to array of ASIC-specific structures, 154 // currently ATOM_PPLIB_CLOCK_INFO. 155 USHORT usClockInfoArrayOffset; 156 157 // offset from start of this table to array of ATOM_PPLIB_NONCLOCK_INFO 158 USHORT usNonClockInfoArrayOffset; 159 160 USHORT usBackbiasTime; // in microseconds 161 USHORT usVoltageTime; // in microseconds 162 USHORT usTableSize; //the size of this structure, or the extended structure 163 164 ULONG ulPlatformCaps; // See ATOM_PPLIB_CAPS_* 165 166 ATOM_PPLIB_THERMALCONTROLLER sThermalController; 167 168 USHORT usBootClockInfoOffset; 169 USHORT usBootNonClockInfoOffset; 170 171 } ATOM_PPLIB_POWERPLAYTABLE; 172 173 typedef struct _ATOM_PPLIB_POWERPLAYTABLE2 174 { 175 ATOM_PPLIB_POWERPLAYTABLE basicTable; 176 UCHAR ucNumCustomThermalPolicy; 177 USHORT usCustomThermalPolicyArrayOffset; 178 }ATOM_PPLIB_POWERPLAYTABLE2, *LPATOM_PPLIB_POWERPLAYTABLE2; 179 180 typedef struct _ATOM_PPLIB_POWERPLAYTABLE3 181 { 182 ATOM_PPLIB_POWERPLAYTABLE2 basicTable2; 183 USHORT usFormatID; // To be used ONLY by PPGen. 184 USHORT usFanTableOffset; 185 USHORT usExtendendedHeaderOffset; 186 } ATOM_PPLIB_POWERPLAYTABLE3, *LPATOM_PPLIB_POWERPLAYTABLE3; 187 188 typedef struct _ATOM_PPLIB_POWERPLAYTABLE4 189 { 190 ATOM_PPLIB_POWERPLAYTABLE3 basicTable3; 191 ULONG ulGoldenPPID; // PPGen use only 192 ULONG ulGoldenRevision; // PPGen use only 193 USHORT usVddcDependencyOnSCLKOffset; 194 USHORT usVddciDependencyOnMCLKOffset; 195 USHORT usVddcDependencyOnMCLKOffset; 196 USHORT usMaxClockVoltageOnDCOffset; 197 USHORT usVddcPhaseShedLimitsTableOffset; // Points to ATOM_PPLIB_PhaseSheddingLimits_Table 198 USHORT usMvddDependencyOnMCLKOffset; 199 } ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4; 200 201 typedef struct _ATOM_PPLIB_POWERPLAYTABLE5 202 { 203 ATOM_PPLIB_POWERPLAYTABLE4 basicTable4; 204 ULONG ulTDPLimit; 205 ULONG ulNearTDPLimit; 206 ULONG ulSQRampingThreshold; 207 USHORT usCACLeakageTableOffset; // Points to ATOM_PPLIB_CAC_Leakage_Table 208 ULONG ulCACLeakage; // The iLeakage for driver calculated CAC leakage table 209 USHORT usTDPODLimit; 210 USHORT usLoadLineSlope; // in milliOhms * 100 211 } ATOM_PPLIB_POWERPLAYTABLE5, *LPATOM_PPLIB_POWERPLAYTABLE5; 212 213 //// ATOM_PPLIB_NONCLOCK_INFO::usClassification 214 #define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007 215 #define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0 216 #define ATOM_PPLIB_CLASSIFICATION_UI_NONE 0 217 #define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1 218 #define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3 219 #define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5 220 // 2, 4, 6, 7 are reserved 221 222 #define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008 223 #define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010 224 #define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020 225 #define ATOM_PPLIB_CLASSIFICATION_REST 0x0040 226 #define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080 227 #define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100 228 #define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200 229 #define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400 230 #define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800 231 #define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000 232 #define ATOM_PPLIB_CLASSIFICATION_HD2STATE 0x2000 233 #define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000 234 #define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000 235 236 //// ATOM_PPLIB_NONCLOCK_INFO::usClassification2 237 #define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 0x0001 238 #define ATOM_PPLIB_CLASSIFICATION2_ULV 0x0002 239 #define ATOM_PPLIB_CLASSIFICATION2_MVC 0x0004 //Multi-View Codec (BD-3D) 240 241 //// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings 242 #define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001 243 #define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK 0x00000002 244 245 // 0 is 2.5Gb/s, 1 is 5Gb/s 246 #define ATOM_PPLIB_PCIE_LINK_SPEED_MASK 0x00000004 247 #define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT 2 248 249 // lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec 250 #define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK 0x000000F8 251 #define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT 3 252 253 // lookup into reduced refresh-rate table 254 #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK 0x00000F00 255 #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8 256 257 #define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED 0 258 #define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ 1 259 // 2-15 TBD as needed. 260 261 #define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000 262 #define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000 263 264 #define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000 265 266 #define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000 267 268 //memory related flags 269 #define ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF 0x000010000 270 271 //M3 Arb //2bits, current 3 sets of parameters in total 272 #define ATOM_PPLIB_M3ARB_MASK 0x00060000 273 #define ATOM_PPLIB_M3ARB_SHIFT 17 274 275 #define ATOM_PPLIB_ENABLE_DRR 0x00080000 276 277 // remaining 16 bits are reserved 278 typedef struct _ATOM_PPLIB_THERMAL_STATE 279 { 280 UCHAR ucMinTemperature; 281 UCHAR ucMaxTemperature; 282 UCHAR ucThermalAction; 283 }ATOM_PPLIB_THERMAL_STATE, *LPATOM_PPLIB_THERMAL_STATE; 284 285 // Contained in an array starting at the offset 286 // in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset. 287 // referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex 288 #define ATOM_PPLIB_NONCLOCKINFO_VER1 12 289 #define ATOM_PPLIB_NONCLOCKINFO_VER2 24 290 typedef struct _ATOM_PPLIB_NONCLOCK_INFO 291 { 292 USHORT usClassification; 293 UCHAR ucMinTemperature; 294 UCHAR ucMaxTemperature; 295 ULONG ulCapsAndSettings; 296 UCHAR ucRequiredPower; 297 USHORT usClassification2; 298 ULONG ulVCLK; 299 ULONG ulDCLK; 300 UCHAR ucUnused[5]; 301 } ATOM_PPLIB_NONCLOCK_INFO; 302 303 // Contained in an array starting at the offset 304 // in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset. 305 // referenced from ATOM_PPLIB_STATE::ucClockStateIndices 306 typedef struct _ATOM_PPLIB_R600_CLOCK_INFO 307 { 308 USHORT usEngineClockLow; 309 UCHAR ucEngineClockHigh; 310 311 USHORT usMemoryClockLow; 312 UCHAR ucMemoryClockHigh; 313 314 USHORT usVDDC; 315 USHORT usUnused1; 316 USHORT usUnused2; 317 318 ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* 319 320 } ATOM_PPLIB_R600_CLOCK_INFO; 321 322 // ulFlags in ATOM_PPLIB_R600_CLOCK_INFO 323 #define ATOM_PPLIB_R600_FLAGS_PCIEGEN2 1 324 #define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2 325 #define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4 326 #define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8 327 #define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16 328 #define ATOM_PPLIB_R600_FLAGS_LOWPOWER 32 // On the RV770 use 'low power' setting (sequencer S0). 329 330 typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO 331 332 { 333 USHORT usLowEngineClockLow; // Low Engine clock in MHz (the same way as on the R600). 334 UCHAR ucLowEngineClockHigh; 335 USHORT usHighEngineClockLow; // High Engine clock in MHz. 336 UCHAR ucHighEngineClockHigh; 337 USHORT usMemoryClockLow; // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants. 338 UCHAR ucMemoryClockHigh; // Currentyl unused. 339 UCHAR ucPadding; // For proper alignment and size. 340 USHORT usVDDC; // For the 780, use: None, Low, High, Variable 341 UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16} 342 UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could 343 USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200). 344 ULONG ulFlags; 345 } ATOM_PPLIB_RS780_CLOCK_INFO; 346 347 #define ATOM_PPLIB_RS780_VOLTAGE_NONE 0 348 #define ATOM_PPLIB_RS780_VOLTAGE_LOW 1 349 #define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2 350 #define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3 351 352 #define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is. 353 #define ATOM_PPLIB_RS780_SPMCLK_LOW 1 354 #define ATOM_PPLIB_RS780_SPMCLK_HIGH 2 355 356 #define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0 357 #define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1 358 #define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2 359 360 typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO 361 { 362 USHORT usEngineClockLow; 363 UCHAR ucEngineClockHigh; 364 365 USHORT usMemoryClockLow; 366 UCHAR ucMemoryClockHigh; 367 368 USHORT usVDDC; 369 USHORT usVDDCI; 370 USHORT usUnused; 371 372 ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* 373 374 } ATOM_PPLIB_EVERGREEN_CLOCK_INFO; 375 376 typedef struct _ATOM_PPLIB_SI_CLOCK_INFO 377 { 378 USHORT usEngineClockLow; 379 UCHAR ucEngineClockHigh; 380 381 USHORT usMemoryClockLow; 382 UCHAR ucMemoryClockHigh; 383 384 USHORT usVDDC; 385 USHORT usVDDCI; 386 UCHAR ucPCIEGen; 387 UCHAR ucUnused1; 388 389 ULONG ulFlags; // ATOM_PPLIB_SI_FLAGS_*, no flag is necessary for now 390 391 } ATOM_PPLIB_SI_CLOCK_INFO; 392 393 typedef struct _ATOM_PPLIB_CI_CLOCK_INFO 394 { 395 USHORT usEngineClockLow; 396 UCHAR ucEngineClockHigh; 397 398 USHORT usMemoryClockLow; 399 UCHAR ucMemoryClockHigh; 400 401 UCHAR ucPCIEGen; 402 USHORT usPCIELane; 403 } ATOM_PPLIB_CI_CLOCK_INFO; 404 405 typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{ 406 USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz 407 UCHAR ucEngineClockHigh; //clockfrequency >> 16. 408 UCHAR vddcIndex; //2-bit vddc index; 409 USHORT tdpLimit; 410 //please initalize to 0 411 USHORT rsv1; 412 //please initialize to 0s 413 ULONG rsv2[2]; 414 }ATOM_PPLIB_SUMO_CLOCK_INFO; 415 416 typedef struct _ATOM_PPLIB_STATE_V2 417 { 418 //number of valid dpm levels in this state; Driver uses it to calculate the whole 419 //size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR) 420 UCHAR ucNumDPMLevels; 421 422 //a index to the array of nonClockInfos 423 UCHAR nonClockInfoIndex; 424 /** 425 * Driver will read the first ucNumDPMLevels in this array 426 */ 427 UCHAR clockInfoIndex[1]; 428 } ATOM_PPLIB_STATE_V2; 429 430 typedef struct _StateArray{ 431 //how many states we have 432 UCHAR ucNumEntries; 433 434 ATOM_PPLIB_STATE_V2 states[1]; 435 }StateArray; 436 437 438 typedef struct _ClockInfoArray{ 439 //how many clock levels we have 440 UCHAR ucNumEntries; 441 442 //sizeof(ATOM_PPLIB_CLOCK_INFO) 443 UCHAR ucEntrySize; 444 445 UCHAR clockInfo[1]; 446 }ClockInfoArray; 447 448 typedef struct _NonClockInfoArray{ 449 450 //how many non-clock levels we have. normally should be same as number of states 451 UCHAR ucNumEntries; 452 //sizeof(ATOM_PPLIB_NONCLOCK_INFO) 453 UCHAR ucEntrySize; 454 455 ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1]; 456 }NonClockInfoArray; 457 458 typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record 459 { 460 USHORT usClockLow; 461 UCHAR ucClockHigh; 462 USHORT usVoltage; 463 }ATOM_PPLIB_Clock_Voltage_Dependency_Record; 464 465 typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Table 466 { 467 UCHAR ucNumEntries; // Number of entries. 468 ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[1]; // Dynamically allocate entries. 469 }ATOM_PPLIB_Clock_Voltage_Dependency_Table; 470 471 typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record 472 { 473 USHORT usSclkLow; 474 UCHAR ucSclkHigh; 475 USHORT usMclkLow; 476 UCHAR ucMclkHigh; 477 USHORT usVddc; 478 USHORT usVddci; 479 }ATOM_PPLIB_Clock_Voltage_Limit_Record; 480 481 typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table 482 { 483 UCHAR ucNumEntries; // Number of entries. 484 ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1]; // Dynamically allocate entries. 485 }ATOM_PPLIB_Clock_Voltage_Limit_Table; 486 487 union _ATOM_PPLIB_CAC_Leakage_Record 488 { 489 struct 490 { 491 USHORT usVddc; // We use this field for the "fake" standardized VDDC for power calculations; For CI and newer, we use this as the real VDDC value. in CI we read it as StdVoltageHiSidd 492 ULONG ulLeakageValue; // For CI and newer we use this as the "fake" standar VDDC value. in CI we read it as StdVoltageLoSidd 493 494 }; 495 struct 496 { 497 USHORT usVddc1; 498 USHORT usVddc2; 499 USHORT usVddc3; 500 }; 501 }; 502 503 typedef union _ATOM_PPLIB_CAC_Leakage_Record ATOM_PPLIB_CAC_Leakage_Record; 504 505 typedef struct _ATOM_PPLIB_CAC_Leakage_Table 506 { 507 UCHAR ucNumEntries; // Number of entries. 508 ATOM_PPLIB_CAC_Leakage_Record entries[1]; // Dynamically allocate entries. 509 }ATOM_PPLIB_CAC_Leakage_Table; 510 511 typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record 512 { 513 USHORT usVoltage; 514 USHORT usSclkLow; 515 UCHAR ucSclkHigh; 516 USHORT usMclkLow; 517 UCHAR ucMclkHigh; 518 }ATOM_PPLIB_PhaseSheddingLimits_Record; 519 520 typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Table 521 { 522 UCHAR ucNumEntries; // Number of entries. 523 ATOM_PPLIB_PhaseSheddingLimits_Record entries[1]; // Dynamically allocate entries. 524 }ATOM_PPLIB_PhaseSheddingLimits_Table; 525 526 typedef struct _VCEClockInfo{ 527 USHORT usEVClkLow; 528 UCHAR ucEVClkHigh; 529 USHORT usECClkLow; 530 UCHAR ucECClkHigh; 531 }VCEClockInfo; 532 533 typedef struct _VCEClockInfoArray{ 534 UCHAR ucNumEntries; 535 VCEClockInfo entries[1]; 536 }VCEClockInfoArray; 537 538 typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record 539 { 540 USHORT usVoltage; 541 UCHAR ucVCEClockInfoIndex; 542 }ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record; 543 544 typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table 545 { 546 UCHAR numEntries; 547 ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record entries[1]; 548 }ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table; 549 550 typedef struct _ATOM_PPLIB_VCE_State_Record 551 { 552 UCHAR ucVCEClockInfoIndex; 553 UCHAR ucClockInfoIndex; //highest 2 bits indicates memory p-states, lower 6bits indicates index to ClockInfoArrary 554 }ATOM_PPLIB_VCE_State_Record; 555 556 typedef struct _ATOM_PPLIB_VCE_State_Table 557 { 558 UCHAR numEntries; 559 ATOM_PPLIB_VCE_State_Record entries[1]; 560 }ATOM_PPLIB_VCE_State_Table; 561 562 563 typedef struct _ATOM_PPLIB_VCE_Table 564 { 565 UCHAR revid; 566 // VCEClockInfoArray array; 567 // ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table limits; 568 // ATOM_PPLIB_VCE_State_Table states; 569 }ATOM_PPLIB_VCE_Table; 570 571 572 typedef struct _UVDClockInfo{ 573 USHORT usVClkLow; 574 UCHAR ucVClkHigh; 575 USHORT usDClkLow; 576 UCHAR ucDClkHigh; 577 }UVDClockInfo; 578 579 typedef struct _UVDClockInfoArray{ 580 UCHAR ucNumEntries; 581 UVDClockInfo entries[1]; 582 }UVDClockInfoArray; 583 584 typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record 585 { 586 USHORT usVoltage; 587 UCHAR ucUVDClockInfoIndex; 588 }ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record; 589 590 typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table 591 { 592 UCHAR numEntries; 593 ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record entries[1]; 594 }ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table; 595 596 typedef struct _ATOM_PPLIB_UVD_Table 597 { 598 UCHAR revid; 599 // UVDClockInfoArray array; 600 // ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table limits; 601 }ATOM_PPLIB_UVD_Table; 602 603 typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Record 604 { 605 USHORT usVoltage; 606 USHORT usSAMClockLow; 607 UCHAR ucSAMClockHigh; 608 }ATOM_PPLIB_SAMClk_Voltage_Limit_Record; 609 610 typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Table{ 611 UCHAR numEntries; 612 ATOM_PPLIB_SAMClk_Voltage_Limit_Record entries[1]; 613 }ATOM_PPLIB_SAMClk_Voltage_Limit_Table; 614 615 typedef struct _ATOM_PPLIB_SAMU_Table 616 { 617 UCHAR revid; 618 ATOM_PPLIB_SAMClk_Voltage_Limit_Table limits; 619 }ATOM_PPLIB_SAMU_Table; 620 621 typedef struct _ATOM_PPLIB_ACPClk_Voltage_Limit_Record 622 { 623 USHORT usVoltage; 624 USHORT usACPClockLow; 625 UCHAR ucACPClockHigh; 626 }ATOM_PPLIB_ACPClk_Voltage_Limit_Record; 627 628 typedef struct _ATOM_PPLIB_ACPClk_Voltage_Limit_Table{ 629 UCHAR numEntries; 630 ATOM_PPLIB_ACPClk_Voltage_Limit_Record entries[1]; 631 }ATOM_PPLIB_ACPClk_Voltage_Limit_Table; 632 633 typedef struct _ATOM_PPLIB_ACP_Table 634 { 635 UCHAR revid; 636 ATOM_PPLIB_ACPClk_Voltage_Limit_Table limits; 637 }ATOM_PPLIB_ACP_Table; 638 639 typedef struct _ATOM_PowerTune_Table{ 640 USHORT usTDP; 641 USHORT usConfigurableTDP; 642 USHORT usTDC; 643 USHORT usBatteryPowerLimit; 644 USHORT usSmallPowerLimit; 645 USHORT usLowCACLeakage; 646 USHORT usHighCACLeakage; 647 }ATOM_PowerTune_Table; 648 649 typedef struct _ATOM_PPLIB_POWERTUNE_Table 650 { 651 UCHAR revid; 652 ATOM_PowerTune_Table power_tune_table; 653 }ATOM_PPLIB_POWERTUNE_Table; 654 655 typedef struct _ATOM_PPLIB_POWERTUNE_Table_V1 656 { 657 UCHAR revid; 658 ATOM_PowerTune_Table power_tune_table; 659 USHORT usMaximumPowerDeliveryLimit; 660 USHORT usReserve[7]; 661 } ATOM_PPLIB_POWERTUNE_Table_V1; 662 663 #define ATOM_PPM_A_A 1 664 #define ATOM_PPM_A_I 2 665 typedef struct _ATOM_PPLIB_PPM_Table 666 { 667 UCHAR ucRevId; 668 UCHAR ucPpmDesign; //A+I or A+A 669 USHORT usCpuCoreNumber; 670 ULONG ulPlatformTDP; 671 ULONG ulSmallACPlatformTDP; 672 ULONG ulPlatformTDC; 673 ULONG ulSmallACPlatformTDC; 674 ULONG ulApuTDP; 675 ULONG ulDGpuTDP; 676 ULONG ulDGpuUlvPower; 677 ULONG ulTjmax; 678 } ATOM_PPLIB_PPM_Table; 679 680 #pragma pack(pop) 681 682 #endif 683