1 /* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #ifndef NI_H 25 #define NI_H 26 27 #define CAYMAN_MAX_SH_GPRS 256 28 #define CAYMAN_MAX_TEMP_GPRS 16 29 #define CAYMAN_MAX_SH_THREADS 256 30 #define CAYMAN_MAX_SH_STACK_ENTRIES 4096 31 #define CAYMAN_MAX_FRC_EOV_CNT 16384 32 #define CAYMAN_MAX_BACKENDS 8 33 #define CAYMAN_MAX_BACKENDS_MASK 0xFF 34 #define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF 35 #define CAYMAN_MAX_SIMDS 16 36 #define CAYMAN_MAX_SIMDS_MASK 0xFFFF 37 #define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF 38 #define CAYMAN_MAX_PIPES 8 39 #define CAYMAN_MAX_PIPES_MASK 0xFF 40 #define CAYMAN_MAX_LDS_NUM 0xFFFF 41 #define CAYMAN_MAX_TCC 16 42 #define CAYMAN_MAX_TCC_MASK 0xFF 43 44 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 45 #define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001 46 47 #define DMIF_ADDR_CONFIG 0xBD4 48 #define SRBM_GFX_CNTL 0x0E44 49 #define RINGID(x) (((x) & 0x3) << 0) 50 #define VMID(x) (((x) & 0x7) << 0) 51 #define SRBM_STATUS 0x0E50 52 53 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 54 #define REQUEST_TYPE(x) (((x) & 0xf) << 0) 55 #define RESPONSE_TYPE_MASK 0x000000F0 56 #define RESPONSE_TYPE_SHIFT 4 57 #define VM_L2_CNTL 0x1400 58 #define ENABLE_L2_CACHE (1 << 0) 59 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 60 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 61 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 62 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 63 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 18) 64 /* CONTEXT1_IDENTITY_ACCESS_MODE 65 * 0 physical = logical 66 * 1 logical via context1 page table 67 * 2 inside identity aperture use translation, outside physical = logical 68 * 3 inside identity aperture physical = logical, outside use translation 69 */ 70 #define VM_L2_CNTL2 0x1404 71 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 72 #define INVALIDATE_L2_CACHE (1 << 1) 73 #define VM_L2_CNTL3 0x1408 74 #define BANK_SELECT(x) ((x) << 0) 75 #define CACHE_UPDATE_MODE(x) ((x) << 6) 76 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 77 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 78 #define VM_L2_STATUS 0x140C 79 #define L2_BUSY (1 << 0) 80 #define VM_CONTEXT0_CNTL 0x1410 81 #define ENABLE_CONTEXT (1 << 0) 82 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 83 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 84 #define VM_CONTEXT1_CNTL 0x1414 85 #define VM_CONTEXT0_CNTL2 0x1430 86 #define VM_CONTEXT1_CNTL2 0x1434 87 #define VM_INVALIDATE_REQUEST 0x1478 88 #define VM_INVALIDATE_RESPONSE 0x147c 89 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 90 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 91 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 92 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 93 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 94 95 #define MC_SHARED_CHMAP 0x2004 96 #define NOOFCHAN_SHIFT 12 97 #define NOOFCHAN_MASK 0x00003000 98 #define MC_SHARED_CHREMAP 0x2008 99 100 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 101 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 102 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 103 #define MC_VM_MX_L1_TLB_CNTL 0x2064 104 #define ENABLE_L1_TLB (1 << 0) 105 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 106 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 107 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 108 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 109 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 110 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 111 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 112 #define FUS_MC_VM_FB_OFFSET 0x2068 113 114 #define MC_SHARED_BLACKOUT_CNTL 0x20ac 115 #define MC_ARB_RAMCFG 0x2760 116 #define NOOFBANK_SHIFT 0 117 #define NOOFBANK_MASK 0x00000003 118 #define NOOFRANK_SHIFT 2 119 #define NOOFRANK_MASK 0x00000004 120 #define NOOFROWS_SHIFT 3 121 #define NOOFROWS_MASK 0x00000038 122 #define NOOFCOLS_SHIFT 6 123 #define NOOFCOLS_MASK 0x000000C0 124 #define CHANSIZE_SHIFT 8 125 #define CHANSIZE_MASK 0x00000100 126 #define BURSTLENGTH_SHIFT 9 127 #define BURSTLENGTH_MASK 0x00000200 128 #define CHANSIZE_OVERRIDE (1 << 11) 129 #define MC_SEQ_SUP_CNTL 0x28c8 130 #define RUN_MASK (1 << 0) 131 #define MC_SEQ_SUP_PGM 0x28cc 132 #define MC_IO_PAD_CNTL_D0 0x29d0 133 #define MEM_FALL_OUT_CMD (1 << 8) 134 #define MC_SEQ_MISC0 0x2a00 135 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 136 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 137 #define MC_SEQ_MISC0_GDDR5_VALUE 5 138 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 139 #define MC_SEQ_IO_DEBUG_DATA 0x2a48 140 141 #define HDP_HOST_PATH_CNTL 0x2C00 142 #define HDP_NONSURFACE_BASE 0x2C04 143 #define HDP_NONSURFACE_INFO 0x2C08 144 #define HDP_NONSURFACE_SIZE 0x2C0C 145 #define HDP_ADDR_CONFIG 0x2F48 146 #define HDP_MISC_CNTL 0x2F4C 147 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 148 149 #define CC_SYS_RB_BACKEND_DISABLE 0x3F88 150 #define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C 151 #define CGTS_SYS_TCC_DISABLE 0x3F90 152 #define CGTS_USER_SYS_TCC_DISABLE 0x3F94 153 154 #define RLC_GFX_INDEX 0x3FC4 155 156 #define CONFIG_MEMSIZE 0x5428 157 158 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 159 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 160 161 #define GRBM_CNTL 0x8000 162 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 163 #define GRBM_STATUS 0x8010 164 #define CMDFIFO_AVAIL_MASK 0x0000000F 165 #define RING2_RQ_PENDING (1 << 4) 166 #define SRBM_RQ_PENDING (1 << 5) 167 #define RING1_RQ_PENDING (1 << 6) 168 #define CF_RQ_PENDING (1 << 7) 169 #define PF_RQ_PENDING (1 << 8) 170 #define GDS_DMA_RQ_PENDING (1 << 9) 171 #define GRBM_EE_BUSY (1 << 10) 172 #define SX_CLEAN (1 << 11) 173 #define DB_CLEAN (1 << 12) 174 #define CB_CLEAN (1 << 13) 175 #define TA_BUSY (1 << 14) 176 #define GDS_BUSY (1 << 15) 177 #define VGT_BUSY_NO_DMA (1 << 16) 178 #define VGT_BUSY (1 << 17) 179 #define IA_BUSY_NO_DMA (1 << 18) 180 #define IA_BUSY (1 << 19) 181 #define SX_BUSY (1 << 20) 182 #define SH_BUSY (1 << 21) 183 #define SPI_BUSY (1 << 22) 184 #define SC_BUSY (1 << 24) 185 #define PA_BUSY (1 << 25) 186 #define DB_BUSY (1 << 26) 187 #define CP_COHERENCY_BUSY (1 << 28) 188 #define CP_BUSY (1 << 29) 189 #define CB_BUSY (1 << 30) 190 #define GUI_ACTIVE (1 << 31) 191 #define GRBM_STATUS_SE0 0x8014 192 #define GRBM_STATUS_SE1 0x8018 193 #define SE_SX_CLEAN (1 << 0) 194 #define SE_DB_CLEAN (1 << 1) 195 #define SE_CB_CLEAN (1 << 2) 196 #define SE_VGT_BUSY (1 << 23) 197 #define SE_PA_BUSY (1 << 24) 198 #define SE_TA_BUSY (1 << 25) 199 #define SE_SX_BUSY (1 << 26) 200 #define SE_SPI_BUSY (1 << 27) 201 #define SE_SH_BUSY (1 << 28) 202 #define SE_SC_BUSY (1 << 29) 203 #define SE_DB_BUSY (1 << 30) 204 #define SE_CB_BUSY (1 << 31) 205 #define GRBM_SOFT_RESET 0x8020 206 #define SOFT_RESET_CP (1 << 0) 207 #define SOFT_RESET_CB (1 << 1) 208 #define SOFT_RESET_DB (1 << 3) 209 #define SOFT_RESET_GDS (1 << 4) 210 #define SOFT_RESET_PA (1 << 5) 211 #define SOFT_RESET_SC (1 << 6) 212 #define SOFT_RESET_SPI (1 << 8) 213 #define SOFT_RESET_SH (1 << 9) 214 #define SOFT_RESET_SX (1 << 10) 215 #define SOFT_RESET_TC (1 << 11) 216 #define SOFT_RESET_TA (1 << 12) 217 #define SOFT_RESET_VGT (1 << 14) 218 #define SOFT_RESET_IA (1 << 15) 219 220 #define GRBM_GFX_INDEX 0x802C 221 #define INSTANCE_INDEX(x) ((x) << 0) 222 #define SE_INDEX(x) ((x) << 16) 223 #define INSTANCE_BROADCAST_WRITES (1 << 30) 224 #define SE_BROADCAST_WRITES (1 << 31) 225 226 #define SCRATCH_REG0 0x8500 227 #define SCRATCH_REG1 0x8504 228 #define SCRATCH_REG2 0x8508 229 #define SCRATCH_REG3 0x850C 230 #define SCRATCH_REG4 0x8510 231 #define SCRATCH_REG5 0x8514 232 #define SCRATCH_REG6 0x8518 233 #define SCRATCH_REG7 0x851C 234 #define SCRATCH_UMSK 0x8540 235 #define SCRATCH_ADDR 0x8544 236 #define CP_SEM_WAIT_TIMER 0x85BC 237 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 238 #define CP_COHER_CNTL2 0x85E8 239 #define CP_STALLED_STAT1 0x8674 240 #define CP_STALLED_STAT2 0x8678 241 #define CP_BUSY_STAT 0x867C 242 #define CP_STAT 0x8680 243 #define CP_ME_CNTL 0x86D8 244 #define CP_ME_HALT (1 << 28) 245 #define CP_PFP_HALT (1 << 26) 246 #define CP_RB2_RPTR 0x86f8 247 #define CP_RB1_RPTR 0x86fc 248 #define CP_RB0_RPTR 0x8700 249 #define CP_RB_WPTR_DELAY 0x8704 250 #define CP_MEQ_THRESHOLDS 0x8764 251 #define MEQ1_START(x) ((x) << 0) 252 #define MEQ2_START(x) ((x) << 8) 253 #define CP_PERFMON_CNTL 0x87FC 254 255 #define VGT_CACHE_INVALIDATION 0x88C4 256 #define CACHE_INVALIDATION(x) ((x) << 0) 257 #define VC_ONLY 0 258 #define TC_ONLY 1 259 #define VC_AND_TC 2 260 #define AUTO_INVLD_EN(x) ((x) << 6) 261 #define NO_AUTO 0 262 #define ES_AUTO 1 263 #define GS_AUTO 2 264 #define ES_AND_GS_AUTO 3 265 #define VGT_GS_VERTEX_REUSE 0x88D4 266 267 #define CC_GC_SHADER_PIPE_CONFIG 0x8950 268 #define GC_USER_SHADER_PIPE_CONFIG 0x8954 269 #define INACTIVE_QD_PIPES(x) ((x) << 8) 270 #define INACTIVE_QD_PIPES_MASK 0x0000FF00 271 #define INACTIVE_QD_PIPES_SHIFT 8 272 #define INACTIVE_SIMDS(x) ((x) << 16) 273 #define INACTIVE_SIMDS_MASK 0xFFFF0000 274 #define INACTIVE_SIMDS_SHIFT 16 275 276 #define VGT_PRIMITIVE_TYPE 0x8958 277 #define VGT_NUM_INSTANCES 0x8974 278 #define VGT_TF_RING_SIZE 0x8988 279 #define VGT_OFFCHIP_LDS_BASE 0x89b4 280 281 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 282 #define PA_CL_ENHANCE 0x8A14 283 #define CLIP_VTX_REORDER_ENA (1 << 0) 284 #define NUM_CLIP_SEQ(x) ((x) << 1) 285 #define PA_SC_FIFO_SIZE 0x8BCC 286 #define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 287 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 288 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 289 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 290 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 291 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 292 293 #define SQ_CONFIG 0x8C00 294 #define VC_ENABLE (1 << 0) 295 #define EXPORT_SRC_C (1 << 1) 296 #define GFX_PRIO(x) ((x) << 2) 297 #define CS1_PRIO(x) ((x) << 4) 298 #define CS2_PRIO(x) ((x) << 6) 299 #define SQ_GPR_RESOURCE_MGMT_1 0x8C04 300 #define NUM_PS_GPRS(x) ((x) << 0) 301 #define NUM_VS_GPRS(x) ((x) << 16) 302 #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 303 #define SQ_ESGS_RING_SIZE 0x8c44 304 #define SQ_GSVS_RING_SIZE 0x8c4c 305 #define SQ_ESTMP_RING_BASE 0x8c50 306 #define SQ_ESTMP_RING_SIZE 0x8c54 307 #define SQ_GSTMP_RING_BASE 0x8c58 308 #define SQ_GSTMP_RING_SIZE 0x8c5c 309 #define SQ_VSTMP_RING_BASE 0x8c60 310 #define SQ_VSTMP_RING_SIZE 0x8c64 311 #define SQ_PSTMP_RING_BASE 0x8c68 312 #define SQ_PSTMP_RING_SIZE 0x8c6c 313 #define SQ_MS_FIFO_SIZES 0x8CF0 314 #define CACHE_FIFO_SIZE(x) ((x) << 0) 315 #define FETCH_FIFO_HIWATER(x) ((x) << 8) 316 #define DONE_FIFO_HIWATER(x) ((x) << 16) 317 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 318 #define SQ_LSTMP_RING_BASE 0x8e10 319 #define SQ_LSTMP_RING_SIZE 0x8e14 320 #define SQ_HSTMP_RING_BASE 0x8e18 321 #define SQ_HSTMP_RING_SIZE 0x8e1c 322 #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C 323 #define DYN_GPR_ENABLE (1 << 8) 324 #define SQ_CONST_MEM_BASE 0x8df8 325 326 #define SX_EXPORT_BUFFER_SIZES 0x900C 327 #define COLOR_BUFFER_SIZE(x) ((x) << 0) 328 #define POSITION_BUFFER_SIZE(x) ((x) << 8) 329 #define SMX_BUFFER_SIZE(x) ((x) << 16) 330 #define SX_DEBUG_1 0x9058 331 #define ENABLE_NEW_SMX_ADDRESS (1 << 16) 332 333 #define SPI_CONFIG_CNTL 0x9100 334 #define GPR_WRITE_PRIORITY(x) ((x) << 0) 335 #define SPI_CONFIG_CNTL_1 0x913C 336 #define VTX_DONE_DELAY(x) ((x) << 0) 337 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 338 #define CRC_SIMD_ID_WADDR_DISABLE (1 << 8) 339 340 #define CGTS_TCC_DISABLE 0x9148 341 #define CGTS_USER_TCC_DISABLE 0x914C 342 #define TCC_DISABLE_MASK 0xFFFF0000 343 #define TCC_DISABLE_SHIFT 16 344 #define CGTS_SM_CTRL_REG 0x9150 345 #define OVERRIDE (1 << 21) 346 347 #define TA_CNTL_AUX 0x9508 348 #define DISABLE_CUBE_WRAP (1 << 0) 349 #define DISABLE_CUBE_ANISO (1 << 1) 350 351 #define TCP_CHAN_STEER_LO 0x960c 352 #define TCP_CHAN_STEER_HI 0x9610 353 354 #define CC_RB_BACKEND_DISABLE 0x98F4 355 #define BACKEND_DISABLE(x) ((x) << 16) 356 #define GB_ADDR_CONFIG 0x98F8 357 #define NUM_PIPES(x) ((x) << 0) 358 #define NUM_PIPES_MASK 0x00000007 359 #define NUM_PIPES_SHIFT 0 360 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 361 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 362 #define PIPE_INTERLEAVE_SIZE_SHIFT 4 363 #define BANK_INTERLEAVE_SIZE(x) ((x) << 8) 364 #define NUM_SHADER_ENGINES(x) ((x) << 12) 365 #define NUM_SHADER_ENGINES_MASK 0x00003000 366 #define NUM_SHADER_ENGINES_SHIFT 12 367 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 368 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 369 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 370 #define NUM_GPUS(x) ((x) << 20) 371 #define NUM_GPUS_MASK 0x00700000 372 #define NUM_GPUS_SHIFT 20 373 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 374 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000 375 #define MULTI_GPU_TILE_SIZE_SHIFT 24 376 #define ROW_SIZE(x) ((x) << 28) 377 #define ROW_SIZE_MASK 0x30000000 378 #define ROW_SIZE_SHIFT 28 379 #define NUM_LOWER_PIPES(x) ((x) << 30) 380 #define NUM_LOWER_PIPES_MASK 0x40000000 381 #define NUM_LOWER_PIPES_SHIFT 30 382 #define GB_BACKEND_MAP 0x98FC 383 384 #define CB_PERF_CTR0_SEL_0 0x9A20 385 #define CB_PERF_CTR0_SEL_1 0x9A24 386 #define CB_PERF_CTR1_SEL_0 0x9A28 387 #define CB_PERF_CTR1_SEL_1 0x9A2C 388 #define CB_PERF_CTR2_SEL_0 0x9A30 389 #define CB_PERF_CTR2_SEL_1 0x9A34 390 #define CB_PERF_CTR3_SEL_0 0x9A38 391 #define CB_PERF_CTR3_SEL_1 0x9A3C 392 393 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 394 #define BACKEND_DISABLE_MASK 0x00FF0000 395 #define BACKEND_DISABLE_SHIFT 16 396 397 #define SMX_DC_CTL0 0xA020 398 #define USE_HASH_FUNCTION (1 << 0) 399 #define NUMBER_OF_SETS(x) ((x) << 1) 400 #define FLUSH_ALL_ON_EVENT (1 << 10) 401 #define STALL_ON_EVENT (1 << 11) 402 #define SMX_EVENT_CTL 0xA02C 403 #define ES_FLUSH_CTL(x) ((x) << 0) 404 #define GS_FLUSH_CTL(x) ((x) << 3) 405 #define ACK_FLUSH_CTL(x) ((x) << 6) 406 #define SYNC_FLUSH_CTL (1 << 8) 407 408 #define CP_RB0_BASE 0xC100 409 #define CP_RB0_CNTL 0xC104 410 #define RB_BUFSZ(x) ((x) << 0) 411 #define RB_BLKSZ(x) ((x) << 8) 412 #define RB_NO_UPDATE (1 << 27) 413 #define RB_RPTR_WR_ENA (1 << 31) 414 #define BUF_SWAP_32BIT (2 << 16) 415 #define CP_RB0_RPTR_ADDR 0xC10C 416 #define CP_RB0_RPTR_ADDR_HI 0xC110 417 #define CP_RB0_WPTR 0xC114 418 419 #define CP_INT_CNTL 0xC124 420 # define CNTX_BUSY_INT_ENABLE (1 << 19) 421 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 422 # define TIME_STAMP_INT_ENABLE (1 << 26) 423 424 #define CP_RB1_BASE 0xC180 425 #define CP_RB1_CNTL 0xC184 426 #define CP_RB1_RPTR_ADDR 0xC188 427 #define CP_RB1_RPTR_ADDR_HI 0xC18C 428 #define CP_RB1_WPTR 0xC190 429 #define CP_RB2_BASE 0xC194 430 #define CP_RB2_CNTL 0xC198 431 #define CP_RB2_RPTR_ADDR 0xC19C 432 #define CP_RB2_RPTR_ADDR_HI 0xC1A0 433 #define CP_RB2_WPTR 0xC1A4 434 #define CP_PFP_UCODE_ADDR 0xC150 435 #define CP_PFP_UCODE_DATA 0xC154 436 #define CP_ME_RAM_RADDR 0xC158 437 #define CP_ME_RAM_WADDR 0xC15C 438 #define CP_ME_RAM_DATA 0xC160 439 #define CP_DEBUG 0xC1FC 440 441 #define VGT_EVENT_INITIATOR 0x28a90 442 # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) 443 # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 444 445 /* 446 * PM4 447 */ 448 #define PACKET_TYPE0 0 449 #define PACKET_TYPE1 1 450 #define PACKET_TYPE2 2 451 #define PACKET_TYPE3 3 452 453 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 454 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 455 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 456 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 457 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 458 (((reg) >> 2) & 0xFFFF) | \ 459 ((n) & 0x3FFF) << 16) 460 #define CP_PACKET2 0x80000000 461 #define PACKET2_PAD_SHIFT 0 462 #define PACKET2_PAD_MASK (0x3fffffff << 0) 463 464 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 465 466 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 467 (((op) & 0xFF) << 8) | \ 468 ((n) & 0x3FFF) << 16) 469 470 /* Packet 3 types */ 471 #define PACKET3_NOP 0x10 472 #define PACKET3_SET_BASE 0x11 473 #define PACKET3_CLEAR_STATE 0x12 474 #define PACKET3_INDEX_BUFFER_SIZE 0x13 475 #define PACKET3_DEALLOC_STATE 0x14 476 #define PACKET3_DISPATCH_DIRECT 0x15 477 #define PACKET3_DISPATCH_INDIRECT 0x16 478 #define PACKET3_INDIRECT_BUFFER_END 0x17 479 #define PACKET3_MODE_CONTROL 0x18 480 #define PACKET3_SET_PREDICATION 0x20 481 #define PACKET3_REG_RMW 0x21 482 #define PACKET3_COND_EXEC 0x22 483 #define PACKET3_PRED_EXEC 0x23 484 #define PACKET3_DRAW_INDIRECT 0x24 485 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 486 #define PACKET3_INDEX_BASE 0x26 487 #define PACKET3_DRAW_INDEX_2 0x27 488 #define PACKET3_CONTEXT_CONTROL 0x28 489 #define PACKET3_DRAW_INDEX_OFFSET 0x29 490 #define PACKET3_INDEX_TYPE 0x2A 491 #define PACKET3_DRAW_INDEX 0x2B 492 #define PACKET3_DRAW_INDEX_AUTO 0x2D 493 #define PACKET3_DRAW_INDEX_IMMD 0x2E 494 #define PACKET3_NUM_INSTANCES 0x2F 495 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 496 #define PACKET3_INDIRECT_BUFFER 0x32 497 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 498 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 499 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 500 #define PACKET3_WRITE_DATA 0x37 501 #define PACKET3_MEM_SEMAPHORE 0x39 502 #define PACKET3_MPEG_INDEX 0x3A 503 #define PACKET3_WAIT_REG_MEM 0x3C 504 #define PACKET3_MEM_WRITE 0x3D 505 #define PACKET3_SURFACE_SYNC 0x43 506 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 507 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 508 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 509 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 510 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 511 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 512 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 513 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 514 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 515 # define PACKET3_CB8_DEST_BASE_ENA (1 << 15) 516 # define PACKET3_CB9_DEST_BASE_ENA (1 << 16) 517 # define PACKET3_CB10_DEST_BASE_ENA (1 << 17) 518 # define PACKET3_CB11_DEST_BASE_ENA (1 << 18) 519 # define PACKET3_FULL_CACHE_ENA (1 << 20) 520 # define PACKET3_TC_ACTION_ENA (1 << 23) 521 # define PACKET3_CB_ACTION_ENA (1 << 25) 522 # define PACKET3_DB_ACTION_ENA (1 << 26) 523 # define PACKET3_SH_ACTION_ENA (1 << 27) 524 # define PACKET3_SX_ACTION_ENA (1 << 28) 525 #define PACKET3_ME_INITIALIZE 0x44 526 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 527 #define PACKET3_COND_WRITE 0x45 528 #define PACKET3_EVENT_WRITE 0x46 529 #define EVENT_TYPE(x) ((x) << 0) 530 #define EVENT_INDEX(x) ((x) << 8) 531 /* 0 - any non-TS event 532 * 1 - ZPASS_DONE 533 * 2 - SAMPLE_PIPELINESTAT 534 * 3 - SAMPLE_STREAMOUTSTAT* 535 * 4 - *S_PARTIAL_FLUSH 536 * 5 - TS events 537 */ 538 #define PACKET3_EVENT_WRITE_EOP 0x47 539 #define DATA_SEL(x) ((x) << 29) 540 /* 0 - discard 541 * 1 - send low 32bit data 542 * 2 - send 64bit data 543 * 3 - send 64bit counter value 544 */ 545 #define INT_SEL(x) ((x) << 24) 546 /* 0 - none 547 * 1 - interrupt only (DATA_SEL = 0) 548 * 2 - interrupt when data write is confirmed 549 */ 550 #define PACKET3_EVENT_WRITE_EOS 0x48 551 #define PACKET3_PREAMBLE_CNTL 0x4A 552 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 553 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 554 #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C 555 #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D 556 #define PACKET3_ALU_PS_CONST_UPDATE 0x4E 557 #define PACKET3_ALU_VS_CONST_UPDATE 0x4F 558 #define PACKET3_ONE_REG_WRITE 0x57 559 #define PACKET3_SET_CONFIG_REG 0x68 560 #define PACKET3_SET_CONFIG_REG_START 0x00008000 561 #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 562 #define PACKET3_SET_CONTEXT_REG 0x69 563 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 564 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 565 #define PACKET3_SET_ALU_CONST 0x6A 566 /* alu const buffers only; no reg file */ 567 #define PACKET3_SET_BOOL_CONST 0x6B 568 #define PACKET3_SET_BOOL_CONST_START 0x0003a500 569 #define PACKET3_SET_BOOL_CONST_END 0x0003a518 570 #define PACKET3_SET_LOOP_CONST 0x6C 571 #define PACKET3_SET_LOOP_CONST_START 0x0003a200 572 #define PACKET3_SET_LOOP_CONST_END 0x0003a500 573 #define PACKET3_SET_RESOURCE 0x6D 574 #define PACKET3_SET_RESOURCE_START 0x00030000 575 #define PACKET3_SET_RESOURCE_END 0x00038000 576 #define PACKET3_SET_SAMPLER 0x6E 577 #define PACKET3_SET_SAMPLER_START 0x0003c000 578 #define PACKET3_SET_SAMPLER_END 0x0003c600 579 #define PACKET3_SET_CTL_CONST 0x6F 580 #define PACKET3_SET_CTL_CONST_START 0x0003cff0 581 #define PACKET3_SET_CTL_CONST_END 0x0003ff0c 582 #define PACKET3_SET_RESOURCE_OFFSET 0x70 583 #define PACKET3_SET_ALU_CONST_VS 0x71 584 #define PACKET3_SET_ALU_CONST_DI 0x72 585 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 586 #define PACKET3_SET_RESOURCE_INDIRECT 0x74 587 #define PACKET3_SET_APPEND_CNT 0x75 588 589 #endif 590 591