1 /* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <linux/platform_device.h> 26 #include <linux/slab.h> 27 #include <linux/module.h> 28 #include "drmP.h" 29 #include "radeon.h" 30 #include "radeon_asic.h" 31 #include "radeon_drm.h" 32 #include "nid.h" 33 #include "atom.h" 34 #include "ni_reg.h" 35 #include "cayman_blit_shaders.h" 36 37 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); 38 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); 39 extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev); 40 extern void evergreen_mc_program(struct radeon_device *rdev); 41 extern void evergreen_irq_suspend(struct radeon_device *rdev); 42 extern int evergreen_mc_init(struct radeon_device *rdev); 43 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev); 44 extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev); 45 extern void si_rlc_fini(struct radeon_device *rdev); 46 extern int si_rlc_init(struct radeon_device *rdev); 47 48 #define EVERGREEN_PFP_UCODE_SIZE 1120 49 #define EVERGREEN_PM4_UCODE_SIZE 1376 50 #define EVERGREEN_RLC_UCODE_SIZE 768 51 #define BTC_MC_UCODE_SIZE 6024 52 53 #define CAYMAN_PFP_UCODE_SIZE 2176 54 #define CAYMAN_PM4_UCODE_SIZE 2176 55 #define CAYMAN_RLC_UCODE_SIZE 1024 56 #define CAYMAN_MC_UCODE_SIZE 6037 57 58 #define ARUBA_RLC_UCODE_SIZE 1536 59 60 /* Firmware Names */ 61 MODULE_FIRMWARE("radeon/BARTS_pfp.bin"); 62 MODULE_FIRMWARE("radeon/BARTS_me.bin"); 63 MODULE_FIRMWARE("radeon/BARTS_mc.bin"); 64 MODULE_FIRMWARE("radeon/BTC_rlc.bin"); 65 MODULE_FIRMWARE("radeon/TURKS_pfp.bin"); 66 MODULE_FIRMWARE("radeon/TURKS_me.bin"); 67 MODULE_FIRMWARE("radeon/TURKS_mc.bin"); 68 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin"); 69 MODULE_FIRMWARE("radeon/CAICOS_me.bin"); 70 MODULE_FIRMWARE("radeon/CAICOS_mc.bin"); 71 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin"); 72 MODULE_FIRMWARE("radeon/CAYMAN_me.bin"); 73 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin"); 74 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin"); 75 MODULE_FIRMWARE("radeon/ARUBA_pfp.bin"); 76 MODULE_FIRMWARE("radeon/ARUBA_me.bin"); 77 MODULE_FIRMWARE("radeon/ARUBA_rlc.bin"); 78 79 #define BTC_IO_MC_REGS_SIZE 29 80 81 static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { 82 {0x00000077, 0xff010100}, 83 {0x00000078, 0x00000000}, 84 {0x00000079, 0x00001434}, 85 {0x0000007a, 0xcc08ec08}, 86 {0x0000007b, 0x00040000}, 87 {0x0000007c, 0x000080c0}, 88 {0x0000007d, 0x09000000}, 89 {0x0000007e, 0x00210404}, 90 {0x00000081, 0x08a8e800}, 91 {0x00000082, 0x00030444}, 92 {0x00000083, 0x00000000}, 93 {0x00000085, 0x00000001}, 94 {0x00000086, 0x00000002}, 95 {0x00000087, 0x48490000}, 96 {0x00000088, 0x20244647}, 97 {0x00000089, 0x00000005}, 98 {0x0000008b, 0x66030000}, 99 {0x0000008c, 0x00006603}, 100 {0x0000008d, 0x00000100}, 101 {0x0000008f, 0x00001c0a}, 102 {0x00000090, 0xff000001}, 103 {0x00000094, 0x00101101}, 104 {0x00000095, 0x00000fff}, 105 {0x00000096, 0x00116fff}, 106 {0x00000097, 0x60010000}, 107 {0x00000098, 0x10010000}, 108 {0x00000099, 0x00006000}, 109 {0x0000009a, 0x00001000}, 110 {0x0000009f, 0x00946a00} 111 }; 112 113 static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { 114 {0x00000077, 0xff010100}, 115 {0x00000078, 0x00000000}, 116 {0x00000079, 0x00001434}, 117 {0x0000007a, 0xcc08ec08}, 118 {0x0000007b, 0x00040000}, 119 {0x0000007c, 0x000080c0}, 120 {0x0000007d, 0x09000000}, 121 {0x0000007e, 0x00210404}, 122 {0x00000081, 0x08a8e800}, 123 {0x00000082, 0x00030444}, 124 {0x00000083, 0x00000000}, 125 {0x00000085, 0x00000001}, 126 {0x00000086, 0x00000002}, 127 {0x00000087, 0x48490000}, 128 {0x00000088, 0x20244647}, 129 {0x00000089, 0x00000005}, 130 {0x0000008b, 0x66030000}, 131 {0x0000008c, 0x00006603}, 132 {0x0000008d, 0x00000100}, 133 {0x0000008f, 0x00001c0a}, 134 {0x00000090, 0xff000001}, 135 {0x00000094, 0x00101101}, 136 {0x00000095, 0x00000fff}, 137 {0x00000096, 0x00116fff}, 138 {0x00000097, 0x60010000}, 139 {0x00000098, 0x10010000}, 140 {0x00000099, 0x00006000}, 141 {0x0000009a, 0x00001000}, 142 {0x0000009f, 0x00936a00} 143 }; 144 145 static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { 146 {0x00000077, 0xff010100}, 147 {0x00000078, 0x00000000}, 148 {0x00000079, 0x00001434}, 149 {0x0000007a, 0xcc08ec08}, 150 {0x0000007b, 0x00040000}, 151 {0x0000007c, 0x000080c0}, 152 {0x0000007d, 0x09000000}, 153 {0x0000007e, 0x00210404}, 154 {0x00000081, 0x08a8e800}, 155 {0x00000082, 0x00030444}, 156 {0x00000083, 0x00000000}, 157 {0x00000085, 0x00000001}, 158 {0x00000086, 0x00000002}, 159 {0x00000087, 0x48490000}, 160 {0x00000088, 0x20244647}, 161 {0x00000089, 0x00000005}, 162 {0x0000008b, 0x66030000}, 163 {0x0000008c, 0x00006603}, 164 {0x0000008d, 0x00000100}, 165 {0x0000008f, 0x00001c0a}, 166 {0x00000090, 0xff000001}, 167 {0x00000094, 0x00101101}, 168 {0x00000095, 0x00000fff}, 169 {0x00000096, 0x00116fff}, 170 {0x00000097, 0x60010000}, 171 {0x00000098, 0x10010000}, 172 {0x00000099, 0x00006000}, 173 {0x0000009a, 0x00001000}, 174 {0x0000009f, 0x00916a00} 175 }; 176 177 static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { 178 {0x00000077, 0xff010100}, 179 {0x00000078, 0x00000000}, 180 {0x00000079, 0x00001434}, 181 {0x0000007a, 0xcc08ec08}, 182 {0x0000007b, 0x00040000}, 183 {0x0000007c, 0x000080c0}, 184 {0x0000007d, 0x09000000}, 185 {0x0000007e, 0x00210404}, 186 {0x00000081, 0x08a8e800}, 187 {0x00000082, 0x00030444}, 188 {0x00000083, 0x00000000}, 189 {0x00000085, 0x00000001}, 190 {0x00000086, 0x00000002}, 191 {0x00000087, 0x48490000}, 192 {0x00000088, 0x20244647}, 193 {0x00000089, 0x00000005}, 194 {0x0000008b, 0x66030000}, 195 {0x0000008c, 0x00006603}, 196 {0x0000008d, 0x00000100}, 197 {0x0000008f, 0x00001c0a}, 198 {0x00000090, 0xff000001}, 199 {0x00000094, 0x00101101}, 200 {0x00000095, 0x00000fff}, 201 {0x00000096, 0x00116fff}, 202 {0x00000097, 0x60010000}, 203 {0x00000098, 0x10010000}, 204 {0x00000099, 0x00006000}, 205 {0x0000009a, 0x00001000}, 206 {0x0000009f, 0x00976b00} 207 }; 208 209 int ni_mc_load_microcode(struct radeon_device *rdev) 210 { 211 const __be32 *fw_data; 212 u32 mem_type, running, blackout = 0; 213 u32 *io_mc_regs; 214 int i, ucode_size, regs_size; 215 216 if (!rdev->mc_fw) 217 return -EINVAL; 218 219 switch (rdev->family) { 220 case CHIP_BARTS: 221 io_mc_regs = (u32 *)&barts_io_mc_regs; 222 ucode_size = BTC_MC_UCODE_SIZE; 223 regs_size = BTC_IO_MC_REGS_SIZE; 224 break; 225 case CHIP_TURKS: 226 io_mc_regs = (u32 *)&turks_io_mc_regs; 227 ucode_size = BTC_MC_UCODE_SIZE; 228 regs_size = BTC_IO_MC_REGS_SIZE; 229 break; 230 case CHIP_CAICOS: 231 default: 232 io_mc_regs = (u32 *)&caicos_io_mc_regs; 233 ucode_size = BTC_MC_UCODE_SIZE; 234 regs_size = BTC_IO_MC_REGS_SIZE; 235 break; 236 case CHIP_CAYMAN: 237 io_mc_regs = (u32 *)&cayman_io_mc_regs; 238 ucode_size = CAYMAN_MC_UCODE_SIZE; 239 regs_size = BTC_IO_MC_REGS_SIZE; 240 break; 241 } 242 243 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT; 244 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; 245 246 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) { 247 if (running) { 248 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); 249 WREG32(MC_SHARED_BLACKOUT_CNTL, 1); 250 } 251 252 /* reset the engine and set to writable */ 253 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); 254 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); 255 256 /* load mc io regs */ 257 for (i = 0; i < regs_size; i++) { 258 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); 259 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); 260 } 261 /* load the MC ucode */ 262 fw_data = (const __be32 *)rdev->mc_fw->data; 263 for (i = 0; i < ucode_size; i++) 264 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); 265 266 /* put the engine back into the active state */ 267 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); 268 WREG32(MC_SEQ_SUP_CNTL, 0x00000004); 269 WREG32(MC_SEQ_SUP_CNTL, 0x00000001); 270 271 /* wait for training to complete */ 272 for (i = 0; i < rdev->usec_timeout; i++) { 273 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD) 274 break; 275 udelay(1); 276 } 277 278 if (running) 279 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout); 280 } 281 282 return 0; 283 } 284 285 int ni_init_microcode(struct radeon_device *rdev) 286 { 287 struct platform_device *pdev; 288 const char *chip_name; 289 const char *rlc_chip_name; 290 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size; 291 char fw_name[30]; 292 int err; 293 294 DRM_DEBUG("\n"); 295 296 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); 297 err = IS_ERR(pdev); 298 if (err) { 299 printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); 300 return -EINVAL; 301 } 302 303 switch (rdev->family) { 304 case CHIP_BARTS: 305 chip_name = "BARTS"; 306 rlc_chip_name = "BTC"; 307 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 308 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 309 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 310 mc_req_size = BTC_MC_UCODE_SIZE * 4; 311 break; 312 case CHIP_TURKS: 313 chip_name = "TURKS"; 314 rlc_chip_name = "BTC"; 315 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 316 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 317 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 318 mc_req_size = BTC_MC_UCODE_SIZE * 4; 319 break; 320 case CHIP_CAICOS: 321 chip_name = "CAICOS"; 322 rlc_chip_name = "BTC"; 323 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 324 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 325 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 326 mc_req_size = BTC_MC_UCODE_SIZE * 4; 327 break; 328 case CHIP_CAYMAN: 329 chip_name = "CAYMAN"; 330 rlc_chip_name = "CAYMAN"; 331 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4; 332 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4; 333 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4; 334 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4; 335 break; 336 case CHIP_ARUBA: 337 chip_name = "ARUBA"; 338 rlc_chip_name = "ARUBA"; 339 /* pfp/me same size as CAYMAN */ 340 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4; 341 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4; 342 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4; 343 mc_req_size = 0; 344 break; 345 default: BUG(); 346 } 347 348 DRM_INFO("Loading %s Microcode\n", chip_name); 349 350 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 351 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev); 352 if (err) 353 goto out; 354 if (rdev->pfp_fw->size != pfp_req_size) { 355 printk(KERN_ERR 356 "ni_cp: Bogus length %zu in firmware \"%s\"\n", 357 rdev->pfp_fw->size, fw_name); 358 err = -EINVAL; 359 goto out; 360 } 361 362 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 363 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); 364 if (err) 365 goto out; 366 if (rdev->me_fw->size != me_req_size) { 367 printk(KERN_ERR 368 "ni_cp: Bogus length %zu in firmware \"%s\"\n", 369 rdev->me_fw->size, fw_name); 370 err = -EINVAL; 371 } 372 373 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); 374 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev); 375 if (err) 376 goto out; 377 if (rdev->rlc_fw->size != rlc_req_size) { 378 printk(KERN_ERR 379 "ni_rlc: Bogus length %zu in firmware \"%s\"\n", 380 rdev->rlc_fw->size, fw_name); 381 err = -EINVAL; 382 } 383 384 /* no MC ucode on TN */ 385 if (!(rdev->flags & RADEON_IS_IGP)) { 386 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); 387 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev); 388 if (err) 389 goto out; 390 if (rdev->mc_fw->size != mc_req_size) { 391 printk(KERN_ERR 392 "ni_mc: Bogus length %zu in firmware \"%s\"\n", 393 rdev->mc_fw->size, fw_name); 394 err = -EINVAL; 395 } 396 } 397 out: 398 platform_device_unregister(pdev); 399 400 if (err) { 401 if (err != -EINVAL) 402 printk(KERN_ERR 403 "ni_cp: Failed to load firmware \"%s\"\n", 404 fw_name); 405 release_firmware(rdev->pfp_fw); 406 rdev->pfp_fw = NULL; 407 release_firmware(rdev->me_fw); 408 rdev->me_fw = NULL; 409 release_firmware(rdev->rlc_fw); 410 rdev->rlc_fw = NULL; 411 release_firmware(rdev->mc_fw); 412 rdev->mc_fw = NULL; 413 } 414 return err; 415 } 416 417 /* 418 * Core functions 419 */ 420 static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev, 421 u32 num_tile_pipes, 422 u32 num_backends_per_asic, 423 u32 *backend_disable_mask_per_asic, 424 u32 num_shader_engines) 425 { 426 u32 backend_map = 0; 427 u32 enabled_backends_mask = 0; 428 u32 enabled_backends_count = 0; 429 u32 num_backends_per_se; 430 u32 cur_pipe; 431 u32 swizzle_pipe[CAYMAN_MAX_PIPES]; 432 u32 cur_backend = 0; 433 u32 i; 434 bool force_no_swizzle; 435 436 /* force legal values */ 437 if (num_tile_pipes < 1) 438 num_tile_pipes = 1; 439 if (num_tile_pipes > rdev->config.cayman.max_tile_pipes) 440 num_tile_pipes = rdev->config.cayman.max_tile_pipes; 441 if (num_shader_engines < 1) 442 num_shader_engines = 1; 443 if (num_shader_engines > rdev->config.cayman.max_shader_engines) 444 num_shader_engines = rdev->config.cayman.max_shader_engines; 445 if (num_backends_per_asic < num_shader_engines) 446 num_backends_per_asic = num_shader_engines; 447 if (num_backends_per_asic > (rdev->config.cayman.max_backends_per_se * num_shader_engines)) 448 num_backends_per_asic = rdev->config.cayman.max_backends_per_se * num_shader_engines; 449 450 /* make sure we have the same number of backends per se */ 451 num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines); 452 /* set up the number of backends per se */ 453 num_backends_per_se = num_backends_per_asic / num_shader_engines; 454 if (num_backends_per_se > rdev->config.cayman.max_backends_per_se) { 455 num_backends_per_se = rdev->config.cayman.max_backends_per_se; 456 num_backends_per_asic = num_backends_per_se * num_shader_engines; 457 } 458 459 /* create enable mask and count for enabled backends */ 460 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) { 461 if (((*backend_disable_mask_per_asic >> i) & 1) == 0) { 462 enabled_backends_mask |= (1 << i); 463 ++enabled_backends_count; 464 } 465 if (enabled_backends_count == num_backends_per_asic) 466 break; 467 } 468 469 /* force the backends mask to match the current number of backends */ 470 if (enabled_backends_count != num_backends_per_asic) { 471 u32 this_backend_enabled; 472 u32 shader_engine; 473 u32 backend_per_se; 474 475 enabled_backends_mask = 0; 476 enabled_backends_count = 0; 477 *backend_disable_mask_per_asic = CAYMAN_MAX_BACKENDS_MASK; 478 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) { 479 /* calc the current se */ 480 shader_engine = i / rdev->config.cayman.max_backends_per_se; 481 /* calc the backend per se */ 482 backend_per_se = i % rdev->config.cayman.max_backends_per_se; 483 /* default to not enabled */ 484 this_backend_enabled = 0; 485 if ((shader_engine < num_shader_engines) && 486 (backend_per_se < num_backends_per_se)) 487 this_backend_enabled = 1; 488 if (this_backend_enabled) { 489 enabled_backends_mask |= (1 << i); 490 *backend_disable_mask_per_asic &= ~(1 << i); 491 ++enabled_backends_count; 492 } 493 } 494 } 495 496 497 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * CAYMAN_MAX_PIPES); 498 switch (rdev->family) { 499 case CHIP_CAYMAN: 500 case CHIP_ARUBA: 501 force_no_swizzle = true; 502 break; 503 default: 504 force_no_swizzle = false; 505 break; 506 } 507 if (force_no_swizzle) { 508 bool last_backend_enabled = false; 509 510 force_no_swizzle = false; 511 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) { 512 if (((enabled_backends_mask >> i) & 1) == 1) { 513 if (last_backend_enabled) 514 force_no_swizzle = true; 515 last_backend_enabled = true; 516 } else 517 last_backend_enabled = false; 518 } 519 } 520 521 switch (num_tile_pipes) { 522 case 1: 523 case 3: 524 case 5: 525 case 7: 526 DRM_ERROR("odd number of pipes!\n"); 527 break; 528 case 2: 529 swizzle_pipe[0] = 0; 530 swizzle_pipe[1] = 1; 531 break; 532 case 4: 533 if (force_no_swizzle) { 534 swizzle_pipe[0] = 0; 535 swizzle_pipe[1] = 1; 536 swizzle_pipe[2] = 2; 537 swizzle_pipe[3] = 3; 538 } else { 539 swizzle_pipe[0] = 0; 540 swizzle_pipe[1] = 2; 541 swizzle_pipe[2] = 1; 542 swizzle_pipe[3] = 3; 543 } 544 break; 545 case 6: 546 if (force_no_swizzle) { 547 swizzle_pipe[0] = 0; 548 swizzle_pipe[1] = 1; 549 swizzle_pipe[2] = 2; 550 swizzle_pipe[3] = 3; 551 swizzle_pipe[4] = 4; 552 swizzle_pipe[5] = 5; 553 } else { 554 swizzle_pipe[0] = 0; 555 swizzle_pipe[1] = 2; 556 swizzle_pipe[2] = 4; 557 swizzle_pipe[3] = 1; 558 swizzle_pipe[4] = 3; 559 swizzle_pipe[5] = 5; 560 } 561 break; 562 case 8: 563 if (force_no_swizzle) { 564 swizzle_pipe[0] = 0; 565 swizzle_pipe[1] = 1; 566 swizzle_pipe[2] = 2; 567 swizzle_pipe[3] = 3; 568 swizzle_pipe[4] = 4; 569 swizzle_pipe[5] = 5; 570 swizzle_pipe[6] = 6; 571 swizzle_pipe[7] = 7; 572 } else { 573 swizzle_pipe[0] = 0; 574 swizzle_pipe[1] = 2; 575 swizzle_pipe[2] = 4; 576 swizzle_pipe[3] = 6; 577 swizzle_pipe[4] = 1; 578 swizzle_pipe[5] = 3; 579 swizzle_pipe[6] = 5; 580 swizzle_pipe[7] = 7; 581 } 582 break; 583 } 584 585 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 586 while (((1 << cur_backend) & enabled_backends_mask) == 0) 587 cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS; 588 589 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4))); 590 591 cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS; 592 } 593 594 return backend_map; 595 } 596 597 static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev, 598 u32 disable_mask_per_se, 599 u32 max_disable_mask_per_se, 600 u32 num_shader_engines) 601 { 602 u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se); 603 u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se; 604 605 if (num_shader_engines == 1) 606 return disable_mask_per_asic; 607 else if (num_shader_engines == 2) 608 return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se); 609 else 610 return 0xffffffff; 611 } 612 613 static void cayman_gpu_init(struct radeon_device *rdev) 614 { 615 u32 cc_rb_backend_disable = 0; 616 u32 cc_gc_shader_pipe_config; 617 u32 gb_addr_config = 0; 618 u32 mc_shared_chmap, mc_arb_ramcfg; 619 u32 gb_backend_map; 620 u32 cgts_tcc_disable; 621 u32 sx_debug_1; 622 u32 smx_dc_ctl0; 623 u32 gc_user_shader_pipe_config; 624 u32 gc_user_rb_backend_disable; 625 u32 cgts_user_tcc_disable; 626 u32 cgts_sm_ctrl_reg; 627 u32 hdp_host_path_cntl; 628 u32 tmp; 629 int i, j; 630 631 switch (rdev->family) { 632 case CHIP_CAYMAN: 633 rdev->config.cayman.max_shader_engines = 2; 634 rdev->config.cayman.max_pipes_per_simd = 4; 635 rdev->config.cayman.max_tile_pipes = 8; 636 rdev->config.cayman.max_simds_per_se = 12; 637 rdev->config.cayman.max_backends_per_se = 4; 638 rdev->config.cayman.max_texture_channel_caches = 8; 639 rdev->config.cayman.max_gprs = 256; 640 rdev->config.cayman.max_threads = 256; 641 rdev->config.cayman.max_gs_threads = 32; 642 rdev->config.cayman.max_stack_entries = 512; 643 rdev->config.cayman.sx_num_of_sets = 8; 644 rdev->config.cayman.sx_max_export_size = 256; 645 rdev->config.cayman.sx_max_export_pos_size = 64; 646 rdev->config.cayman.sx_max_export_smx_size = 192; 647 rdev->config.cayman.max_hw_contexts = 8; 648 rdev->config.cayman.sq_num_cf_insts = 2; 649 650 rdev->config.cayman.sc_prim_fifo_size = 0x100; 651 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; 652 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; 653 break; 654 case CHIP_ARUBA: 655 default: 656 rdev->config.cayman.max_shader_engines = 1; 657 rdev->config.cayman.max_pipes_per_simd = 4; 658 rdev->config.cayman.max_tile_pipes = 2; 659 if ((rdev->pdev->device == 0x9900) || 660 (rdev->pdev->device == 0x9901)) { 661 rdev->config.cayman.max_simds_per_se = 6; 662 rdev->config.cayman.max_backends_per_se = 2; 663 } else if ((rdev->pdev->device == 0x9903) || 664 (rdev->pdev->device == 0x9904)) { 665 rdev->config.cayman.max_simds_per_se = 4; 666 rdev->config.cayman.max_backends_per_se = 2; 667 } else if ((rdev->pdev->device == 0x9990) || 668 (rdev->pdev->device == 0x9991)) { 669 rdev->config.cayman.max_simds_per_se = 3; 670 rdev->config.cayman.max_backends_per_se = 1; 671 } else { 672 rdev->config.cayman.max_simds_per_se = 2; 673 rdev->config.cayman.max_backends_per_se = 1; 674 } 675 rdev->config.cayman.max_texture_channel_caches = 2; 676 rdev->config.cayman.max_gprs = 256; 677 rdev->config.cayman.max_threads = 256; 678 rdev->config.cayman.max_gs_threads = 32; 679 rdev->config.cayman.max_stack_entries = 512; 680 rdev->config.cayman.sx_num_of_sets = 8; 681 rdev->config.cayman.sx_max_export_size = 256; 682 rdev->config.cayman.sx_max_export_pos_size = 64; 683 rdev->config.cayman.sx_max_export_smx_size = 192; 684 rdev->config.cayman.max_hw_contexts = 8; 685 rdev->config.cayman.sq_num_cf_insts = 2; 686 687 rdev->config.cayman.sc_prim_fifo_size = 0x40; 688 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; 689 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; 690 break; 691 } 692 693 /* Initialize HDP */ 694 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 695 WREG32((0x2c14 + j), 0x00000000); 696 WREG32((0x2c18 + j), 0x00000000); 697 WREG32((0x2c1c + j), 0x00000000); 698 WREG32((0x2c20 + j), 0x00000000); 699 WREG32((0x2c24 + j), 0x00000000); 700 } 701 702 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 703 704 evergreen_fix_pci_max_read_req_size(rdev); 705 706 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); 707 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 708 709 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE); 710 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG); 711 cgts_tcc_disable = 0xffff0000; 712 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++) 713 cgts_tcc_disable &= ~(1 << (16 + i)); 714 gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE); 715 gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG); 716 cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE); 717 718 rdev->config.cayman.num_shader_engines = rdev->config.cayman.max_shader_engines; 719 tmp = ((~gc_user_shader_pipe_config) & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT; 720 rdev->config.cayman.num_shader_pipes_per_simd = r600_count_pipe_bits(tmp); 721 rdev->config.cayman.num_tile_pipes = rdev->config.cayman.max_tile_pipes; 722 tmp = ((~gc_user_shader_pipe_config) & INACTIVE_SIMDS_MASK) >> INACTIVE_SIMDS_SHIFT; 723 rdev->config.cayman.num_simds_per_se = r600_count_pipe_bits(tmp); 724 tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT; 725 rdev->config.cayman.num_backends_per_se = r600_count_pipe_bits(tmp); 726 tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT; 727 rdev->config.cayman.backend_disable_mask_per_asic = 728 cayman_get_disable_mask_per_asic(rdev, tmp, CAYMAN_MAX_BACKENDS_PER_SE_MASK, 729 rdev->config.cayman.num_shader_engines); 730 rdev->config.cayman.backend_map = 731 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes, 732 rdev->config.cayman.num_backends_per_se * 733 rdev->config.cayman.num_shader_engines, 734 &rdev->config.cayman.backend_disable_mask_per_asic, 735 rdev->config.cayman.num_shader_engines); 736 tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT; 737 rdev->config.cayman.num_texture_channel_caches = r600_count_pipe_bits(tmp); 738 tmp = (mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT; 739 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256; 740 if (rdev->config.cayman.mem_max_burst_length_bytes > 512) 741 rdev->config.cayman.mem_max_burst_length_bytes = 512; 742 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT; 743 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 744 if (rdev->config.cayman.mem_row_size_in_kb > 4) 745 rdev->config.cayman.mem_row_size_in_kb = 4; 746 /* XXX use MC settings? */ 747 rdev->config.cayman.shader_engine_tile_size = 32; 748 rdev->config.cayman.num_gpus = 1; 749 rdev->config.cayman.multi_gpu_tile_size = 64; 750 751 //gb_addr_config = 0x02011003 752 #if 0 753 gb_addr_config = RREG32(GB_ADDR_CONFIG); 754 #else 755 gb_addr_config = 0; 756 switch (rdev->config.cayman.num_tile_pipes) { 757 case 1: 758 default: 759 gb_addr_config |= NUM_PIPES(0); 760 break; 761 case 2: 762 gb_addr_config |= NUM_PIPES(1); 763 break; 764 case 4: 765 gb_addr_config |= NUM_PIPES(2); 766 break; 767 case 8: 768 gb_addr_config |= NUM_PIPES(3); 769 break; 770 } 771 772 tmp = (rdev->config.cayman.mem_max_burst_length_bytes / 256) - 1; 773 gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp); 774 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.cayman.num_shader_engines - 1); 775 tmp = (rdev->config.cayman.shader_engine_tile_size / 16) - 1; 776 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp); 777 switch (rdev->config.cayman.num_gpus) { 778 case 1: 779 default: 780 gb_addr_config |= NUM_GPUS(0); 781 break; 782 case 2: 783 gb_addr_config |= NUM_GPUS(1); 784 break; 785 case 4: 786 gb_addr_config |= NUM_GPUS(2); 787 break; 788 } 789 switch (rdev->config.cayman.multi_gpu_tile_size) { 790 case 16: 791 gb_addr_config |= MULTI_GPU_TILE_SIZE(0); 792 break; 793 case 32: 794 default: 795 gb_addr_config |= MULTI_GPU_TILE_SIZE(1); 796 break; 797 case 64: 798 gb_addr_config |= MULTI_GPU_TILE_SIZE(2); 799 break; 800 case 128: 801 gb_addr_config |= MULTI_GPU_TILE_SIZE(3); 802 break; 803 } 804 switch (rdev->config.cayman.mem_row_size_in_kb) { 805 case 1: 806 default: 807 gb_addr_config |= ROW_SIZE(0); 808 break; 809 case 2: 810 gb_addr_config |= ROW_SIZE(1); 811 break; 812 case 4: 813 gb_addr_config |= ROW_SIZE(2); 814 break; 815 } 816 #endif 817 818 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT; 819 rdev->config.cayman.num_tile_pipes = (1 << tmp); 820 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT; 821 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256; 822 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT; 823 rdev->config.cayman.num_shader_engines = tmp + 1; 824 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT; 825 rdev->config.cayman.num_gpus = tmp + 1; 826 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT; 827 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp; 828 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT; 829 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp; 830 831 //gb_backend_map = 0x76541032; 832 #if 0 833 gb_backend_map = RREG32(GB_BACKEND_MAP); 834 #else 835 gb_backend_map = 836 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes, 837 rdev->config.cayman.num_backends_per_se * 838 rdev->config.cayman.num_shader_engines, 839 &rdev->config.cayman.backend_disable_mask_per_asic, 840 rdev->config.cayman.num_shader_engines); 841 #endif 842 /* setup tiling info dword. gb_addr_config is not adequate since it does 843 * not have bank info, so create a custom tiling dword. 844 * bits 3:0 num_pipes 845 * bits 7:4 num_banks 846 * bits 11:8 group_size 847 * bits 15:12 row_size 848 */ 849 rdev->config.cayman.tile_config = 0; 850 switch (rdev->config.cayman.num_tile_pipes) { 851 case 1: 852 default: 853 rdev->config.cayman.tile_config |= (0 << 0); 854 break; 855 case 2: 856 rdev->config.cayman.tile_config |= (1 << 0); 857 break; 858 case 4: 859 rdev->config.cayman.tile_config |= (2 << 0); 860 break; 861 case 8: 862 rdev->config.cayman.tile_config |= (3 << 0); 863 break; 864 } 865 866 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */ 867 if (rdev->flags & RADEON_IS_IGP) 868 rdev->config.evergreen.tile_config |= 1 << 4; 869 else 870 rdev->config.cayman.tile_config |= 871 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4; 872 rdev->config.cayman.tile_config |= 873 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; 874 rdev->config.cayman.tile_config |= 875 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; 876 877 rdev->config.cayman.backend_map = gb_backend_map; 878 WREG32(GB_BACKEND_MAP, gb_backend_map); 879 WREG32(GB_ADDR_CONFIG, gb_addr_config); 880 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 881 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 882 883 /* primary versions */ 884 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 885 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); 886 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 887 888 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable); 889 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable); 890 891 /* user versions */ 892 WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable); 893 WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); 894 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 895 896 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable); 897 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable); 898 899 /* reprogram the shader complex */ 900 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG); 901 for (i = 0; i < 16; i++) 902 WREG32(CGTS_SM_CTRL_REG, OVERRIDE); 903 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg); 904 905 /* set HW defaults for 3D engine */ 906 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); 907 908 sx_debug_1 = RREG32(SX_DEBUG_1); 909 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; 910 WREG32(SX_DEBUG_1, sx_debug_1); 911 912 smx_dc_ctl0 = RREG32(SMX_DC_CTL0); 913 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff); 914 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets); 915 WREG32(SMX_DC_CTL0, smx_dc_ctl0); 916 917 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE); 918 919 /* need to be explicitly zero-ed */ 920 WREG32(VGT_OFFCHIP_LDS_BASE, 0); 921 WREG32(SQ_LSTMP_RING_BASE, 0); 922 WREG32(SQ_HSTMP_RING_BASE, 0); 923 WREG32(SQ_ESTMP_RING_BASE, 0); 924 WREG32(SQ_GSTMP_RING_BASE, 0); 925 WREG32(SQ_VSTMP_RING_BASE, 0); 926 WREG32(SQ_PSTMP_RING_BASE, 0); 927 928 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO); 929 930 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) | 931 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) | 932 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1))); 933 934 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) | 935 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) | 936 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size))); 937 938 939 WREG32(VGT_NUM_INSTANCES, 1); 940 941 WREG32(CP_PERFMON_CNTL, 0); 942 943 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) | 944 FETCH_FIFO_HIWATER(0x4) | 945 DONE_FIFO_HIWATER(0xe0) | 946 ALU_UPDATE_FIFO_HIWATER(0x8))); 947 948 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4)); 949 WREG32(SQ_CONFIG, (VC_ENABLE | 950 EXPORT_SRC_C | 951 GFX_PRIO(0) | 952 CS1_PRIO(0) | 953 CS2_PRIO(1))); 954 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE); 955 956 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | 957 FORCE_EOV_MAX_REZ_CNT(255))); 958 959 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | 960 AUTO_INVLD_EN(ES_AND_GS_AUTO)); 961 962 WREG32(VGT_GS_VERTEX_REUSE, 16); 963 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 964 965 WREG32(CB_PERF_CTR0_SEL_0, 0); 966 WREG32(CB_PERF_CTR0_SEL_1, 0); 967 WREG32(CB_PERF_CTR1_SEL_0, 0); 968 WREG32(CB_PERF_CTR1_SEL_1, 0); 969 WREG32(CB_PERF_CTR2_SEL_0, 0); 970 WREG32(CB_PERF_CTR2_SEL_1, 0); 971 WREG32(CB_PERF_CTR3_SEL_0, 0); 972 WREG32(CB_PERF_CTR3_SEL_1, 0); 973 974 tmp = RREG32(HDP_MISC_CNTL); 975 tmp |= HDP_FLUSH_INVALIDATE_CACHE; 976 WREG32(HDP_MISC_CNTL, tmp); 977 978 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 979 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 980 981 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); 982 983 udelay(50); 984 } 985 986 /* 987 * GART 988 */ 989 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev) 990 { 991 /* flush hdp cache */ 992 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 993 994 /* bits 0-7 are the VM contexts0-7 */ 995 WREG32(VM_INVALIDATE_REQUEST, 1); 996 } 997 998 int cayman_pcie_gart_enable(struct radeon_device *rdev) 999 { 1000 int i, r; 1001 1002 if (rdev->gart.robj == NULL) { 1003 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 1004 return -EINVAL; 1005 } 1006 r = radeon_gart_table_vram_pin(rdev); 1007 if (r) 1008 return r; 1009 radeon_gart_restore(rdev); 1010 /* Setup TLB control */ 1011 WREG32(MC_VM_MX_L1_TLB_CNTL, 1012 (0xA << 7) | 1013 ENABLE_L1_TLB | 1014 ENABLE_L1_FRAGMENT_PROCESSING | 1015 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1016 ENABLE_ADVANCED_DRIVER_MODEL | 1017 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); 1018 /* Setup L2 cache */ 1019 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | 1020 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1021 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | 1022 EFFECTIVE_L2_QUEUE_SIZE(7) | 1023 CONTEXT1_IDENTITY_ACCESS_MODE(1)); 1024 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); 1025 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | 1026 L2_CACHE_BIGK_FRAGMENT_SIZE(6)); 1027 /* setup context0 */ 1028 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 1029 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 1030 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 1031 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 1032 (u32)(rdev->dummy_page.addr >> 12)); 1033 WREG32(VM_CONTEXT0_CNTL2, 0); 1034 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 1035 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 1036 1037 WREG32(0x15D4, 0); 1038 WREG32(0x15D8, 0); 1039 WREG32(0x15DC, 0); 1040 1041 /* empty context1-7 */ 1042 for (i = 1; i < 8; i++) { 1043 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0); 1044 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), 0); 1045 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), 1046 rdev->gart.table_addr >> 12); 1047 } 1048 1049 /* enable context1-7 */ 1050 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 1051 (u32)(rdev->dummy_page.addr >> 12)); 1052 WREG32(VM_CONTEXT1_CNTL2, 0); 1053 WREG32(VM_CONTEXT1_CNTL, 0); 1054 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 1055 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 1056 1057 cayman_pcie_gart_tlb_flush(rdev); 1058 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1059 (unsigned)(rdev->mc.gtt_size >> 20), 1060 (unsigned long long)rdev->gart.table_addr); 1061 rdev->gart.ready = true; 1062 return 0; 1063 } 1064 1065 void cayman_pcie_gart_disable(struct radeon_device *rdev) 1066 { 1067 /* Disable all tables */ 1068 WREG32(VM_CONTEXT0_CNTL, 0); 1069 WREG32(VM_CONTEXT1_CNTL, 0); 1070 /* Setup TLB control */ 1071 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING | 1072 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1073 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); 1074 /* Setup L2 cache */ 1075 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1076 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | 1077 EFFECTIVE_L2_QUEUE_SIZE(7) | 1078 CONTEXT1_IDENTITY_ACCESS_MODE(1)); 1079 WREG32(VM_L2_CNTL2, 0); 1080 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | 1081 L2_CACHE_BIGK_FRAGMENT_SIZE(6)); 1082 radeon_gart_table_vram_unpin(rdev); 1083 } 1084 1085 void cayman_pcie_gart_fini(struct radeon_device *rdev) 1086 { 1087 cayman_pcie_gart_disable(rdev); 1088 radeon_gart_table_vram_free(rdev); 1089 radeon_gart_fini(rdev); 1090 } 1091 1092 void cayman_cp_int_cntl_setup(struct radeon_device *rdev, 1093 int ring, u32 cp_int_cntl) 1094 { 1095 u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3; 1096 1097 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3)); 1098 WREG32(CP_INT_CNTL, cp_int_cntl); 1099 } 1100 1101 /* 1102 * CP. 1103 */ 1104 void cayman_fence_ring_emit(struct radeon_device *rdev, 1105 struct radeon_fence *fence) 1106 { 1107 struct radeon_ring *ring = &rdev->ring[fence->ring]; 1108 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 1109 1110 /* flush read cache over gart for this vmid */ 1111 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1112 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); 1113 radeon_ring_write(ring, 0); 1114 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1115 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA); 1116 radeon_ring_write(ring, 0xFFFFFFFF); 1117 radeon_ring_write(ring, 0); 1118 radeon_ring_write(ring, 10); /* poll interval */ 1119 /* EVENT_WRITE_EOP - flush caches, send int */ 1120 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 1121 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); 1122 radeon_ring_write(ring, addr & 0xffffffff); 1123 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 1124 radeon_ring_write(ring, fence->seq); 1125 radeon_ring_write(ring, 0); 1126 } 1127 1128 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 1129 { 1130 struct radeon_ring *ring = &rdev->ring[ib->fence->ring]; 1131 1132 /* set to DX10/11 mode */ 1133 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); 1134 radeon_ring_write(ring, 1); 1135 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 1136 radeon_ring_write(ring, 1137 #ifdef __BIG_ENDIAN 1138 (2 << 0) | 1139 #endif 1140 (ib->gpu_addr & 0xFFFFFFFC)); 1141 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); 1142 radeon_ring_write(ring, ib->length_dw | (ib->vm_id << 24)); 1143 1144 /* flush read cache over gart for this vmid */ 1145 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1146 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); 1147 radeon_ring_write(ring, ib->vm_id); 1148 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1149 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA); 1150 radeon_ring_write(ring, 0xFFFFFFFF); 1151 radeon_ring_write(ring, 0); 1152 radeon_ring_write(ring, 10); /* poll interval */ 1153 } 1154 1155 static void cayman_cp_enable(struct radeon_device *rdev, bool enable) 1156 { 1157 if (enable) 1158 WREG32(CP_ME_CNTL, 0); 1159 else { 1160 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1161 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); 1162 WREG32(SCRATCH_UMSK, 0); 1163 } 1164 } 1165 1166 static int cayman_cp_load_microcode(struct radeon_device *rdev) 1167 { 1168 const __be32 *fw_data; 1169 int i; 1170 1171 if (!rdev->me_fw || !rdev->pfp_fw) 1172 return -EINVAL; 1173 1174 cayman_cp_enable(rdev, false); 1175 1176 fw_data = (const __be32 *)rdev->pfp_fw->data; 1177 WREG32(CP_PFP_UCODE_ADDR, 0); 1178 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++) 1179 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 1180 WREG32(CP_PFP_UCODE_ADDR, 0); 1181 1182 fw_data = (const __be32 *)rdev->me_fw->data; 1183 WREG32(CP_ME_RAM_WADDR, 0); 1184 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++) 1185 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 1186 1187 WREG32(CP_PFP_UCODE_ADDR, 0); 1188 WREG32(CP_ME_RAM_WADDR, 0); 1189 WREG32(CP_ME_RAM_RADDR, 0); 1190 return 0; 1191 } 1192 1193 static int cayman_cp_start(struct radeon_device *rdev) 1194 { 1195 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1196 int r, i; 1197 1198 r = radeon_ring_lock(rdev, ring, 7); 1199 if (r) { 1200 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1201 return r; 1202 } 1203 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 1204 radeon_ring_write(ring, 0x1); 1205 radeon_ring_write(ring, 0x0); 1206 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1); 1207 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 1208 radeon_ring_write(ring, 0); 1209 radeon_ring_write(ring, 0); 1210 radeon_ring_unlock_commit(rdev, ring); 1211 1212 cayman_cp_enable(rdev, true); 1213 1214 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19); 1215 if (r) { 1216 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1217 return r; 1218 } 1219 1220 /* setup clear context state */ 1221 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1222 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1223 1224 for (i = 0; i < cayman_default_size; i++) 1225 radeon_ring_write(ring, cayman_default_state[i]); 1226 1227 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1228 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 1229 1230 /* set clear context state */ 1231 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 1232 radeon_ring_write(ring, 0); 1233 1234 /* SQ_VTX_BASE_VTX_LOC */ 1235 radeon_ring_write(ring, 0xc0026f00); 1236 radeon_ring_write(ring, 0x00000000); 1237 radeon_ring_write(ring, 0x00000000); 1238 radeon_ring_write(ring, 0x00000000); 1239 1240 /* Clear consts */ 1241 radeon_ring_write(ring, 0xc0036f00); 1242 radeon_ring_write(ring, 0x00000bc4); 1243 radeon_ring_write(ring, 0xffffffff); 1244 radeon_ring_write(ring, 0xffffffff); 1245 radeon_ring_write(ring, 0xffffffff); 1246 1247 radeon_ring_write(ring, 0xc0026900); 1248 radeon_ring_write(ring, 0x00000316); 1249 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 1250 radeon_ring_write(ring, 0x00000010); /* */ 1251 1252 radeon_ring_unlock_commit(rdev, ring); 1253 1254 /* XXX init other rings */ 1255 1256 return 0; 1257 } 1258 1259 static void cayman_cp_fini(struct radeon_device *rdev) 1260 { 1261 cayman_cp_enable(rdev, false); 1262 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1263 } 1264 1265 int cayman_cp_resume(struct radeon_device *rdev) 1266 { 1267 struct radeon_ring *ring; 1268 u32 tmp; 1269 u32 rb_bufsz; 1270 int r; 1271 1272 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ 1273 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | 1274 SOFT_RESET_PA | 1275 SOFT_RESET_SH | 1276 SOFT_RESET_VGT | 1277 SOFT_RESET_SPI | 1278 SOFT_RESET_SX)); 1279 RREG32(GRBM_SOFT_RESET); 1280 mdelay(15); 1281 WREG32(GRBM_SOFT_RESET, 0); 1282 RREG32(GRBM_SOFT_RESET); 1283 1284 WREG32(CP_SEM_WAIT_TIMER, 0x0); 1285 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 1286 1287 /* Set the write pointer delay */ 1288 WREG32(CP_RB_WPTR_DELAY, 0); 1289 1290 WREG32(CP_DEBUG, (1 << 27)); 1291 1292 /* ring 0 - compute and gfx */ 1293 /* Set ring buffer size */ 1294 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1295 rb_bufsz = drm_order(ring->ring_size / 8); 1296 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 1297 #ifdef __BIG_ENDIAN 1298 tmp |= BUF_SWAP_32BIT; 1299 #endif 1300 WREG32(CP_RB0_CNTL, tmp); 1301 1302 /* Initialize the ring buffer's read and write pointers */ 1303 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); 1304 ring->wptr = 0; 1305 WREG32(CP_RB0_WPTR, ring->wptr); 1306 1307 /* set the wb address wether it's enabled or not */ 1308 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); 1309 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 1310 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 1311 1312 if (rdev->wb.enabled) 1313 WREG32(SCRATCH_UMSK, 0xff); 1314 else { 1315 tmp |= RB_NO_UPDATE; 1316 WREG32(SCRATCH_UMSK, 0); 1317 } 1318 1319 mdelay(1); 1320 WREG32(CP_RB0_CNTL, tmp); 1321 1322 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8); 1323 1324 ring->rptr = RREG32(CP_RB0_RPTR); 1325 1326 /* ring1 - compute only */ 1327 /* Set ring buffer size */ 1328 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; 1329 rb_bufsz = drm_order(ring->ring_size / 8); 1330 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 1331 #ifdef __BIG_ENDIAN 1332 tmp |= BUF_SWAP_32BIT; 1333 #endif 1334 WREG32(CP_RB1_CNTL, tmp); 1335 1336 /* Initialize the ring buffer's read and write pointers */ 1337 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); 1338 ring->wptr = 0; 1339 WREG32(CP_RB1_WPTR, ring->wptr); 1340 1341 /* set the wb address wether it's enabled or not */ 1342 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); 1343 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); 1344 1345 mdelay(1); 1346 WREG32(CP_RB1_CNTL, tmp); 1347 1348 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8); 1349 1350 ring->rptr = RREG32(CP_RB1_RPTR); 1351 1352 /* ring2 - compute only */ 1353 /* Set ring buffer size */ 1354 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; 1355 rb_bufsz = drm_order(ring->ring_size / 8); 1356 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 1357 #ifdef __BIG_ENDIAN 1358 tmp |= BUF_SWAP_32BIT; 1359 #endif 1360 WREG32(CP_RB2_CNTL, tmp); 1361 1362 /* Initialize the ring buffer's read and write pointers */ 1363 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); 1364 ring->wptr = 0; 1365 WREG32(CP_RB2_WPTR, ring->wptr); 1366 1367 /* set the wb address wether it's enabled or not */ 1368 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); 1369 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF); 1370 1371 mdelay(1); 1372 WREG32(CP_RB2_CNTL, tmp); 1373 1374 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8); 1375 1376 ring->rptr = RREG32(CP_RB2_RPTR); 1377 1378 /* start the rings */ 1379 cayman_cp_start(rdev); 1380 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; 1381 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; 1382 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; 1383 /* this only test cp0 */ 1384 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1385 if (r) { 1386 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1387 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; 1388 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; 1389 return r; 1390 } 1391 1392 return 0; 1393 } 1394 1395 static int cayman_gpu_soft_reset(struct radeon_device *rdev) 1396 { 1397 struct evergreen_mc_save save; 1398 u32 grbm_reset = 0; 1399 1400 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 1401 return 0; 1402 1403 dev_info(rdev->dev, "GPU softreset \n"); 1404 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", 1405 RREG32(GRBM_STATUS)); 1406 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", 1407 RREG32(GRBM_STATUS_SE0)); 1408 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", 1409 RREG32(GRBM_STATUS_SE1)); 1410 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", 1411 RREG32(SRBM_STATUS)); 1412 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n", 1413 RREG32(0x14F8)); 1414 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n", 1415 RREG32(0x14D8)); 1416 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1417 RREG32(0x14FC)); 1418 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1419 RREG32(0x14DC)); 1420 1421 evergreen_mc_stop(rdev, &save); 1422 if (evergreen_mc_wait_for_idle(rdev)) { 1423 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1424 } 1425 /* Disable CP parsing/prefetching */ 1426 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); 1427 1428 /* reset all the gfx blocks */ 1429 grbm_reset = (SOFT_RESET_CP | 1430 SOFT_RESET_CB | 1431 SOFT_RESET_DB | 1432 SOFT_RESET_GDS | 1433 SOFT_RESET_PA | 1434 SOFT_RESET_SC | 1435 SOFT_RESET_SPI | 1436 SOFT_RESET_SH | 1437 SOFT_RESET_SX | 1438 SOFT_RESET_TC | 1439 SOFT_RESET_TA | 1440 SOFT_RESET_VGT | 1441 SOFT_RESET_IA); 1442 1443 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset); 1444 WREG32(GRBM_SOFT_RESET, grbm_reset); 1445 (void)RREG32(GRBM_SOFT_RESET); 1446 udelay(50); 1447 WREG32(GRBM_SOFT_RESET, 0); 1448 (void)RREG32(GRBM_SOFT_RESET); 1449 /* Wait a little for things to settle down */ 1450 udelay(50); 1451 1452 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", 1453 RREG32(GRBM_STATUS)); 1454 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", 1455 RREG32(GRBM_STATUS_SE0)); 1456 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", 1457 RREG32(GRBM_STATUS_SE1)); 1458 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", 1459 RREG32(SRBM_STATUS)); 1460 evergreen_mc_resume(rdev, &save); 1461 return 0; 1462 } 1463 1464 int cayman_asic_reset(struct radeon_device *rdev) 1465 { 1466 return cayman_gpu_soft_reset(rdev); 1467 } 1468 1469 static int cayman_startup(struct radeon_device *rdev) 1470 { 1471 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1472 int r; 1473 1474 /* enable pcie gen2 link */ 1475 evergreen_pcie_gen2_enable(rdev); 1476 1477 if (rdev->flags & RADEON_IS_IGP) { 1478 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 1479 r = ni_init_microcode(rdev); 1480 if (r) { 1481 DRM_ERROR("Failed to load firmware!\n"); 1482 return r; 1483 } 1484 } 1485 } else { 1486 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { 1487 r = ni_init_microcode(rdev); 1488 if (r) { 1489 DRM_ERROR("Failed to load firmware!\n"); 1490 return r; 1491 } 1492 } 1493 1494 r = ni_mc_load_microcode(rdev); 1495 if (r) { 1496 DRM_ERROR("Failed to load MC firmware!\n"); 1497 return r; 1498 } 1499 } 1500 1501 r = r600_vram_scratch_init(rdev); 1502 if (r) 1503 return r; 1504 1505 evergreen_mc_program(rdev); 1506 r = cayman_pcie_gart_enable(rdev); 1507 if (r) 1508 return r; 1509 cayman_gpu_init(rdev); 1510 1511 r = evergreen_blit_init(rdev); 1512 if (r) { 1513 r600_blit_fini(rdev); 1514 rdev->asic->copy.copy = NULL; 1515 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 1516 } 1517 1518 /* allocate rlc buffers */ 1519 if (rdev->flags & RADEON_IS_IGP) { 1520 r = si_rlc_init(rdev); 1521 if (r) { 1522 DRM_ERROR("Failed to init rlc BOs!\n"); 1523 return r; 1524 } 1525 } 1526 1527 /* allocate wb buffer */ 1528 r = radeon_wb_init(rdev); 1529 if (r) 1530 return r; 1531 1532 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 1533 if (r) { 1534 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 1535 return r; 1536 } 1537 1538 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX); 1539 if (r) { 1540 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 1541 return r; 1542 } 1543 1544 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX); 1545 if (r) { 1546 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 1547 return r; 1548 } 1549 1550 /* Enable IRQ */ 1551 r = r600_irq_init(rdev); 1552 if (r) { 1553 DRM_ERROR("radeon: IH init failed (%d).\n", r); 1554 radeon_irq_kms_fini(rdev); 1555 return r; 1556 } 1557 evergreen_irq_set(rdev); 1558 1559 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 1560 CP_RB0_RPTR, CP_RB0_WPTR, 1561 0, 0xfffff, RADEON_CP_PACKET2); 1562 if (r) 1563 return r; 1564 r = cayman_cp_load_microcode(rdev); 1565 if (r) 1566 return r; 1567 r = cayman_cp_resume(rdev); 1568 if (r) 1569 return r; 1570 1571 r = radeon_ib_pool_start(rdev); 1572 if (r) 1573 return r; 1574 1575 r = radeon_ib_ring_tests(rdev); 1576 if (r) 1577 return r; 1578 1579 r = radeon_vm_manager_start(rdev); 1580 if (r) 1581 return r; 1582 1583 return 0; 1584 } 1585 1586 int cayman_resume(struct radeon_device *rdev) 1587 { 1588 int r; 1589 1590 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, 1591 * posting will perform necessary task to bring back GPU into good 1592 * shape. 1593 */ 1594 /* post card */ 1595 atom_asic_init(rdev->mode_info.atom_context); 1596 1597 rdev->accel_working = true; 1598 r = cayman_startup(rdev); 1599 if (r) { 1600 DRM_ERROR("cayman startup failed on resume\n"); 1601 rdev->accel_working = false; 1602 return r; 1603 } 1604 return r; 1605 } 1606 1607 int cayman_suspend(struct radeon_device *rdev) 1608 { 1609 /* FIXME: we should wait for ring to be empty */ 1610 radeon_ib_pool_suspend(rdev); 1611 radeon_vm_manager_suspend(rdev); 1612 r600_blit_suspend(rdev); 1613 cayman_cp_enable(rdev, false); 1614 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1615 evergreen_irq_suspend(rdev); 1616 radeon_wb_disable(rdev); 1617 cayman_pcie_gart_disable(rdev); 1618 return 0; 1619 } 1620 1621 /* Plan is to move initialization in that function and use 1622 * helper function so that radeon_device_init pretty much 1623 * do nothing more than calling asic specific function. This 1624 * should also allow to remove a bunch of callback function 1625 * like vram_info. 1626 */ 1627 int cayman_init(struct radeon_device *rdev) 1628 { 1629 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1630 int r; 1631 1632 /* Read BIOS */ 1633 if (!radeon_get_bios(rdev)) { 1634 if (ASIC_IS_AVIVO(rdev)) 1635 return -EINVAL; 1636 } 1637 /* Must be an ATOMBIOS */ 1638 if (!rdev->is_atom_bios) { 1639 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n"); 1640 return -EINVAL; 1641 } 1642 r = radeon_atombios_init(rdev); 1643 if (r) 1644 return r; 1645 1646 /* Post card if necessary */ 1647 if (!radeon_card_posted(rdev)) { 1648 if (!rdev->bios) { 1649 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 1650 return -EINVAL; 1651 } 1652 DRM_INFO("GPU not posted. posting now...\n"); 1653 atom_asic_init(rdev->mode_info.atom_context); 1654 } 1655 /* Initialize scratch registers */ 1656 r600_scratch_init(rdev); 1657 /* Initialize surface registers */ 1658 radeon_surface_init(rdev); 1659 /* Initialize clocks */ 1660 radeon_get_clock_info(rdev->ddev); 1661 /* Fence driver */ 1662 r = radeon_fence_driver_init(rdev); 1663 if (r) 1664 return r; 1665 /* initialize memory controller */ 1666 r = evergreen_mc_init(rdev); 1667 if (r) 1668 return r; 1669 /* Memory manager */ 1670 r = radeon_bo_init(rdev); 1671 if (r) 1672 return r; 1673 1674 r = radeon_irq_kms_init(rdev); 1675 if (r) 1676 return r; 1677 1678 ring->ring_obj = NULL; 1679 r600_ring_init(rdev, ring, 1024 * 1024); 1680 1681 rdev->ih.ring_obj = NULL; 1682 r600_ih_ring_init(rdev, 64 * 1024); 1683 1684 r = r600_pcie_gart_init(rdev); 1685 if (r) 1686 return r; 1687 1688 r = radeon_ib_pool_init(rdev); 1689 rdev->accel_working = true; 1690 if (r) { 1691 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 1692 rdev->accel_working = false; 1693 } 1694 r = radeon_vm_manager_init(rdev); 1695 if (r) { 1696 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r); 1697 } 1698 1699 r = cayman_startup(rdev); 1700 if (r) { 1701 dev_err(rdev->dev, "disabling GPU acceleration\n"); 1702 cayman_cp_fini(rdev); 1703 r600_irq_fini(rdev); 1704 if (rdev->flags & RADEON_IS_IGP) 1705 si_rlc_fini(rdev); 1706 radeon_wb_fini(rdev); 1707 r100_ib_fini(rdev); 1708 radeon_vm_manager_fini(rdev); 1709 radeon_irq_kms_fini(rdev); 1710 cayman_pcie_gart_fini(rdev); 1711 rdev->accel_working = false; 1712 } 1713 1714 /* Don't start up if the MC ucode is missing. 1715 * The default clocks and voltages before the MC ucode 1716 * is loaded are not suffient for advanced operations. 1717 * 1718 * We can skip this check for TN, because there is no MC 1719 * ucode. 1720 */ 1721 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) { 1722 DRM_ERROR("radeon: MC ucode required for NI+.\n"); 1723 return -EINVAL; 1724 } 1725 1726 return 0; 1727 } 1728 1729 void cayman_fini(struct radeon_device *rdev) 1730 { 1731 r600_blit_fini(rdev); 1732 cayman_cp_fini(rdev); 1733 r600_irq_fini(rdev); 1734 if (rdev->flags & RADEON_IS_IGP) 1735 si_rlc_fini(rdev); 1736 radeon_wb_fini(rdev); 1737 radeon_vm_manager_fini(rdev); 1738 r100_ib_fini(rdev); 1739 radeon_irq_kms_fini(rdev); 1740 cayman_pcie_gart_fini(rdev); 1741 r600_vram_scratch_fini(rdev); 1742 radeon_gem_fini(rdev); 1743 radeon_fence_driver_fini(rdev); 1744 radeon_bo_fini(rdev); 1745 radeon_atombios_fini(rdev); 1746 kfree(rdev->bios); 1747 rdev->bios = NULL; 1748 } 1749 1750 /* 1751 * vm 1752 */ 1753 int cayman_vm_init(struct radeon_device *rdev) 1754 { 1755 /* number of VMs */ 1756 rdev->vm_manager.nvm = 8; 1757 /* base offset of vram pages */ 1758 if (rdev->flags & RADEON_IS_IGP) { 1759 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET); 1760 tmp <<= 22; 1761 rdev->vm_manager.vram_base_offset = tmp; 1762 } else 1763 rdev->vm_manager.vram_base_offset = 0; 1764 return 0; 1765 } 1766 1767 void cayman_vm_fini(struct radeon_device *rdev) 1768 { 1769 } 1770 1771 int cayman_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id) 1772 { 1773 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (id << 2), 0); 1774 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (id << 2), vm->last_pfn); 1775 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (id << 2), vm->pt_gpu_addr >> 12); 1776 /* flush hdp cache */ 1777 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 1778 /* bits 0-7 are the VM contexts0-7 */ 1779 WREG32(VM_INVALIDATE_REQUEST, 1 << id); 1780 return 0; 1781 } 1782 1783 void cayman_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm) 1784 { 1785 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (vm->id << 2), 0); 1786 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (vm->id << 2), 0); 1787 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0); 1788 /* flush hdp cache */ 1789 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 1790 /* bits 0-7 are the VM contexts0-7 */ 1791 WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id); 1792 } 1793 1794 void cayman_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm) 1795 { 1796 if (vm->id == -1) 1797 return; 1798 1799 /* flush hdp cache */ 1800 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 1801 /* bits 0-7 are the VM contexts0-7 */ 1802 WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id); 1803 } 1804 1805 #define R600_PTE_VALID (1 << 0) 1806 #define R600_PTE_SYSTEM (1 << 1) 1807 #define R600_PTE_SNOOPED (1 << 2) 1808 #define R600_PTE_READABLE (1 << 5) 1809 #define R600_PTE_WRITEABLE (1 << 6) 1810 1811 uint32_t cayman_vm_page_flags(struct radeon_device *rdev, 1812 struct radeon_vm *vm, 1813 uint32_t flags) 1814 { 1815 uint32_t r600_flags = 0; 1816 1817 r600_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_PTE_VALID : 0; 1818 r600_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0; 1819 r600_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0; 1820 if (flags & RADEON_VM_PAGE_SYSTEM) { 1821 r600_flags |= R600_PTE_SYSTEM; 1822 r600_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0; 1823 } 1824 return r600_flags; 1825 } 1826 1827 void cayman_vm_set_page(struct radeon_device *rdev, struct radeon_vm *vm, 1828 unsigned pfn, uint64_t addr, uint32_t flags) 1829 { 1830 void __iomem *ptr = (void *)vm->pt; 1831 1832 addr = addr & 0xFFFFFFFFFFFFF000ULL; 1833 addr |= flags; 1834 writeq(addr, ptr + (pfn * 8)); 1835 } 1836