1 /* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <linux/platform_device.h> 26 #include <linux/slab.h> 27 #include "drmP.h" 28 #include "radeon.h" 29 #include "radeon_asic.h" 30 #include "radeon_drm.h" 31 #include "nid.h" 32 #include "atom.h" 33 #include "ni_reg.h" 34 #include "cayman_blit_shaders.h" 35 36 #define EVERGREEN_PFP_UCODE_SIZE 1120 37 #define EVERGREEN_PM4_UCODE_SIZE 1376 38 #define EVERGREEN_RLC_UCODE_SIZE 768 39 #define BTC_MC_UCODE_SIZE 6024 40 41 #define CAYMAN_PFP_UCODE_SIZE 2176 42 #define CAYMAN_PM4_UCODE_SIZE 2176 43 #define CAYMAN_RLC_UCODE_SIZE 1024 44 #define CAYMAN_MC_UCODE_SIZE 6037 45 46 /* Firmware Names */ 47 MODULE_FIRMWARE("radeon/BARTS_pfp.bin"); 48 MODULE_FIRMWARE("radeon/BARTS_me.bin"); 49 MODULE_FIRMWARE("radeon/BARTS_mc.bin"); 50 MODULE_FIRMWARE("radeon/BTC_rlc.bin"); 51 MODULE_FIRMWARE("radeon/TURKS_pfp.bin"); 52 MODULE_FIRMWARE("radeon/TURKS_me.bin"); 53 MODULE_FIRMWARE("radeon/TURKS_mc.bin"); 54 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin"); 55 MODULE_FIRMWARE("radeon/CAICOS_me.bin"); 56 MODULE_FIRMWARE("radeon/CAICOS_mc.bin"); 57 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin"); 58 MODULE_FIRMWARE("radeon/CAYMAN_me.bin"); 59 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin"); 60 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin"); 61 62 #define BTC_IO_MC_REGS_SIZE 29 63 64 static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { 65 {0x00000077, 0xff010100}, 66 {0x00000078, 0x00000000}, 67 {0x00000079, 0x00001434}, 68 {0x0000007a, 0xcc08ec08}, 69 {0x0000007b, 0x00040000}, 70 {0x0000007c, 0x000080c0}, 71 {0x0000007d, 0x09000000}, 72 {0x0000007e, 0x00210404}, 73 {0x00000081, 0x08a8e800}, 74 {0x00000082, 0x00030444}, 75 {0x00000083, 0x00000000}, 76 {0x00000085, 0x00000001}, 77 {0x00000086, 0x00000002}, 78 {0x00000087, 0x48490000}, 79 {0x00000088, 0x20244647}, 80 {0x00000089, 0x00000005}, 81 {0x0000008b, 0x66030000}, 82 {0x0000008c, 0x00006603}, 83 {0x0000008d, 0x00000100}, 84 {0x0000008f, 0x00001c0a}, 85 {0x00000090, 0xff000001}, 86 {0x00000094, 0x00101101}, 87 {0x00000095, 0x00000fff}, 88 {0x00000096, 0x00116fff}, 89 {0x00000097, 0x60010000}, 90 {0x00000098, 0x10010000}, 91 {0x00000099, 0x00006000}, 92 {0x0000009a, 0x00001000}, 93 {0x0000009f, 0x00946a00} 94 }; 95 96 static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { 97 {0x00000077, 0xff010100}, 98 {0x00000078, 0x00000000}, 99 {0x00000079, 0x00001434}, 100 {0x0000007a, 0xcc08ec08}, 101 {0x0000007b, 0x00040000}, 102 {0x0000007c, 0x000080c0}, 103 {0x0000007d, 0x09000000}, 104 {0x0000007e, 0x00210404}, 105 {0x00000081, 0x08a8e800}, 106 {0x00000082, 0x00030444}, 107 {0x00000083, 0x00000000}, 108 {0x00000085, 0x00000001}, 109 {0x00000086, 0x00000002}, 110 {0x00000087, 0x48490000}, 111 {0x00000088, 0x20244647}, 112 {0x00000089, 0x00000005}, 113 {0x0000008b, 0x66030000}, 114 {0x0000008c, 0x00006603}, 115 {0x0000008d, 0x00000100}, 116 {0x0000008f, 0x00001c0a}, 117 {0x00000090, 0xff000001}, 118 {0x00000094, 0x00101101}, 119 {0x00000095, 0x00000fff}, 120 {0x00000096, 0x00116fff}, 121 {0x00000097, 0x60010000}, 122 {0x00000098, 0x10010000}, 123 {0x00000099, 0x00006000}, 124 {0x0000009a, 0x00001000}, 125 {0x0000009f, 0x00936a00} 126 }; 127 128 static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { 129 {0x00000077, 0xff010100}, 130 {0x00000078, 0x00000000}, 131 {0x00000079, 0x00001434}, 132 {0x0000007a, 0xcc08ec08}, 133 {0x0000007b, 0x00040000}, 134 {0x0000007c, 0x000080c0}, 135 {0x0000007d, 0x09000000}, 136 {0x0000007e, 0x00210404}, 137 {0x00000081, 0x08a8e800}, 138 {0x00000082, 0x00030444}, 139 {0x00000083, 0x00000000}, 140 {0x00000085, 0x00000001}, 141 {0x00000086, 0x00000002}, 142 {0x00000087, 0x48490000}, 143 {0x00000088, 0x20244647}, 144 {0x00000089, 0x00000005}, 145 {0x0000008b, 0x66030000}, 146 {0x0000008c, 0x00006603}, 147 {0x0000008d, 0x00000100}, 148 {0x0000008f, 0x00001c0a}, 149 {0x00000090, 0xff000001}, 150 {0x00000094, 0x00101101}, 151 {0x00000095, 0x00000fff}, 152 {0x00000096, 0x00116fff}, 153 {0x00000097, 0x60010000}, 154 {0x00000098, 0x10010000}, 155 {0x00000099, 0x00006000}, 156 {0x0000009a, 0x00001000}, 157 {0x0000009f, 0x00916a00} 158 }; 159 160 static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { 161 {0x00000077, 0xff010100}, 162 {0x00000078, 0x00000000}, 163 {0x00000079, 0x00001434}, 164 {0x0000007a, 0xcc08ec08}, 165 {0x0000007b, 0x00040000}, 166 {0x0000007c, 0x000080c0}, 167 {0x0000007d, 0x09000000}, 168 {0x0000007e, 0x00210404}, 169 {0x00000081, 0x08a8e800}, 170 {0x00000082, 0x00030444}, 171 {0x00000083, 0x00000000}, 172 {0x00000085, 0x00000001}, 173 {0x00000086, 0x00000002}, 174 {0x00000087, 0x48490000}, 175 {0x00000088, 0x20244647}, 176 {0x00000089, 0x00000005}, 177 {0x0000008b, 0x66030000}, 178 {0x0000008c, 0x00006603}, 179 {0x0000008d, 0x00000100}, 180 {0x0000008f, 0x00001c0a}, 181 {0x00000090, 0xff000001}, 182 {0x00000094, 0x00101101}, 183 {0x00000095, 0x00000fff}, 184 {0x00000096, 0x00116fff}, 185 {0x00000097, 0x60010000}, 186 {0x00000098, 0x10010000}, 187 {0x00000099, 0x00006000}, 188 {0x0000009a, 0x00001000}, 189 {0x0000009f, 0x00976b00} 190 }; 191 192 int btc_mc_load_microcode(struct radeon_device *rdev) 193 { 194 const __be32 *fw_data; 195 u32 mem_type, running, blackout = 0; 196 u32 *io_mc_regs; 197 int i, ucode_size, regs_size; 198 199 if (!rdev->mc_fw) 200 return -EINVAL; 201 202 switch (rdev->family) { 203 case CHIP_BARTS: 204 io_mc_regs = (u32 *)&barts_io_mc_regs; 205 ucode_size = BTC_MC_UCODE_SIZE; 206 regs_size = BTC_IO_MC_REGS_SIZE; 207 break; 208 case CHIP_TURKS: 209 io_mc_regs = (u32 *)&turks_io_mc_regs; 210 ucode_size = BTC_MC_UCODE_SIZE; 211 regs_size = BTC_IO_MC_REGS_SIZE; 212 break; 213 case CHIP_CAICOS: 214 default: 215 io_mc_regs = (u32 *)&caicos_io_mc_regs; 216 ucode_size = BTC_MC_UCODE_SIZE; 217 regs_size = BTC_IO_MC_REGS_SIZE; 218 break; 219 case CHIP_CAYMAN: 220 io_mc_regs = (u32 *)&cayman_io_mc_regs; 221 ucode_size = CAYMAN_MC_UCODE_SIZE; 222 regs_size = BTC_IO_MC_REGS_SIZE; 223 break; 224 } 225 226 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT; 227 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; 228 229 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) { 230 if (running) { 231 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); 232 WREG32(MC_SHARED_BLACKOUT_CNTL, 1); 233 } 234 235 /* reset the engine and set to writable */ 236 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); 237 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); 238 239 /* load mc io regs */ 240 for (i = 0; i < regs_size; i++) { 241 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); 242 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); 243 } 244 /* load the MC ucode */ 245 fw_data = (const __be32 *)rdev->mc_fw->data; 246 for (i = 0; i < ucode_size; i++) 247 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); 248 249 /* put the engine back into the active state */ 250 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); 251 WREG32(MC_SEQ_SUP_CNTL, 0x00000004); 252 WREG32(MC_SEQ_SUP_CNTL, 0x00000001); 253 254 /* wait for training to complete */ 255 while (!(RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)) 256 udelay(10); 257 258 if (running) 259 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout); 260 } 261 262 return 0; 263 } 264 265 int ni_init_microcode(struct radeon_device *rdev) 266 { 267 struct platform_device *pdev; 268 const char *chip_name; 269 const char *rlc_chip_name; 270 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size; 271 char fw_name[30]; 272 int err; 273 274 DRM_DEBUG("\n"); 275 276 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); 277 err = IS_ERR(pdev); 278 if (err) { 279 printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); 280 return -EINVAL; 281 } 282 283 switch (rdev->family) { 284 case CHIP_BARTS: 285 chip_name = "BARTS"; 286 rlc_chip_name = "BTC"; 287 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 288 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 289 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 290 mc_req_size = BTC_MC_UCODE_SIZE * 4; 291 break; 292 case CHIP_TURKS: 293 chip_name = "TURKS"; 294 rlc_chip_name = "BTC"; 295 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 296 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 297 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 298 mc_req_size = BTC_MC_UCODE_SIZE * 4; 299 break; 300 case CHIP_CAICOS: 301 chip_name = "CAICOS"; 302 rlc_chip_name = "BTC"; 303 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 304 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 305 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 306 mc_req_size = BTC_MC_UCODE_SIZE * 4; 307 break; 308 case CHIP_CAYMAN: 309 chip_name = "CAYMAN"; 310 rlc_chip_name = "CAYMAN"; 311 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4; 312 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4; 313 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4; 314 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4; 315 break; 316 default: BUG(); 317 } 318 319 DRM_INFO("Loading %s Microcode\n", chip_name); 320 321 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 322 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev); 323 if (err) 324 goto out; 325 if (rdev->pfp_fw->size != pfp_req_size) { 326 printk(KERN_ERR 327 "ni_cp: Bogus length %zu in firmware \"%s\"\n", 328 rdev->pfp_fw->size, fw_name); 329 err = -EINVAL; 330 goto out; 331 } 332 333 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 334 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); 335 if (err) 336 goto out; 337 if (rdev->me_fw->size != me_req_size) { 338 printk(KERN_ERR 339 "ni_cp: Bogus length %zu in firmware \"%s\"\n", 340 rdev->me_fw->size, fw_name); 341 err = -EINVAL; 342 } 343 344 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); 345 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev); 346 if (err) 347 goto out; 348 if (rdev->rlc_fw->size != rlc_req_size) { 349 printk(KERN_ERR 350 "ni_rlc: Bogus length %zu in firmware \"%s\"\n", 351 rdev->rlc_fw->size, fw_name); 352 err = -EINVAL; 353 } 354 355 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); 356 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev); 357 if (err) 358 goto out; 359 if (rdev->mc_fw->size != mc_req_size) { 360 printk(KERN_ERR 361 "ni_mc: Bogus length %zu in firmware \"%s\"\n", 362 rdev->mc_fw->size, fw_name); 363 err = -EINVAL; 364 } 365 out: 366 platform_device_unregister(pdev); 367 368 if (err) { 369 if (err != -EINVAL) 370 printk(KERN_ERR 371 "ni_cp: Failed to load firmware \"%s\"\n", 372 fw_name); 373 release_firmware(rdev->pfp_fw); 374 rdev->pfp_fw = NULL; 375 release_firmware(rdev->me_fw); 376 rdev->me_fw = NULL; 377 release_firmware(rdev->rlc_fw); 378 rdev->rlc_fw = NULL; 379 release_firmware(rdev->mc_fw); 380 rdev->mc_fw = NULL; 381 } 382 return err; 383 } 384 385 /* 386 * Core functions 387 */ 388 static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev, 389 u32 num_tile_pipes, 390 u32 num_backends_per_asic, 391 u32 *backend_disable_mask_per_asic, 392 u32 num_shader_engines) 393 { 394 u32 backend_map = 0; 395 u32 enabled_backends_mask = 0; 396 u32 enabled_backends_count = 0; 397 u32 num_backends_per_se; 398 u32 cur_pipe; 399 u32 swizzle_pipe[CAYMAN_MAX_PIPES]; 400 u32 cur_backend = 0; 401 u32 i; 402 bool force_no_swizzle; 403 404 /* force legal values */ 405 if (num_tile_pipes < 1) 406 num_tile_pipes = 1; 407 if (num_tile_pipes > rdev->config.cayman.max_tile_pipes) 408 num_tile_pipes = rdev->config.cayman.max_tile_pipes; 409 if (num_shader_engines < 1) 410 num_shader_engines = 1; 411 if (num_shader_engines > rdev->config.cayman.max_shader_engines) 412 num_shader_engines = rdev->config.cayman.max_shader_engines; 413 if (num_backends_per_asic > num_shader_engines) 414 num_backends_per_asic = num_shader_engines; 415 if (num_backends_per_asic > (rdev->config.cayman.max_backends_per_se * num_shader_engines)) 416 num_backends_per_asic = rdev->config.cayman.max_backends_per_se * num_shader_engines; 417 418 /* make sure we have the same number of backends per se */ 419 num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines); 420 /* set up the number of backends per se */ 421 num_backends_per_se = num_backends_per_asic / num_shader_engines; 422 if (num_backends_per_se > rdev->config.cayman.max_backends_per_se) { 423 num_backends_per_se = rdev->config.cayman.max_backends_per_se; 424 num_backends_per_asic = num_backends_per_se * num_shader_engines; 425 } 426 427 /* create enable mask and count for enabled backends */ 428 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) { 429 if (((*backend_disable_mask_per_asic >> i) & 1) == 0) { 430 enabled_backends_mask |= (1 << i); 431 ++enabled_backends_count; 432 } 433 if (enabled_backends_count == num_backends_per_asic) 434 break; 435 } 436 437 /* force the backends mask to match the current number of backends */ 438 if (enabled_backends_count != num_backends_per_asic) { 439 u32 this_backend_enabled; 440 u32 shader_engine; 441 u32 backend_per_se; 442 443 enabled_backends_mask = 0; 444 enabled_backends_count = 0; 445 *backend_disable_mask_per_asic = CAYMAN_MAX_BACKENDS_MASK; 446 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) { 447 /* calc the current se */ 448 shader_engine = i / rdev->config.cayman.max_backends_per_se; 449 /* calc the backend per se */ 450 backend_per_se = i % rdev->config.cayman.max_backends_per_se; 451 /* default to not enabled */ 452 this_backend_enabled = 0; 453 if ((shader_engine < num_shader_engines) && 454 (backend_per_se < num_backends_per_se)) 455 this_backend_enabled = 1; 456 if (this_backend_enabled) { 457 enabled_backends_mask |= (1 << i); 458 *backend_disable_mask_per_asic &= ~(1 << i); 459 ++enabled_backends_count; 460 } 461 } 462 } 463 464 465 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * CAYMAN_MAX_PIPES); 466 switch (rdev->family) { 467 case CHIP_CAYMAN: 468 force_no_swizzle = true; 469 break; 470 default: 471 force_no_swizzle = false; 472 break; 473 } 474 if (force_no_swizzle) { 475 bool last_backend_enabled = false; 476 477 force_no_swizzle = false; 478 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) { 479 if (((enabled_backends_mask >> i) & 1) == 1) { 480 if (last_backend_enabled) 481 force_no_swizzle = true; 482 last_backend_enabled = true; 483 } else 484 last_backend_enabled = false; 485 } 486 } 487 488 switch (num_tile_pipes) { 489 case 1: 490 case 3: 491 case 5: 492 case 7: 493 DRM_ERROR("odd number of pipes!\n"); 494 break; 495 case 2: 496 swizzle_pipe[0] = 0; 497 swizzle_pipe[1] = 1; 498 break; 499 case 4: 500 if (force_no_swizzle) { 501 swizzle_pipe[0] = 0; 502 swizzle_pipe[1] = 1; 503 swizzle_pipe[2] = 2; 504 swizzle_pipe[3] = 3; 505 } else { 506 swizzle_pipe[0] = 0; 507 swizzle_pipe[1] = 2; 508 swizzle_pipe[2] = 1; 509 swizzle_pipe[3] = 3; 510 } 511 break; 512 case 6: 513 if (force_no_swizzle) { 514 swizzle_pipe[0] = 0; 515 swizzle_pipe[1] = 1; 516 swizzle_pipe[2] = 2; 517 swizzle_pipe[3] = 3; 518 swizzle_pipe[4] = 4; 519 swizzle_pipe[5] = 5; 520 } else { 521 swizzle_pipe[0] = 0; 522 swizzle_pipe[1] = 2; 523 swizzle_pipe[2] = 4; 524 swizzle_pipe[3] = 1; 525 swizzle_pipe[4] = 3; 526 swizzle_pipe[5] = 5; 527 } 528 break; 529 case 8: 530 if (force_no_swizzle) { 531 swizzle_pipe[0] = 0; 532 swizzle_pipe[1] = 1; 533 swizzle_pipe[2] = 2; 534 swizzle_pipe[3] = 3; 535 swizzle_pipe[4] = 4; 536 swizzle_pipe[5] = 5; 537 swizzle_pipe[6] = 6; 538 swizzle_pipe[7] = 7; 539 } else { 540 swizzle_pipe[0] = 0; 541 swizzle_pipe[1] = 2; 542 swizzle_pipe[2] = 4; 543 swizzle_pipe[3] = 6; 544 swizzle_pipe[4] = 1; 545 swizzle_pipe[5] = 3; 546 swizzle_pipe[6] = 5; 547 swizzle_pipe[7] = 7; 548 } 549 break; 550 } 551 552 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 553 while (((1 << cur_backend) & enabled_backends_mask) == 0) 554 cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS; 555 556 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4))); 557 558 cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS; 559 } 560 561 return backend_map; 562 } 563 564 static void cayman_program_channel_remap(struct radeon_device *rdev) 565 { 566 u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp; 567 568 tmp = RREG32(MC_SHARED_CHMAP); 569 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 570 case 0: 571 case 1: 572 case 2: 573 case 3: 574 default: 575 /* default mapping */ 576 mc_shared_chremap = 0x00fac688; 577 break; 578 } 579 580 switch (rdev->family) { 581 case CHIP_CAYMAN: 582 default: 583 //tcp_chan_steer_lo = 0x54763210 584 tcp_chan_steer_lo = 0x76543210; 585 tcp_chan_steer_hi = 0x0000ba98; 586 break; 587 } 588 589 WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo); 590 WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi); 591 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap); 592 } 593 594 static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev, 595 u32 disable_mask_per_se, 596 u32 max_disable_mask_per_se, 597 u32 num_shader_engines) 598 { 599 u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se); 600 u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se; 601 602 if (num_shader_engines == 1) 603 return disable_mask_per_asic; 604 else if (num_shader_engines == 2) 605 return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se); 606 else 607 return 0xffffffff; 608 } 609 610 static void cayman_gpu_init(struct radeon_device *rdev) 611 { 612 u32 cc_rb_backend_disable = 0; 613 u32 cc_gc_shader_pipe_config; 614 u32 gb_addr_config = 0; 615 u32 mc_shared_chmap, mc_arb_ramcfg; 616 u32 gb_backend_map; 617 u32 cgts_tcc_disable; 618 u32 sx_debug_1; 619 u32 smx_dc_ctl0; 620 u32 gc_user_shader_pipe_config; 621 u32 gc_user_rb_backend_disable; 622 u32 cgts_user_tcc_disable; 623 u32 cgts_sm_ctrl_reg; 624 u32 hdp_host_path_cntl; 625 u32 tmp; 626 int i, j; 627 628 switch (rdev->family) { 629 case CHIP_CAYMAN: 630 default: 631 rdev->config.cayman.max_shader_engines = 2; 632 rdev->config.cayman.max_pipes_per_simd = 4; 633 rdev->config.cayman.max_tile_pipes = 8; 634 rdev->config.cayman.max_simds_per_se = 12; 635 rdev->config.cayman.max_backends_per_se = 4; 636 rdev->config.cayman.max_texture_channel_caches = 8; 637 rdev->config.cayman.max_gprs = 256; 638 rdev->config.cayman.max_threads = 256; 639 rdev->config.cayman.max_gs_threads = 32; 640 rdev->config.cayman.max_stack_entries = 512; 641 rdev->config.cayman.sx_num_of_sets = 8; 642 rdev->config.cayman.sx_max_export_size = 256; 643 rdev->config.cayman.sx_max_export_pos_size = 64; 644 rdev->config.cayman.sx_max_export_smx_size = 192; 645 rdev->config.cayman.max_hw_contexts = 8; 646 rdev->config.cayman.sq_num_cf_insts = 2; 647 648 rdev->config.cayman.sc_prim_fifo_size = 0x100; 649 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; 650 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; 651 break; 652 } 653 654 /* Initialize HDP */ 655 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 656 WREG32((0x2c14 + j), 0x00000000); 657 WREG32((0x2c18 + j), 0x00000000); 658 WREG32((0x2c1c + j), 0x00000000); 659 WREG32((0x2c20 + j), 0x00000000); 660 WREG32((0x2c24 + j), 0x00000000); 661 } 662 663 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 664 665 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); 666 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 667 668 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE); 669 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG); 670 cgts_tcc_disable = RREG32(CGTS_TCC_DISABLE); 671 gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE); 672 gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG); 673 cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE); 674 675 rdev->config.cayman.num_shader_engines = rdev->config.cayman.max_shader_engines; 676 tmp = ((~gc_user_shader_pipe_config) & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT; 677 rdev->config.cayman.num_shader_pipes_per_simd = r600_count_pipe_bits(tmp); 678 rdev->config.cayman.num_tile_pipes = rdev->config.cayman.max_tile_pipes; 679 tmp = ((~gc_user_shader_pipe_config) & INACTIVE_SIMDS_MASK) >> INACTIVE_SIMDS_SHIFT; 680 rdev->config.cayman.num_simds_per_se = r600_count_pipe_bits(tmp); 681 tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT; 682 rdev->config.cayman.num_backends_per_se = r600_count_pipe_bits(tmp); 683 tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT; 684 rdev->config.cayman.backend_disable_mask_per_asic = 685 cayman_get_disable_mask_per_asic(rdev, tmp, CAYMAN_MAX_BACKENDS_PER_SE_MASK, 686 rdev->config.cayman.num_shader_engines); 687 rdev->config.cayman.backend_map = 688 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes, 689 rdev->config.cayman.num_backends_per_se * 690 rdev->config.cayman.num_shader_engines, 691 &rdev->config.cayman.backend_disable_mask_per_asic, 692 rdev->config.cayman.num_shader_engines); 693 tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT; 694 rdev->config.cayman.num_texture_channel_caches = r600_count_pipe_bits(tmp); 695 tmp = (mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT; 696 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256; 697 if (rdev->config.cayman.mem_max_burst_length_bytes > 512) 698 rdev->config.cayman.mem_max_burst_length_bytes = 512; 699 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT; 700 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 701 if (rdev->config.cayman.mem_row_size_in_kb > 4) 702 rdev->config.cayman.mem_row_size_in_kb = 4; 703 /* XXX use MC settings? */ 704 rdev->config.cayman.shader_engine_tile_size = 32; 705 rdev->config.cayman.num_gpus = 1; 706 rdev->config.cayman.multi_gpu_tile_size = 64; 707 708 //gb_addr_config = 0x02011003 709 #if 0 710 gb_addr_config = RREG32(GB_ADDR_CONFIG); 711 #else 712 gb_addr_config = 0; 713 switch (rdev->config.cayman.num_tile_pipes) { 714 case 1: 715 default: 716 gb_addr_config |= NUM_PIPES(0); 717 break; 718 case 2: 719 gb_addr_config |= NUM_PIPES(1); 720 break; 721 case 4: 722 gb_addr_config |= NUM_PIPES(2); 723 break; 724 case 8: 725 gb_addr_config |= NUM_PIPES(3); 726 break; 727 } 728 729 tmp = (rdev->config.cayman.mem_max_burst_length_bytes / 256) - 1; 730 gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp); 731 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.cayman.num_shader_engines - 1); 732 tmp = (rdev->config.cayman.shader_engine_tile_size / 16) - 1; 733 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp); 734 switch (rdev->config.cayman.num_gpus) { 735 case 1: 736 default: 737 gb_addr_config |= NUM_GPUS(0); 738 break; 739 case 2: 740 gb_addr_config |= NUM_GPUS(1); 741 break; 742 case 4: 743 gb_addr_config |= NUM_GPUS(2); 744 break; 745 } 746 switch (rdev->config.cayman.multi_gpu_tile_size) { 747 case 16: 748 gb_addr_config |= MULTI_GPU_TILE_SIZE(0); 749 break; 750 case 32: 751 default: 752 gb_addr_config |= MULTI_GPU_TILE_SIZE(1); 753 break; 754 case 64: 755 gb_addr_config |= MULTI_GPU_TILE_SIZE(2); 756 break; 757 case 128: 758 gb_addr_config |= MULTI_GPU_TILE_SIZE(3); 759 break; 760 } 761 switch (rdev->config.cayman.mem_row_size_in_kb) { 762 case 1: 763 default: 764 gb_addr_config |= ROW_SIZE(0); 765 break; 766 case 2: 767 gb_addr_config |= ROW_SIZE(1); 768 break; 769 case 4: 770 gb_addr_config |= ROW_SIZE(2); 771 break; 772 } 773 #endif 774 775 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT; 776 rdev->config.cayman.num_tile_pipes = (1 << tmp); 777 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT; 778 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256; 779 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT; 780 rdev->config.cayman.num_shader_engines = tmp + 1; 781 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT; 782 rdev->config.cayman.num_gpus = tmp + 1; 783 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT; 784 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp; 785 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT; 786 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp; 787 788 //gb_backend_map = 0x76541032; 789 #if 0 790 gb_backend_map = RREG32(GB_BACKEND_MAP); 791 #else 792 gb_backend_map = 793 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes, 794 rdev->config.cayman.num_backends_per_se * 795 rdev->config.cayman.num_shader_engines, 796 &rdev->config.cayman.backend_disable_mask_per_asic, 797 rdev->config.cayman.num_shader_engines); 798 #endif 799 /* setup tiling info dword. gb_addr_config is not adequate since it does 800 * not have bank info, so create a custom tiling dword. 801 * bits 3:0 num_pipes 802 * bits 7:4 num_banks 803 * bits 11:8 group_size 804 * bits 15:12 row_size 805 */ 806 rdev->config.cayman.tile_config = 0; 807 switch (rdev->config.cayman.num_tile_pipes) { 808 case 1: 809 default: 810 rdev->config.cayman.tile_config |= (0 << 0); 811 break; 812 case 2: 813 rdev->config.cayman.tile_config |= (1 << 0); 814 break; 815 case 4: 816 rdev->config.cayman.tile_config |= (2 << 0); 817 break; 818 case 8: 819 rdev->config.cayman.tile_config |= (3 << 0); 820 break; 821 } 822 rdev->config.cayman.tile_config |= 823 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4; 824 rdev->config.cayman.tile_config |= 825 (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT; 826 rdev->config.cayman.tile_config |= 827 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; 828 829 WREG32(GB_BACKEND_MAP, gb_backend_map); 830 WREG32(GB_ADDR_CONFIG, gb_addr_config); 831 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 832 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 833 834 cayman_program_channel_remap(rdev); 835 836 /* primary versions */ 837 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 838 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); 839 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 840 841 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable); 842 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable); 843 844 /* user versions */ 845 WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable); 846 WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); 847 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 848 849 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable); 850 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable); 851 852 /* reprogram the shader complex */ 853 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG); 854 for (i = 0; i < 16; i++) 855 WREG32(CGTS_SM_CTRL_REG, OVERRIDE); 856 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg); 857 858 /* set HW defaults for 3D engine */ 859 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); 860 861 sx_debug_1 = RREG32(SX_DEBUG_1); 862 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; 863 WREG32(SX_DEBUG_1, sx_debug_1); 864 865 smx_dc_ctl0 = RREG32(SMX_DC_CTL0); 866 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff); 867 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets); 868 WREG32(SMX_DC_CTL0, smx_dc_ctl0); 869 870 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE); 871 872 /* need to be explicitly zero-ed */ 873 WREG32(VGT_OFFCHIP_LDS_BASE, 0); 874 WREG32(SQ_LSTMP_RING_BASE, 0); 875 WREG32(SQ_HSTMP_RING_BASE, 0); 876 WREG32(SQ_ESTMP_RING_BASE, 0); 877 WREG32(SQ_GSTMP_RING_BASE, 0); 878 WREG32(SQ_VSTMP_RING_BASE, 0); 879 WREG32(SQ_PSTMP_RING_BASE, 0); 880 881 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO); 882 883 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) | 884 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) | 885 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1))); 886 887 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) | 888 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) | 889 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size))); 890 891 892 WREG32(VGT_NUM_INSTANCES, 1); 893 894 WREG32(CP_PERFMON_CNTL, 0); 895 896 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) | 897 FETCH_FIFO_HIWATER(0x4) | 898 DONE_FIFO_HIWATER(0xe0) | 899 ALU_UPDATE_FIFO_HIWATER(0x8))); 900 901 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4)); 902 WREG32(SQ_CONFIG, (VC_ENABLE | 903 EXPORT_SRC_C | 904 GFX_PRIO(0) | 905 CS1_PRIO(0) | 906 CS2_PRIO(1))); 907 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE); 908 909 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | 910 FORCE_EOV_MAX_REZ_CNT(255))); 911 912 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | 913 AUTO_INVLD_EN(ES_AND_GS_AUTO)); 914 915 WREG32(VGT_GS_VERTEX_REUSE, 16); 916 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 917 918 WREG32(CB_PERF_CTR0_SEL_0, 0); 919 WREG32(CB_PERF_CTR0_SEL_1, 0); 920 WREG32(CB_PERF_CTR1_SEL_0, 0); 921 WREG32(CB_PERF_CTR1_SEL_1, 0); 922 WREG32(CB_PERF_CTR2_SEL_0, 0); 923 WREG32(CB_PERF_CTR2_SEL_1, 0); 924 WREG32(CB_PERF_CTR3_SEL_0, 0); 925 WREG32(CB_PERF_CTR3_SEL_1, 0); 926 927 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 928 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 929 930 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); 931 932 udelay(50); 933 } 934 935 /* 936 * GART 937 */ 938 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev) 939 { 940 /* flush hdp cache */ 941 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 942 943 /* bits 0-7 are the VM contexts0-7 */ 944 WREG32(VM_INVALIDATE_REQUEST, 1); 945 } 946 947 int cayman_pcie_gart_enable(struct radeon_device *rdev) 948 { 949 int r; 950 951 if (rdev->gart.table.vram.robj == NULL) { 952 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 953 return -EINVAL; 954 } 955 r = radeon_gart_table_vram_pin(rdev); 956 if (r) 957 return r; 958 radeon_gart_restore(rdev); 959 /* Setup TLB control */ 960 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB | 961 ENABLE_L1_FRAGMENT_PROCESSING | 962 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 963 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); 964 /* Setup L2 cache */ 965 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | 966 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 967 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | 968 EFFECTIVE_L2_QUEUE_SIZE(7) | 969 CONTEXT1_IDENTITY_ACCESS_MODE(1)); 970 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); 971 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | 972 L2_CACHE_BIGK_FRAGMENT_SIZE(6)); 973 /* setup context0 */ 974 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 975 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 976 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 977 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 978 (u32)(rdev->dummy_page.addr >> 12)); 979 WREG32(VM_CONTEXT0_CNTL2, 0); 980 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 981 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 982 /* disable context1-7 */ 983 WREG32(VM_CONTEXT1_CNTL2, 0); 984 WREG32(VM_CONTEXT1_CNTL, 0); 985 986 cayman_pcie_gart_tlb_flush(rdev); 987 rdev->gart.ready = true; 988 return 0; 989 } 990 991 void cayman_pcie_gart_disable(struct radeon_device *rdev) 992 { 993 int r; 994 995 /* Disable all tables */ 996 WREG32(VM_CONTEXT0_CNTL, 0); 997 WREG32(VM_CONTEXT1_CNTL, 0); 998 /* Setup TLB control */ 999 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING | 1000 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1001 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); 1002 /* Setup L2 cache */ 1003 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1004 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | 1005 EFFECTIVE_L2_QUEUE_SIZE(7) | 1006 CONTEXT1_IDENTITY_ACCESS_MODE(1)); 1007 WREG32(VM_L2_CNTL2, 0); 1008 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | 1009 L2_CACHE_BIGK_FRAGMENT_SIZE(6)); 1010 if (rdev->gart.table.vram.robj) { 1011 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); 1012 if (likely(r == 0)) { 1013 radeon_bo_kunmap(rdev->gart.table.vram.robj); 1014 radeon_bo_unpin(rdev->gart.table.vram.robj); 1015 radeon_bo_unreserve(rdev->gart.table.vram.robj); 1016 } 1017 } 1018 } 1019 1020 void cayman_pcie_gart_fini(struct radeon_device *rdev) 1021 { 1022 cayman_pcie_gart_disable(rdev); 1023 radeon_gart_table_vram_free(rdev); 1024 radeon_gart_fini(rdev); 1025 } 1026 1027 /* 1028 * CP. 1029 */ 1030 static void cayman_cp_enable(struct radeon_device *rdev, bool enable) 1031 { 1032 if (enable) 1033 WREG32(CP_ME_CNTL, 0); 1034 else { 1035 rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 1036 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); 1037 WREG32(SCRATCH_UMSK, 0); 1038 } 1039 } 1040 1041 static int cayman_cp_load_microcode(struct radeon_device *rdev) 1042 { 1043 const __be32 *fw_data; 1044 int i; 1045 1046 if (!rdev->me_fw || !rdev->pfp_fw) 1047 return -EINVAL; 1048 1049 cayman_cp_enable(rdev, false); 1050 1051 fw_data = (const __be32 *)rdev->pfp_fw->data; 1052 WREG32(CP_PFP_UCODE_ADDR, 0); 1053 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++) 1054 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 1055 WREG32(CP_PFP_UCODE_ADDR, 0); 1056 1057 fw_data = (const __be32 *)rdev->me_fw->data; 1058 WREG32(CP_ME_RAM_WADDR, 0); 1059 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++) 1060 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 1061 1062 WREG32(CP_PFP_UCODE_ADDR, 0); 1063 WREG32(CP_ME_RAM_WADDR, 0); 1064 WREG32(CP_ME_RAM_RADDR, 0); 1065 return 0; 1066 } 1067 1068 static int cayman_cp_start(struct radeon_device *rdev) 1069 { 1070 int r, i; 1071 1072 r = radeon_ring_lock(rdev, 7); 1073 if (r) { 1074 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1075 return r; 1076 } 1077 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); 1078 radeon_ring_write(rdev, 0x1); 1079 radeon_ring_write(rdev, 0x0); 1080 radeon_ring_write(rdev, rdev->config.cayman.max_hw_contexts - 1); 1081 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 1082 radeon_ring_write(rdev, 0); 1083 radeon_ring_write(rdev, 0); 1084 radeon_ring_unlock_commit(rdev); 1085 1086 cayman_cp_enable(rdev, true); 1087 1088 r = radeon_ring_lock(rdev, cayman_default_size + 15); 1089 if (r) { 1090 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1091 return r; 1092 } 1093 1094 /* setup clear context state */ 1095 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1096 radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1097 1098 for (i = 0; i < cayman_default_size; i++) 1099 radeon_ring_write(rdev, cayman_default_state[i]); 1100 1101 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1102 radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE); 1103 1104 /* set clear context state */ 1105 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0)); 1106 radeon_ring_write(rdev, 0); 1107 1108 /* SQ_VTX_BASE_VTX_LOC */ 1109 radeon_ring_write(rdev, 0xc0026f00); 1110 radeon_ring_write(rdev, 0x00000000); 1111 radeon_ring_write(rdev, 0x00000000); 1112 radeon_ring_write(rdev, 0x00000000); 1113 1114 /* Clear consts */ 1115 radeon_ring_write(rdev, 0xc0036f00); 1116 radeon_ring_write(rdev, 0x00000bc4); 1117 radeon_ring_write(rdev, 0xffffffff); 1118 radeon_ring_write(rdev, 0xffffffff); 1119 radeon_ring_write(rdev, 0xffffffff); 1120 1121 radeon_ring_unlock_commit(rdev); 1122 1123 /* XXX init other rings */ 1124 1125 return 0; 1126 } 1127 1128 int cayman_cp_resume(struct radeon_device *rdev) 1129 { 1130 u32 tmp; 1131 u32 rb_bufsz; 1132 int r; 1133 1134 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ 1135 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | 1136 SOFT_RESET_PA | 1137 SOFT_RESET_SH | 1138 SOFT_RESET_VGT | 1139 SOFT_RESET_SX)); 1140 RREG32(GRBM_SOFT_RESET); 1141 mdelay(15); 1142 WREG32(GRBM_SOFT_RESET, 0); 1143 RREG32(GRBM_SOFT_RESET); 1144 1145 WREG32(CP_SEM_WAIT_TIMER, 0x4); 1146 1147 /* Set the write pointer delay */ 1148 WREG32(CP_RB_WPTR_DELAY, 0); 1149 1150 WREG32(CP_DEBUG, (1 << 27)); 1151 1152 /* ring 0 - compute and gfx */ 1153 /* Set ring buffer size */ 1154 rb_bufsz = drm_order(rdev->cp.ring_size / 8); 1155 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 1156 #ifdef __BIG_ENDIAN 1157 tmp |= BUF_SWAP_32BIT; 1158 #endif 1159 WREG32(CP_RB0_CNTL, tmp); 1160 1161 /* Initialize the ring buffer's read and write pointers */ 1162 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); 1163 WREG32(CP_RB0_WPTR, 0); 1164 1165 /* set the wb address wether it's enabled or not */ 1166 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); 1167 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 1168 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 1169 1170 if (rdev->wb.enabled) 1171 WREG32(SCRATCH_UMSK, 0xff); 1172 else { 1173 tmp |= RB_NO_UPDATE; 1174 WREG32(SCRATCH_UMSK, 0); 1175 } 1176 1177 mdelay(1); 1178 WREG32(CP_RB0_CNTL, tmp); 1179 1180 WREG32(CP_RB0_BASE, rdev->cp.gpu_addr >> 8); 1181 1182 rdev->cp.rptr = RREG32(CP_RB0_RPTR); 1183 rdev->cp.wptr = RREG32(CP_RB0_WPTR); 1184 1185 /* ring1 - compute only */ 1186 /* Set ring buffer size */ 1187 rb_bufsz = drm_order(rdev->cp1.ring_size / 8); 1188 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 1189 #ifdef __BIG_ENDIAN 1190 tmp |= BUF_SWAP_32BIT; 1191 #endif 1192 WREG32(CP_RB1_CNTL, tmp); 1193 1194 /* Initialize the ring buffer's read and write pointers */ 1195 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); 1196 WREG32(CP_RB1_WPTR, 0); 1197 1198 /* set the wb address wether it's enabled or not */ 1199 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); 1200 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); 1201 1202 mdelay(1); 1203 WREG32(CP_RB1_CNTL, tmp); 1204 1205 WREG32(CP_RB1_BASE, rdev->cp1.gpu_addr >> 8); 1206 1207 rdev->cp1.rptr = RREG32(CP_RB1_RPTR); 1208 rdev->cp1.wptr = RREG32(CP_RB1_WPTR); 1209 1210 /* ring2 - compute only */ 1211 /* Set ring buffer size */ 1212 rb_bufsz = drm_order(rdev->cp2.ring_size / 8); 1213 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 1214 #ifdef __BIG_ENDIAN 1215 tmp |= BUF_SWAP_32BIT; 1216 #endif 1217 WREG32(CP_RB2_CNTL, tmp); 1218 1219 /* Initialize the ring buffer's read and write pointers */ 1220 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); 1221 WREG32(CP_RB2_WPTR, 0); 1222 1223 /* set the wb address wether it's enabled or not */ 1224 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); 1225 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF); 1226 1227 mdelay(1); 1228 WREG32(CP_RB2_CNTL, tmp); 1229 1230 WREG32(CP_RB2_BASE, rdev->cp2.gpu_addr >> 8); 1231 1232 rdev->cp2.rptr = RREG32(CP_RB2_RPTR); 1233 rdev->cp2.wptr = RREG32(CP_RB2_WPTR); 1234 1235 /* start the rings */ 1236 cayman_cp_start(rdev); 1237 rdev->cp.ready = true; 1238 rdev->cp1.ready = true; 1239 rdev->cp2.ready = true; 1240 /* this only test cp0 */ 1241 r = radeon_ring_test(rdev); 1242 if (r) { 1243 rdev->cp.ready = false; 1244 rdev->cp1.ready = false; 1245 rdev->cp2.ready = false; 1246 return r; 1247 } 1248 1249 return 0; 1250 } 1251 1252