1 /* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #ifndef EVERGREEND_H 25 #define EVERGREEND_H 26 27 #define EVERGREEN_MAX_SH_GPRS 256 28 #define EVERGREEN_MAX_TEMP_GPRS 16 29 #define EVERGREEN_MAX_SH_THREADS 256 30 #define EVERGREEN_MAX_SH_STACK_ENTRIES 4096 31 #define EVERGREEN_MAX_FRC_EOV_CNT 16384 32 #define EVERGREEN_MAX_BACKENDS 8 33 #define EVERGREEN_MAX_BACKENDS_MASK 0xFF 34 #define EVERGREEN_MAX_SIMDS 16 35 #define EVERGREEN_MAX_SIMDS_MASK 0xFFFF 36 #define EVERGREEN_MAX_PIPES 8 37 #define EVERGREEN_MAX_PIPES_MASK 0xFF 38 #define EVERGREEN_MAX_LDS_NUM 0xFFFF 39 40 #define CYPRESS_GB_ADDR_CONFIG_GOLDEN 0x02011003 41 #define BARTS_GB_ADDR_CONFIG_GOLDEN 0x02011003 42 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 43 #define JUNIPER_GB_ADDR_CONFIG_GOLDEN 0x02010002 44 #define REDWOOD_GB_ADDR_CONFIG_GOLDEN 0x02010002 45 #define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002 46 #define CEDAR_GB_ADDR_CONFIG_GOLDEN 0x02010001 47 #define CAICOS_GB_ADDR_CONFIG_GOLDEN 0x02010001 48 #define SUMO_GB_ADDR_CONFIG_GOLDEN 0x02010002 49 #define SUMO2_GB_ADDR_CONFIG_GOLDEN 0x02010002 50 51 /* pm registers */ 52 #define SMC_MSG 0x20c 53 #define HOST_SMC_MSG(x) ((x) << 0) 54 #define HOST_SMC_MSG_MASK (0xff << 0) 55 #define HOST_SMC_MSG_SHIFT 0 56 #define HOST_SMC_RESP(x) ((x) << 8) 57 #define HOST_SMC_RESP_MASK (0xff << 8) 58 #define HOST_SMC_RESP_SHIFT 8 59 #define SMC_HOST_MSG(x) ((x) << 16) 60 #define SMC_HOST_MSG_MASK (0xff << 16) 61 #define SMC_HOST_MSG_SHIFT 16 62 #define SMC_HOST_RESP(x) ((x) << 24) 63 #define SMC_HOST_RESP_MASK (0xff << 24) 64 #define SMC_HOST_RESP_SHIFT 24 65 66 #define DCCG_DISP_SLOW_SELECT_REG 0x4fc 67 #define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0) 68 #define DCCG_DISP1_SLOW_SELECT_MASK (7 << 0) 69 #define DCCG_DISP1_SLOW_SELECT_SHIFT 0 70 #define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4) 71 #define DCCG_DISP2_SLOW_SELECT_MASK (7 << 4) 72 #define DCCG_DISP2_SLOW_SELECT_SHIFT 4 73 74 #define CG_SPLL_FUNC_CNTL 0x600 75 #define SPLL_RESET (1 << 0) 76 #define SPLL_SLEEP (1 << 1) 77 #define SPLL_BYPASS_EN (1 << 3) 78 #define SPLL_REF_DIV(x) ((x) << 4) 79 #define SPLL_REF_DIV_MASK (0x3f << 4) 80 #define SPLL_PDIV_A(x) ((x) << 20) 81 #define SPLL_PDIV_A_MASK (0x7f << 20) 82 #define CG_SPLL_FUNC_CNTL_2 0x604 83 #define SCLK_MUX_SEL(x) ((x) << 0) 84 #define SCLK_MUX_SEL_MASK (0x1ff << 0) 85 #define CG_SPLL_FUNC_CNTL_3 0x608 86 #define SPLL_FB_DIV(x) ((x) << 0) 87 #define SPLL_FB_DIV_MASK (0x3ffffff << 0) 88 #define SPLL_DITHEN (1 << 28) 89 90 #define MPLL_CNTL_MODE 0x61c 91 # define SS_SSEN (1 << 24) 92 # define SS_DSMODE_EN (1 << 25) 93 94 #define MPLL_AD_FUNC_CNTL 0x624 95 #define CLKF(x) ((x) << 0) 96 #define CLKF_MASK (0x7f << 0) 97 #define CLKR(x) ((x) << 7) 98 #define CLKR_MASK (0x1f << 7) 99 #define CLKFRAC(x) ((x) << 12) 100 #define CLKFRAC_MASK (0x1f << 12) 101 #define YCLK_POST_DIV(x) ((x) << 17) 102 #define YCLK_POST_DIV_MASK (3 << 17) 103 #define IBIAS(x) ((x) << 20) 104 #define IBIAS_MASK (0x3ff << 20) 105 #define RESET (1 << 30) 106 #define PDNB (1 << 31) 107 #define MPLL_AD_FUNC_CNTL_2 0x628 108 #define BYPASS (1 << 19) 109 #define BIAS_GEN_PDNB (1 << 24) 110 #define RESET_EN (1 << 25) 111 #define VCO_MODE (1 << 29) 112 #define MPLL_DQ_FUNC_CNTL 0x62c 113 #define MPLL_DQ_FUNC_CNTL_2 0x630 114 115 #define GENERAL_PWRMGT 0x63c 116 # define GLOBAL_PWRMGT_EN (1 << 0) 117 # define STATIC_PM_EN (1 << 1) 118 # define THERMAL_PROTECTION_DIS (1 << 2) 119 # define THERMAL_PROTECTION_TYPE (1 << 3) 120 # define ENABLE_GEN2PCIE (1 << 4) 121 # define ENABLE_GEN2XSP (1 << 5) 122 # define SW_SMIO_INDEX(x) ((x) << 6) 123 # define SW_SMIO_INDEX_MASK (3 << 6) 124 # define SW_SMIO_INDEX_SHIFT 6 125 # define LOW_VOLT_D2_ACPI (1 << 8) 126 # define LOW_VOLT_D3_ACPI (1 << 9) 127 # define VOLT_PWRMGT_EN (1 << 10) 128 # define BACKBIAS_PAD_EN (1 << 18) 129 # define BACKBIAS_VALUE (1 << 19) 130 # define DYN_SPREAD_SPECTRUM_EN (1 << 23) 131 # define AC_DC_SW (1 << 24) 132 133 #define SCLK_PWRMGT_CNTL 0x644 134 # define SCLK_PWRMGT_OFF (1 << 0) 135 # define SCLK_LOW_D1 (1 << 1) 136 # define FIR_RESET (1 << 4) 137 # define FIR_FORCE_TREND_SEL (1 << 5) 138 # define FIR_TREND_MODE (1 << 6) 139 # define DYN_GFX_CLK_OFF_EN (1 << 7) 140 # define GFX_CLK_FORCE_ON (1 << 8) 141 # define GFX_CLK_REQUEST_OFF (1 << 9) 142 # define GFX_CLK_FORCE_OFF (1 << 10) 143 # define GFX_CLK_OFF_ACPI_D1 (1 << 11) 144 # define GFX_CLK_OFF_ACPI_D2 (1 << 12) 145 # define GFX_CLK_OFF_ACPI_D3 (1 << 13) 146 # define DYN_LIGHT_SLEEP_EN (1 << 14) 147 #define MCLK_PWRMGT_CNTL 0x648 148 # define DLL_SPEED(x) ((x) << 0) 149 # define DLL_SPEED_MASK (0x1f << 0) 150 # define MPLL_PWRMGT_OFF (1 << 5) 151 # define DLL_READY (1 << 6) 152 # define MC_INT_CNTL (1 << 7) 153 # define MRDCKA0_PDNB (1 << 8) 154 # define MRDCKA1_PDNB (1 << 9) 155 # define MRDCKB0_PDNB (1 << 10) 156 # define MRDCKB1_PDNB (1 << 11) 157 # define MRDCKC0_PDNB (1 << 12) 158 # define MRDCKC1_PDNB (1 << 13) 159 # define MRDCKD0_PDNB (1 << 14) 160 # define MRDCKD1_PDNB (1 << 15) 161 # define MRDCKA0_RESET (1 << 16) 162 # define MRDCKA1_RESET (1 << 17) 163 # define MRDCKB0_RESET (1 << 18) 164 # define MRDCKB1_RESET (1 << 19) 165 # define MRDCKC0_RESET (1 << 20) 166 # define MRDCKC1_RESET (1 << 21) 167 # define MRDCKD0_RESET (1 << 22) 168 # define MRDCKD1_RESET (1 << 23) 169 # define DLL_READY_READ (1 << 24) 170 # define USE_DISPLAY_GAP (1 << 25) 171 # define USE_DISPLAY_URGENT_NORMAL (1 << 26) 172 # define MPLL_TURNOFF_D2 (1 << 28) 173 #define DLL_CNTL 0x64c 174 # define MRDCKA0_BYPASS (1 << 24) 175 # define MRDCKA1_BYPASS (1 << 25) 176 # define MRDCKB0_BYPASS (1 << 26) 177 # define MRDCKB1_BYPASS (1 << 27) 178 # define MRDCKC0_BYPASS (1 << 28) 179 # define MRDCKC1_BYPASS (1 << 29) 180 # define MRDCKD0_BYPASS (1 << 30) 181 # define MRDCKD1_BYPASS (1 << 31) 182 183 #define CG_AT 0x6d4 184 # define CG_R(x) ((x) << 0) 185 # define CG_R_MASK (0xffff << 0) 186 # define CG_L(x) ((x) << 16) 187 # define CG_L_MASK (0xffff << 16) 188 189 #define CG_DISPLAY_GAP_CNTL 0x714 190 # define DISP1_GAP(x) ((x) << 0) 191 # define DISP1_GAP_MASK (3 << 0) 192 # define DISP2_GAP(x) ((x) << 2) 193 # define DISP2_GAP_MASK (3 << 2) 194 # define VBI_TIMER_COUNT(x) ((x) << 4) 195 # define VBI_TIMER_COUNT_MASK (0x3fff << 4) 196 # define VBI_TIMER_UNIT(x) ((x) << 20) 197 # define VBI_TIMER_UNIT_MASK (7 << 20) 198 # define DISP1_GAP_MCHG(x) ((x) << 24) 199 # define DISP1_GAP_MCHG_MASK (3 << 24) 200 # define DISP2_GAP_MCHG(x) ((x) << 26) 201 # define DISP2_GAP_MCHG_MASK (3 << 26) 202 203 #define CG_BIF_REQ_AND_RSP 0x7f4 204 #define CG_CLIENT_REQ(x) ((x) << 0) 205 #define CG_CLIENT_REQ_MASK (0xff << 0) 206 #define CG_CLIENT_REQ_SHIFT 0 207 #define CG_CLIENT_RESP(x) ((x) << 8) 208 #define CG_CLIENT_RESP_MASK (0xff << 8) 209 #define CG_CLIENT_RESP_SHIFT 8 210 #define CLIENT_CG_REQ(x) ((x) << 16) 211 #define CLIENT_CG_REQ_MASK (0xff << 16) 212 #define CLIENT_CG_REQ_SHIFT 16 213 #define CLIENT_CG_RESP(x) ((x) << 24) 214 #define CLIENT_CG_RESP_MASK (0xff << 24) 215 #define CLIENT_CG_RESP_SHIFT 24 216 217 #define CG_SPLL_SPREAD_SPECTRUM 0x790 218 #define SSEN (1 << 0) 219 #define CG_SPLL_SPREAD_SPECTRUM_2 0x794 220 221 #define MPLL_SS1 0x85c 222 #define CLKV(x) ((x) << 0) 223 #define CLKV_MASK (0x3ffffff << 0) 224 #define MPLL_SS2 0x860 225 #define CLKS(x) ((x) << 0) 226 #define CLKS_MASK (0xfff << 0) 227 228 #define CG_IND_ADDR 0x8f8 229 #define CG_IND_DATA 0x8fc 230 /* CGIND regs */ 231 #define CG_CGTT_LOCAL_0 0x00 232 #define CG_CGTT_LOCAL_1 0x01 233 #define CG_CGTT_LOCAL_2 0x02 234 #define CG_CGTT_LOCAL_3 0x03 235 #define CG_CGLS_TILE_0 0x20 236 #define CG_CGLS_TILE_1 0x21 237 #define CG_CGLS_TILE_2 0x22 238 #define CG_CGLS_TILE_3 0x23 239 #define CG_CGLS_TILE_4 0x24 240 #define CG_CGLS_TILE_5 0x25 241 #define CG_CGLS_TILE_6 0x26 242 #define CG_CGLS_TILE_7 0x27 243 #define CG_CGLS_TILE_8 0x28 244 #define CG_CGLS_TILE_9 0x29 245 #define CG_CGLS_TILE_10 0x2a 246 #define CG_CGLS_TILE_11 0x2b 247 248 #define VM_L2_CG 0x15c0 249 250 #define MC_CONFIG 0x2000 251 252 #define MC_CONFIG_MCD 0x20a0 253 #define MC_CG_CONFIG_MCD 0x20a4 254 #define MC_RD_ENABLE_MCD(x) ((x) << 8) 255 #define MC_RD_ENABLE_MCD_MASK (7 << 8) 256 257 #define MC_HUB_MISC_HUB_CG 0x20b8 258 #define MC_HUB_MISC_VM_CG 0x20bc 259 #define MC_HUB_MISC_SIP_CG 0x20c0 260 261 #define MC_XPB_CLK_GAT 0x2478 262 263 #define MC_CG_CONFIG 0x25bc 264 #define MC_RD_ENABLE(x) ((x) << 4) 265 #define MC_RD_ENABLE_MASK (3 << 4) 266 267 #define MC_CITF_MISC_RD_CG 0x2648 268 #define MC_CITF_MISC_WR_CG 0x264c 269 #define MC_CITF_MISC_VM_CG 0x2650 270 # define MEM_LS_ENABLE (1 << 19) 271 272 #define MC_ARB_BURST_TIME 0x2808 273 #define STATE0(x) ((x) << 0) 274 #define STATE0_MASK (0x1f << 0) 275 #define STATE1(x) ((x) << 5) 276 #define STATE1_MASK (0x1f << 5) 277 #define STATE2(x) ((x) << 10) 278 #define STATE2_MASK (0x1f << 10) 279 #define STATE3(x) ((x) << 15) 280 #define STATE3_MASK (0x1f << 15) 281 282 #define MC_SEQ_RAS_TIMING 0x28a0 283 #define MC_SEQ_CAS_TIMING 0x28a4 284 #define MC_SEQ_MISC_TIMING 0x28a8 285 #define MC_SEQ_MISC_TIMING2 0x28ac 286 287 #define MC_SEQ_RD_CTL_D0 0x28b4 288 #define MC_SEQ_RD_CTL_D1 0x28b8 289 #define MC_SEQ_WR_CTL_D0 0x28bc 290 #define MC_SEQ_WR_CTL_D1 0x28c0 291 292 #define MC_SEQ_STATUS_M 0x29f4 293 # define PMG_PWRSTATE (1 << 16) 294 295 #define MC_SEQ_MISC1 0x2a04 296 #define MC_SEQ_RESERVE_M 0x2a08 297 #define MC_PMG_CMD_EMRS 0x2a0c 298 299 #define MC_SEQ_MISC3 0x2a2c 300 301 #define MC_SEQ_MISC5 0x2a54 302 #define MC_SEQ_MISC6 0x2a58 303 304 #define MC_SEQ_MISC7 0x2a64 305 306 #define MC_SEQ_CG 0x2a68 307 #define CG_SEQ_REQ(x) ((x) << 0) 308 #define CG_SEQ_REQ_MASK (0xff << 0) 309 #define CG_SEQ_REQ_SHIFT 0 310 #define CG_SEQ_RESP(x) ((x) << 8) 311 #define CG_SEQ_RESP_MASK (0xff << 8) 312 #define CG_SEQ_RESP_SHIFT 8 313 #define SEQ_CG_REQ(x) ((x) << 16) 314 #define SEQ_CG_REQ_MASK (0xff << 16) 315 #define SEQ_CG_REQ_SHIFT 16 316 #define SEQ_CG_RESP(x) ((x) << 24) 317 #define SEQ_CG_RESP_MASK (0xff << 24) 318 #define SEQ_CG_RESP_SHIFT 24 319 #define MC_SEQ_RAS_TIMING_LP 0x2a6c 320 #define MC_SEQ_CAS_TIMING_LP 0x2a70 321 #define MC_SEQ_MISC_TIMING_LP 0x2a74 322 #define MC_SEQ_MISC_TIMING2_LP 0x2a78 323 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c 324 #define MC_SEQ_WR_CTL_D1_LP 0x2a80 325 #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 326 #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 327 328 #define MC_PMG_CMD_MRS 0x2aac 329 330 #define MC_SEQ_RD_CTL_D0_LP 0x2b1c 331 #define MC_SEQ_RD_CTL_D1_LP 0x2b20 332 333 #define MC_PMG_CMD_MRS1 0x2b44 334 #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 335 336 #define CGTS_SM_CTRL_REG 0x9150 337 338 /* Registers */ 339 340 #define RCU_IND_INDEX 0x100 341 #define RCU_IND_DATA 0x104 342 343 /* discrete uvd clocks */ 344 #define CG_UPLL_FUNC_CNTL 0x718 345 # define UPLL_RESET_MASK 0x00000001 346 # define UPLL_SLEEP_MASK 0x00000002 347 # define UPLL_BYPASS_EN_MASK 0x00000004 348 # define UPLL_CTLREQ_MASK 0x00000008 349 # define UPLL_REF_DIV_MASK 0x003F0000 350 # define UPLL_VCO_MODE_MASK 0x00000200 351 # define UPLL_CTLACK_MASK 0x40000000 352 # define UPLL_CTLACK2_MASK 0x80000000 353 #define CG_UPLL_FUNC_CNTL_2 0x71c 354 # define UPLL_PDIV_A(x) ((x) << 0) 355 # define UPLL_PDIV_A_MASK 0x0000007F 356 # define UPLL_PDIV_B(x) ((x) << 8) 357 # define UPLL_PDIV_B_MASK 0x00007F00 358 # define VCLK_SRC_SEL(x) ((x) << 20) 359 # define VCLK_SRC_SEL_MASK 0x01F00000 360 # define DCLK_SRC_SEL(x) ((x) << 25) 361 # define DCLK_SRC_SEL_MASK 0x3E000000 362 #define CG_UPLL_FUNC_CNTL_3 0x720 363 # define UPLL_FB_DIV(x) ((x) << 0) 364 # define UPLL_FB_DIV_MASK 0x01FFFFFF 365 #define CG_UPLL_FUNC_CNTL_4 0x854 366 # define UPLL_SPARE_ISPARE9 0x00020000 367 #define CG_UPLL_SPREAD_SPECTRUM 0x79c 368 # define SSEN_MASK 0x00000001 369 370 /* fusion uvd clocks */ 371 #define CG_DCLK_CNTL 0x610 372 # define DCLK_DIVIDER_MASK 0x7f 373 # define DCLK_DIR_CNTL_EN (1 << 8) 374 #define CG_DCLK_STATUS 0x614 375 # define DCLK_STATUS (1 << 0) 376 #define CG_VCLK_CNTL 0x618 377 #define CG_VCLK_STATUS 0x61c 378 #define CG_SCRATCH1 0x820 379 380 #define RLC_CNTL 0x3f00 381 # define RLC_ENABLE (1 << 0) 382 # define GFX_POWER_GATING_ENABLE (1 << 7) 383 # define GFX_POWER_GATING_SRC (1 << 8) 384 # define DYN_PER_SIMD_PG_ENABLE (1 << 27) 385 # define LB_CNT_SPIM_ACTIVE (1 << 30) 386 # define LOAD_BALANCE_ENABLE (1 << 31) 387 388 #define RLC_HB_BASE 0x3f10 389 #define RLC_HB_CNTL 0x3f0c 390 #define RLC_HB_RPTR 0x3f20 391 #define RLC_HB_WPTR 0x3f1c 392 #define RLC_HB_WPTR_LSB_ADDR 0x3f14 393 #define RLC_HB_WPTR_MSB_ADDR 0x3f18 394 #define RLC_MC_CNTL 0x3f44 395 #define RLC_UCODE_CNTL 0x3f48 396 #define RLC_UCODE_ADDR 0x3f2c 397 #define RLC_UCODE_DATA 0x3f30 398 399 /* new for TN */ 400 #define TN_RLC_SAVE_AND_RESTORE_BASE 0x3f10 401 #define TN_RLC_LB_CNTR_MAX 0x3f14 402 #define TN_RLC_LB_CNTR_INIT 0x3f18 403 #define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20 404 #define TN_RLC_LB_INIT_SIMD_MASK 0x3fe4 405 #define TN_RLC_LB_ALWAYS_ACTIVE_SIMD_MASK 0x3fe8 406 #define TN_RLC_LB_PARAMS 0x3fec 407 408 #define GRBM_GFX_INDEX 0x802C 409 #define INSTANCE_INDEX(x) ((x) << 0) 410 #define SE_INDEX(x) ((x) << 16) 411 #define INSTANCE_BROADCAST_WRITES (1 << 30) 412 #define SE_BROADCAST_WRITES (1 << 31) 413 #define RLC_GFX_INDEX 0x3fC4 414 #define CC_GC_SHADER_PIPE_CONFIG 0x8950 415 #define WRITE_DIS (1 << 0) 416 #define CC_RB_BACKEND_DISABLE 0x98F4 417 #define BACKEND_DISABLE(x) ((x) << 16) 418 #define GB_ADDR_CONFIG 0x98F8 419 #define NUM_PIPES(x) ((x) << 0) 420 #define NUM_PIPES_MASK 0x0000000f 421 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 422 #define BANK_INTERLEAVE_SIZE(x) ((x) << 8) 423 #define NUM_SHADER_ENGINES(x) ((x) << 12) 424 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 425 #define NUM_GPUS(x) ((x) << 20) 426 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 427 #define ROW_SIZE(x) ((x) << 28) 428 #define GB_BACKEND_MAP 0x98FC 429 #define DMIF_ADDR_CONFIG 0xBD4 430 #define HDP_ADDR_CONFIG 0x2F48 431 #define HDP_MISC_CNTL 0x2F4C 432 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 433 434 #define CC_SYS_RB_BACKEND_DISABLE 0x3F88 435 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 436 437 #define CGTS_SYS_TCC_DISABLE 0x3F90 438 #define CGTS_TCC_DISABLE 0x9148 439 #define CGTS_USER_SYS_TCC_DISABLE 0x3F94 440 #define CGTS_USER_TCC_DISABLE 0x914C 441 442 #define CONFIG_MEMSIZE 0x5428 443 444 #define BIF_FB_EN 0x5490 445 #define FB_READ_EN (1 << 0) 446 #define FB_WRITE_EN (1 << 1) 447 448 #define CP_STRMOUT_CNTL 0x84FC 449 450 #define CP_COHER_CNTL 0x85F0 451 #define CP_COHER_SIZE 0x85F4 452 #define CP_COHER_BASE 0x85F8 453 #define CP_STALLED_STAT1 0x8674 454 #define CP_STALLED_STAT2 0x8678 455 #define CP_BUSY_STAT 0x867C 456 #define CP_STAT 0x8680 457 #define CP_ME_CNTL 0x86D8 458 #define CP_ME_HALT (1 << 28) 459 #define CP_PFP_HALT (1 << 26) 460 #define CP_ME_RAM_DATA 0xC160 461 #define CP_ME_RAM_RADDR 0xC158 462 #define CP_ME_RAM_WADDR 0xC15C 463 #define CP_MEQ_THRESHOLDS 0x8764 464 #define STQ_SPLIT(x) ((x) << 0) 465 #define CP_PERFMON_CNTL 0x87FC 466 #define CP_PFP_UCODE_ADDR 0xC150 467 #define CP_PFP_UCODE_DATA 0xC154 468 #define CP_QUEUE_THRESHOLDS 0x8760 469 #define ROQ_IB1_START(x) ((x) << 0) 470 #define ROQ_IB2_START(x) ((x) << 8) 471 #define CP_RB_BASE 0xC100 472 #define CP_RB_CNTL 0xC104 473 #define RB_BUFSZ(x) ((x) << 0) 474 #define RB_BLKSZ(x) ((x) << 8) 475 #define RB_NO_UPDATE (1 << 27) 476 #define RB_RPTR_WR_ENA (1 << 31) 477 #define BUF_SWAP_32BIT (2 << 16) 478 #define CP_RB_RPTR 0x8700 479 #define CP_RB_RPTR_ADDR 0xC10C 480 #define RB_RPTR_SWAP(x) ((x) << 0) 481 #define CP_RB_RPTR_ADDR_HI 0xC110 482 #define CP_RB_RPTR_WR 0xC108 483 #define CP_RB_WPTR 0xC114 484 #define CP_RB_WPTR_ADDR 0xC118 485 #define CP_RB_WPTR_ADDR_HI 0xC11C 486 #define CP_RB_WPTR_DELAY 0x8704 487 #define CP_SEM_WAIT_TIMER 0x85BC 488 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 489 #define CP_DEBUG 0xC1FC 490 491 /* Audio clocks */ 492 #define DCCG_AUDIO_DTO_SOURCE 0x05ac 493 # define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */ 494 # define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */ 495 496 #define DCCG_AUDIO_DTO0_PHASE 0x05b0 497 #define DCCG_AUDIO_DTO0_MODULE 0x05b4 498 #define DCCG_AUDIO_DTO0_LOAD 0x05b8 499 #define DCCG_AUDIO_DTO0_CNTL 0x05bc 500 # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO(x) (((x) & 7) << 0) 501 # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK 7 502 # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_SHIFT 0 503 504 #define DCCG_AUDIO_DTO1_PHASE 0x05c0 505 #define DCCG_AUDIO_DTO1_MODULE 0x05c4 506 #define DCCG_AUDIO_DTO1_LOAD 0x05c8 507 #define DCCG_AUDIO_DTO1_CNTL 0x05cc 508 509 /* DCE 4.0 AFMT */ 510 #define HDMI_CONTROL 0x7030 511 # define HDMI_KEEPOUT_MODE (1 << 0) 512 # define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */ 513 # define HDMI_ERROR_ACK (1 << 8) 514 # define HDMI_ERROR_MASK (1 << 9) 515 # define HDMI_DEEP_COLOR_ENABLE (1 << 24) 516 # define HDMI_DEEP_COLOR_DEPTH (((x) & 3) << 28) 517 # define HDMI_24BIT_DEEP_COLOR 0 518 # define HDMI_30BIT_DEEP_COLOR 1 519 # define HDMI_36BIT_DEEP_COLOR 2 520 #define HDMI_STATUS 0x7034 521 # define HDMI_ACTIVE_AVMUTE (1 << 0) 522 # define HDMI_AUDIO_PACKET_ERROR (1 << 16) 523 # define HDMI_VBI_PACKET_ERROR (1 << 20) 524 #define HDMI_AUDIO_PACKET_CONTROL 0x7038 525 # define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4) 526 # define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) 527 #define HDMI_ACR_PACKET_CONTROL 0x703c 528 # define HDMI_ACR_SEND (1 << 0) 529 # define HDMI_ACR_CONT (1 << 1) 530 # define HDMI_ACR_SELECT(x) (((x) & 3) << 4) 531 # define HDMI_ACR_HW 0 532 # define HDMI_ACR_32 1 533 # define HDMI_ACR_44 2 534 # define HDMI_ACR_48 3 535 # define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ 536 # define HDMI_ACR_AUTO_SEND (1 << 12) 537 # define HDMI_ACR_N_MULTIPLE(x) (((x) & 7) << 16) 538 # define HDMI_ACR_X1 1 539 # define HDMI_ACR_X2 2 540 # define HDMI_ACR_X4 4 541 # define HDMI_ACR_AUDIO_PRIORITY (1 << 31) 542 #define HDMI_VBI_PACKET_CONTROL 0x7040 543 # define HDMI_NULL_SEND (1 << 0) 544 # define HDMI_GC_SEND (1 << 4) 545 # define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ 546 #define HDMI_INFOFRAME_CONTROL0 0x7044 547 # define HDMI_AVI_INFO_SEND (1 << 0) 548 # define HDMI_AVI_INFO_CONT (1 << 1) 549 # define HDMI_AUDIO_INFO_SEND (1 << 4) 550 # define HDMI_AUDIO_INFO_CONT (1 << 5) 551 # define HDMI_MPEG_INFO_SEND (1 << 8) 552 # define HDMI_MPEG_INFO_CONT (1 << 9) 553 #define HDMI_INFOFRAME_CONTROL1 0x7048 554 # define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) 555 # define HDMI_AVI_INFO_LINE_MASK (0x3f << 0) 556 # define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) 557 # define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) 558 #define HDMI_GENERIC_PACKET_CONTROL 0x704c 559 # define HDMI_GENERIC0_SEND (1 << 0) 560 # define HDMI_GENERIC0_CONT (1 << 1) 561 # define HDMI_GENERIC1_SEND (1 << 4) 562 # define HDMI_GENERIC1_CONT (1 << 5) 563 # define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16) 564 # define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24) 565 #define HDMI_GC 0x7058 566 # define HDMI_GC_AVMUTE (1 << 0) 567 # define HDMI_GC_AVMUTE_CONT (1 << 2) 568 #define AFMT_AUDIO_PACKET_CONTROL2 0x705c 569 # define AFMT_AUDIO_LAYOUT_OVRD (1 << 0) 570 # define AFMT_AUDIO_LAYOUT_SELECT (1 << 1) 571 # define AFMT_60958_CS_SOURCE (1 << 4) 572 # define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8) 573 # define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16) 574 #define AFMT_AVI_INFO0 0x7084 575 # define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 576 # define AFMT_AVI_INFO_S(x) (((x) & 3) << 8) 577 # define AFMT_AVI_INFO_B(x) (((x) & 3) << 10) 578 # define AFMT_AVI_INFO_A(x) (((x) & 1) << 12) 579 # define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13) 580 # define AFMT_AVI_INFO_Y_RGB 0 581 # define AFMT_AVI_INFO_Y_YCBCR422 1 582 # define AFMT_AVI_INFO_Y_YCBCR444 2 583 # define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) 584 # define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16) 585 # define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20) 586 # define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22) 587 # define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) 588 # define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24) 589 # define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26) 590 # define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28) 591 # define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31) 592 # define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) 593 #define AFMT_AVI_INFO1 0x7088 594 # define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ 595 # define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ 596 # define AFMT_AVI_INFO_CN(x) (((x) & 0x3) << 12) 597 # define AFMT_AVI_INFO_YQ(x) (((x) & 0x3) << 14) 598 # define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) 599 #define AFMT_AVI_INFO2 0x708c 600 # define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) 601 # define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) 602 #define AFMT_AVI_INFO3 0x7090 603 # define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) 604 # define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24) 605 #define AFMT_MPEG_INFO0 0x7094 606 # define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 607 # define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) 608 # define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) 609 # define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) 610 #define AFMT_MPEG_INFO1 0x7098 611 # define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) 612 # define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8) 613 # define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12) 614 #define AFMT_GENERIC0_HDR 0x709c 615 #define AFMT_GENERIC0_0 0x70a0 616 #define AFMT_GENERIC0_1 0x70a4 617 #define AFMT_GENERIC0_2 0x70a8 618 #define AFMT_GENERIC0_3 0x70ac 619 #define AFMT_GENERIC0_4 0x70b0 620 #define AFMT_GENERIC0_5 0x70b4 621 #define AFMT_GENERIC0_6 0x70b8 622 #define AFMT_GENERIC1_HDR 0x70bc 623 #define AFMT_GENERIC1_0 0x70c0 624 #define AFMT_GENERIC1_1 0x70c4 625 #define AFMT_GENERIC1_2 0x70c8 626 #define AFMT_GENERIC1_3 0x70cc 627 #define AFMT_GENERIC1_4 0x70d0 628 #define AFMT_GENERIC1_5 0x70d4 629 #define AFMT_GENERIC1_6 0x70d8 630 #define HDMI_ACR_32_0 0x70dc 631 # define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12) 632 #define HDMI_ACR_32_1 0x70e0 633 # define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0) 634 #define HDMI_ACR_44_0 0x70e4 635 # define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12) 636 #define HDMI_ACR_44_1 0x70e8 637 # define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0) 638 #define HDMI_ACR_48_0 0x70ec 639 # define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12) 640 #define HDMI_ACR_48_1 0x70f0 641 # define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0) 642 #define HDMI_ACR_STATUS_0 0x70f4 643 #define HDMI_ACR_STATUS_1 0x70f8 644 #define AFMT_AUDIO_INFO0 0x70fc 645 # define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 646 # define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8) 647 # define AFMT_AUDIO_INFO_CT(x) (((x) & 0xf) << 11) 648 # define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16) 649 # define AFMT_AUDIO_INFO_CXT(x) (((x) & 0x1f) << 24) 650 #define AFMT_AUDIO_INFO1 0x7100 651 # define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) 652 # define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) 653 # define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) 654 # define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) 655 # define AFMT_AUDIO_INFO_LFEBPL(x) (((x) & 3) << 16) 656 #define AFMT_60958_0 0x7104 657 # define AFMT_60958_CS_A(x) (((x) & 1) << 0) 658 # define AFMT_60958_CS_B(x) (((x) & 1) << 1) 659 # define AFMT_60958_CS_C(x) (((x) & 1) << 2) 660 # define AFMT_60958_CS_D(x) (((x) & 3) << 3) 661 # define AFMT_60958_CS_MODE(x) (((x) & 3) << 6) 662 # define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) 663 # define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) 664 # define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) 665 # define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) 666 # define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) 667 #define AFMT_60958_1 0x7108 668 # define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) 669 # define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) 670 # define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16) 671 # define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18) 672 # define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) 673 #define AFMT_AUDIO_CRC_CONTROL 0x710c 674 # define AFMT_AUDIO_CRC_EN (1 << 0) 675 #define AFMT_RAMP_CONTROL0 0x7110 676 # define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) 677 # define AFMT_RAMP_DATA_SIGN (1 << 31) 678 #define AFMT_RAMP_CONTROL1 0x7114 679 # define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) 680 # define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24) 681 #define AFMT_RAMP_CONTROL2 0x7118 682 # define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) 683 #define AFMT_RAMP_CONTROL3 0x711c 684 # define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) 685 #define AFMT_60958_2 0x7120 686 # define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) 687 # define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) 688 # define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) 689 # define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) 690 # define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) 691 # define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) 692 #define AFMT_STATUS 0x7128 693 # define AFMT_AUDIO_ENABLE (1 << 4) 694 # define AFMT_AUDIO_HBR_ENABLE (1 << 8) 695 # define AFMT_AZ_FORMAT_WTRIG (1 << 28) 696 # define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) 697 # define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) 698 #define AFMT_AUDIO_PACKET_CONTROL 0x712c 699 # define AFMT_AUDIO_SAMPLE_SEND (1 << 0) 700 # define AFMT_RESET_FIFO_WHEN_AUDIO_DIS (1 << 11) /* set to 1 */ 701 # define AFMT_AUDIO_TEST_EN (1 << 12) 702 # define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) 703 # define AFMT_60958_CS_UPDATE (1 << 26) 704 # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) 705 # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) 706 # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) 707 # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) 708 #define AFMT_VBI_PACKET_CONTROL 0x7130 709 # define AFMT_GENERIC0_UPDATE (1 << 2) 710 #define AFMT_INFOFRAME_CONTROL0 0x7134 711 # define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - afmt regs */ 712 # define AFMT_AUDIO_INFO_UPDATE (1 << 7) 713 # define AFMT_MPEG_INFO_UPDATE (1 << 10) 714 #define AFMT_GENERIC0_7 0x7138 715 716 /* DCE4/5 ELD audio interface */ 717 #define AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER 0x5f78 718 #define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0) 719 #define SPEAKER_ALLOCATION_MASK (0x7f << 0) 720 #define SPEAKER_ALLOCATION_SHIFT 0 721 #define HDMI_CONNECTION (1 << 16) 722 #define DP_CONNECTION (1 << 17) 723 724 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x5f84 /* LPCM */ 725 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x5f88 /* AC3 */ 726 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x5f8c /* MPEG1 */ 727 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x5f90 /* MP3 */ 728 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x5f94 /* MPEG2 */ 729 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x5f98 /* AAC */ 730 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x5f9c /* DTS */ 731 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x5fa0 /* ATRAC */ 732 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x5fa4 /* one bit audio - leave at 0 (default) */ 733 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x5fa8 /* Dolby Digital */ 734 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x5fac /* DTS-HD */ 735 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x5fb0 /* MAT-MLP */ 736 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x5fb4 /* DTS */ 737 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x5fb8 /* WMA Pro */ 738 # define MAX_CHANNELS(x) (((x) & 0x7) << 0) 739 /* max channels minus one. 7 = 8 channels */ 740 # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) 741 # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) 742 # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ 743 /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO 744 * bit0 = 32 kHz 745 * bit1 = 44.1 kHz 746 * bit2 = 48 kHz 747 * bit3 = 88.2 kHz 748 * bit4 = 96 kHz 749 * bit5 = 176.4 kHz 750 * bit6 = 192 kHz 751 */ 752 753 #define AZ_CHANNEL_COUNT_CONTROL 0x5fe4 754 # define HBR_CHANNEL_COUNT(x) (((x) & 0x7) << 0) 755 # define COMPRESSED_CHANNEL_COUNT(x) (((x) & 0x7) << 4) 756 /* HBR_CHANNEL_COUNT, COMPRESSED_CHANNEL_COUNT 757 * 0 = use stream header 758 * 1-7 = channel count - 1 759 */ 760 #define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC 0x5fe8 761 # define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0) 762 # define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8) 763 /* VIDEO_LIPSYNC, AUDIO_LIPSYNC 764 * 0 = invalid 765 * x = legal delay value 766 * 255 = sync not supported 767 */ 768 #define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_HBR 0x5fec 769 # define HBR_CAPABLE (1 << 0) /* enabled by default */ 770 771 #define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0 0x5ff4 772 # define DISPLAY0_TYPE(x) (((x) & 0x3) << 0) 773 # define DISPLAY_TYPE_NONE 0 774 # define DISPLAY_TYPE_HDMI 1 775 # define DISPLAY_TYPE_DP 2 776 # define DISPLAY0_ID(x) (((x) & 0x3f) << 2) 777 # define DISPLAY1_TYPE(x) (((x) & 0x3) << 8) 778 # define DISPLAY1_ID(x) (((x) & 0x3f) << 10) 779 # define DISPLAY2_TYPE(x) (((x) & 0x3) << 16) 780 # define DISPLAY2_ID(x) (((x) & 0x3f) << 18) 781 # define DISPLAY3_TYPE(x) (((x) & 0x3) << 24) 782 # define DISPLAY3_ID(x) (((x) & 0x3f) << 26) 783 #define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1 0x5ff8 784 # define DISPLAY4_TYPE(x) (((x) & 0x3) << 0) 785 # define DISPLAY4_ID(x) (((x) & 0x3f) << 2) 786 # define DISPLAY5_TYPE(x) (((x) & 0x3) << 8) 787 # define DISPLAY5_ID(x) (((x) & 0x3f) << 10) 788 #define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_NUMBER 0x5ffc 789 # define NUMBER_OF_DISPLAY_ID(x) (((x) & 0x7) << 0) 790 791 #define AZ_HOT_PLUG_CONTROL 0x5e78 792 # define AZ_FORCE_CODEC_WAKE (1 << 0) 793 # define PIN0_JACK_DETECTION_ENABLE (1 << 4) 794 # define PIN1_JACK_DETECTION_ENABLE (1 << 5) 795 # define PIN2_JACK_DETECTION_ENABLE (1 << 6) 796 # define PIN3_JACK_DETECTION_ENABLE (1 << 7) 797 # define PIN0_UNSOLICITED_RESPONSE_ENABLE (1 << 8) 798 # define PIN1_UNSOLICITED_RESPONSE_ENABLE (1 << 9) 799 # define PIN2_UNSOLICITED_RESPONSE_ENABLE (1 << 10) 800 # define PIN3_UNSOLICITED_RESPONSE_ENABLE (1 << 11) 801 # define CODEC_HOT_PLUG_ENABLE (1 << 12) 802 # define PIN0_AUDIO_ENABLED (1 << 24) 803 # define PIN1_AUDIO_ENABLED (1 << 25) 804 # define PIN2_AUDIO_ENABLED (1 << 26) 805 # define PIN3_AUDIO_ENABLED (1 << 27) 806 # define AUDIO_ENABLED (1 << 31) 807 808 809 #define GC_USER_SHADER_PIPE_CONFIG 0x8954 810 #define INACTIVE_QD_PIPES(x) ((x) << 8) 811 #define INACTIVE_QD_PIPES_MASK 0x0000FF00 812 #define INACTIVE_SIMDS(x) ((x) << 16) 813 #define INACTIVE_SIMDS_MASK 0x00FF0000 814 815 #define GRBM_CNTL 0x8000 816 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 817 #define GRBM_SOFT_RESET 0x8020 818 #define SOFT_RESET_CP (1 << 0) 819 #define SOFT_RESET_CB (1 << 1) 820 #define SOFT_RESET_DB (1 << 3) 821 #define SOFT_RESET_PA (1 << 5) 822 #define SOFT_RESET_SC (1 << 6) 823 #define SOFT_RESET_SPI (1 << 8) 824 #define SOFT_RESET_SH (1 << 9) 825 #define SOFT_RESET_SX (1 << 10) 826 #define SOFT_RESET_TC (1 << 11) 827 #define SOFT_RESET_TA (1 << 12) 828 #define SOFT_RESET_VC (1 << 13) 829 #define SOFT_RESET_VGT (1 << 14) 830 831 #define GRBM_STATUS 0x8010 832 #define CMDFIFO_AVAIL_MASK 0x0000000F 833 #define SRBM_RQ_PENDING (1 << 5) 834 #define CF_RQ_PENDING (1 << 7) 835 #define PF_RQ_PENDING (1 << 8) 836 #define GRBM_EE_BUSY (1 << 10) 837 #define SX_CLEAN (1 << 11) 838 #define DB_CLEAN (1 << 12) 839 #define CB_CLEAN (1 << 13) 840 #define TA_BUSY (1 << 14) 841 #define VGT_BUSY_NO_DMA (1 << 16) 842 #define VGT_BUSY (1 << 17) 843 #define SX_BUSY (1 << 20) 844 #define SH_BUSY (1 << 21) 845 #define SPI_BUSY (1 << 22) 846 #define SC_BUSY (1 << 24) 847 #define PA_BUSY (1 << 25) 848 #define DB_BUSY (1 << 26) 849 #define CP_COHERENCY_BUSY (1 << 28) 850 #define CP_BUSY (1 << 29) 851 #define CB_BUSY (1 << 30) 852 #define GUI_ACTIVE (1 << 31) 853 #define GRBM_STATUS_SE0 0x8014 854 #define GRBM_STATUS_SE1 0x8018 855 #define SE_SX_CLEAN (1 << 0) 856 #define SE_DB_CLEAN (1 << 1) 857 #define SE_CB_CLEAN (1 << 2) 858 #define SE_TA_BUSY (1 << 25) 859 #define SE_SX_BUSY (1 << 26) 860 #define SE_SPI_BUSY (1 << 27) 861 #define SE_SH_BUSY (1 << 28) 862 #define SE_SC_BUSY (1 << 29) 863 #define SE_DB_BUSY (1 << 30) 864 #define SE_CB_BUSY (1 << 31) 865 /* evergreen */ 866 #define CG_THERMAL_CTRL 0x72c 867 #define TOFFSET_MASK 0x00003FE0 868 #define TOFFSET_SHIFT 5 869 #define DIG_THERM_DPM(x) ((x) << 14) 870 #define DIG_THERM_DPM_MASK 0x003FC000 871 #define DIG_THERM_DPM_SHIFT 14 872 873 #define CG_THERMAL_INT 0x734 874 #define DIG_THERM_INTH(x) ((x) << 8) 875 #define DIG_THERM_INTH_MASK 0x0000FF00 876 #define DIG_THERM_INTH_SHIFT 8 877 #define DIG_THERM_INTL(x) ((x) << 16) 878 #define DIG_THERM_INTL_MASK 0x00FF0000 879 #define DIG_THERM_INTL_SHIFT 16 880 #define THERM_INT_MASK_HIGH (1 << 24) 881 #define THERM_INT_MASK_LOW (1 << 25) 882 883 #define TN_CG_THERMAL_INT_CTRL 0x738 884 #define TN_DIG_THERM_INTH(x) ((x) << 0) 885 #define TN_DIG_THERM_INTH_MASK 0x000000FF 886 #define TN_DIG_THERM_INTH_SHIFT 0 887 #define TN_DIG_THERM_INTL(x) ((x) << 8) 888 #define TN_DIG_THERM_INTL_MASK 0x0000FF00 889 #define TN_DIG_THERM_INTL_SHIFT 8 890 #define TN_THERM_INT_MASK_HIGH (1 << 24) 891 #define TN_THERM_INT_MASK_LOW (1 << 25) 892 893 #define CG_MULT_THERMAL_STATUS 0x740 894 #define ASIC_T(x) ((x) << 16) 895 #define ASIC_T_MASK 0x07FF0000 896 #define ASIC_T_SHIFT 16 897 #define CG_TS0_STATUS 0x760 898 #define TS0_ADC_DOUT_MASK 0x000003FF 899 #define TS0_ADC_DOUT_SHIFT 0 900 901 /* APU */ 902 #define CG_THERMAL_STATUS 0x678 903 904 #define HDP_HOST_PATH_CNTL 0x2C00 905 #define HDP_NONSURFACE_BASE 0x2C04 906 #define HDP_NONSURFACE_INFO 0x2C08 907 #define HDP_NONSURFACE_SIZE 0x2C0C 908 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 909 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 910 #define HDP_TILING_CONFIG 0x2F3C 911 912 #define MC_SHARED_CHMAP 0x2004 913 #define NOOFCHAN_SHIFT 12 914 #define NOOFCHAN_MASK 0x00003000 915 #define MC_SHARED_CHREMAP 0x2008 916 917 #define MC_SHARED_BLACKOUT_CNTL 0x20ac 918 #define BLACKOUT_MODE_MASK 0x00000007 919 920 #define MC_ARB_RAMCFG 0x2760 921 #define NOOFBANK_SHIFT 0 922 #define NOOFBANK_MASK 0x00000003 923 #define NOOFRANK_SHIFT 2 924 #define NOOFRANK_MASK 0x00000004 925 #define NOOFROWS_SHIFT 3 926 #define NOOFROWS_MASK 0x00000038 927 #define NOOFCOLS_SHIFT 6 928 #define NOOFCOLS_MASK 0x000000C0 929 #define CHANSIZE_SHIFT 8 930 #define CHANSIZE_MASK 0x00000100 931 #define BURSTLENGTH_SHIFT 9 932 #define BURSTLENGTH_MASK 0x00000200 933 #define CHANSIZE_OVERRIDE (1 << 11) 934 #define FUS_MC_ARB_RAMCFG 0x2768 935 #define MC_VM_AGP_TOP 0x2028 936 #define MC_VM_AGP_BOT 0x202C 937 #define MC_VM_AGP_BASE 0x2030 938 #define MC_VM_FB_LOCATION 0x2024 939 #define MC_FUS_VM_FB_OFFSET 0x2898 940 #define MC_VM_MB_L1_TLB0_CNTL 0x2234 941 #define MC_VM_MB_L1_TLB1_CNTL 0x2238 942 #define MC_VM_MB_L1_TLB2_CNTL 0x223C 943 #define MC_VM_MB_L1_TLB3_CNTL 0x2240 944 #define ENABLE_L1_TLB (1 << 0) 945 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 946 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 947 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 948 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 949 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 950 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 951 #define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) 952 #define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) 953 #define MC_VM_MD_L1_TLB0_CNTL 0x2654 954 #define MC_VM_MD_L1_TLB1_CNTL 0x2658 955 #define MC_VM_MD_L1_TLB2_CNTL 0x265C 956 #define MC_VM_MD_L1_TLB3_CNTL 0x2698 957 958 #define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C 959 #define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660 960 #define FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664 961 962 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 963 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 964 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 965 966 #define PA_CL_ENHANCE 0x8A14 967 #define CLIP_VTX_REORDER_ENA (1 << 0) 968 #define NUM_CLIP_SEQ(x) ((x) << 1) 969 #define PA_SC_ENHANCE 0x8BF0 970 #define PA_SC_AA_CONFIG 0x28C04 971 #define MSAA_NUM_SAMPLES_SHIFT 0 972 #define MSAA_NUM_SAMPLES_MASK 0x3 973 #define PA_SC_CLIPRECT_RULE 0x2820C 974 #define PA_SC_EDGERULE 0x28230 975 #define PA_SC_FIFO_SIZE 0x8BCC 976 #define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 977 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 978 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 979 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 980 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 981 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 982 #define PA_SC_LINE_STIPPLE 0x28A0C 983 #define PA_SU_LINE_STIPPLE_VALUE 0x8A60 984 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 985 986 #define SCRATCH_REG0 0x8500 987 #define SCRATCH_REG1 0x8504 988 #define SCRATCH_REG2 0x8508 989 #define SCRATCH_REG3 0x850C 990 #define SCRATCH_REG4 0x8510 991 #define SCRATCH_REG5 0x8514 992 #define SCRATCH_REG6 0x8518 993 #define SCRATCH_REG7 0x851C 994 #define SCRATCH_UMSK 0x8540 995 #define SCRATCH_ADDR 0x8544 996 997 #define SMX_SAR_CTL0 0xA008 998 #define SMX_DC_CTL0 0xA020 999 #define USE_HASH_FUNCTION (1 << 0) 1000 #define NUMBER_OF_SETS(x) ((x) << 1) 1001 #define FLUSH_ALL_ON_EVENT (1 << 10) 1002 #define STALL_ON_EVENT (1 << 11) 1003 #define SMX_EVENT_CTL 0xA02C 1004 #define ES_FLUSH_CTL(x) ((x) << 0) 1005 #define GS_FLUSH_CTL(x) ((x) << 3) 1006 #define ACK_FLUSH_CTL(x) ((x) << 6) 1007 #define SYNC_FLUSH_CTL (1 << 8) 1008 1009 #define SPI_CONFIG_CNTL 0x9100 1010 #define GPR_WRITE_PRIORITY(x) ((x) << 0) 1011 #define SPI_CONFIG_CNTL_1 0x913C 1012 #define VTX_DONE_DELAY(x) ((x) << 0) 1013 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 1014 #define SPI_INPUT_Z 0x286D8 1015 #define SPI_PS_IN_CONTROL_0 0x286CC 1016 #define NUM_INTERP(x) ((x)<<0) 1017 #define POSITION_ENA (1<<8) 1018 #define POSITION_CENTROID (1<<9) 1019 #define POSITION_ADDR(x) ((x)<<10) 1020 #define PARAM_GEN(x) ((x)<<15) 1021 #define PARAM_GEN_ADDR(x) ((x)<<19) 1022 #define BARYC_SAMPLE_CNTL(x) ((x)<<26) 1023 #define PERSP_GRADIENT_ENA (1<<28) 1024 #define LINEAR_GRADIENT_ENA (1<<29) 1025 #define POSITION_SAMPLE (1<<30) 1026 #define BARYC_AT_SAMPLE_ENA (1<<31) 1027 1028 #define SQ_CONFIG 0x8C00 1029 #define VC_ENABLE (1 << 0) 1030 #define EXPORT_SRC_C (1 << 1) 1031 #define CS_PRIO(x) ((x) << 18) 1032 #define LS_PRIO(x) ((x) << 20) 1033 #define HS_PRIO(x) ((x) << 22) 1034 #define PS_PRIO(x) ((x) << 24) 1035 #define VS_PRIO(x) ((x) << 26) 1036 #define GS_PRIO(x) ((x) << 28) 1037 #define ES_PRIO(x) ((x) << 30) 1038 #define SQ_GPR_RESOURCE_MGMT_1 0x8C04 1039 #define NUM_PS_GPRS(x) ((x) << 0) 1040 #define NUM_VS_GPRS(x) ((x) << 16) 1041 #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 1042 #define SQ_GPR_RESOURCE_MGMT_2 0x8C08 1043 #define NUM_GS_GPRS(x) ((x) << 0) 1044 #define NUM_ES_GPRS(x) ((x) << 16) 1045 #define SQ_GPR_RESOURCE_MGMT_3 0x8C0C 1046 #define NUM_HS_GPRS(x) ((x) << 0) 1047 #define NUM_LS_GPRS(x) ((x) << 16) 1048 #define SQ_GLOBAL_GPR_RESOURCE_MGMT_1 0x8C10 1049 #define SQ_GLOBAL_GPR_RESOURCE_MGMT_2 0x8C14 1050 #define SQ_THREAD_RESOURCE_MGMT 0x8C18 1051 #define NUM_PS_THREADS(x) ((x) << 0) 1052 #define NUM_VS_THREADS(x) ((x) << 8) 1053 #define NUM_GS_THREADS(x) ((x) << 16) 1054 #define NUM_ES_THREADS(x) ((x) << 24) 1055 #define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C 1056 #define NUM_HS_THREADS(x) ((x) << 0) 1057 #define NUM_LS_THREADS(x) ((x) << 8) 1058 #define SQ_STACK_RESOURCE_MGMT_1 0x8C20 1059 #define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 1060 #define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 1061 #define SQ_STACK_RESOURCE_MGMT_2 0x8C24 1062 #define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 1063 #define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 1064 #define SQ_STACK_RESOURCE_MGMT_3 0x8C28 1065 #define NUM_HS_STACK_ENTRIES(x) ((x) << 0) 1066 #define NUM_LS_STACK_ENTRIES(x) ((x) << 16) 1067 #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C 1068 #define SQ_DYN_GPR_SIMD_LOCK_EN 0x8D94 1069 #define SQ_STATIC_THREAD_MGMT_1 0x8E20 1070 #define SQ_STATIC_THREAD_MGMT_2 0x8E24 1071 #define SQ_STATIC_THREAD_MGMT_3 0x8E28 1072 #define SQ_LDS_RESOURCE_MGMT 0x8E2C 1073 1074 #define SQ_MS_FIFO_SIZES 0x8CF0 1075 #define CACHE_FIFO_SIZE(x) ((x) << 0) 1076 #define FETCH_FIFO_HIWATER(x) ((x) << 8) 1077 #define DONE_FIFO_HIWATER(x) ((x) << 16) 1078 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 1079 1080 #define SX_DEBUG_1 0x9058 1081 #define ENABLE_NEW_SMX_ADDRESS (1 << 16) 1082 #define SX_EXPORT_BUFFER_SIZES 0x900C 1083 #define COLOR_BUFFER_SIZE(x) ((x) << 0) 1084 #define POSITION_BUFFER_SIZE(x) ((x) << 8) 1085 #define SMX_BUFFER_SIZE(x) ((x) << 16) 1086 #define SX_MEMORY_EXPORT_BASE 0x9010 1087 #define SX_MISC 0x28350 1088 1089 #define CB_PERF_CTR0_SEL_0 0x9A20 1090 #define CB_PERF_CTR0_SEL_1 0x9A24 1091 #define CB_PERF_CTR1_SEL_0 0x9A28 1092 #define CB_PERF_CTR1_SEL_1 0x9A2C 1093 #define CB_PERF_CTR2_SEL_0 0x9A30 1094 #define CB_PERF_CTR2_SEL_1 0x9A34 1095 #define CB_PERF_CTR3_SEL_0 0x9A38 1096 #define CB_PERF_CTR3_SEL_1 0x9A3C 1097 1098 #define TA_CNTL_AUX 0x9508 1099 #define DISABLE_CUBE_WRAP (1 << 0) 1100 #define DISABLE_CUBE_ANISO (1 << 1) 1101 #define SYNC_GRADIENT (1 << 24) 1102 #define SYNC_WALKER (1 << 25) 1103 #define SYNC_ALIGNER (1 << 26) 1104 1105 #define TCP_CHAN_STEER_LO 0x960c 1106 #define TCP_CHAN_STEER_HI 0x9610 1107 1108 #define VGT_CACHE_INVALIDATION 0x88C4 1109 #define CACHE_INVALIDATION(x) ((x) << 0) 1110 #define VC_ONLY 0 1111 #define TC_ONLY 1 1112 #define VC_AND_TC 2 1113 #define AUTO_INVLD_EN(x) ((x) << 6) 1114 #define NO_AUTO 0 1115 #define ES_AUTO 1 1116 #define GS_AUTO 2 1117 #define ES_AND_GS_AUTO 3 1118 #define VGT_GS_VERTEX_REUSE 0x88D4 1119 #define VGT_NUM_INSTANCES 0x8974 1120 #define VGT_OUT_DEALLOC_CNTL 0x28C5C 1121 #define DEALLOC_DIST_MASK 0x0000007F 1122 #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 1123 #define VTX_REUSE_DEPTH_MASK 0x000000FF 1124 1125 #define VM_CONTEXT0_CNTL 0x1410 1126 #define ENABLE_CONTEXT (1 << 0) 1127 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 1128 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 1129 #define VM_CONTEXT1_CNTL 0x1414 1130 #define VM_CONTEXT1_CNTL2 0x1434 1131 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 1132 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 1133 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 1134 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 1135 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 1136 #define REQUEST_TYPE(x) (((x) & 0xf) << 0) 1137 #define RESPONSE_TYPE_MASK 0x000000F0 1138 #define RESPONSE_TYPE_SHIFT 4 1139 #define VM_L2_CNTL 0x1400 1140 #define ENABLE_L2_CACHE (1 << 0) 1141 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 1142 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 1143 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 1144 #define VM_L2_CNTL2 0x1404 1145 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 1146 #define INVALIDATE_L2_CACHE (1 << 1) 1147 #define VM_L2_CNTL3 0x1408 1148 #define BANK_SELECT(x) ((x) << 0) 1149 #define CACHE_UPDATE_MODE(x) ((x) << 6) 1150 #define VM_L2_STATUS 0x140C 1151 #define L2_BUSY (1 << 0) 1152 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 1153 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 1154 1155 #define WAIT_UNTIL 0x8040 1156 1157 #define SRBM_STATUS 0x0E50 1158 #define RLC_RQ_PENDING (1 << 3) 1159 #define GRBM_RQ_PENDING (1 << 5) 1160 #define VMC_BUSY (1 << 8) 1161 #define MCB_BUSY (1 << 9) 1162 #define MCB_NON_DISPLAY_BUSY (1 << 10) 1163 #define MCC_BUSY (1 << 11) 1164 #define MCD_BUSY (1 << 12) 1165 #define SEM_BUSY (1 << 14) 1166 #define RLC_BUSY (1 << 15) 1167 #define IH_BUSY (1 << 17) 1168 #define SRBM_STATUS2 0x0EC4 1169 #define DMA_BUSY (1 << 5) 1170 #define SRBM_SOFT_RESET 0x0E60 1171 #define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6 1172 #define SOFT_RESET_BIF (1 << 1) 1173 #define SOFT_RESET_CG (1 << 2) 1174 #define SOFT_RESET_DC (1 << 5) 1175 #define SOFT_RESET_GRBM (1 << 8) 1176 #define SOFT_RESET_HDP (1 << 9) 1177 #define SOFT_RESET_IH (1 << 10) 1178 #define SOFT_RESET_MC (1 << 11) 1179 #define SOFT_RESET_RLC (1 << 13) 1180 #define SOFT_RESET_ROM (1 << 14) 1181 #define SOFT_RESET_SEM (1 << 15) 1182 #define SOFT_RESET_VMC (1 << 17) 1183 #define SOFT_RESET_DMA (1 << 20) 1184 #define SOFT_RESET_TST (1 << 21) 1185 #define SOFT_RESET_REGBB (1 << 22) 1186 #define SOFT_RESET_ORB (1 << 23) 1187 1188 /* display watermarks */ 1189 #define DC_LB_MEMORY_SPLIT 0x6b0c 1190 #define PRIORITY_A_CNT 0x6b18 1191 #define PRIORITY_MARK_MASK 0x7fff 1192 #define PRIORITY_OFF (1 << 16) 1193 #define PRIORITY_ALWAYS_ON (1 << 20) 1194 #define PRIORITY_B_CNT 0x6b1c 1195 #define PIPE0_ARBITRATION_CONTROL3 0x0bf0 1196 # define LATENCY_WATERMARK_MASK(x) ((x) << 16) 1197 #define PIPE0_LATENCY_CONTROL 0x0bf4 1198 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 1199 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 1200 1201 #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0 1202 # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0) 1203 # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4) 1204 1205 #define IH_RB_CNTL 0x3e00 1206 # define IH_RB_ENABLE (1 << 0) 1207 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 1208 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 1209 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 1210 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 1211 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 1212 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 1213 #define IH_RB_BASE 0x3e04 1214 #define IH_RB_RPTR 0x3e08 1215 #define IH_RB_WPTR 0x3e0c 1216 # define RB_OVERFLOW (1 << 0) 1217 # define WPTR_OFFSET_MASK 0x3fffc 1218 #define IH_RB_WPTR_ADDR_HI 0x3e10 1219 #define IH_RB_WPTR_ADDR_LO 0x3e14 1220 #define IH_CNTL 0x3e18 1221 # define ENABLE_INTR (1 << 0) 1222 # define IH_MC_SWAP(x) ((x) << 1) 1223 # define IH_MC_SWAP_NONE 0 1224 # define IH_MC_SWAP_16BIT 1 1225 # define IH_MC_SWAP_32BIT 2 1226 # define IH_MC_SWAP_64BIT 3 1227 # define RPTR_REARM (1 << 4) 1228 # define MC_WRREQ_CREDIT(x) ((x) << 15) 1229 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 1230 1231 #define CP_INT_CNTL 0xc124 1232 # define CNTX_BUSY_INT_ENABLE (1 << 19) 1233 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 1234 # define SCRATCH_INT_ENABLE (1 << 25) 1235 # define TIME_STAMP_INT_ENABLE (1 << 26) 1236 # define IB2_INT_ENABLE (1 << 29) 1237 # define IB1_INT_ENABLE (1 << 30) 1238 # define RB_INT_ENABLE (1 << 31) 1239 #define CP_INT_STATUS 0xc128 1240 # define SCRATCH_INT_STAT (1 << 25) 1241 # define TIME_STAMP_INT_STAT (1 << 26) 1242 # define IB2_INT_STAT (1 << 29) 1243 # define IB1_INT_STAT (1 << 30) 1244 # define RB_INT_STAT (1 << 31) 1245 1246 #define GRBM_INT_CNTL 0x8060 1247 # define RDERR_INT_ENABLE (1 << 0) 1248 # define GUI_IDLE_INT_ENABLE (1 << 19) 1249 1250 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ 1251 #define CRTC_STATUS_FRAME_COUNT 0x6e98 1252 1253 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ 1254 #define VLINE_STATUS 0x6bb8 1255 # define VLINE_OCCURRED (1 << 0) 1256 # define VLINE_ACK (1 << 4) 1257 # define VLINE_STAT (1 << 12) 1258 # define VLINE_INTERRUPT (1 << 16) 1259 # define VLINE_INTERRUPT_TYPE (1 << 17) 1260 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ 1261 #define VBLANK_STATUS 0x6bbc 1262 # define VBLANK_OCCURRED (1 << 0) 1263 # define VBLANK_ACK (1 << 4) 1264 # define VBLANK_STAT (1 << 12) 1265 # define VBLANK_INTERRUPT (1 << 16) 1266 # define VBLANK_INTERRUPT_TYPE (1 << 17) 1267 1268 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ 1269 #define INT_MASK 0x6b40 1270 # define VBLANK_INT_MASK (1 << 0) 1271 # define VLINE_INT_MASK (1 << 4) 1272 1273 #define DISP_INTERRUPT_STATUS 0x60f4 1274 # define LB_D1_VLINE_INTERRUPT (1 << 2) 1275 # define LB_D1_VBLANK_INTERRUPT (1 << 3) 1276 # define DC_HPD1_INTERRUPT (1 << 17) 1277 # define DC_HPD1_RX_INTERRUPT (1 << 18) 1278 # define DACA_AUTODETECT_INTERRUPT (1 << 22) 1279 # define DACB_AUTODETECT_INTERRUPT (1 << 23) 1280 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 1281 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 1282 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 1283 # define LB_D2_VLINE_INTERRUPT (1 << 2) 1284 # define LB_D2_VBLANK_INTERRUPT (1 << 3) 1285 # define DC_HPD2_INTERRUPT (1 << 17) 1286 # define DC_HPD2_RX_INTERRUPT (1 << 18) 1287 # define DISP_TIMER_INTERRUPT (1 << 24) 1288 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 1289 # define LB_D3_VLINE_INTERRUPT (1 << 2) 1290 # define LB_D3_VBLANK_INTERRUPT (1 << 3) 1291 # define DC_HPD3_INTERRUPT (1 << 17) 1292 # define DC_HPD3_RX_INTERRUPT (1 << 18) 1293 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 1294 # define LB_D4_VLINE_INTERRUPT (1 << 2) 1295 # define LB_D4_VBLANK_INTERRUPT (1 << 3) 1296 # define DC_HPD4_INTERRUPT (1 << 17) 1297 # define DC_HPD4_RX_INTERRUPT (1 << 18) 1298 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 1299 # define LB_D5_VLINE_INTERRUPT (1 << 2) 1300 # define LB_D5_VBLANK_INTERRUPT (1 << 3) 1301 # define DC_HPD5_INTERRUPT (1 << 17) 1302 # define DC_HPD5_RX_INTERRUPT (1 << 18) 1303 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 1304 # define LB_D6_VLINE_INTERRUPT (1 << 2) 1305 # define LB_D6_VBLANK_INTERRUPT (1 << 3) 1306 # define DC_HPD6_INTERRUPT (1 << 17) 1307 # define DC_HPD6_RX_INTERRUPT (1 << 18) 1308 1309 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 1310 #define GRPH_INT_STATUS 0x6858 1311 # define GRPH_PFLIP_INT_OCCURRED (1 << 0) 1312 # define GRPH_PFLIP_INT_CLEAR (1 << 8) 1313 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 1314 #define GRPH_INT_CONTROL 0x685c 1315 # define GRPH_PFLIP_INT_MASK (1 << 0) 1316 # define GRPH_PFLIP_INT_TYPE (1 << 8) 1317 1318 #define DACA_AUTODETECT_INT_CONTROL 0x66c8 1319 #define DACB_AUTODETECT_INT_CONTROL 0x67c8 1320 1321 #define DC_HPD1_INT_STATUS 0x601c 1322 #define DC_HPD2_INT_STATUS 0x6028 1323 #define DC_HPD3_INT_STATUS 0x6034 1324 #define DC_HPD4_INT_STATUS 0x6040 1325 #define DC_HPD5_INT_STATUS 0x604c 1326 #define DC_HPD6_INT_STATUS 0x6058 1327 # define DC_HPDx_INT_STATUS (1 << 0) 1328 # define DC_HPDx_SENSE (1 << 1) 1329 # define DC_HPDx_RX_INT_STATUS (1 << 8) 1330 1331 #define DC_HPD1_INT_CONTROL 0x6020 1332 #define DC_HPD2_INT_CONTROL 0x602c 1333 #define DC_HPD3_INT_CONTROL 0x6038 1334 #define DC_HPD4_INT_CONTROL 0x6044 1335 #define DC_HPD5_INT_CONTROL 0x6050 1336 #define DC_HPD6_INT_CONTROL 0x605c 1337 # define DC_HPDx_INT_ACK (1 << 0) 1338 # define DC_HPDx_INT_POLARITY (1 << 8) 1339 # define DC_HPDx_INT_EN (1 << 16) 1340 # define DC_HPDx_RX_INT_ACK (1 << 20) 1341 # define DC_HPDx_RX_INT_EN (1 << 24) 1342 1343 #define DC_HPD1_CONTROL 0x6024 1344 #define DC_HPD2_CONTROL 0x6030 1345 #define DC_HPD3_CONTROL 0x603c 1346 #define DC_HPD4_CONTROL 0x6048 1347 #define DC_HPD5_CONTROL 0x6054 1348 #define DC_HPD6_CONTROL 0x6060 1349 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 1350 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 1351 # define DC_HPDx_EN (1 << 28) 1352 1353 /* DCE4/5/6 FMT blocks */ 1354 #define FMT_DYNAMIC_EXP_CNTL 0x6fb4 1355 # define FMT_DYNAMIC_EXP_EN (1 << 0) 1356 # define FMT_DYNAMIC_EXP_MODE (1 << 4) 1357 /* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */ 1358 #define FMT_CONTROL 0x6fb8 1359 # define FMT_PIXEL_ENCODING (1 << 16) 1360 /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */ 1361 #define FMT_BIT_DEPTH_CONTROL 0x6fc8 1362 # define FMT_TRUNCATE_EN (1 << 0) 1363 # define FMT_TRUNCATE_DEPTH (1 << 4) 1364 # define FMT_SPATIAL_DITHER_EN (1 << 8) 1365 # define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9) 1366 # define FMT_SPATIAL_DITHER_DEPTH (1 << 12) 1367 # define FMT_FRAME_RANDOM_ENABLE (1 << 13) 1368 # define FMT_RGB_RANDOM_ENABLE (1 << 14) 1369 # define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15) 1370 # define FMT_TEMPORAL_DITHER_EN (1 << 16) 1371 # define FMT_TEMPORAL_DITHER_DEPTH (1 << 20) 1372 # define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21) 1373 # define FMT_TEMPORAL_LEVEL (1 << 24) 1374 # define FMT_TEMPORAL_DITHER_RESET (1 << 25) 1375 # define FMT_25FRC_SEL(x) ((x) << 26) 1376 # define FMT_50FRC_SEL(x) ((x) << 28) 1377 # define FMT_75FRC_SEL(x) ((x) << 30) 1378 #define FMT_CLAMP_CONTROL 0x6fe4 1379 # define FMT_CLAMP_DATA_EN (1 << 0) 1380 # define FMT_CLAMP_COLOR_FORMAT(x) ((x) << 16) 1381 # define FMT_CLAMP_6BPC 0 1382 # define FMT_CLAMP_8BPC 1 1383 # define FMT_CLAMP_10BPC 2 1384 1385 /* ASYNC DMA */ 1386 #define DMA_RB_RPTR 0xd008 1387 #define DMA_RB_WPTR 0xd00c 1388 1389 #define DMA_CNTL 0xd02c 1390 # define TRAP_ENABLE (1 << 0) 1391 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 1392 # define SEM_WAIT_INT_ENABLE (1 << 2) 1393 # define DATA_SWAP_ENABLE (1 << 3) 1394 # define FENCE_SWAP_ENABLE (1 << 4) 1395 # define CTXEMPTY_INT_ENABLE (1 << 28) 1396 #define DMA_TILING_CONFIG 0xD0B8 1397 1398 #define CAYMAN_DMA1_CNTL 0xd82c 1399 1400 /* async DMA packets */ 1401 #define DMA_PACKET(cmd, sub_cmd, n) ((((cmd) & 0xF) << 28) | \ 1402 (((sub_cmd) & 0xFF) << 20) |\ 1403 (((n) & 0xFFFFF) << 0)) 1404 #define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28) 1405 #define GET_DMA_COUNT(h) ((h) & 0x000fffff) 1406 #define GET_DMA_SUB_CMD(h) (((h) & 0x0ff00000) >> 20) 1407 1408 /* async DMA Packet types */ 1409 #define DMA_PACKET_WRITE 0x2 1410 #define DMA_PACKET_COPY 0x3 1411 #define DMA_PACKET_INDIRECT_BUFFER 0x4 1412 #define DMA_PACKET_SEMAPHORE 0x5 1413 #define DMA_PACKET_FENCE 0x6 1414 #define DMA_PACKET_TRAP 0x7 1415 #define DMA_PACKET_SRBM_WRITE 0x9 1416 #define DMA_PACKET_CONSTANT_FILL 0xd 1417 #define DMA_PACKET_NOP 0xf 1418 1419 /* PIF PHY0 indirect regs */ 1420 #define PB0_PIF_CNTL 0x10 1421 # define LS2_EXIT_TIME(x) ((x) << 17) 1422 # define LS2_EXIT_TIME_MASK (0x7 << 17) 1423 # define LS2_EXIT_TIME_SHIFT 17 1424 #define PB0_PIF_PAIRING 0x11 1425 # define MULTI_PIF (1 << 25) 1426 #define PB0_PIF_PWRDOWN_0 0x12 1427 # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7) 1428 # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7) 1429 # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7 1430 # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10) 1431 # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10) 1432 # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10 1433 # define PLL_RAMP_UP_TIME_0(x) ((x) << 24) 1434 # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24) 1435 # define PLL_RAMP_UP_TIME_0_SHIFT 24 1436 #define PB0_PIF_PWRDOWN_1 0x13 1437 # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7) 1438 # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7) 1439 # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7 1440 # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10) 1441 # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10) 1442 # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10 1443 # define PLL_RAMP_UP_TIME_1(x) ((x) << 24) 1444 # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24) 1445 # define PLL_RAMP_UP_TIME_1_SHIFT 24 1446 /* PIF PHY1 indirect regs */ 1447 #define PB1_PIF_CNTL 0x10 1448 #define PB1_PIF_PAIRING 0x11 1449 #define PB1_PIF_PWRDOWN_0 0x12 1450 #define PB1_PIF_PWRDOWN_1 0x13 1451 /* PCIE PORT indirect regs */ 1452 #define PCIE_LC_CNTL 0xa0 1453 # define LC_L0S_INACTIVITY(x) ((x) << 8) 1454 # define LC_L0S_INACTIVITY_MASK (0xf << 8) 1455 # define LC_L0S_INACTIVITY_SHIFT 8 1456 # define LC_L1_INACTIVITY(x) ((x) << 12) 1457 # define LC_L1_INACTIVITY_MASK (0xf << 12) 1458 # define LC_L1_INACTIVITY_SHIFT 12 1459 # define LC_PMI_TO_L1_DIS (1 << 16) 1460 # define LC_ASPM_TO_L1_DIS (1 << 24) 1461 #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 1462 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 1463 # define LC_LINK_WIDTH_SHIFT 0 1464 # define LC_LINK_WIDTH_MASK 0x7 1465 # define LC_LINK_WIDTH_X0 0 1466 # define LC_LINK_WIDTH_X1 1 1467 # define LC_LINK_WIDTH_X2 2 1468 # define LC_LINK_WIDTH_X4 3 1469 # define LC_LINK_WIDTH_X8 4 1470 # define LC_LINK_WIDTH_X16 6 1471 # define LC_LINK_WIDTH_RD_SHIFT 4 1472 # define LC_LINK_WIDTH_RD_MASK 0x70 1473 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 1474 # define LC_RECONFIG_NOW (1 << 8) 1475 # define LC_RENEGOTIATION_SUPPORT (1 << 9) 1476 # define LC_RENEGOTIATE_EN (1 << 10) 1477 # define LC_SHORT_RECONFIG_EN (1 << 11) 1478 # define LC_UPCONFIGURE_SUPPORT (1 << 12) 1479 # define LC_UPCONFIGURE_DIS (1 << 13) 1480 # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21) 1481 # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21) 1482 # define LC_DYN_LANES_PWR_STATE_SHIFT 21 1483 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 1484 # define LC_GEN2_EN_STRAP (1 << 0) 1485 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 1486 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 1487 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 1488 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 1489 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 1490 # define LC_CURRENT_DATA_RATE (1 << 11) 1491 # define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12) 1492 # define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12) 1493 # define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12 1494 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 1495 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 1496 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 1497 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 1498 #define MM_CFGREGS_CNTL 0x544c 1499 # define MM_WR_TO_CFG_EN (1 << 3) 1500 #define LINK_CNTL2 0x88 /* F0 */ 1501 # define TARGET_LINK_SPEED_MASK (0xf << 0) 1502 # define SELECTABLE_DEEMPHASIS (1 << 6) 1503 1504 1505 /* 1506 * UVD 1507 */ 1508 #define UVD_UDEC_ADDR_CONFIG 0xef4c 1509 #define UVD_UDEC_DB_ADDR_CONFIG 0xef50 1510 #define UVD_UDEC_DBW_ADDR_CONFIG 0xef54 1511 #define UVD_RBC_RB_RPTR 0xf690 1512 #define UVD_RBC_RB_WPTR 0xf694 1513 1514 /* 1515 * PM4 1516 */ 1517 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 1518 (((reg) >> 2) & 0xFFFF) | \ 1519 ((n) & 0x3FFF) << 16) 1520 #define CP_PACKET2 0x80000000 1521 #define PACKET2_PAD_SHIFT 0 1522 #define PACKET2_PAD_MASK (0x3fffffff << 0) 1523 1524 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 1525 1526 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 1527 (((op) & 0xFF) << 8) | \ 1528 ((n) & 0x3FFF) << 16) 1529 1530 /* Packet 3 types */ 1531 #define PACKET3_NOP 0x10 1532 #define PACKET3_SET_BASE 0x11 1533 #define PACKET3_CLEAR_STATE 0x12 1534 #define PACKET3_INDEX_BUFFER_SIZE 0x13 1535 #define PACKET3_DISPATCH_DIRECT 0x15 1536 #define PACKET3_DISPATCH_INDIRECT 0x16 1537 #define PACKET3_INDIRECT_BUFFER_END 0x17 1538 #define PACKET3_MODE_CONTROL 0x18 1539 #define PACKET3_SET_PREDICATION 0x20 1540 #define PACKET3_REG_RMW 0x21 1541 #define PACKET3_COND_EXEC 0x22 1542 #define PACKET3_PRED_EXEC 0x23 1543 #define PACKET3_DRAW_INDIRECT 0x24 1544 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 1545 #define PACKET3_INDEX_BASE 0x26 1546 #define PACKET3_DRAW_INDEX_2 0x27 1547 #define PACKET3_CONTEXT_CONTROL 0x28 1548 #define PACKET3_DRAW_INDEX_OFFSET 0x29 1549 #define PACKET3_INDEX_TYPE 0x2A 1550 #define PACKET3_DRAW_INDEX 0x2B 1551 #define PACKET3_DRAW_INDEX_AUTO 0x2D 1552 #define PACKET3_DRAW_INDEX_IMMD 0x2E 1553 #define PACKET3_NUM_INSTANCES 0x2F 1554 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 1555 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 1556 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 1557 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 1558 #define PACKET3_MEM_SEMAPHORE 0x39 1559 #define PACKET3_MPEG_INDEX 0x3A 1560 #define PACKET3_COPY_DW 0x3B 1561 #define PACKET3_WAIT_REG_MEM 0x3C 1562 #define PACKET3_MEM_WRITE 0x3D 1563 #define PACKET3_INDIRECT_BUFFER 0x32 1564 #define PACKET3_CP_DMA 0x41 1565 /* 1. header 1566 * 2. SRC_ADDR_LO or DATA [31:0] 1567 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | 1568 * SRC_ADDR_HI [7:0] 1569 * 4. DST_ADDR_LO [31:0] 1570 * 5. DST_ADDR_HI [7:0] 1571 * 6. COMMAND [29:22] | BYTE_COUNT [20:0] 1572 */ 1573 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) 1574 /* 0 - DST_ADDR 1575 * 1 - GDS 1576 */ 1577 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) 1578 /* 0 - ME 1579 * 1 - PFP 1580 */ 1581 # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) 1582 /* 0 - SRC_ADDR 1583 * 1 - GDS 1584 * 2 - DATA 1585 */ 1586 # define PACKET3_CP_DMA_CP_SYNC (1 << 31) 1587 /* COMMAND */ 1588 # define PACKET3_CP_DMA_DIS_WC (1 << 21) 1589 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) 1590 /* 0 - none 1591 * 1 - 8 in 16 1592 * 2 - 8 in 32 1593 * 3 - 8 in 64 1594 */ 1595 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 1596 /* 0 - none 1597 * 1 - 8 in 16 1598 * 2 - 8 in 32 1599 * 3 - 8 in 64 1600 */ 1601 # define PACKET3_CP_DMA_CMD_SAS (1 << 26) 1602 /* 0 - memory 1603 * 1 - register 1604 */ 1605 # define PACKET3_CP_DMA_CMD_DAS (1 << 27) 1606 /* 0 - memory 1607 * 1 - register 1608 */ 1609 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 1610 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 1611 #define PACKET3_SURFACE_SYNC 0x43 1612 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1613 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 1614 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 1615 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 1616 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 1617 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 1618 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 1619 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 1620 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 1621 # define PACKET3_CB8_DEST_BASE_ENA (1 << 15) 1622 # define PACKET3_CB9_DEST_BASE_ENA (1 << 16) 1623 # define PACKET3_CB10_DEST_BASE_ENA (1 << 17) 1624 # define PACKET3_CB11_DEST_BASE_ENA (1 << 18) 1625 # define PACKET3_FULL_CACHE_ENA (1 << 20) 1626 # define PACKET3_TC_ACTION_ENA (1 << 23) 1627 # define PACKET3_VC_ACTION_ENA (1 << 24) 1628 # define PACKET3_CB_ACTION_ENA (1 << 25) 1629 # define PACKET3_DB_ACTION_ENA (1 << 26) 1630 # define PACKET3_SH_ACTION_ENA (1 << 27) 1631 # define PACKET3_SX_ACTION_ENA (1 << 28) 1632 #define PACKET3_ME_INITIALIZE 0x44 1633 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1634 #define PACKET3_COND_WRITE 0x45 1635 #define PACKET3_EVENT_WRITE 0x46 1636 #define PACKET3_EVENT_WRITE_EOP 0x47 1637 #define PACKET3_EVENT_WRITE_EOS 0x48 1638 #define PACKET3_PREAMBLE_CNTL 0x4A 1639 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 1640 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 1641 #define PACKET3_RB_OFFSET 0x4B 1642 #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C 1643 #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D 1644 #define PACKET3_ALU_PS_CONST_UPDATE 0x4E 1645 #define PACKET3_ALU_VS_CONST_UPDATE 0x4F 1646 #define PACKET3_ONE_REG_WRITE 0x57 1647 #define PACKET3_SET_CONFIG_REG 0x68 1648 #define PACKET3_SET_CONFIG_REG_START 0x00008000 1649 #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 1650 #define PACKET3_SET_CONTEXT_REG 0x69 1651 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 1652 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 1653 #define PACKET3_SET_ALU_CONST 0x6A 1654 /* alu const buffers only; no reg file */ 1655 #define PACKET3_SET_BOOL_CONST 0x6B 1656 #define PACKET3_SET_BOOL_CONST_START 0x0003a500 1657 #define PACKET3_SET_BOOL_CONST_END 0x0003a518 1658 #define PACKET3_SET_LOOP_CONST 0x6C 1659 #define PACKET3_SET_LOOP_CONST_START 0x0003a200 1660 #define PACKET3_SET_LOOP_CONST_END 0x0003a500 1661 #define PACKET3_SET_RESOURCE 0x6D 1662 #define PACKET3_SET_RESOURCE_START 0x00030000 1663 #define PACKET3_SET_RESOURCE_END 0x00038000 1664 #define PACKET3_SET_SAMPLER 0x6E 1665 #define PACKET3_SET_SAMPLER_START 0x0003c000 1666 #define PACKET3_SET_SAMPLER_END 0x0003c600 1667 #define PACKET3_SET_CTL_CONST 0x6F 1668 #define PACKET3_SET_CTL_CONST_START 0x0003cff0 1669 #define PACKET3_SET_CTL_CONST_END 0x0003ff0c 1670 #define PACKET3_SET_RESOURCE_OFFSET 0x70 1671 #define PACKET3_SET_ALU_CONST_VS 0x71 1672 #define PACKET3_SET_ALU_CONST_DI 0x72 1673 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 1674 #define PACKET3_SET_RESOURCE_INDIRECT 0x74 1675 #define PACKET3_SET_APPEND_CNT 0x75 1676 1677 #define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c 1678 #define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30) 1679 #define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3) 1680 #define SQ_TEX_VTX_INVALID_TEXTURE 0x0 1681 #define SQ_TEX_VTX_INVALID_BUFFER 0x1 1682 #define SQ_TEX_VTX_VALID_TEXTURE 0x2 1683 #define SQ_TEX_VTX_VALID_BUFFER 0x3 1684 1685 #define VGT_VTX_VECT_EJECT_REG 0x88b0 1686 1687 #define SQ_CONST_MEM_BASE 0x8df8 1688 1689 #define SQ_ESGS_RING_BASE 0x8c40 1690 #define SQ_ESGS_RING_SIZE 0x8c44 1691 #define SQ_GSVS_RING_BASE 0x8c48 1692 #define SQ_GSVS_RING_SIZE 0x8c4c 1693 #define SQ_ESTMP_RING_BASE 0x8c50 1694 #define SQ_ESTMP_RING_SIZE 0x8c54 1695 #define SQ_GSTMP_RING_BASE 0x8c58 1696 #define SQ_GSTMP_RING_SIZE 0x8c5c 1697 #define SQ_VSTMP_RING_BASE 0x8c60 1698 #define SQ_VSTMP_RING_SIZE 0x8c64 1699 #define SQ_PSTMP_RING_BASE 0x8c68 1700 #define SQ_PSTMP_RING_SIZE 0x8c6c 1701 #define SQ_LSTMP_RING_BASE 0x8e10 1702 #define SQ_LSTMP_RING_SIZE 0x8e14 1703 #define SQ_HSTMP_RING_BASE 0x8e18 1704 #define SQ_HSTMP_RING_SIZE 0x8e1c 1705 #define VGT_TF_RING_SIZE 0x8988 1706 1707 #define SQ_ESGS_RING_ITEMSIZE 0x28900 1708 #define SQ_GSVS_RING_ITEMSIZE 0x28904 1709 #define SQ_ESTMP_RING_ITEMSIZE 0x28908 1710 #define SQ_GSTMP_RING_ITEMSIZE 0x2890c 1711 #define SQ_VSTMP_RING_ITEMSIZE 0x28910 1712 #define SQ_PSTMP_RING_ITEMSIZE 0x28914 1713 #define SQ_LSTMP_RING_ITEMSIZE 0x28830 1714 #define SQ_HSTMP_RING_ITEMSIZE 0x28834 1715 1716 #define SQ_GS_VERT_ITEMSIZE 0x2891c 1717 #define SQ_GS_VERT_ITEMSIZE_1 0x28920 1718 #define SQ_GS_VERT_ITEMSIZE_2 0x28924 1719 #define SQ_GS_VERT_ITEMSIZE_3 0x28928 1720 #define SQ_GSVS_RING_OFFSET_1 0x2892c 1721 #define SQ_GSVS_RING_OFFSET_2 0x28930 1722 #define SQ_GSVS_RING_OFFSET_3 0x28934 1723 1724 #define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140 1725 #define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80 1726 1727 #define SQ_ALU_CONST_CACHE_PS_0 0x28940 1728 #define SQ_ALU_CONST_CACHE_PS_1 0x28944 1729 #define SQ_ALU_CONST_CACHE_PS_2 0x28948 1730 #define SQ_ALU_CONST_CACHE_PS_3 0x2894c 1731 #define SQ_ALU_CONST_CACHE_PS_4 0x28950 1732 #define SQ_ALU_CONST_CACHE_PS_5 0x28954 1733 #define SQ_ALU_CONST_CACHE_PS_6 0x28958 1734 #define SQ_ALU_CONST_CACHE_PS_7 0x2895c 1735 #define SQ_ALU_CONST_CACHE_PS_8 0x28960 1736 #define SQ_ALU_CONST_CACHE_PS_9 0x28964 1737 #define SQ_ALU_CONST_CACHE_PS_10 0x28968 1738 #define SQ_ALU_CONST_CACHE_PS_11 0x2896c 1739 #define SQ_ALU_CONST_CACHE_PS_12 0x28970 1740 #define SQ_ALU_CONST_CACHE_PS_13 0x28974 1741 #define SQ_ALU_CONST_CACHE_PS_14 0x28978 1742 #define SQ_ALU_CONST_CACHE_PS_15 0x2897c 1743 #define SQ_ALU_CONST_CACHE_VS_0 0x28980 1744 #define SQ_ALU_CONST_CACHE_VS_1 0x28984 1745 #define SQ_ALU_CONST_CACHE_VS_2 0x28988 1746 #define SQ_ALU_CONST_CACHE_VS_3 0x2898c 1747 #define SQ_ALU_CONST_CACHE_VS_4 0x28990 1748 #define SQ_ALU_CONST_CACHE_VS_5 0x28994 1749 #define SQ_ALU_CONST_CACHE_VS_6 0x28998 1750 #define SQ_ALU_CONST_CACHE_VS_7 0x2899c 1751 #define SQ_ALU_CONST_CACHE_VS_8 0x289a0 1752 #define SQ_ALU_CONST_CACHE_VS_9 0x289a4 1753 #define SQ_ALU_CONST_CACHE_VS_10 0x289a8 1754 #define SQ_ALU_CONST_CACHE_VS_11 0x289ac 1755 #define SQ_ALU_CONST_CACHE_VS_12 0x289b0 1756 #define SQ_ALU_CONST_CACHE_VS_13 0x289b4 1757 #define SQ_ALU_CONST_CACHE_VS_14 0x289b8 1758 #define SQ_ALU_CONST_CACHE_VS_15 0x289bc 1759 #define SQ_ALU_CONST_CACHE_GS_0 0x289c0 1760 #define SQ_ALU_CONST_CACHE_GS_1 0x289c4 1761 #define SQ_ALU_CONST_CACHE_GS_2 0x289c8 1762 #define SQ_ALU_CONST_CACHE_GS_3 0x289cc 1763 #define SQ_ALU_CONST_CACHE_GS_4 0x289d0 1764 #define SQ_ALU_CONST_CACHE_GS_5 0x289d4 1765 #define SQ_ALU_CONST_CACHE_GS_6 0x289d8 1766 #define SQ_ALU_CONST_CACHE_GS_7 0x289dc 1767 #define SQ_ALU_CONST_CACHE_GS_8 0x289e0 1768 #define SQ_ALU_CONST_CACHE_GS_9 0x289e4 1769 #define SQ_ALU_CONST_CACHE_GS_10 0x289e8 1770 #define SQ_ALU_CONST_CACHE_GS_11 0x289ec 1771 #define SQ_ALU_CONST_CACHE_GS_12 0x289f0 1772 #define SQ_ALU_CONST_CACHE_GS_13 0x289f4 1773 #define SQ_ALU_CONST_CACHE_GS_14 0x289f8 1774 #define SQ_ALU_CONST_CACHE_GS_15 0x289fc 1775 #define SQ_ALU_CONST_CACHE_HS_0 0x28f00 1776 #define SQ_ALU_CONST_CACHE_HS_1 0x28f04 1777 #define SQ_ALU_CONST_CACHE_HS_2 0x28f08 1778 #define SQ_ALU_CONST_CACHE_HS_3 0x28f0c 1779 #define SQ_ALU_CONST_CACHE_HS_4 0x28f10 1780 #define SQ_ALU_CONST_CACHE_HS_5 0x28f14 1781 #define SQ_ALU_CONST_CACHE_HS_6 0x28f18 1782 #define SQ_ALU_CONST_CACHE_HS_7 0x28f1c 1783 #define SQ_ALU_CONST_CACHE_HS_8 0x28f20 1784 #define SQ_ALU_CONST_CACHE_HS_9 0x28f24 1785 #define SQ_ALU_CONST_CACHE_HS_10 0x28f28 1786 #define SQ_ALU_CONST_CACHE_HS_11 0x28f2c 1787 #define SQ_ALU_CONST_CACHE_HS_12 0x28f30 1788 #define SQ_ALU_CONST_CACHE_HS_13 0x28f34 1789 #define SQ_ALU_CONST_CACHE_HS_14 0x28f38 1790 #define SQ_ALU_CONST_CACHE_HS_15 0x28f3c 1791 #define SQ_ALU_CONST_CACHE_LS_0 0x28f40 1792 #define SQ_ALU_CONST_CACHE_LS_1 0x28f44 1793 #define SQ_ALU_CONST_CACHE_LS_2 0x28f48 1794 #define SQ_ALU_CONST_CACHE_LS_3 0x28f4c 1795 #define SQ_ALU_CONST_CACHE_LS_4 0x28f50 1796 #define SQ_ALU_CONST_CACHE_LS_5 0x28f54 1797 #define SQ_ALU_CONST_CACHE_LS_6 0x28f58 1798 #define SQ_ALU_CONST_CACHE_LS_7 0x28f5c 1799 #define SQ_ALU_CONST_CACHE_LS_8 0x28f60 1800 #define SQ_ALU_CONST_CACHE_LS_9 0x28f64 1801 #define SQ_ALU_CONST_CACHE_LS_10 0x28f68 1802 #define SQ_ALU_CONST_CACHE_LS_11 0x28f6c 1803 #define SQ_ALU_CONST_CACHE_LS_12 0x28f70 1804 #define SQ_ALU_CONST_CACHE_LS_13 0x28f74 1805 #define SQ_ALU_CONST_CACHE_LS_14 0x28f78 1806 #define SQ_ALU_CONST_CACHE_LS_15 0x28f7c 1807 1808 #define PA_SC_SCREEN_SCISSOR_TL 0x28030 1809 #define PA_SC_GENERIC_SCISSOR_TL 0x28240 1810 #define PA_SC_WINDOW_SCISSOR_TL 0x28204 1811 1812 #define VGT_PRIMITIVE_TYPE 0x8958 1813 #define VGT_INDEX_TYPE 0x895C 1814 1815 #define VGT_NUM_INDICES 0x8970 1816 1817 #define VGT_COMPUTE_DIM_X 0x8990 1818 #define VGT_COMPUTE_DIM_Y 0x8994 1819 #define VGT_COMPUTE_DIM_Z 0x8998 1820 #define VGT_COMPUTE_START_X 0x899C 1821 #define VGT_COMPUTE_START_Y 0x89A0 1822 #define VGT_COMPUTE_START_Z 0x89A4 1823 #define VGT_COMPUTE_INDEX 0x89A8 1824 #define VGT_COMPUTE_THREAD_GROUP_SIZE 0x89AC 1825 #define VGT_HS_OFFCHIP_PARAM 0x89B0 1826 1827 #define DB_DEBUG 0x9830 1828 #define DB_DEBUG2 0x9834 1829 #define DB_DEBUG3 0x9838 1830 #define DB_DEBUG4 0x983C 1831 #define DB_WATERMARKS 0x9854 1832 #define DB_DEPTH_CONTROL 0x28800 1833 #define R_028800_DB_DEPTH_CONTROL 0x028800 1834 #define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) 1835 #define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) 1836 #define C_028800_STENCIL_ENABLE 0xFFFFFFFE 1837 #define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) 1838 #define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) 1839 #define C_028800_Z_ENABLE 0xFFFFFFFD 1840 #define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) 1841 #define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) 1842 #define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB 1843 #define S_028800_ZFUNC(x) (((x) & 0x7) << 4) 1844 #define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) 1845 #define C_028800_ZFUNC 0xFFFFFF8F 1846 #define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) 1847 #define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) 1848 #define C_028800_BACKFACE_ENABLE 0xFFFFFF7F 1849 #define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) 1850 #define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) 1851 #define C_028800_STENCILFUNC 0xFFFFF8FF 1852 #define V_028800_STENCILFUNC_NEVER 0x00000000 1853 #define V_028800_STENCILFUNC_LESS 0x00000001 1854 #define V_028800_STENCILFUNC_EQUAL 0x00000002 1855 #define V_028800_STENCILFUNC_LEQUAL 0x00000003 1856 #define V_028800_STENCILFUNC_GREATER 0x00000004 1857 #define V_028800_STENCILFUNC_NOTEQUAL 0x00000005 1858 #define V_028800_STENCILFUNC_GEQUAL 0x00000006 1859 #define V_028800_STENCILFUNC_ALWAYS 0x00000007 1860 #define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) 1861 #define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) 1862 #define C_028800_STENCILFAIL 0xFFFFC7FF 1863 #define V_028800_STENCIL_KEEP 0x00000000 1864 #define V_028800_STENCIL_ZERO 0x00000001 1865 #define V_028800_STENCIL_REPLACE 0x00000002 1866 #define V_028800_STENCIL_INCR 0x00000003 1867 #define V_028800_STENCIL_DECR 0x00000004 1868 #define V_028800_STENCIL_INVERT 0x00000005 1869 #define V_028800_STENCIL_INCR_WRAP 0x00000006 1870 #define V_028800_STENCIL_DECR_WRAP 0x00000007 1871 #define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) 1872 #define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) 1873 #define C_028800_STENCILZPASS 0xFFFE3FFF 1874 #define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) 1875 #define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) 1876 #define C_028800_STENCILZFAIL 0xFFF1FFFF 1877 #define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) 1878 #define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) 1879 #define C_028800_STENCILFUNC_BF 0xFF8FFFFF 1880 #define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) 1881 #define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) 1882 #define C_028800_STENCILFAIL_BF 0xFC7FFFFF 1883 #define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) 1884 #define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) 1885 #define C_028800_STENCILZPASS_BF 0xE3FFFFFF 1886 #define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) 1887 #define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) 1888 #define C_028800_STENCILZFAIL_BF 0x1FFFFFFF 1889 #define DB_DEPTH_VIEW 0x28008 1890 #define R_028008_DB_DEPTH_VIEW 0x00028008 1891 #define S_028008_SLICE_START(x) (((x) & 0x7FF) << 0) 1892 #define G_028008_SLICE_START(x) (((x) >> 0) & 0x7FF) 1893 #define C_028008_SLICE_START 0xFFFFF800 1894 #define S_028008_SLICE_MAX(x) (((x) & 0x7FF) << 13) 1895 #define G_028008_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 1896 #define C_028008_SLICE_MAX 0xFF001FFF 1897 #define DB_HTILE_DATA_BASE 0x28014 1898 #define DB_HTILE_SURFACE 0x28abc 1899 #define S_028ABC_HTILE_WIDTH(x) (((x) & 0x1) << 0) 1900 #define G_028ABC_HTILE_WIDTH(x) (((x) >> 0) & 0x1) 1901 #define C_028ABC_HTILE_WIDTH 0xFFFFFFFE 1902 #define S_028ABC_HTILE_HEIGHT(x) (((x) & 0x1) << 1) 1903 #define G_028ABC_HTILE_HEIGHT(x) (((x) >> 1) & 0x1) 1904 #define C_028ABC_HTILE_HEIGHT 0xFFFFFFFD 1905 #define G_028ABC_LINEAR(x) (((x) >> 2) & 0x1) 1906 #define DB_Z_INFO 0x28040 1907 # define Z_ARRAY_MODE(x) ((x) << 4) 1908 # define DB_TILE_SPLIT(x) (((x) & 0x7) << 8) 1909 # define DB_NUM_BANKS(x) (((x) & 0x3) << 12) 1910 # define DB_BANK_WIDTH(x) (((x) & 0x3) << 16) 1911 # define DB_BANK_HEIGHT(x) (((x) & 0x3) << 20) 1912 # define DB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24) 1913 #define R_028040_DB_Z_INFO 0x028040 1914 #define S_028040_FORMAT(x) (((x) & 0x3) << 0) 1915 #define G_028040_FORMAT(x) (((x) >> 0) & 0x3) 1916 #define C_028040_FORMAT 0xFFFFFFFC 1917 #define V_028040_Z_INVALID 0x00000000 1918 #define V_028040_Z_16 0x00000001 1919 #define V_028040_Z_24 0x00000002 1920 #define V_028040_Z_32_FLOAT 0x00000003 1921 #define S_028040_ARRAY_MODE(x) (((x) & 0xF) << 4) 1922 #define G_028040_ARRAY_MODE(x) (((x) >> 4) & 0xF) 1923 #define C_028040_ARRAY_MODE 0xFFFFFF0F 1924 #define S_028040_READ_SIZE(x) (((x) & 0x1) << 28) 1925 #define G_028040_READ_SIZE(x) (((x) >> 28) & 0x1) 1926 #define C_028040_READ_SIZE 0xEFFFFFFF 1927 #define S_028040_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 29) 1928 #define G_028040_TILE_SURFACE_ENABLE(x) (((x) >> 29) & 0x1) 1929 #define C_028040_TILE_SURFACE_ENABLE 0xDFFFFFFF 1930 #define S_028040_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) 1931 #define G_028040_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) 1932 #define C_028040_ZRANGE_PRECISION 0x7FFFFFFF 1933 #define S_028040_TILE_SPLIT(x) (((x) & 0x7) << 8) 1934 #define G_028040_TILE_SPLIT(x) (((x) >> 8) & 0x7) 1935 #define S_028040_NUM_BANKS(x) (((x) & 0x3) << 12) 1936 #define G_028040_NUM_BANKS(x) (((x) >> 12) & 0x3) 1937 #define S_028040_BANK_WIDTH(x) (((x) & 0x3) << 16) 1938 #define G_028040_BANK_WIDTH(x) (((x) >> 16) & 0x3) 1939 #define S_028040_BANK_HEIGHT(x) (((x) & 0x3) << 20) 1940 #define G_028040_BANK_HEIGHT(x) (((x) >> 20) & 0x3) 1941 #define S_028040_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24) 1942 #define G_028040_MACRO_TILE_ASPECT(x) (((x) >> 24) & 0x3) 1943 #define DB_STENCIL_INFO 0x28044 1944 #define R_028044_DB_STENCIL_INFO 0x028044 1945 #define S_028044_FORMAT(x) (((x) & 0x1) << 0) 1946 #define G_028044_FORMAT(x) (((x) >> 0) & 0x1) 1947 #define C_028044_FORMAT 0xFFFFFFFE 1948 #define V_028044_STENCIL_INVALID 0 1949 #define V_028044_STENCIL_8 1 1950 #define G_028044_TILE_SPLIT(x) (((x) >> 8) & 0x7) 1951 #define DB_Z_READ_BASE 0x28048 1952 #define DB_STENCIL_READ_BASE 0x2804c 1953 #define DB_Z_WRITE_BASE 0x28050 1954 #define DB_STENCIL_WRITE_BASE 0x28054 1955 #define DB_DEPTH_SIZE 0x28058 1956 #define R_028058_DB_DEPTH_SIZE 0x028058 1957 #define S_028058_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0) 1958 #define G_028058_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF) 1959 #define C_028058_PITCH_TILE_MAX 0xFFFFF800 1960 #define S_028058_HEIGHT_TILE_MAX(x) (((x) & 0x7FF) << 11) 1961 #define G_028058_HEIGHT_TILE_MAX(x) (((x) >> 11) & 0x7FF) 1962 #define C_028058_HEIGHT_TILE_MAX 0xFFC007FF 1963 #define R_02805C_DB_DEPTH_SLICE 0x02805C 1964 #define S_02805C_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0) 1965 #define G_02805C_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF) 1966 #define C_02805C_SLICE_TILE_MAX 0xFFC00000 1967 1968 #define SQ_PGM_START_PS 0x28840 1969 #define SQ_PGM_START_VS 0x2885c 1970 #define SQ_PGM_START_GS 0x28874 1971 #define SQ_PGM_START_ES 0x2888c 1972 #define SQ_PGM_START_FS 0x288a4 1973 #define SQ_PGM_START_HS 0x288b8 1974 #define SQ_PGM_START_LS 0x288d0 1975 1976 #define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 1977 #define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 1978 #define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 1979 #define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 1980 #define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0 1981 #define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0 1982 #define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0 1983 #define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00 1984 #define VGT_STRMOUT_CONFIG 0x28b94 1985 #define VGT_STRMOUT_BUFFER_CONFIG 0x28b98 1986 1987 #define CB_TARGET_MASK 0x28238 1988 #define CB_SHADER_MASK 0x2823c 1989 1990 #define GDS_ADDR_BASE 0x28720 1991 1992 #define CB_IMMED0_BASE 0x28b9c 1993 #define CB_IMMED1_BASE 0x28ba0 1994 #define CB_IMMED2_BASE 0x28ba4 1995 #define CB_IMMED3_BASE 0x28ba8 1996 #define CB_IMMED4_BASE 0x28bac 1997 #define CB_IMMED5_BASE 0x28bb0 1998 #define CB_IMMED6_BASE 0x28bb4 1999 #define CB_IMMED7_BASE 0x28bb8 2000 #define CB_IMMED8_BASE 0x28bbc 2001 #define CB_IMMED9_BASE 0x28bc0 2002 #define CB_IMMED10_BASE 0x28bc4 2003 #define CB_IMMED11_BASE 0x28bc8 2004 2005 /* all 12 CB blocks have these regs */ 2006 #define CB_COLOR0_BASE 0x28c60 2007 #define CB_COLOR0_PITCH 0x28c64 2008 #define CB_COLOR0_SLICE 0x28c68 2009 #define CB_COLOR0_VIEW 0x28c6c 2010 #define R_028C6C_CB_COLOR0_VIEW 0x00028C6C 2011 #define S_028C6C_SLICE_START(x) (((x) & 0x7FF) << 0) 2012 #define G_028C6C_SLICE_START(x) (((x) >> 0) & 0x7FF) 2013 #define C_028C6C_SLICE_START 0xFFFFF800 2014 #define S_028C6C_SLICE_MAX(x) (((x) & 0x7FF) << 13) 2015 #define G_028C6C_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 2016 #define C_028C6C_SLICE_MAX 0xFF001FFF 2017 #define R_028C70_CB_COLOR0_INFO 0x028C70 2018 #define S_028C70_ENDIAN(x) (((x) & 0x3) << 0) 2019 #define G_028C70_ENDIAN(x) (((x) >> 0) & 0x3) 2020 #define C_028C70_ENDIAN 0xFFFFFFFC 2021 #define S_028C70_FORMAT(x) (((x) & 0x3F) << 2) 2022 #define G_028C70_FORMAT(x) (((x) >> 2) & 0x3F) 2023 #define C_028C70_FORMAT 0xFFFFFF03 2024 #define V_028C70_COLOR_INVALID 0x00000000 2025 #define V_028C70_COLOR_8 0x00000001 2026 #define V_028C70_COLOR_4_4 0x00000002 2027 #define V_028C70_COLOR_3_3_2 0x00000003 2028 #define V_028C70_COLOR_16 0x00000005 2029 #define V_028C70_COLOR_16_FLOAT 0x00000006 2030 #define V_028C70_COLOR_8_8 0x00000007 2031 #define V_028C70_COLOR_5_6_5 0x00000008 2032 #define V_028C70_COLOR_6_5_5 0x00000009 2033 #define V_028C70_COLOR_1_5_5_5 0x0000000A 2034 #define V_028C70_COLOR_4_4_4_4 0x0000000B 2035 #define V_028C70_COLOR_5_5_5_1 0x0000000C 2036 #define V_028C70_COLOR_32 0x0000000D 2037 #define V_028C70_COLOR_32_FLOAT 0x0000000E 2038 #define V_028C70_COLOR_16_16 0x0000000F 2039 #define V_028C70_COLOR_16_16_FLOAT 0x00000010 2040 #define V_028C70_COLOR_8_24 0x00000011 2041 #define V_028C70_COLOR_8_24_FLOAT 0x00000012 2042 #define V_028C70_COLOR_24_8 0x00000013 2043 #define V_028C70_COLOR_24_8_FLOAT 0x00000014 2044 #define V_028C70_COLOR_10_11_11 0x00000015 2045 #define V_028C70_COLOR_10_11_11_FLOAT 0x00000016 2046 #define V_028C70_COLOR_11_11_10 0x00000017 2047 #define V_028C70_COLOR_11_11_10_FLOAT 0x00000018 2048 #define V_028C70_COLOR_2_10_10_10 0x00000019 2049 #define V_028C70_COLOR_8_8_8_8 0x0000001A 2050 #define V_028C70_COLOR_10_10_10_2 0x0000001B 2051 #define V_028C70_COLOR_X24_8_32_FLOAT 0x0000001C 2052 #define V_028C70_COLOR_32_32 0x0000001D 2053 #define V_028C70_COLOR_32_32_FLOAT 0x0000001E 2054 #define V_028C70_COLOR_16_16_16_16 0x0000001F 2055 #define V_028C70_COLOR_16_16_16_16_FLOAT 0x00000020 2056 #define V_028C70_COLOR_32_32_32_32 0x00000022 2057 #define V_028C70_COLOR_32_32_32_32_FLOAT 0x00000023 2058 #define V_028C70_COLOR_32_32_32_FLOAT 0x00000030 2059 #define S_028C70_ARRAY_MODE(x) (((x) & 0xF) << 8) 2060 #define G_028C70_ARRAY_MODE(x) (((x) >> 8) & 0xF) 2061 #define C_028C70_ARRAY_MODE 0xFFFFF0FF 2062 #define V_028C70_ARRAY_LINEAR_GENERAL 0x00000000 2063 #define V_028C70_ARRAY_LINEAR_ALIGNED 0x00000001 2064 #define V_028C70_ARRAY_1D_TILED_THIN1 0x00000002 2065 #define V_028C70_ARRAY_2D_TILED_THIN1 0x00000004 2066 #define S_028C70_NUMBER_TYPE(x) (((x) & 0x7) << 12) 2067 #define G_028C70_NUMBER_TYPE(x) (((x) >> 12) & 0x7) 2068 #define C_028C70_NUMBER_TYPE 0xFFFF8FFF 2069 #define V_028C70_NUMBER_UNORM 0x00000000 2070 #define V_028C70_NUMBER_SNORM 0x00000001 2071 #define V_028C70_NUMBER_USCALED 0x00000002 2072 #define V_028C70_NUMBER_SSCALED 0x00000003 2073 #define V_028C70_NUMBER_UINT 0x00000004 2074 #define V_028C70_NUMBER_SINT 0x00000005 2075 #define V_028C70_NUMBER_SRGB 0x00000006 2076 #define V_028C70_NUMBER_FLOAT 0x00000007 2077 #define S_028C70_COMP_SWAP(x) (((x) & 0x3) << 15) 2078 #define G_028C70_COMP_SWAP(x) (((x) >> 15) & 0x3) 2079 #define C_028C70_COMP_SWAP 0xFFFE7FFF 2080 #define V_028C70_SWAP_STD 0x00000000 2081 #define V_028C70_SWAP_ALT 0x00000001 2082 #define V_028C70_SWAP_STD_REV 0x00000002 2083 #define V_028C70_SWAP_ALT_REV 0x00000003 2084 #define S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 17) 2085 #define G_028C70_FAST_CLEAR(x) (((x) >> 17) & 0x1) 2086 #define C_028C70_FAST_CLEAR 0xFFFDFFFF 2087 #define S_028C70_COMPRESSION(x) (((x) & 0x3) << 18) 2088 #define G_028C70_COMPRESSION(x) (((x) >> 18) & 0x3) 2089 #define C_028C70_COMPRESSION 0xFFF3FFFF 2090 #define S_028C70_BLEND_CLAMP(x) (((x) & 0x1) << 19) 2091 #define G_028C70_BLEND_CLAMP(x) (((x) >> 19) & 0x1) 2092 #define C_028C70_BLEND_CLAMP 0xFFF7FFFF 2093 #define S_028C70_BLEND_BYPASS(x) (((x) & 0x1) << 20) 2094 #define G_028C70_BLEND_BYPASS(x) (((x) >> 20) & 0x1) 2095 #define C_028C70_BLEND_BYPASS 0xFFEFFFFF 2096 #define S_028C70_SIMPLE_FLOAT(x) (((x) & 0x1) << 21) 2097 #define G_028C70_SIMPLE_FLOAT(x) (((x) >> 21) & 0x1) 2098 #define C_028C70_SIMPLE_FLOAT 0xFFDFFFFF 2099 #define S_028C70_ROUND_MODE(x) (((x) & 0x1) << 22) 2100 #define G_028C70_ROUND_MODE(x) (((x) >> 22) & 0x1) 2101 #define C_028C70_ROUND_MODE 0xFFBFFFFF 2102 #define S_028C70_TILE_COMPACT(x) (((x) & 0x1) << 23) 2103 #define G_028C70_TILE_COMPACT(x) (((x) >> 23) & 0x1) 2104 #define C_028C70_TILE_COMPACT 0xFF7FFFFF 2105 #define S_028C70_SOURCE_FORMAT(x) (((x) & 0x3) << 24) 2106 #define G_028C70_SOURCE_FORMAT(x) (((x) >> 24) & 0x3) 2107 #define C_028C70_SOURCE_FORMAT 0xFCFFFFFF 2108 #define V_028C70_EXPORT_4C_32BPC 0x0 2109 #define V_028C70_EXPORT_4C_16BPC 0x1 2110 #define V_028C70_EXPORT_2C_32BPC 0x2 /* Do not use */ 2111 #define S_028C70_RAT(x) (((x) & 0x1) << 26) 2112 #define G_028C70_RAT(x) (((x) >> 26) & 0x1) 2113 #define C_028C70_RAT 0xFBFFFFFF 2114 #define S_028C70_RESOURCE_TYPE(x) (((x) & 0x7) << 27) 2115 #define G_028C70_RESOURCE_TYPE(x) (((x) >> 27) & 0x7) 2116 #define C_028C70_RESOURCE_TYPE 0xC7FFFFFF 2117 2118 #define CB_COLOR0_INFO 0x28c70 2119 # define CB_FORMAT(x) ((x) << 2) 2120 # define CB_ARRAY_MODE(x) ((x) << 8) 2121 # define ARRAY_LINEAR_GENERAL 0 2122 # define ARRAY_LINEAR_ALIGNED 1 2123 # define ARRAY_1D_TILED_THIN1 2 2124 # define ARRAY_2D_TILED_THIN1 4 2125 # define CB_SOURCE_FORMAT(x) ((x) << 24) 2126 # define CB_SF_EXPORT_FULL 0 2127 # define CB_SF_EXPORT_NORM 1 2128 #define R_028C74_CB_COLOR0_ATTRIB 0x028C74 2129 #define S_028C74_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 4) 2130 #define G_028C74_NON_DISP_TILING_ORDER(x) (((x) >> 4) & 0x1) 2131 #define C_028C74_NON_DISP_TILING_ORDER 0xFFFFFFEF 2132 #define S_028C74_TILE_SPLIT(x) (((x) & 0xf) << 5) 2133 #define G_028C74_TILE_SPLIT(x) (((x) >> 5) & 0xf) 2134 #define S_028C74_NUM_BANKS(x) (((x) & 0x3) << 10) 2135 #define G_028C74_NUM_BANKS(x) (((x) >> 10) & 0x3) 2136 #define S_028C74_BANK_WIDTH(x) (((x) & 0x3) << 13) 2137 #define G_028C74_BANK_WIDTH(x) (((x) >> 13) & 0x3) 2138 #define S_028C74_BANK_HEIGHT(x) (((x) & 0x3) << 16) 2139 #define G_028C74_BANK_HEIGHT(x) (((x) >> 16) & 0x3) 2140 #define S_028C74_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19) 2141 #define G_028C74_MACRO_TILE_ASPECT(x) (((x) >> 19) & 0x3) 2142 #define CB_COLOR0_ATTRIB 0x28c74 2143 # define CB_TILE_SPLIT(x) (((x) & 0x7) << 5) 2144 # define ADDR_SURF_TILE_SPLIT_64B 0 2145 # define ADDR_SURF_TILE_SPLIT_128B 1 2146 # define ADDR_SURF_TILE_SPLIT_256B 2 2147 # define ADDR_SURF_TILE_SPLIT_512B 3 2148 # define ADDR_SURF_TILE_SPLIT_1KB 4 2149 # define ADDR_SURF_TILE_SPLIT_2KB 5 2150 # define ADDR_SURF_TILE_SPLIT_4KB 6 2151 # define CB_NUM_BANKS(x) (((x) & 0x3) << 10) 2152 # define ADDR_SURF_2_BANK 0 2153 # define ADDR_SURF_4_BANK 1 2154 # define ADDR_SURF_8_BANK 2 2155 # define ADDR_SURF_16_BANK 3 2156 # define CB_BANK_WIDTH(x) (((x) & 0x3) << 13) 2157 # define ADDR_SURF_BANK_WIDTH_1 0 2158 # define ADDR_SURF_BANK_WIDTH_2 1 2159 # define ADDR_SURF_BANK_WIDTH_4 2 2160 # define ADDR_SURF_BANK_WIDTH_8 3 2161 # define CB_BANK_HEIGHT(x) (((x) & 0x3) << 16) 2162 # define ADDR_SURF_BANK_HEIGHT_1 0 2163 # define ADDR_SURF_BANK_HEIGHT_2 1 2164 # define ADDR_SURF_BANK_HEIGHT_4 2 2165 # define ADDR_SURF_BANK_HEIGHT_8 3 2166 # define CB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19) 2167 #define CB_COLOR0_DIM 0x28c78 2168 /* only CB0-7 blocks have these regs */ 2169 #define CB_COLOR0_CMASK 0x28c7c 2170 #define CB_COLOR0_CMASK_SLICE 0x28c80 2171 #define CB_COLOR0_FMASK 0x28c84 2172 #define CB_COLOR0_FMASK_SLICE 0x28c88 2173 #define CB_COLOR0_CLEAR_WORD0 0x28c8c 2174 #define CB_COLOR0_CLEAR_WORD1 0x28c90 2175 #define CB_COLOR0_CLEAR_WORD2 0x28c94 2176 #define CB_COLOR0_CLEAR_WORD3 0x28c98 2177 2178 #define CB_COLOR1_BASE 0x28c9c 2179 #define CB_COLOR2_BASE 0x28cd8 2180 #define CB_COLOR3_BASE 0x28d14 2181 #define CB_COLOR4_BASE 0x28d50 2182 #define CB_COLOR5_BASE 0x28d8c 2183 #define CB_COLOR6_BASE 0x28dc8 2184 #define CB_COLOR7_BASE 0x28e04 2185 #define CB_COLOR8_BASE 0x28e40 2186 #define CB_COLOR9_BASE 0x28e5c 2187 #define CB_COLOR10_BASE 0x28e78 2188 #define CB_COLOR11_BASE 0x28e94 2189 2190 #define CB_COLOR1_PITCH 0x28ca0 2191 #define CB_COLOR2_PITCH 0x28cdc 2192 #define CB_COLOR3_PITCH 0x28d18 2193 #define CB_COLOR4_PITCH 0x28d54 2194 #define CB_COLOR5_PITCH 0x28d90 2195 #define CB_COLOR6_PITCH 0x28dcc 2196 #define CB_COLOR7_PITCH 0x28e08 2197 #define CB_COLOR8_PITCH 0x28e44 2198 #define CB_COLOR9_PITCH 0x28e60 2199 #define CB_COLOR10_PITCH 0x28e7c 2200 #define CB_COLOR11_PITCH 0x28e98 2201 2202 #define CB_COLOR1_SLICE 0x28ca4 2203 #define CB_COLOR2_SLICE 0x28ce0 2204 #define CB_COLOR3_SLICE 0x28d1c 2205 #define CB_COLOR4_SLICE 0x28d58 2206 #define CB_COLOR5_SLICE 0x28d94 2207 #define CB_COLOR6_SLICE 0x28dd0 2208 #define CB_COLOR7_SLICE 0x28e0c 2209 #define CB_COLOR8_SLICE 0x28e48 2210 #define CB_COLOR9_SLICE 0x28e64 2211 #define CB_COLOR10_SLICE 0x28e80 2212 #define CB_COLOR11_SLICE 0x28e9c 2213 2214 #define CB_COLOR1_VIEW 0x28ca8 2215 #define CB_COLOR2_VIEW 0x28ce4 2216 #define CB_COLOR3_VIEW 0x28d20 2217 #define CB_COLOR4_VIEW 0x28d5c 2218 #define CB_COLOR5_VIEW 0x28d98 2219 #define CB_COLOR6_VIEW 0x28dd4 2220 #define CB_COLOR7_VIEW 0x28e10 2221 #define CB_COLOR8_VIEW 0x28e4c 2222 #define CB_COLOR9_VIEW 0x28e68 2223 #define CB_COLOR10_VIEW 0x28e84 2224 #define CB_COLOR11_VIEW 0x28ea0 2225 2226 #define CB_COLOR1_INFO 0x28cac 2227 #define CB_COLOR2_INFO 0x28ce8 2228 #define CB_COLOR3_INFO 0x28d24 2229 #define CB_COLOR4_INFO 0x28d60 2230 #define CB_COLOR5_INFO 0x28d9c 2231 #define CB_COLOR6_INFO 0x28dd8 2232 #define CB_COLOR7_INFO 0x28e14 2233 #define CB_COLOR8_INFO 0x28e50 2234 #define CB_COLOR9_INFO 0x28e6c 2235 #define CB_COLOR10_INFO 0x28e88 2236 #define CB_COLOR11_INFO 0x28ea4 2237 2238 #define CB_COLOR1_ATTRIB 0x28cb0 2239 #define CB_COLOR2_ATTRIB 0x28cec 2240 #define CB_COLOR3_ATTRIB 0x28d28 2241 #define CB_COLOR4_ATTRIB 0x28d64 2242 #define CB_COLOR5_ATTRIB 0x28da0 2243 #define CB_COLOR6_ATTRIB 0x28ddc 2244 #define CB_COLOR7_ATTRIB 0x28e18 2245 #define CB_COLOR8_ATTRIB 0x28e54 2246 #define CB_COLOR9_ATTRIB 0x28e70 2247 #define CB_COLOR10_ATTRIB 0x28e8c 2248 #define CB_COLOR11_ATTRIB 0x28ea8 2249 2250 #define CB_COLOR1_DIM 0x28cb4 2251 #define CB_COLOR2_DIM 0x28cf0 2252 #define CB_COLOR3_DIM 0x28d2c 2253 #define CB_COLOR4_DIM 0x28d68 2254 #define CB_COLOR5_DIM 0x28da4 2255 #define CB_COLOR6_DIM 0x28de0 2256 #define CB_COLOR7_DIM 0x28e1c 2257 #define CB_COLOR8_DIM 0x28e58 2258 #define CB_COLOR9_DIM 0x28e74 2259 #define CB_COLOR10_DIM 0x28e90 2260 #define CB_COLOR11_DIM 0x28eac 2261 2262 #define CB_COLOR1_CMASK 0x28cb8 2263 #define CB_COLOR2_CMASK 0x28cf4 2264 #define CB_COLOR3_CMASK 0x28d30 2265 #define CB_COLOR4_CMASK 0x28d6c 2266 #define CB_COLOR5_CMASK 0x28da8 2267 #define CB_COLOR6_CMASK 0x28de4 2268 #define CB_COLOR7_CMASK 0x28e20 2269 2270 #define CB_COLOR1_CMASK_SLICE 0x28cbc 2271 #define CB_COLOR2_CMASK_SLICE 0x28cf8 2272 #define CB_COLOR3_CMASK_SLICE 0x28d34 2273 #define CB_COLOR4_CMASK_SLICE 0x28d70 2274 #define CB_COLOR5_CMASK_SLICE 0x28dac 2275 #define CB_COLOR6_CMASK_SLICE 0x28de8 2276 #define CB_COLOR7_CMASK_SLICE 0x28e24 2277 2278 #define CB_COLOR1_FMASK 0x28cc0 2279 #define CB_COLOR2_FMASK 0x28cfc 2280 #define CB_COLOR3_FMASK 0x28d38 2281 #define CB_COLOR4_FMASK 0x28d74 2282 #define CB_COLOR5_FMASK 0x28db0 2283 #define CB_COLOR6_FMASK 0x28dec 2284 #define CB_COLOR7_FMASK 0x28e28 2285 2286 #define CB_COLOR1_FMASK_SLICE 0x28cc4 2287 #define CB_COLOR2_FMASK_SLICE 0x28d00 2288 #define CB_COLOR3_FMASK_SLICE 0x28d3c 2289 #define CB_COLOR4_FMASK_SLICE 0x28d78 2290 #define CB_COLOR5_FMASK_SLICE 0x28db4 2291 #define CB_COLOR6_FMASK_SLICE 0x28df0 2292 #define CB_COLOR7_FMASK_SLICE 0x28e2c 2293 2294 #define CB_COLOR1_CLEAR_WORD0 0x28cc8 2295 #define CB_COLOR2_CLEAR_WORD0 0x28d04 2296 #define CB_COLOR3_CLEAR_WORD0 0x28d40 2297 #define CB_COLOR4_CLEAR_WORD0 0x28d7c 2298 #define CB_COLOR5_CLEAR_WORD0 0x28db8 2299 #define CB_COLOR6_CLEAR_WORD0 0x28df4 2300 #define CB_COLOR7_CLEAR_WORD0 0x28e30 2301 2302 #define CB_COLOR1_CLEAR_WORD1 0x28ccc 2303 #define CB_COLOR2_CLEAR_WORD1 0x28d08 2304 #define CB_COLOR3_CLEAR_WORD1 0x28d44 2305 #define CB_COLOR4_CLEAR_WORD1 0x28d80 2306 #define CB_COLOR5_CLEAR_WORD1 0x28dbc 2307 #define CB_COLOR6_CLEAR_WORD1 0x28df8 2308 #define CB_COLOR7_CLEAR_WORD1 0x28e34 2309 2310 #define CB_COLOR1_CLEAR_WORD2 0x28cd0 2311 #define CB_COLOR2_CLEAR_WORD2 0x28d0c 2312 #define CB_COLOR3_CLEAR_WORD2 0x28d48 2313 #define CB_COLOR4_CLEAR_WORD2 0x28d84 2314 #define CB_COLOR5_CLEAR_WORD2 0x28dc0 2315 #define CB_COLOR6_CLEAR_WORD2 0x28dfc 2316 #define CB_COLOR7_CLEAR_WORD2 0x28e38 2317 2318 #define CB_COLOR1_CLEAR_WORD3 0x28cd4 2319 #define CB_COLOR2_CLEAR_WORD3 0x28d10 2320 #define CB_COLOR3_CLEAR_WORD3 0x28d4c 2321 #define CB_COLOR4_CLEAR_WORD3 0x28d88 2322 #define CB_COLOR5_CLEAR_WORD3 0x28dc4 2323 #define CB_COLOR6_CLEAR_WORD3 0x28e00 2324 #define CB_COLOR7_CLEAR_WORD3 0x28e3c 2325 2326 #define SQ_TEX_RESOURCE_WORD0_0 0x30000 2327 # define TEX_DIM(x) ((x) << 0) 2328 # define SQ_TEX_DIM_1D 0 2329 # define SQ_TEX_DIM_2D 1 2330 # define SQ_TEX_DIM_3D 2 2331 # define SQ_TEX_DIM_CUBEMAP 3 2332 # define SQ_TEX_DIM_1D_ARRAY 4 2333 # define SQ_TEX_DIM_2D_ARRAY 5 2334 # define SQ_TEX_DIM_2D_MSAA 6 2335 # define SQ_TEX_DIM_2D_ARRAY_MSAA 7 2336 #define SQ_TEX_RESOURCE_WORD1_0 0x30004 2337 # define TEX_ARRAY_MODE(x) ((x) << 28) 2338 #define SQ_TEX_RESOURCE_WORD2_0 0x30008 2339 #define SQ_TEX_RESOURCE_WORD3_0 0x3000C 2340 #define SQ_TEX_RESOURCE_WORD4_0 0x30010 2341 # define TEX_DST_SEL_X(x) ((x) << 16) 2342 # define TEX_DST_SEL_Y(x) ((x) << 19) 2343 # define TEX_DST_SEL_Z(x) ((x) << 22) 2344 # define TEX_DST_SEL_W(x) ((x) << 25) 2345 # define SQ_SEL_X 0 2346 # define SQ_SEL_Y 1 2347 # define SQ_SEL_Z 2 2348 # define SQ_SEL_W 3 2349 # define SQ_SEL_0 4 2350 # define SQ_SEL_1 5 2351 #define SQ_TEX_RESOURCE_WORD5_0 0x30014 2352 #define SQ_TEX_RESOURCE_WORD6_0 0x30018 2353 # define TEX_TILE_SPLIT(x) (((x) & 0x7) << 29) 2354 #define SQ_TEX_RESOURCE_WORD7_0 0x3001c 2355 # define MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6) 2356 # define TEX_BANK_WIDTH(x) (((x) & 0x3) << 8) 2357 # define TEX_BANK_HEIGHT(x) (((x) & 0x3) << 10) 2358 # define TEX_NUM_BANKS(x) (((x) & 0x3) << 16) 2359 #define R_030000_SQ_TEX_RESOURCE_WORD0_0 0x030000 2360 #define S_030000_DIM(x) (((x) & 0x7) << 0) 2361 #define G_030000_DIM(x) (((x) >> 0) & 0x7) 2362 #define C_030000_DIM 0xFFFFFFF8 2363 #define V_030000_SQ_TEX_DIM_1D 0x00000000 2364 #define V_030000_SQ_TEX_DIM_2D 0x00000001 2365 #define V_030000_SQ_TEX_DIM_3D 0x00000002 2366 #define V_030000_SQ_TEX_DIM_CUBEMAP 0x00000003 2367 #define V_030000_SQ_TEX_DIM_1D_ARRAY 0x00000004 2368 #define V_030000_SQ_TEX_DIM_2D_ARRAY 0x00000005 2369 #define V_030000_SQ_TEX_DIM_2D_MSAA 0x00000006 2370 #define V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 2371 #define S_030000_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 5) 2372 #define G_030000_NON_DISP_TILING_ORDER(x) (((x) >> 5) & 0x1) 2373 #define C_030000_NON_DISP_TILING_ORDER 0xFFFFFFDF 2374 #define S_030000_PITCH(x) (((x) & 0xFFF) << 6) 2375 #define G_030000_PITCH(x) (((x) >> 6) & 0xFFF) 2376 #define C_030000_PITCH 0xFFFC003F 2377 #define S_030000_TEX_WIDTH(x) (((x) & 0x3FFF) << 18) 2378 #define G_030000_TEX_WIDTH(x) (((x) >> 18) & 0x3FFF) 2379 #define C_030000_TEX_WIDTH 0x0003FFFF 2380 #define R_030004_SQ_TEX_RESOURCE_WORD1_0 0x030004 2381 #define S_030004_TEX_HEIGHT(x) (((x) & 0x3FFF) << 0) 2382 #define G_030004_TEX_HEIGHT(x) (((x) >> 0) & 0x3FFF) 2383 #define C_030004_TEX_HEIGHT 0xFFFFC000 2384 #define S_030004_TEX_DEPTH(x) (((x) & 0x1FFF) << 14) 2385 #define G_030004_TEX_DEPTH(x) (((x) >> 14) & 0x1FFF) 2386 #define C_030004_TEX_DEPTH 0xF8003FFF 2387 #define S_030004_ARRAY_MODE(x) (((x) & 0xF) << 28) 2388 #define G_030004_ARRAY_MODE(x) (((x) >> 28) & 0xF) 2389 #define C_030004_ARRAY_MODE 0x0FFFFFFF 2390 #define R_030008_SQ_TEX_RESOURCE_WORD2_0 0x030008 2391 #define S_030008_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 2392 #define G_030008_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 2393 #define C_030008_BASE_ADDRESS 0x00000000 2394 #define R_03000C_SQ_TEX_RESOURCE_WORD3_0 0x03000C 2395 #define S_03000C_MIP_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 2396 #define G_03000C_MIP_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 2397 #define C_03000C_MIP_ADDRESS 0x00000000 2398 #define R_030010_SQ_TEX_RESOURCE_WORD4_0 0x030010 2399 #define S_030010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) 2400 #define G_030010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) 2401 #define C_030010_FORMAT_COMP_X 0xFFFFFFFC 2402 #define V_030010_SQ_FORMAT_COMP_UNSIGNED 0x00000000 2403 #define V_030010_SQ_FORMAT_COMP_SIGNED 0x00000001 2404 #define V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED 0x00000002 2405 #define S_030010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) 2406 #define G_030010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) 2407 #define C_030010_FORMAT_COMP_Y 0xFFFFFFF3 2408 #define S_030010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) 2409 #define G_030010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) 2410 #define C_030010_FORMAT_COMP_Z 0xFFFFFFCF 2411 #define S_030010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) 2412 #define G_030010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) 2413 #define C_030010_FORMAT_COMP_W 0xFFFFFF3F 2414 #define S_030010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) 2415 #define G_030010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) 2416 #define C_030010_NUM_FORMAT_ALL 0xFFFFFCFF 2417 #define V_030010_SQ_NUM_FORMAT_NORM 0x00000000 2418 #define V_030010_SQ_NUM_FORMAT_INT 0x00000001 2419 #define V_030010_SQ_NUM_FORMAT_SCALED 0x00000002 2420 #define S_030010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) 2421 #define G_030010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) 2422 #define C_030010_SRF_MODE_ALL 0xFFFFFBFF 2423 #define V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE 0x00000000 2424 #define V_030010_SRF_MODE_NO_ZERO 0x00000001 2425 #define S_030010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) 2426 #define G_030010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) 2427 #define C_030010_FORCE_DEGAMMA 0xFFFFF7FF 2428 #define S_030010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) 2429 #define G_030010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) 2430 #define C_030010_ENDIAN_SWAP 0xFFFFCFFF 2431 #define S_030010_DST_SEL_X(x) (((x) & 0x7) << 16) 2432 #define G_030010_DST_SEL_X(x) (((x) >> 16) & 0x7) 2433 #define C_030010_DST_SEL_X 0xFFF8FFFF 2434 #define V_030010_SQ_SEL_X 0x00000000 2435 #define V_030010_SQ_SEL_Y 0x00000001 2436 #define V_030010_SQ_SEL_Z 0x00000002 2437 #define V_030010_SQ_SEL_W 0x00000003 2438 #define V_030010_SQ_SEL_0 0x00000004 2439 #define V_030010_SQ_SEL_1 0x00000005 2440 #define S_030010_DST_SEL_Y(x) (((x) & 0x7) << 19) 2441 #define G_030010_DST_SEL_Y(x) (((x) >> 19) & 0x7) 2442 #define C_030010_DST_SEL_Y 0xFFC7FFFF 2443 #define S_030010_DST_SEL_Z(x) (((x) & 0x7) << 22) 2444 #define G_030010_DST_SEL_Z(x) (((x) >> 22) & 0x7) 2445 #define C_030010_DST_SEL_Z 0xFE3FFFFF 2446 #define S_030010_DST_SEL_W(x) (((x) & 0x7) << 25) 2447 #define G_030010_DST_SEL_W(x) (((x) >> 25) & 0x7) 2448 #define C_030010_DST_SEL_W 0xF1FFFFFF 2449 #define S_030010_BASE_LEVEL(x) (((x) & 0xF) << 28) 2450 #define G_030010_BASE_LEVEL(x) (((x) >> 28) & 0xF) 2451 #define C_030010_BASE_LEVEL 0x0FFFFFFF 2452 #define R_030014_SQ_TEX_RESOURCE_WORD5_0 0x030014 2453 #define S_030014_LAST_LEVEL(x) (((x) & 0xF) << 0) 2454 #define G_030014_LAST_LEVEL(x) (((x) >> 0) & 0xF) 2455 #define C_030014_LAST_LEVEL 0xFFFFFFF0 2456 #define S_030014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) 2457 #define G_030014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) 2458 #define C_030014_BASE_ARRAY 0xFFFE000F 2459 #define S_030014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) 2460 #define G_030014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) 2461 #define C_030014_LAST_ARRAY 0xC001FFFF 2462 #define R_030018_SQ_TEX_RESOURCE_WORD6_0 0x030018 2463 #define S_030018_MAX_ANISO(x) (((x) & 0x7) << 0) 2464 #define G_030018_MAX_ANISO(x) (((x) >> 0) & 0x7) 2465 #define C_030018_MAX_ANISO 0xFFFFFFF8 2466 #define S_030018_PERF_MODULATION(x) (((x) & 0x7) << 3) 2467 #define G_030018_PERF_MODULATION(x) (((x) >> 3) & 0x7) 2468 #define C_030018_PERF_MODULATION 0xFFFFFFC7 2469 #define S_030018_INTERLACED(x) (((x) & 0x1) << 6) 2470 #define G_030018_INTERLACED(x) (((x) >> 6) & 0x1) 2471 #define C_030018_INTERLACED 0xFFFFFFBF 2472 #define S_030018_TILE_SPLIT(x) (((x) & 0x7) << 29) 2473 #define G_030018_TILE_SPLIT(x) (((x) >> 29) & 0x7) 2474 #define R_03001C_SQ_TEX_RESOURCE_WORD7_0 0x03001C 2475 #define S_03001C_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6) 2476 #define G_03001C_MACRO_TILE_ASPECT(x) (((x) >> 6) & 0x3) 2477 #define S_03001C_BANK_WIDTH(x) (((x) & 0x3) << 8) 2478 #define G_03001C_BANK_WIDTH(x) (((x) >> 8) & 0x3) 2479 #define S_03001C_BANK_HEIGHT(x) (((x) & 0x3) << 10) 2480 #define G_03001C_BANK_HEIGHT(x) (((x) >> 10) & 0x3) 2481 #define S_03001C_NUM_BANKS(x) (((x) & 0x3) << 16) 2482 #define G_03001C_NUM_BANKS(x) (((x) >> 16) & 0x3) 2483 #define S_03001C_TYPE(x) (((x) & 0x3) << 30) 2484 #define G_03001C_TYPE(x) (((x) >> 30) & 0x3) 2485 #define C_03001C_TYPE 0x3FFFFFFF 2486 #define V_03001C_SQ_TEX_VTX_INVALID_TEXTURE 0x00000000 2487 #define V_03001C_SQ_TEX_VTX_INVALID_BUFFER 0x00000001 2488 #define V_03001C_SQ_TEX_VTX_VALID_TEXTURE 0x00000002 2489 #define V_03001C_SQ_TEX_VTX_VALID_BUFFER 0x00000003 2490 #define S_03001C_DATA_FORMAT(x) (((x) & 0x3F) << 0) 2491 #define G_03001C_DATA_FORMAT(x) (((x) >> 0) & 0x3F) 2492 #define C_03001C_DATA_FORMAT 0xFFFFFFC0 2493 2494 #define SQ_VTX_CONSTANT_WORD0_0 0x30000 2495 #define SQ_VTX_CONSTANT_WORD1_0 0x30004 2496 #define SQ_VTX_CONSTANT_WORD2_0 0x30008 2497 # define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0) 2498 # define SQ_VTXC_STRIDE(x) ((x) << 8) 2499 # define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30) 2500 # define SQ_ENDIAN_NONE 0 2501 # define SQ_ENDIAN_8IN16 1 2502 # define SQ_ENDIAN_8IN32 2 2503 #define SQ_VTX_CONSTANT_WORD3_0 0x3000C 2504 # define SQ_VTCX_SEL_X(x) ((x) << 3) 2505 # define SQ_VTCX_SEL_Y(x) ((x) << 6) 2506 # define SQ_VTCX_SEL_Z(x) ((x) << 9) 2507 # define SQ_VTCX_SEL_W(x) ((x) << 12) 2508 #define SQ_VTX_CONSTANT_WORD4_0 0x30010 2509 #define SQ_VTX_CONSTANT_WORD5_0 0x30014 2510 #define SQ_VTX_CONSTANT_WORD6_0 0x30018 2511 #define SQ_VTX_CONSTANT_WORD7_0 0x3001c 2512 2513 #define TD_PS_BORDER_COLOR_INDEX 0xA400 2514 #define TD_PS_BORDER_COLOR_RED 0xA404 2515 #define TD_PS_BORDER_COLOR_GREEN 0xA408 2516 #define TD_PS_BORDER_COLOR_BLUE 0xA40C 2517 #define TD_PS_BORDER_COLOR_ALPHA 0xA410 2518 #define TD_VS_BORDER_COLOR_INDEX 0xA414 2519 #define TD_VS_BORDER_COLOR_RED 0xA418 2520 #define TD_VS_BORDER_COLOR_GREEN 0xA41C 2521 #define TD_VS_BORDER_COLOR_BLUE 0xA420 2522 #define TD_VS_BORDER_COLOR_ALPHA 0xA424 2523 #define TD_GS_BORDER_COLOR_INDEX 0xA428 2524 #define TD_GS_BORDER_COLOR_RED 0xA42C 2525 #define TD_GS_BORDER_COLOR_GREEN 0xA430 2526 #define TD_GS_BORDER_COLOR_BLUE 0xA434 2527 #define TD_GS_BORDER_COLOR_ALPHA 0xA438 2528 #define TD_HS_BORDER_COLOR_INDEX 0xA43C 2529 #define TD_HS_BORDER_COLOR_RED 0xA440 2530 #define TD_HS_BORDER_COLOR_GREEN 0xA444 2531 #define TD_HS_BORDER_COLOR_BLUE 0xA448 2532 #define TD_HS_BORDER_COLOR_ALPHA 0xA44C 2533 #define TD_LS_BORDER_COLOR_INDEX 0xA450 2534 #define TD_LS_BORDER_COLOR_RED 0xA454 2535 #define TD_LS_BORDER_COLOR_GREEN 0xA458 2536 #define TD_LS_BORDER_COLOR_BLUE 0xA45C 2537 #define TD_LS_BORDER_COLOR_ALPHA 0xA460 2538 #define TD_CS_BORDER_COLOR_INDEX 0xA464 2539 #define TD_CS_BORDER_COLOR_RED 0xA468 2540 #define TD_CS_BORDER_COLOR_GREEN 0xA46C 2541 #define TD_CS_BORDER_COLOR_BLUE 0xA470 2542 #define TD_CS_BORDER_COLOR_ALPHA 0xA474 2543 2544 /* cayman 3D regs */ 2545 #define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B4 2546 #define CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS 0x8E48 2547 #define CAYMAN_DB_EQAA 0x28804 2548 #define CAYMAN_DB_DEPTH_INFO 0x2803C 2549 #define CAYMAN_PA_SC_AA_CONFIG 0x28BE0 2550 #define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0 2551 #define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7 2552 #define CAYMAN_SX_SCATTER_EXPORT_BASE 0x28358 2553 /* cayman packet3 addition */ 2554 #define CAYMAN_PACKET3_DEALLOC_STATE 0x14 2555 2556 /* DMA regs common on r6xx/r7xx/evergreen/ni */ 2557 #define DMA_RB_CNTL 0xd000 2558 # define DMA_RB_ENABLE (1 << 0) 2559 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 2560 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 2561 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 2562 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 2563 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 2564 #define DMA_STATUS_REG 0xd034 2565 # define DMA_IDLE (1 << 0) 2566 2567 #endif 2568