1 /* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #ifndef EVERGREEND_H 25 #define EVERGREEND_H 26 27 #define EVERGREEN_MAX_SH_GPRS 256 28 #define EVERGREEN_MAX_TEMP_GPRS 16 29 #define EVERGREEN_MAX_SH_THREADS 256 30 #define EVERGREEN_MAX_SH_STACK_ENTRIES 4096 31 #define EVERGREEN_MAX_FRC_EOV_CNT 16384 32 #define EVERGREEN_MAX_BACKENDS 8 33 #define EVERGREEN_MAX_BACKENDS_MASK 0xFF 34 #define EVERGREEN_MAX_SIMDS 16 35 #define EVERGREEN_MAX_SIMDS_MASK 0xFFFF 36 #define EVERGREEN_MAX_PIPES 8 37 #define EVERGREEN_MAX_PIPES_MASK 0xFF 38 #define EVERGREEN_MAX_LDS_NUM 0xFFFF 39 40 /* Registers */ 41 42 #define RCU_IND_INDEX 0x100 43 #define RCU_IND_DATA 0x104 44 45 #define GRBM_GFX_INDEX 0x802C 46 #define INSTANCE_INDEX(x) ((x) << 0) 47 #define SE_INDEX(x) ((x) << 16) 48 #define INSTANCE_BROADCAST_WRITES (1 << 30) 49 #define SE_BROADCAST_WRITES (1 << 31) 50 #define RLC_GFX_INDEX 0x3fC4 51 #define CC_GC_SHADER_PIPE_CONFIG 0x8950 52 #define WRITE_DIS (1 << 0) 53 #define CC_RB_BACKEND_DISABLE 0x98F4 54 #define BACKEND_DISABLE(x) ((x) << 16) 55 #define GB_ADDR_CONFIG 0x98F8 56 #define NUM_PIPES(x) ((x) << 0) 57 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 58 #define BANK_INTERLEAVE_SIZE(x) ((x) << 8) 59 #define NUM_SHADER_ENGINES(x) ((x) << 12) 60 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 61 #define NUM_GPUS(x) ((x) << 20) 62 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 63 #define ROW_SIZE(x) ((x) << 28) 64 #define GB_BACKEND_MAP 0x98FC 65 #define DMIF_ADDR_CONFIG 0xBD4 66 #define HDP_ADDR_CONFIG 0x2F48 67 68 #define CC_SYS_RB_BACKEND_DISABLE 0x3F88 69 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 70 71 #define CGTS_SYS_TCC_DISABLE 0x3F90 72 #define CGTS_TCC_DISABLE 0x9148 73 #define CGTS_USER_SYS_TCC_DISABLE 0x3F94 74 #define CGTS_USER_TCC_DISABLE 0x914C 75 76 #define CONFIG_MEMSIZE 0x5428 77 78 #define CP_ME_CNTL 0x86D8 79 #define CP_ME_HALT (1 << 28) 80 #define CP_PFP_HALT (1 << 26) 81 #define CP_ME_RAM_DATA 0xC160 82 #define CP_ME_RAM_RADDR 0xC158 83 #define CP_ME_RAM_WADDR 0xC15C 84 #define CP_MEQ_THRESHOLDS 0x8764 85 #define STQ_SPLIT(x) ((x) << 0) 86 #define CP_PERFMON_CNTL 0x87FC 87 #define CP_PFP_UCODE_ADDR 0xC150 88 #define CP_PFP_UCODE_DATA 0xC154 89 #define CP_QUEUE_THRESHOLDS 0x8760 90 #define ROQ_IB1_START(x) ((x) << 0) 91 #define ROQ_IB2_START(x) ((x) << 8) 92 #define CP_RB_BASE 0xC100 93 #define CP_RB_CNTL 0xC104 94 #define RB_BUFSZ(x) ((x) << 0) 95 #define RB_BLKSZ(x) ((x) << 8) 96 #define RB_NO_UPDATE (1 << 27) 97 #define RB_RPTR_WR_ENA (1 << 31) 98 #define BUF_SWAP_32BIT (2 << 16) 99 #define CP_RB_RPTR 0x8700 100 #define CP_RB_RPTR_ADDR 0xC10C 101 #define CP_RB_RPTR_ADDR_HI 0xC110 102 #define CP_RB_RPTR_WR 0xC108 103 #define CP_RB_WPTR 0xC114 104 #define CP_RB_WPTR_ADDR 0xC118 105 #define CP_RB_WPTR_ADDR_HI 0xC11C 106 #define CP_RB_WPTR_DELAY 0x8704 107 #define CP_SEM_WAIT_TIMER 0x85BC 108 #define CP_DEBUG 0xC1FC 109 110 111 #define GC_USER_SHADER_PIPE_CONFIG 0x8954 112 #define INACTIVE_QD_PIPES(x) ((x) << 8) 113 #define INACTIVE_QD_PIPES_MASK 0x0000FF00 114 #define INACTIVE_SIMDS(x) ((x) << 16) 115 #define INACTIVE_SIMDS_MASK 0x00FF0000 116 117 #define GRBM_CNTL 0x8000 118 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 119 #define GRBM_SOFT_RESET 0x8020 120 #define SOFT_RESET_CP (1 << 0) 121 #define SOFT_RESET_CB (1 << 1) 122 #define SOFT_RESET_DB (1 << 3) 123 #define SOFT_RESET_PA (1 << 5) 124 #define SOFT_RESET_SC (1 << 6) 125 #define SOFT_RESET_SPI (1 << 8) 126 #define SOFT_RESET_SH (1 << 9) 127 #define SOFT_RESET_SX (1 << 10) 128 #define SOFT_RESET_TC (1 << 11) 129 #define SOFT_RESET_TA (1 << 12) 130 #define SOFT_RESET_VC (1 << 13) 131 #define SOFT_RESET_VGT (1 << 14) 132 133 #define GRBM_STATUS 0x8010 134 #define CMDFIFO_AVAIL_MASK 0x0000000F 135 #define SRBM_RQ_PENDING (1 << 5) 136 #define CF_RQ_PENDING (1 << 7) 137 #define PF_RQ_PENDING (1 << 8) 138 #define GRBM_EE_BUSY (1 << 10) 139 #define SX_CLEAN (1 << 11) 140 #define DB_CLEAN (1 << 12) 141 #define CB_CLEAN (1 << 13) 142 #define TA_BUSY (1 << 14) 143 #define VGT_BUSY_NO_DMA (1 << 16) 144 #define VGT_BUSY (1 << 17) 145 #define SX_BUSY (1 << 20) 146 #define SH_BUSY (1 << 21) 147 #define SPI_BUSY (1 << 22) 148 #define SC_BUSY (1 << 24) 149 #define PA_BUSY (1 << 25) 150 #define DB_BUSY (1 << 26) 151 #define CP_COHERENCY_BUSY (1 << 28) 152 #define CP_BUSY (1 << 29) 153 #define CB_BUSY (1 << 30) 154 #define GUI_ACTIVE (1 << 31) 155 #define GRBM_STATUS_SE0 0x8014 156 #define GRBM_STATUS_SE1 0x8018 157 #define SE_SX_CLEAN (1 << 0) 158 #define SE_DB_CLEAN (1 << 1) 159 #define SE_CB_CLEAN (1 << 2) 160 #define SE_TA_BUSY (1 << 25) 161 #define SE_SX_BUSY (1 << 26) 162 #define SE_SPI_BUSY (1 << 27) 163 #define SE_SH_BUSY (1 << 28) 164 #define SE_SC_BUSY (1 << 29) 165 #define SE_DB_BUSY (1 << 30) 166 #define SE_CB_BUSY (1 << 31) 167 168 #define CG_MULT_THERMAL_STATUS 0x740 169 #define ASIC_T(x) ((x) << 16) 170 #define ASIC_T_MASK 0x7FF0000 171 #define ASIC_T_SHIFT 16 172 173 #define HDP_HOST_PATH_CNTL 0x2C00 174 #define HDP_NONSURFACE_BASE 0x2C04 175 #define HDP_NONSURFACE_INFO 0x2C08 176 #define HDP_NONSURFACE_SIZE 0x2C0C 177 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 178 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 179 #define HDP_TILING_CONFIG 0x2F3C 180 181 #define MC_SHARED_CHMAP 0x2004 182 #define NOOFCHAN_SHIFT 12 183 #define NOOFCHAN_MASK 0x00003000 184 185 #define MC_ARB_RAMCFG 0x2760 186 #define NOOFBANK_SHIFT 0 187 #define NOOFBANK_MASK 0x00000003 188 #define NOOFRANK_SHIFT 2 189 #define NOOFRANK_MASK 0x00000004 190 #define NOOFROWS_SHIFT 3 191 #define NOOFROWS_MASK 0x00000038 192 #define NOOFCOLS_SHIFT 6 193 #define NOOFCOLS_MASK 0x000000C0 194 #define CHANSIZE_SHIFT 8 195 #define CHANSIZE_MASK 0x00000100 196 #define BURSTLENGTH_SHIFT 9 197 #define BURSTLENGTH_MASK 0x00000200 198 #define CHANSIZE_OVERRIDE (1 << 11) 199 #define MC_VM_AGP_TOP 0x2028 200 #define MC_VM_AGP_BOT 0x202C 201 #define MC_VM_AGP_BASE 0x2030 202 #define MC_VM_FB_LOCATION 0x2024 203 #define MC_VM_MB_L1_TLB0_CNTL 0x2234 204 #define MC_VM_MB_L1_TLB1_CNTL 0x2238 205 #define MC_VM_MB_L1_TLB2_CNTL 0x223C 206 #define MC_VM_MB_L1_TLB3_CNTL 0x2240 207 #define ENABLE_L1_TLB (1 << 0) 208 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 209 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 210 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 211 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 212 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 213 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 214 #define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) 215 #define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) 216 #define MC_VM_MD_L1_TLB0_CNTL 0x2654 217 #define MC_VM_MD_L1_TLB1_CNTL 0x2658 218 #define MC_VM_MD_L1_TLB2_CNTL 0x265C 219 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 220 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 221 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 222 223 #define PA_CL_ENHANCE 0x8A14 224 #define CLIP_VTX_REORDER_ENA (1 << 0) 225 #define NUM_CLIP_SEQ(x) ((x) << 1) 226 #define PA_SC_AA_CONFIG 0x28C04 227 #define MSAA_NUM_SAMPLES_SHIFT 0 228 #define MSAA_NUM_SAMPLES_MASK 0x3 229 #define PA_SC_CLIPRECT_RULE 0x2820C 230 #define PA_SC_EDGERULE 0x28230 231 #define PA_SC_FIFO_SIZE 0x8BCC 232 #define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 233 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 234 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 235 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 236 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 237 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 238 #define PA_SC_LINE_STIPPLE 0x28A0C 239 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 240 241 #define SCRATCH_REG0 0x8500 242 #define SCRATCH_REG1 0x8504 243 #define SCRATCH_REG2 0x8508 244 #define SCRATCH_REG3 0x850C 245 #define SCRATCH_REG4 0x8510 246 #define SCRATCH_REG5 0x8514 247 #define SCRATCH_REG6 0x8518 248 #define SCRATCH_REG7 0x851C 249 #define SCRATCH_UMSK 0x8540 250 #define SCRATCH_ADDR 0x8544 251 252 #define SMX_DC_CTL0 0xA020 253 #define USE_HASH_FUNCTION (1 << 0) 254 #define NUMBER_OF_SETS(x) ((x) << 1) 255 #define FLUSH_ALL_ON_EVENT (1 << 10) 256 #define STALL_ON_EVENT (1 << 11) 257 #define SMX_EVENT_CTL 0xA02C 258 #define ES_FLUSH_CTL(x) ((x) << 0) 259 #define GS_FLUSH_CTL(x) ((x) << 3) 260 #define ACK_FLUSH_CTL(x) ((x) << 6) 261 #define SYNC_FLUSH_CTL (1 << 8) 262 263 #define SPI_CONFIG_CNTL 0x9100 264 #define GPR_WRITE_PRIORITY(x) ((x) << 0) 265 #define SPI_CONFIG_CNTL_1 0x913C 266 #define VTX_DONE_DELAY(x) ((x) << 0) 267 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 268 #define SPI_INPUT_Z 0x286D8 269 #define SPI_PS_IN_CONTROL_0 0x286CC 270 #define NUM_INTERP(x) ((x)<<0) 271 #define POSITION_ENA (1<<8) 272 #define POSITION_CENTROID (1<<9) 273 #define POSITION_ADDR(x) ((x)<<10) 274 #define PARAM_GEN(x) ((x)<<15) 275 #define PARAM_GEN_ADDR(x) ((x)<<19) 276 #define BARYC_SAMPLE_CNTL(x) ((x)<<26) 277 #define PERSP_GRADIENT_ENA (1<<28) 278 #define LINEAR_GRADIENT_ENA (1<<29) 279 #define POSITION_SAMPLE (1<<30) 280 #define BARYC_AT_SAMPLE_ENA (1<<31) 281 282 #define SQ_CONFIG 0x8C00 283 #define VC_ENABLE (1 << 0) 284 #define EXPORT_SRC_C (1 << 1) 285 #define CS_PRIO(x) ((x) << 18) 286 #define LS_PRIO(x) ((x) << 20) 287 #define HS_PRIO(x) ((x) << 22) 288 #define PS_PRIO(x) ((x) << 24) 289 #define VS_PRIO(x) ((x) << 26) 290 #define GS_PRIO(x) ((x) << 28) 291 #define ES_PRIO(x) ((x) << 30) 292 #define SQ_GPR_RESOURCE_MGMT_1 0x8C04 293 #define NUM_PS_GPRS(x) ((x) << 0) 294 #define NUM_VS_GPRS(x) ((x) << 16) 295 #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 296 #define SQ_GPR_RESOURCE_MGMT_2 0x8C08 297 #define NUM_GS_GPRS(x) ((x) << 0) 298 #define NUM_ES_GPRS(x) ((x) << 16) 299 #define SQ_GPR_RESOURCE_MGMT_3 0x8C0C 300 #define NUM_HS_GPRS(x) ((x) << 0) 301 #define NUM_LS_GPRS(x) ((x) << 16) 302 #define SQ_THREAD_RESOURCE_MGMT 0x8C18 303 #define NUM_PS_THREADS(x) ((x) << 0) 304 #define NUM_VS_THREADS(x) ((x) << 8) 305 #define NUM_GS_THREADS(x) ((x) << 16) 306 #define NUM_ES_THREADS(x) ((x) << 24) 307 #define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C 308 #define NUM_HS_THREADS(x) ((x) << 0) 309 #define NUM_LS_THREADS(x) ((x) << 8) 310 #define SQ_STACK_RESOURCE_MGMT_1 0x8C20 311 #define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 312 #define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 313 #define SQ_STACK_RESOURCE_MGMT_2 0x8C24 314 #define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 315 #define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 316 #define SQ_STACK_RESOURCE_MGMT_3 0x8C28 317 #define NUM_HS_STACK_ENTRIES(x) ((x) << 0) 318 #define NUM_LS_STACK_ENTRIES(x) ((x) << 16) 319 #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C 320 #define SQ_LDS_RESOURCE_MGMT 0x8E2C 321 322 #define SQ_MS_FIFO_SIZES 0x8CF0 323 #define CACHE_FIFO_SIZE(x) ((x) << 0) 324 #define FETCH_FIFO_HIWATER(x) ((x) << 8) 325 #define DONE_FIFO_HIWATER(x) ((x) << 16) 326 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 327 328 #define SX_DEBUG_1 0x9058 329 #define ENABLE_NEW_SMX_ADDRESS (1 << 16) 330 #define SX_EXPORT_BUFFER_SIZES 0x900C 331 #define COLOR_BUFFER_SIZE(x) ((x) << 0) 332 #define POSITION_BUFFER_SIZE(x) ((x) << 8) 333 #define SMX_BUFFER_SIZE(x) ((x) << 16) 334 #define SX_MISC 0x28350 335 336 #define CB_PERF_CTR0_SEL_0 0x9A20 337 #define CB_PERF_CTR0_SEL_1 0x9A24 338 #define CB_PERF_CTR1_SEL_0 0x9A28 339 #define CB_PERF_CTR1_SEL_1 0x9A2C 340 #define CB_PERF_CTR2_SEL_0 0x9A30 341 #define CB_PERF_CTR2_SEL_1 0x9A34 342 #define CB_PERF_CTR3_SEL_0 0x9A38 343 #define CB_PERF_CTR3_SEL_1 0x9A3C 344 345 #define TA_CNTL_AUX 0x9508 346 #define DISABLE_CUBE_WRAP (1 << 0) 347 #define DISABLE_CUBE_ANISO (1 << 1) 348 #define SYNC_GRADIENT (1 << 24) 349 #define SYNC_WALKER (1 << 25) 350 #define SYNC_ALIGNER (1 << 26) 351 352 #define VGT_CACHE_INVALIDATION 0x88C4 353 #define CACHE_INVALIDATION(x) ((x) << 0) 354 #define VC_ONLY 0 355 #define TC_ONLY 1 356 #define VC_AND_TC 2 357 #define AUTO_INVLD_EN(x) ((x) << 6) 358 #define NO_AUTO 0 359 #define ES_AUTO 1 360 #define GS_AUTO 2 361 #define ES_AND_GS_AUTO 3 362 #define VGT_GS_VERTEX_REUSE 0x88D4 363 #define VGT_NUM_INSTANCES 0x8974 364 #define VGT_OUT_DEALLOC_CNTL 0x28C5C 365 #define DEALLOC_DIST_MASK 0x0000007F 366 #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 367 #define VTX_REUSE_DEPTH_MASK 0x000000FF 368 369 #define VM_CONTEXT0_CNTL 0x1410 370 #define ENABLE_CONTEXT (1 << 0) 371 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 372 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 373 #define VM_CONTEXT1_CNTL 0x1414 374 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 375 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 376 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 377 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 378 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 379 #define REQUEST_TYPE(x) (((x) & 0xf) << 0) 380 #define RESPONSE_TYPE_MASK 0x000000F0 381 #define RESPONSE_TYPE_SHIFT 4 382 #define VM_L2_CNTL 0x1400 383 #define ENABLE_L2_CACHE (1 << 0) 384 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 385 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 386 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 387 #define VM_L2_CNTL2 0x1404 388 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 389 #define INVALIDATE_L2_CACHE (1 << 1) 390 #define VM_L2_CNTL3 0x1408 391 #define BANK_SELECT(x) ((x) << 0) 392 #define CACHE_UPDATE_MODE(x) ((x) << 6) 393 #define VM_L2_STATUS 0x140C 394 #define L2_BUSY (1 << 0) 395 396 #define WAIT_UNTIL 0x8040 397 398 #define SRBM_STATUS 0x0E50 399 #define SRBM_SOFT_RESET 0x0E60 400 #define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6 401 #define SOFT_RESET_BIF (1 << 1) 402 #define SOFT_RESET_CG (1 << 2) 403 #define SOFT_RESET_DC (1 << 5) 404 #define SOFT_RESET_GRBM (1 << 8) 405 #define SOFT_RESET_HDP (1 << 9) 406 #define SOFT_RESET_IH (1 << 10) 407 #define SOFT_RESET_MC (1 << 11) 408 #define SOFT_RESET_RLC (1 << 13) 409 #define SOFT_RESET_ROM (1 << 14) 410 #define SOFT_RESET_SEM (1 << 15) 411 #define SOFT_RESET_VMC (1 << 17) 412 #define SOFT_RESET_TST (1 << 21) 413 #define SOFT_RESET_REGBB (1 << 22) 414 #define SOFT_RESET_ORB (1 << 23) 415 416 /* display watermarks */ 417 #define DC_LB_MEMORY_SPLIT 0x6b0c 418 #define PRIORITY_A_CNT 0x6b18 419 #define PRIORITY_MARK_MASK 0x7fff 420 #define PRIORITY_OFF (1 << 16) 421 #define PRIORITY_ALWAYS_ON (1 << 20) 422 #define PRIORITY_B_CNT 0x6b1c 423 #define PIPE0_ARBITRATION_CONTROL3 0x0bf0 424 # define LATENCY_WATERMARK_MASK(x) ((x) << 16) 425 #define PIPE0_LATENCY_CONTROL 0x0bf4 426 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 427 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 428 429 #define IH_RB_CNTL 0x3e00 430 # define IH_RB_ENABLE (1 << 0) 431 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 432 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 433 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 434 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 435 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 436 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 437 #define IH_RB_BASE 0x3e04 438 #define IH_RB_RPTR 0x3e08 439 #define IH_RB_WPTR 0x3e0c 440 # define RB_OVERFLOW (1 << 0) 441 # define WPTR_OFFSET_MASK 0x3fffc 442 #define IH_RB_WPTR_ADDR_HI 0x3e10 443 #define IH_RB_WPTR_ADDR_LO 0x3e14 444 #define IH_CNTL 0x3e18 445 # define ENABLE_INTR (1 << 0) 446 # define IH_MC_SWAP(x) ((x) << 2) 447 # define IH_MC_SWAP_NONE 0 448 # define IH_MC_SWAP_16BIT 1 449 # define IH_MC_SWAP_32BIT 2 450 # define IH_MC_SWAP_64BIT 3 451 # define RPTR_REARM (1 << 4) 452 # define MC_WRREQ_CREDIT(x) ((x) << 15) 453 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 454 455 #define CP_INT_CNTL 0xc124 456 # define CNTX_BUSY_INT_ENABLE (1 << 19) 457 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 458 # define SCRATCH_INT_ENABLE (1 << 25) 459 # define TIME_STAMP_INT_ENABLE (1 << 26) 460 # define IB2_INT_ENABLE (1 << 29) 461 # define IB1_INT_ENABLE (1 << 30) 462 # define RB_INT_ENABLE (1 << 31) 463 #define CP_INT_STATUS 0xc128 464 # define SCRATCH_INT_STAT (1 << 25) 465 # define TIME_STAMP_INT_STAT (1 << 26) 466 # define IB2_INT_STAT (1 << 29) 467 # define IB1_INT_STAT (1 << 30) 468 # define RB_INT_STAT (1 << 31) 469 470 #define GRBM_INT_CNTL 0x8060 471 # define RDERR_INT_ENABLE (1 << 0) 472 # define GUI_IDLE_INT_ENABLE (1 << 19) 473 474 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ 475 #define CRTC_STATUS_FRAME_COUNT 0x6e98 476 477 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ 478 #define VLINE_STATUS 0x6bb8 479 # define VLINE_OCCURRED (1 << 0) 480 # define VLINE_ACK (1 << 4) 481 # define VLINE_STAT (1 << 12) 482 # define VLINE_INTERRUPT (1 << 16) 483 # define VLINE_INTERRUPT_TYPE (1 << 17) 484 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ 485 #define VBLANK_STATUS 0x6bbc 486 # define VBLANK_OCCURRED (1 << 0) 487 # define VBLANK_ACK (1 << 4) 488 # define VBLANK_STAT (1 << 12) 489 # define VBLANK_INTERRUPT (1 << 16) 490 # define VBLANK_INTERRUPT_TYPE (1 << 17) 491 492 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ 493 #define INT_MASK 0x6b40 494 # define VBLANK_INT_MASK (1 << 0) 495 # define VLINE_INT_MASK (1 << 4) 496 497 #define DISP_INTERRUPT_STATUS 0x60f4 498 # define LB_D1_VLINE_INTERRUPT (1 << 2) 499 # define LB_D1_VBLANK_INTERRUPT (1 << 3) 500 # define DC_HPD1_INTERRUPT (1 << 17) 501 # define DC_HPD1_RX_INTERRUPT (1 << 18) 502 # define DACA_AUTODETECT_INTERRUPT (1 << 22) 503 # define DACB_AUTODETECT_INTERRUPT (1 << 23) 504 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 505 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 506 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 507 # define LB_D2_VLINE_INTERRUPT (1 << 2) 508 # define LB_D2_VBLANK_INTERRUPT (1 << 3) 509 # define DC_HPD2_INTERRUPT (1 << 17) 510 # define DC_HPD2_RX_INTERRUPT (1 << 18) 511 # define DISP_TIMER_INTERRUPT (1 << 24) 512 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 513 # define LB_D3_VLINE_INTERRUPT (1 << 2) 514 # define LB_D3_VBLANK_INTERRUPT (1 << 3) 515 # define DC_HPD3_INTERRUPT (1 << 17) 516 # define DC_HPD3_RX_INTERRUPT (1 << 18) 517 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 518 # define LB_D4_VLINE_INTERRUPT (1 << 2) 519 # define LB_D4_VBLANK_INTERRUPT (1 << 3) 520 # define DC_HPD4_INTERRUPT (1 << 17) 521 # define DC_HPD4_RX_INTERRUPT (1 << 18) 522 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 523 # define LB_D5_VLINE_INTERRUPT (1 << 2) 524 # define LB_D5_VBLANK_INTERRUPT (1 << 3) 525 # define DC_HPD5_INTERRUPT (1 << 17) 526 # define DC_HPD5_RX_INTERRUPT (1 << 18) 527 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6050 528 # define LB_D6_VLINE_INTERRUPT (1 << 2) 529 # define LB_D6_VBLANK_INTERRUPT (1 << 3) 530 # define DC_HPD6_INTERRUPT (1 << 17) 531 # define DC_HPD6_RX_INTERRUPT (1 << 18) 532 533 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 534 #define GRPH_INT_STATUS 0x6858 535 # define GRPH_PFLIP_INT_OCCURRED (1 << 0) 536 # define GRPH_PFLIP_INT_CLEAR (1 << 8) 537 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 538 #define GRPH_INT_CONTROL 0x685c 539 # define GRPH_PFLIP_INT_MASK (1 << 0) 540 # define GRPH_PFLIP_INT_TYPE (1 << 8) 541 542 #define DACA_AUTODETECT_INT_CONTROL 0x66c8 543 #define DACB_AUTODETECT_INT_CONTROL 0x67c8 544 545 #define DC_HPD1_INT_STATUS 0x601c 546 #define DC_HPD2_INT_STATUS 0x6028 547 #define DC_HPD3_INT_STATUS 0x6034 548 #define DC_HPD4_INT_STATUS 0x6040 549 #define DC_HPD5_INT_STATUS 0x604c 550 #define DC_HPD6_INT_STATUS 0x6058 551 # define DC_HPDx_INT_STATUS (1 << 0) 552 # define DC_HPDx_SENSE (1 << 1) 553 # define DC_HPDx_RX_INT_STATUS (1 << 8) 554 555 #define DC_HPD1_INT_CONTROL 0x6020 556 #define DC_HPD2_INT_CONTROL 0x602c 557 #define DC_HPD3_INT_CONTROL 0x6038 558 #define DC_HPD4_INT_CONTROL 0x6044 559 #define DC_HPD5_INT_CONTROL 0x6050 560 #define DC_HPD6_INT_CONTROL 0x605c 561 # define DC_HPDx_INT_ACK (1 << 0) 562 # define DC_HPDx_INT_POLARITY (1 << 8) 563 # define DC_HPDx_INT_EN (1 << 16) 564 # define DC_HPDx_RX_INT_ACK (1 << 20) 565 # define DC_HPDx_RX_INT_EN (1 << 24) 566 567 #define DC_HPD1_CONTROL 0x6024 568 #define DC_HPD2_CONTROL 0x6030 569 #define DC_HPD3_CONTROL 0x603c 570 #define DC_HPD4_CONTROL 0x6048 571 #define DC_HPD5_CONTROL 0x6054 572 #define DC_HPD6_CONTROL 0x6060 573 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 574 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 575 # define DC_HPDx_EN (1 << 28) 576 577 /* 578 * PM4 579 */ 580 #define PACKET_TYPE0 0 581 #define PACKET_TYPE1 1 582 #define PACKET_TYPE2 2 583 #define PACKET_TYPE3 3 584 585 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 586 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 587 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 588 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 589 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 590 (((reg) >> 2) & 0xFFFF) | \ 591 ((n) & 0x3FFF) << 16) 592 #define CP_PACKET2 0x80000000 593 #define PACKET2_PAD_SHIFT 0 594 #define PACKET2_PAD_MASK (0x3fffffff << 0) 595 596 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 597 598 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 599 (((op) & 0xFF) << 8) | \ 600 ((n) & 0x3FFF) << 16) 601 602 /* Packet 3 types */ 603 #define PACKET3_NOP 0x10 604 #define PACKET3_SET_BASE 0x11 605 #define PACKET3_CLEAR_STATE 0x12 606 #define PACKET3_INDIRECT_BUFFER_SIZE 0x13 607 #define PACKET3_DISPATCH_DIRECT 0x15 608 #define PACKET3_DISPATCH_INDIRECT 0x16 609 #define PACKET3_INDIRECT_BUFFER_END 0x17 610 #define PACKET3_SET_PREDICATION 0x20 611 #define PACKET3_REG_RMW 0x21 612 #define PACKET3_COND_EXEC 0x22 613 #define PACKET3_PRED_EXEC 0x23 614 #define PACKET3_DRAW_INDIRECT 0x24 615 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 616 #define PACKET3_INDEX_BASE 0x26 617 #define PACKET3_DRAW_INDEX_2 0x27 618 #define PACKET3_CONTEXT_CONTROL 0x28 619 #define PACKET3_DRAW_INDEX_OFFSET 0x29 620 #define PACKET3_INDEX_TYPE 0x2A 621 #define PACKET3_DRAW_INDEX 0x2B 622 #define PACKET3_DRAW_INDEX_AUTO 0x2D 623 #define PACKET3_DRAW_INDEX_IMMD 0x2E 624 #define PACKET3_NUM_INSTANCES 0x2F 625 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 626 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 627 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 628 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 629 #define PACKET3_MEM_SEMAPHORE 0x39 630 #define PACKET3_MPEG_INDEX 0x3A 631 #define PACKET3_WAIT_REG_MEM 0x3C 632 #define PACKET3_MEM_WRITE 0x3D 633 #define PACKET3_INDIRECT_BUFFER 0x32 634 #define PACKET3_SURFACE_SYNC 0x43 635 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 636 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 637 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 638 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 639 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 640 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 641 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 642 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 643 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 644 # define PACKET3_CB8_DEST_BASE_ENA (1 << 15) 645 # define PACKET3_CB9_DEST_BASE_ENA (1 << 16) 646 # define PACKET3_CB10_DEST_BASE_ENA (1 << 17) 647 # define PACKET3_CB11_DEST_BASE_ENA (1 << 17) 648 # define PACKET3_FULL_CACHE_ENA (1 << 20) 649 # define PACKET3_TC_ACTION_ENA (1 << 23) 650 # define PACKET3_VC_ACTION_ENA (1 << 24) 651 # define PACKET3_CB_ACTION_ENA (1 << 25) 652 # define PACKET3_DB_ACTION_ENA (1 << 26) 653 # define PACKET3_SH_ACTION_ENA (1 << 27) 654 # define PACKET3_SMX_ACTION_ENA (1 << 28) 655 #define PACKET3_ME_INITIALIZE 0x44 656 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 657 #define PACKET3_COND_WRITE 0x45 658 #define PACKET3_EVENT_WRITE 0x46 659 #define PACKET3_EVENT_WRITE_EOP 0x47 660 #define PACKET3_EVENT_WRITE_EOS 0x48 661 #define PACKET3_PREAMBLE_CNTL 0x4A 662 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 663 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 664 #define PACKET3_RB_OFFSET 0x4B 665 #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C 666 #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D 667 #define PACKET3_ALU_PS_CONST_UPDATE 0x4E 668 #define PACKET3_ALU_VS_CONST_UPDATE 0x4F 669 #define PACKET3_ONE_REG_WRITE 0x57 670 #define PACKET3_SET_CONFIG_REG 0x68 671 #define PACKET3_SET_CONFIG_REG_START 0x00008000 672 #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 673 #define PACKET3_SET_CONTEXT_REG 0x69 674 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 675 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 676 #define PACKET3_SET_ALU_CONST 0x6A 677 /* alu const buffers only; no reg file */ 678 #define PACKET3_SET_BOOL_CONST 0x6B 679 #define PACKET3_SET_BOOL_CONST_START 0x0003a500 680 #define PACKET3_SET_BOOL_CONST_END 0x0003a518 681 #define PACKET3_SET_LOOP_CONST 0x6C 682 #define PACKET3_SET_LOOP_CONST_START 0x0003a200 683 #define PACKET3_SET_LOOP_CONST_END 0x0003a500 684 #define PACKET3_SET_RESOURCE 0x6D 685 #define PACKET3_SET_RESOURCE_START 0x00030000 686 #define PACKET3_SET_RESOURCE_END 0x00038000 687 #define PACKET3_SET_SAMPLER 0x6E 688 #define PACKET3_SET_SAMPLER_START 0x0003c000 689 #define PACKET3_SET_SAMPLER_END 0x0003c600 690 #define PACKET3_SET_CTL_CONST 0x6F 691 #define PACKET3_SET_CTL_CONST_START 0x0003cff0 692 #define PACKET3_SET_CTL_CONST_END 0x0003ff0c 693 #define PACKET3_SET_RESOURCE_OFFSET 0x70 694 #define PACKET3_SET_ALU_CONST_VS 0x71 695 #define PACKET3_SET_ALU_CONST_DI 0x72 696 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 697 #define PACKET3_SET_RESOURCE_INDIRECT 0x74 698 #define PACKET3_SET_APPEND_CNT 0x75 699 700 #define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c 701 #define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30) 702 #define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3) 703 #define SQ_TEX_VTX_INVALID_TEXTURE 0x0 704 #define SQ_TEX_VTX_INVALID_BUFFER 0x1 705 #define SQ_TEX_VTX_VALID_TEXTURE 0x2 706 #define SQ_TEX_VTX_VALID_BUFFER 0x3 707 708 #define SQ_CONST_MEM_BASE 0x8df8 709 710 #define SQ_ESGS_RING_SIZE 0x8c44 711 #define SQ_GSVS_RING_SIZE 0x8c4c 712 #define SQ_ESTMP_RING_SIZE 0x8c54 713 #define SQ_GSTMP_RING_SIZE 0x8c5c 714 #define SQ_VSTMP_RING_SIZE 0x8c64 715 #define SQ_PSTMP_RING_SIZE 0x8c6c 716 #define SQ_LSTMP_RING_SIZE 0x8e14 717 #define SQ_HSTMP_RING_SIZE 0x8e1c 718 #define VGT_TF_RING_SIZE 0x8988 719 720 #define SQ_ESGS_RING_ITEMSIZE 0x28900 721 #define SQ_GSVS_RING_ITEMSIZE 0x28904 722 #define SQ_ESTMP_RING_ITEMSIZE 0x28908 723 #define SQ_GSTMP_RING_ITEMSIZE 0x2890c 724 #define SQ_VSTMP_RING_ITEMSIZE 0x28910 725 #define SQ_PSTMP_RING_ITEMSIZE 0x28914 726 #define SQ_LSTMP_RING_ITEMSIZE 0x28830 727 #define SQ_HSTMP_RING_ITEMSIZE 0x28834 728 729 #define SQ_GS_VERT_ITEMSIZE 0x2891c 730 #define SQ_GS_VERT_ITEMSIZE_1 0x28920 731 #define SQ_GS_VERT_ITEMSIZE_2 0x28924 732 #define SQ_GS_VERT_ITEMSIZE_3 0x28928 733 #define SQ_GSVS_RING_OFFSET_1 0x2892c 734 #define SQ_GSVS_RING_OFFSET_2 0x28930 735 #define SQ_GSVS_RING_OFFSET_3 0x28934 736 737 #define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140 738 #define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80 739 740 #define SQ_ALU_CONST_CACHE_PS_0 0x28940 741 #define SQ_ALU_CONST_CACHE_PS_1 0x28944 742 #define SQ_ALU_CONST_CACHE_PS_2 0x28948 743 #define SQ_ALU_CONST_CACHE_PS_3 0x2894c 744 #define SQ_ALU_CONST_CACHE_PS_4 0x28950 745 #define SQ_ALU_CONST_CACHE_PS_5 0x28954 746 #define SQ_ALU_CONST_CACHE_PS_6 0x28958 747 #define SQ_ALU_CONST_CACHE_PS_7 0x2895c 748 #define SQ_ALU_CONST_CACHE_PS_8 0x28960 749 #define SQ_ALU_CONST_CACHE_PS_9 0x28964 750 #define SQ_ALU_CONST_CACHE_PS_10 0x28968 751 #define SQ_ALU_CONST_CACHE_PS_11 0x2896c 752 #define SQ_ALU_CONST_CACHE_PS_12 0x28970 753 #define SQ_ALU_CONST_CACHE_PS_13 0x28974 754 #define SQ_ALU_CONST_CACHE_PS_14 0x28978 755 #define SQ_ALU_CONST_CACHE_PS_15 0x2897c 756 #define SQ_ALU_CONST_CACHE_VS_0 0x28980 757 #define SQ_ALU_CONST_CACHE_VS_1 0x28984 758 #define SQ_ALU_CONST_CACHE_VS_2 0x28988 759 #define SQ_ALU_CONST_CACHE_VS_3 0x2898c 760 #define SQ_ALU_CONST_CACHE_VS_4 0x28990 761 #define SQ_ALU_CONST_CACHE_VS_5 0x28994 762 #define SQ_ALU_CONST_CACHE_VS_6 0x28998 763 #define SQ_ALU_CONST_CACHE_VS_7 0x2899c 764 #define SQ_ALU_CONST_CACHE_VS_8 0x289a0 765 #define SQ_ALU_CONST_CACHE_VS_9 0x289a4 766 #define SQ_ALU_CONST_CACHE_VS_10 0x289a8 767 #define SQ_ALU_CONST_CACHE_VS_11 0x289ac 768 #define SQ_ALU_CONST_CACHE_VS_12 0x289b0 769 #define SQ_ALU_CONST_CACHE_VS_13 0x289b4 770 #define SQ_ALU_CONST_CACHE_VS_14 0x289b8 771 #define SQ_ALU_CONST_CACHE_VS_15 0x289bc 772 #define SQ_ALU_CONST_CACHE_GS_0 0x289c0 773 #define SQ_ALU_CONST_CACHE_GS_1 0x289c4 774 #define SQ_ALU_CONST_CACHE_GS_2 0x289c8 775 #define SQ_ALU_CONST_CACHE_GS_3 0x289cc 776 #define SQ_ALU_CONST_CACHE_GS_4 0x289d0 777 #define SQ_ALU_CONST_CACHE_GS_5 0x289d4 778 #define SQ_ALU_CONST_CACHE_GS_6 0x289d8 779 #define SQ_ALU_CONST_CACHE_GS_7 0x289dc 780 #define SQ_ALU_CONST_CACHE_GS_8 0x289e0 781 #define SQ_ALU_CONST_CACHE_GS_9 0x289e4 782 #define SQ_ALU_CONST_CACHE_GS_10 0x289e8 783 #define SQ_ALU_CONST_CACHE_GS_11 0x289ec 784 #define SQ_ALU_CONST_CACHE_GS_12 0x289f0 785 #define SQ_ALU_CONST_CACHE_GS_13 0x289f4 786 #define SQ_ALU_CONST_CACHE_GS_14 0x289f8 787 #define SQ_ALU_CONST_CACHE_GS_15 0x289fc 788 #define SQ_ALU_CONST_CACHE_HS_0 0x28f00 789 #define SQ_ALU_CONST_CACHE_HS_1 0x28f04 790 #define SQ_ALU_CONST_CACHE_HS_2 0x28f08 791 #define SQ_ALU_CONST_CACHE_HS_3 0x28f0c 792 #define SQ_ALU_CONST_CACHE_HS_4 0x28f10 793 #define SQ_ALU_CONST_CACHE_HS_5 0x28f14 794 #define SQ_ALU_CONST_CACHE_HS_6 0x28f18 795 #define SQ_ALU_CONST_CACHE_HS_7 0x28f1c 796 #define SQ_ALU_CONST_CACHE_HS_8 0x28f20 797 #define SQ_ALU_CONST_CACHE_HS_9 0x28f24 798 #define SQ_ALU_CONST_CACHE_HS_10 0x28f28 799 #define SQ_ALU_CONST_CACHE_HS_11 0x28f2c 800 #define SQ_ALU_CONST_CACHE_HS_12 0x28f30 801 #define SQ_ALU_CONST_CACHE_HS_13 0x28f34 802 #define SQ_ALU_CONST_CACHE_HS_14 0x28f38 803 #define SQ_ALU_CONST_CACHE_HS_15 0x28f3c 804 #define SQ_ALU_CONST_CACHE_LS_0 0x28f40 805 #define SQ_ALU_CONST_CACHE_LS_1 0x28f44 806 #define SQ_ALU_CONST_CACHE_LS_2 0x28f48 807 #define SQ_ALU_CONST_CACHE_LS_3 0x28f4c 808 #define SQ_ALU_CONST_CACHE_LS_4 0x28f50 809 #define SQ_ALU_CONST_CACHE_LS_5 0x28f54 810 #define SQ_ALU_CONST_CACHE_LS_6 0x28f58 811 #define SQ_ALU_CONST_CACHE_LS_7 0x28f5c 812 #define SQ_ALU_CONST_CACHE_LS_8 0x28f60 813 #define SQ_ALU_CONST_CACHE_LS_9 0x28f64 814 #define SQ_ALU_CONST_CACHE_LS_10 0x28f68 815 #define SQ_ALU_CONST_CACHE_LS_11 0x28f6c 816 #define SQ_ALU_CONST_CACHE_LS_12 0x28f70 817 #define SQ_ALU_CONST_CACHE_LS_13 0x28f74 818 #define SQ_ALU_CONST_CACHE_LS_14 0x28f78 819 #define SQ_ALU_CONST_CACHE_LS_15 0x28f7c 820 821 #define PA_SC_SCREEN_SCISSOR_TL 0x28030 822 #define PA_SC_GENERIC_SCISSOR_TL 0x28240 823 #define PA_SC_WINDOW_SCISSOR_TL 0x28204 824 #define VGT_PRIMITIVE_TYPE 0x8958 825 826 #define DB_DEPTH_CONTROL 0x28800 827 #define DB_DEPTH_VIEW 0x28008 828 #define DB_HTILE_DATA_BASE 0x28014 829 #define DB_Z_INFO 0x28040 830 # define Z_ARRAY_MODE(x) ((x) << 4) 831 #define DB_STENCIL_INFO 0x28044 832 #define DB_Z_READ_BASE 0x28048 833 #define DB_STENCIL_READ_BASE 0x2804c 834 #define DB_Z_WRITE_BASE 0x28050 835 #define DB_STENCIL_WRITE_BASE 0x28054 836 #define DB_DEPTH_SIZE 0x28058 837 838 #define SQ_PGM_START_PS 0x28840 839 #define SQ_PGM_START_VS 0x2885c 840 #define SQ_PGM_START_GS 0x28874 841 #define SQ_PGM_START_ES 0x2888c 842 #define SQ_PGM_START_FS 0x288a4 843 #define SQ_PGM_START_HS 0x288b8 844 #define SQ_PGM_START_LS 0x288d0 845 846 #define VGT_STRMOUT_CONFIG 0x28b94 847 #define VGT_STRMOUT_BUFFER_CONFIG 0x28b98 848 849 #define CB_TARGET_MASK 0x28238 850 #define CB_SHADER_MASK 0x2823c 851 852 #define GDS_ADDR_BASE 0x28720 853 854 #define CB_IMMED0_BASE 0x28b9c 855 #define CB_IMMED1_BASE 0x28ba0 856 #define CB_IMMED2_BASE 0x28ba4 857 #define CB_IMMED3_BASE 0x28ba8 858 #define CB_IMMED4_BASE 0x28bac 859 #define CB_IMMED5_BASE 0x28bb0 860 #define CB_IMMED6_BASE 0x28bb4 861 #define CB_IMMED7_BASE 0x28bb8 862 #define CB_IMMED8_BASE 0x28bbc 863 #define CB_IMMED9_BASE 0x28bc0 864 #define CB_IMMED10_BASE 0x28bc4 865 #define CB_IMMED11_BASE 0x28bc8 866 867 /* all 12 CB blocks have these regs */ 868 #define CB_COLOR0_BASE 0x28c60 869 #define CB_COLOR0_PITCH 0x28c64 870 #define CB_COLOR0_SLICE 0x28c68 871 #define CB_COLOR0_VIEW 0x28c6c 872 #define CB_COLOR0_INFO 0x28c70 873 # define CB_ARRAY_MODE(x) ((x) << 8) 874 # define ARRAY_LINEAR_GENERAL 0 875 # define ARRAY_LINEAR_ALIGNED 1 876 # define ARRAY_1D_TILED_THIN1 2 877 # define ARRAY_2D_TILED_THIN1 4 878 #define CB_COLOR0_ATTRIB 0x28c74 879 #define CB_COLOR0_DIM 0x28c78 880 /* only CB0-7 blocks have these regs */ 881 #define CB_COLOR0_CMASK 0x28c7c 882 #define CB_COLOR0_CMASK_SLICE 0x28c80 883 #define CB_COLOR0_FMASK 0x28c84 884 #define CB_COLOR0_FMASK_SLICE 0x28c88 885 #define CB_COLOR0_CLEAR_WORD0 0x28c8c 886 #define CB_COLOR0_CLEAR_WORD1 0x28c90 887 #define CB_COLOR0_CLEAR_WORD2 0x28c94 888 #define CB_COLOR0_CLEAR_WORD3 0x28c98 889 890 #define CB_COLOR1_BASE 0x28c9c 891 #define CB_COLOR2_BASE 0x28cd8 892 #define CB_COLOR3_BASE 0x28d14 893 #define CB_COLOR4_BASE 0x28d50 894 #define CB_COLOR5_BASE 0x28d8c 895 #define CB_COLOR6_BASE 0x28dc8 896 #define CB_COLOR7_BASE 0x28e04 897 #define CB_COLOR8_BASE 0x28e40 898 #define CB_COLOR9_BASE 0x28e5c 899 #define CB_COLOR10_BASE 0x28e78 900 #define CB_COLOR11_BASE 0x28e94 901 902 #define CB_COLOR1_PITCH 0x28ca0 903 #define CB_COLOR2_PITCH 0x28cdc 904 #define CB_COLOR3_PITCH 0x28d18 905 #define CB_COLOR4_PITCH 0x28d54 906 #define CB_COLOR5_PITCH 0x28d90 907 #define CB_COLOR6_PITCH 0x28dcc 908 #define CB_COLOR7_PITCH 0x28e08 909 #define CB_COLOR8_PITCH 0x28e44 910 #define CB_COLOR9_PITCH 0x28e60 911 #define CB_COLOR10_PITCH 0x28e7c 912 #define CB_COLOR11_PITCH 0x28e98 913 914 #define CB_COLOR1_SLICE 0x28ca4 915 #define CB_COLOR2_SLICE 0x28ce0 916 #define CB_COLOR3_SLICE 0x28d1c 917 #define CB_COLOR4_SLICE 0x28d58 918 #define CB_COLOR5_SLICE 0x28d94 919 #define CB_COLOR6_SLICE 0x28dd0 920 #define CB_COLOR7_SLICE 0x28e0c 921 #define CB_COLOR8_SLICE 0x28e48 922 #define CB_COLOR9_SLICE 0x28e64 923 #define CB_COLOR10_SLICE 0x28e80 924 #define CB_COLOR11_SLICE 0x28e9c 925 926 #define CB_COLOR1_VIEW 0x28ca8 927 #define CB_COLOR2_VIEW 0x28ce4 928 #define CB_COLOR3_VIEW 0x28d20 929 #define CB_COLOR4_VIEW 0x28d5c 930 #define CB_COLOR5_VIEW 0x28d98 931 #define CB_COLOR6_VIEW 0x28dd4 932 #define CB_COLOR7_VIEW 0x28e10 933 #define CB_COLOR8_VIEW 0x28e4c 934 #define CB_COLOR9_VIEW 0x28e68 935 #define CB_COLOR10_VIEW 0x28e84 936 #define CB_COLOR11_VIEW 0x28ea0 937 938 #define CB_COLOR1_INFO 0x28cac 939 #define CB_COLOR2_INFO 0x28ce8 940 #define CB_COLOR3_INFO 0x28d24 941 #define CB_COLOR4_INFO 0x28d60 942 #define CB_COLOR5_INFO 0x28d9c 943 #define CB_COLOR6_INFO 0x28dd8 944 #define CB_COLOR7_INFO 0x28e14 945 #define CB_COLOR8_INFO 0x28e50 946 #define CB_COLOR9_INFO 0x28e6c 947 #define CB_COLOR10_INFO 0x28e88 948 #define CB_COLOR11_INFO 0x28ea4 949 950 #define CB_COLOR1_ATTRIB 0x28cb0 951 #define CB_COLOR2_ATTRIB 0x28cec 952 #define CB_COLOR3_ATTRIB 0x28d28 953 #define CB_COLOR4_ATTRIB 0x28d64 954 #define CB_COLOR5_ATTRIB 0x28da0 955 #define CB_COLOR6_ATTRIB 0x28ddc 956 #define CB_COLOR7_ATTRIB 0x28e18 957 #define CB_COLOR8_ATTRIB 0x28e54 958 #define CB_COLOR9_ATTRIB 0x28e70 959 #define CB_COLOR10_ATTRIB 0x28e8c 960 #define CB_COLOR11_ATTRIB 0x28ea8 961 962 #define CB_COLOR1_DIM 0x28cb4 963 #define CB_COLOR2_DIM 0x28cf0 964 #define CB_COLOR3_DIM 0x28d2c 965 #define CB_COLOR4_DIM 0x28d68 966 #define CB_COLOR5_DIM 0x28da4 967 #define CB_COLOR6_DIM 0x28de0 968 #define CB_COLOR7_DIM 0x28e1c 969 #define CB_COLOR8_DIM 0x28e58 970 #define CB_COLOR9_DIM 0x28e74 971 #define CB_COLOR10_DIM 0x28e90 972 #define CB_COLOR11_DIM 0x28eac 973 974 #define CB_COLOR1_CMASK 0x28cb8 975 #define CB_COLOR2_CMASK 0x28cf4 976 #define CB_COLOR3_CMASK 0x28d30 977 #define CB_COLOR4_CMASK 0x28d6c 978 #define CB_COLOR5_CMASK 0x28da8 979 #define CB_COLOR6_CMASK 0x28de4 980 #define CB_COLOR7_CMASK 0x28e20 981 982 #define CB_COLOR1_CMASK_SLICE 0x28cbc 983 #define CB_COLOR2_CMASK_SLICE 0x28cf8 984 #define CB_COLOR3_CMASK_SLICE 0x28d34 985 #define CB_COLOR4_CMASK_SLICE 0x28d70 986 #define CB_COLOR5_CMASK_SLICE 0x28dac 987 #define CB_COLOR6_CMASK_SLICE 0x28de8 988 #define CB_COLOR7_CMASK_SLICE 0x28e24 989 990 #define CB_COLOR1_FMASK 0x28cc0 991 #define CB_COLOR2_FMASK 0x28cfc 992 #define CB_COLOR3_FMASK 0x28d38 993 #define CB_COLOR4_FMASK 0x28d74 994 #define CB_COLOR5_FMASK 0x28db0 995 #define CB_COLOR6_FMASK 0x28dec 996 #define CB_COLOR7_FMASK 0x28e28 997 998 #define CB_COLOR1_FMASK_SLICE 0x28cc4 999 #define CB_COLOR2_FMASK_SLICE 0x28d00 1000 #define CB_COLOR3_FMASK_SLICE 0x28d3c 1001 #define CB_COLOR4_FMASK_SLICE 0x28d78 1002 #define CB_COLOR5_FMASK_SLICE 0x28db4 1003 #define CB_COLOR6_FMASK_SLICE 0x28df0 1004 #define CB_COLOR7_FMASK_SLICE 0x28e2c 1005 1006 #define CB_COLOR1_CLEAR_WORD0 0x28cc8 1007 #define CB_COLOR2_CLEAR_WORD0 0x28d04 1008 #define CB_COLOR3_CLEAR_WORD0 0x28d40 1009 #define CB_COLOR4_CLEAR_WORD0 0x28d7c 1010 #define CB_COLOR5_CLEAR_WORD0 0x28db8 1011 #define CB_COLOR6_CLEAR_WORD0 0x28df4 1012 #define CB_COLOR7_CLEAR_WORD0 0x28e30 1013 1014 #define CB_COLOR1_CLEAR_WORD1 0x28ccc 1015 #define CB_COLOR2_CLEAR_WORD1 0x28d08 1016 #define CB_COLOR3_CLEAR_WORD1 0x28d44 1017 #define CB_COLOR4_CLEAR_WORD1 0x28d80 1018 #define CB_COLOR5_CLEAR_WORD1 0x28dbc 1019 #define CB_COLOR6_CLEAR_WORD1 0x28df8 1020 #define CB_COLOR7_CLEAR_WORD1 0x28e34 1021 1022 #define CB_COLOR1_CLEAR_WORD2 0x28cd0 1023 #define CB_COLOR2_CLEAR_WORD2 0x28d0c 1024 #define CB_COLOR3_CLEAR_WORD2 0x28d48 1025 #define CB_COLOR4_CLEAR_WORD2 0x28d84 1026 #define CB_COLOR5_CLEAR_WORD2 0x28dc0 1027 #define CB_COLOR6_CLEAR_WORD2 0x28dfc 1028 #define CB_COLOR7_CLEAR_WORD2 0x28e38 1029 1030 #define CB_COLOR1_CLEAR_WORD3 0x28cd4 1031 #define CB_COLOR2_CLEAR_WORD3 0x28d10 1032 #define CB_COLOR3_CLEAR_WORD3 0x28d4c 1033 #define CB_COLOR4_CLEAR_WORD3 0x28d88 1034 #define CB_COLOR5_CLEAR_WORD3 0x28dc4 1035 #define CB_COLOR6_CLEAR_WORD3 0x28e00 1036 #define CB_COLOR7_CLEAR_WORD3 0x28e3c 1037 1038 #define SQ_TEX_RESOURCE_WORD0_0 0x30000 1039 #define SQ_TEX_RESOURCE_WORD1_0 0x30004 1040 # define TEX_ARRAY_MODE(x) ((x) << 28) 1041 #define SQ_TEX_RESOURCE_WORD2_0 0x30008 1042 #define SQ_TEX_RESOURCE_WORD3_0 0x3000C 1043 #define SQ_TEX_RESOURCE_WORD4_0 0x30010 1044 #define SQ_TEX_RESOURCE_WORD5_0 0x30014 1045 #define SQ_TEX_RESOURCE_WORD6_0 0x30018 1046 #define SQ_TEX_RESOURCE_WORD7_0 0x3001c 1047 1048 1049 #endif 1050