1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Christian König.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Christian König
25  *          Rafał Miłecki
26  */
27 #include <linux/hdmi.h>
28 #include <drm/drmP.h>
29 #include <drm/radeon_drm.h>
30 #include "radeon.h"
31 #include "radeon_asic.h"
32 #include "evergreend.h"
33 #include "atom.h"
34 
35 extern void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder);
36 extern void dce6_afmt_write_sad_regs(struct drm_encoder *encoder);
37 extern void dce6_afmt_select_pin(struct drm_encoder *encoder);
38 extern void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
39 					   struct drm_display_mode *mode);
40 
41 /*
42  * update the N and CTS parameters for a given pixel clock rate
43  */
44 static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
45 {
46 	struct drm_device *dev = encoder->dev;
47 	struct radeon_device *rdev = dev->dev_private;
48 	struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
49 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
50 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
51 	uint32_t offset = dig->afmt->offset;
52 
53 	WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz));
54 	WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz);
55 
56 	WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz));
57 	WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz);
58 
59 	WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz));
60 	WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
61 }
62 
63 static void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
64 					   struct drm_display_mode *mode)
65 {
66 	struct radeon_device *rdev = encoder->dev->dev_private;
67 	struct drm_connector *connector;
68 	struct radeon_connector *radeon_connector = NULL;
69 	u32 tmp = 0;
70 
71 	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
72 		if (connector->encoder == encoder) {
73 			radeon_connector = to_radeon_connector(connector);
74 			break;
75 		}
76 	}
77 
78 	if (!radeon_connector) {
79 		DRM_ERROR("Couldn't find encoder's connector\n");
80 		return;
81 	}
82 
83 	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
84 		if (connector->latency_present[1])
85 			tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
86 				AUDIO_LIPSYNC(connector->audio_latency[1]);
87 		else
88 			tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
89 	} else {
90 		if (connector->latency_present[0])
91 			tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
92 				AUDIO_LIPSYNC(connector->audio_latency[0]);
93 		else
94 			tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
95 	}
96 	WREG32(AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
97 }
98 
99 static void dce4_afmt_write_speaker_allocation(struct drm_encoder *encoder)
100 {
101 	struct radeon_device *rdev = encoder->dev->dev_private;
102 	struct drm_connector *connector;
103 	struct radeon_connector *radeon_connector = NULL;
104 	u32 tmp;
105 	u8 *sadb;
106 	int sad_count;
107 
108 	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
109 		if (connector->encoder == encoder) {
110 			radeon_connector = to_radeon_connector(connector);
111 			break;
112 		}
113 	}
114 
115 	if (!radeon_connector) {
116 		DRM_ERROR("Couldn't find encoder's connector\n");
117 		return;
118 	}
119 
120 	sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb);
121 	if (sad_count <= 0) {
122 		DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
123 		return;
124 	}
125 
126 	/* program the speaker allocation */
127 	tmp = RREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
128 	tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
129 	/* set HDMI mode */
130 	tmp |= HDMI_CONNECTION;
131 	if (sad_count)
132 		tmp |= SPEAKER_ALLOCATION(sadb[0]);
133 	else
134 		tmp |= SPEAKER_ALLOCATION(5); /* stereo */
135 	WREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
136 
137 	kfree(sadb);
138 }
139 
140 static void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder)
141 {
142 	struct radeon_device *rdev = encoder->dev->dev_private;
143 	struct drm_connector *connector;
144 	struct radeon_connector *radeon_connector = NULL;
145 	struct cea_sad *sads;
146 	int i, sad_count;
147 
148 	static const u16 eld_reg_to_type[][2] = {
149 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
150 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
151 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
152 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
153 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
154 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
155 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
156 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
157 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
158 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
159 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
160 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
161 	};
162 
163 	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
164 		if (connector->encoder == encoder) {
165 			radeon_connector = to_radeon_connector(connector);
166 			break;
167 		}
168 	}
169 
170 	if (!radeon_connector) {
171 		DRM_ERROR("Couldn't find encoder's connector\n");
172 		return;
173 	}
174 
175 	sad_count = drm_edid_to_sad(radeon_connector->edid, &sads);
176 	if (sad_count <= 0) {
177 		DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
178 		return;
179 	}
180 	BUG_ON(!sads);
181 
182 	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
183 		u32 value = 0;
184 		u8 stereo_freqs = 0;
185 		int max_channels = -1;
186 		int j;
187 
188 		for (j = 0; j < sad_count; j++) {
189 			struct cea_sad *sad = &sads[j];
190 
191 			if (sad->format == eld_reg_to_type[i][1]) {
192 				if (sad->channels > max_channels) {
193 					value = MAX_CHANNELS(sad->channels) |
194 						DESCRIPTOR_BYTE_2(sad->byte2) |
195 						SUPPORTED_FREQUENCIES(sad->freq);
196 					max_channels = sad->channels;
197 				}
198 
199 				if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
200 					stereo_freqs |= sad->freq;
201 				else
202 					break;
203 			}
204 		}
205 
206 		value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
207 
208 		WREG32(eld_reg_to_type[i][0], value);
209 	}
210 
211 	kfree(sads);
212 }
213 
214 /*
215  * build a HDMI Video Info Frame
216  */
217 static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
218 						void *buffer, size_t size)
219 {
220 	struct drm_device *dev = encoder->dev;
221 	struct radeon_device *rdev = dev->dev_private;
222 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
223 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
224 	uint32_t offset = dig->afmt->offset;
225 	uint8_t *frame = buffer + 3;
226 	uint8_t *header = buffer;
227 
228 	WREG32(AFMT_AVI_INFO0 + offset,
229 		frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
230 	WREG32(AFMT_AVI_INFO1 + offset,
231 		frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
232 	WREG32(AFMT_AVI_INFO2 + offset,
233 		frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
234 	WREG32(AFMT_AVI_INFO3 + offset,
235 		frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
236 }
237 
238 static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock)
239 {
240 	struct drm_device *dev = encoder->dev;
241 	struct radeon_device *rdev = dev->dev_private;
242 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
243 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
244 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
245 	u32 base_rate = 24000;
246 	u32 max_ratio = clock / base_rate;
247 	u32 dto_phase;
248 	u32 dto_modulo = clock;
249 	u32 wallclock_ratio;
250 	u32 dto_cntl;
251 
252 	if (!dig || !dig->afmt)
253 		return;
254 
255 	if (ASIC_IS_DCE6(rdev)) {
256 		dto_phase = 24 * 1000;
257 	} else {
258 		if (max_ratio >= 8) {
259 			dto_phase = 192 * 1000;
260 			wallclock_ratio = 3;
261 		} else if (max_ratio >= 4) {
262 			dto_phase = 96 * 1000;
263 			wallclock_ratio = 2;
264 		} else if (max_ratio >= 2) {
265 			dto_phase = 48 * 1000;
266 			wallclock_ratio = 1;
267 		} else {
268 			dto_phase = 24 * 1000;
269 			wallclock_ratio = 0;
270 		}
271 		dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
272 		dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
273 		WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);
274 	}
275 
276 	/* XXX two dtos; generally use dto0 for hdmi */
277 	/* Express [24MHz / target pixel clock] as an exact rational
278 	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
279 	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
280 	 */
281 	WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id));
282 	WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
283 	WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo);
284 }
285 
286 
287 /*
288  * update the info frames with the data from the current display mode
289  */
290 void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
291 {
292 	struct drm_device *dev = encoder->dev;
293 	struct radeon_device *rdev = dev->dev_private;
294 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
295 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
296 	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
297 	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
298 	struct hdmi_avi_infoframe frame;
299 	uint32_t offset;
300 	ssize_t err;
301 	uint32_t val;
302 	int bpc = 8;
303 
304 	if (!dig || !dig->afmt)
305 		return;
306 
307 	/* Silent, r600_hdmi_enable will raise WARN for us */
308 	if (!dig->afmt->enabled)
309 		return;
310 	offset = dig->afmt->offset;
311 
312 	/* hdmi deep color mode general control packets setup, if bpc > 8 */
313 	if (encoder->crtc) {
314 		struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
315 		bpc = radeon_crtc->bpc;
316 	}
317 
318 	/* disable audio prior to setting up hw */
319 	if (ASIC_IS_DCE6(rdev)) {
320 		dig->afmt->pin = dce6_audio_get_pin(rdev);
321 		dce6_audio_enable(rdev, dig->afmt->pin, false);
322 	} else {
323 		dig->afmt->pin = r600_audio_get_pin(rdev);
324 		r600_audio_enable(rdev, dig->afmt->pin, false);
325 	}
326 
327 	evergreen_audio_set_dto(encoder, mode->clock);
328 
329 	WREG32(HDMI_VBI_PACKET_CONTROL + offset,
330 	       HDMI_NULL_SEND); /* send null packets when required */
331 
332 	WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
333 
334 	val = RREG32(HDMI_CONTROL + offset);
335 	val &= ~HDMI_DEEP_COLOR_ENABLE;
336 	val &= ~HDMI_DEEP_COLOR_DEPTH_MASK;
337 
338 	switch (bpc) {
339 		case 0:
340 		case 6:
341 		case 8:
342 		case 16:
343 		default:
344 			DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
345 					 connector->name, bpc);
346 			break;
347 		case 10:
348 			val |= HDMI_DEEP_COLOR_ENABLE;
349 			val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR);
350 			DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
351 					 connector->name);
352 			break;
353 		case 12:
354 			val |= HDMI_DEEP_COLOR_ENABLE;
355 			val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR);
356 			DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
357 					 connector->name);
358 			break;
359 	}
360 
361 	WREG32(HDMI_CONTROL + offset, val);
362 
363 	WREG32(HDMI_VBI_PACKET_CONTROL + offset,
364 	       HDMI_NULL_SEND | /* send null packets when required */
365 	       HDMI_GC_SEND | /* send general control packets */
366 	       HDMI_GC_CONT); /* send general control packets every frame */
367 
368 	WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
369 	       HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
370 	       HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
371 
372 	WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
373 	       AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
374 
375 	WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
376 	       HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
377 
378 	WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
379 
380 	WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
381 	       HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
382 	       HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
383 
384 	WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
385 	       AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
386 
387 	/* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
388 
389 	if (bpc > 8)
390 		WREG32(HDMI_ACR_PACKET_CONTROL + offset,
391 		       HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
392 	else
393 		WREG32(HDMI_ACR_PACKET_CONTROL + offset,
394 		       HDMI_ACR_SOURCE | /* select SW CTS value */
395 		       HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
396 
397 	evergreen_hdmi_update_ACR(encoder, mode->clock);
398 
399 	WREG32(AFMT_60958_0 + offset,
400 	       AFMT_60958_CS_CHANNEL_NUMBER_L(1));
401 
402 	WREG32(AFMT_60958_1 + offset,
403 	       AFMT_60958_CS_CHANNEL_NUMBER_R(2));
404 
405 	WREG32(AFMT_60958_2 + offset,
406 	       AFMT_60958_CS_CHANNEL_NUMBER_2(3) |
407 	       AFMT_60958_CS_CHANNEL_NUMBER_3(4) |
408 	       AFMT_60958_CS_CHANNEL_NUMBER_4(5) |
409 	       AFMT_60958_CS_CHANNEL_NUMBER_5(6) |
410 	       AFMT_60958_CS_CHANNEL_NUMBER_6(7) |
411 	       AFMT_60958_CS_CHANNEL_NUMBER_7(8));
412 
413 	if (ASIC_IS_DCE6(rdev)) {
414 		dce6_afmt_write_speaker_allocation(encoder);
415 	} else {
416 		dce4_afmt_write_speaker_allocation(encoder);
417 	}
418 
419 	WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
420 	       AFMT_AUDIO_CHANNEL_ENABLE(0xff));
421 
422 	/* fglrx sets 0x40 in 0x5f80 here */
423 
424 	if (ASIC_IS_DCE6(rdev)) {
425 		dce6_afmt_select_pin(encoder);
426 		dce6_afmt_write_sad_regs(encoder);
427 		dce6_afmt_write_latency_fields(encoder, mode);
428 	} else {
429 		evergreen_hdmi_write_sad_regs(encoder);
430 		dce4_afmt_write_latency_fields(encoder, mode);
431 	}
432 
433 	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
434 	if (err < 0) {
435 		DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
436 		return;
437 	}
438 
439 	err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
440 	if (err < 0) {
441 		DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
442 		return;
443 	}
444 
445 	evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
446 
447 	WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset,
448 		  HDMI_AVI_INFO_SEND | /* enable AVI info frames */
449 		  HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */
450 
451 	WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
452 		 HDMI_AVI_INFO_LINE(2), /* anything other than 0 */
453 		 ~HDMI_AVI_INFO_LINE_MASK);
454 
455 	WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
456 		  AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */
457 
458 	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
459 	WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
460 	WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
461 	WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
462 	WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);
463 
464 	/* enable audio after to setting up hw */
465 	if (ASIC_IS_DCE6(rdev))
466 		dce6_audio_enable(rdev, dig->afmt->pin, true);
467 	else
468 		r600_audio_enable(rdev, dig->afmt->pin, true);
469 }
470 
471 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
472 {
473 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
474 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
475 
476 	if (!dig || !dig->afmt)
477 		return;
478 
479 	/* Silent, r600_hdmi_enable will raise WARN for us */
480 	if (enable && dig->afmt->enabled)
481 		return;
482 	if (!enable && !dig->afmt->enabled)
483 		return;
484 
485 	dig->afmt->enabled = enable;
486 
487 	DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
488 		  enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
489 }
490