1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Christian König.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Christian König
25  *          Rafał Miłecki
26  */
27 #include <linux/hdmi.h>
28 
29 #include <drm/radeon_drm.h>
30 #include "radeon.h"
31 #include "radeon_asic.h"
32 #include "radeon_audio.h"
33 #include "evergreend.h"
34 #include "atom.h"
35 
36 /* enable the audio stream */
37 void dce4_audio_enable(struct radeon_device *rdev,
38 			      struct r600_audio_pin *pin,
39 			      u8 enable_mask)
40 {
41 	u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
42 
43 	if (!pin)
44 		return;
45 
46 	if (enable_mask) {
47 		tmp |= AUDIO_ENABLED;
48 		if (enable_mask & 1)
49 			tmp |= PIN0_AUDIO_ENABLED;
50 		if (enable_mask & 2)
51 			tmp |= PIN1_AUDIO_ENABLED;
52 		if (enable_mask & 4)
53 			tmp |= PIN2_AUDIO_ENABLED;
54 		if (enable_mask & 8)
55 			tmp |= PIN3_AUDIO_ENABLED;
56 	} else {
57 		tmp &= ~(AUDIO_ENABLED |
58 			 PIN0_AUDIO_ENABLED |
59 			 PIN1_AUDIO_ENABLED |
60 			 PIN2_AUDIO_ENABLED |
61 			 PIN3_AUDIO_ENABLED);
62 	}
63 
64 	WREG32(AZ_HOT_PLUG_CONTROL, tmp);
65 }
66 
67 void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset,
68 	const struct radeon_hdmi_acr *acr)
69 {
70 	struct drm_device *dev = encoder->dev;
71 	struct radeon_device *rdev = dev->dev_private;
72 	int bpc = 8;
73 
74 	if (encoder->crtc) {
75 		struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
76 		bpc = radeon_crtc->bpc;
77 	}
78 
79 	if (bpc > 8)
80 		WREG32(HDMI_ACR_PACKET_CONTROL + offset,
81 			HDMI_ACR_AUTO_SEND);	/* allow hw to sent ACR packets when required */
82 	else
83 		WREG32(HDMI_ACR_PACKET_CONTROL + offset,
84 			HDMI_ACR_SOURCE |		/* select SW CTS value */
85 			HDMI_ACR_AUTO_SEND);	/* allow hw to sent ACR packets when required */
86 
87 	WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz));
88 	WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz);
89 
90 	WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz));
91 	WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz);
92 
93 	WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz));
94 	WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz);
95 }
96 
97 void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
98 		struct drm_connector *connector, struct drm_display_mode *mode)
99 {
100 	struct radeon_device *rdev = encoder->dev->dev_private;
101 	u32 tmp = 0;
102 
103 	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
104 		if (connector->latency_present[1])
105 			tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
106 				AUDIO_LIPSYNC(connector->audio_latency[1]);
107 		else
108 			tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
109 	} else {
110 		if (connector->latency_present[0])
111 			tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
112 				AUDIO_LIPSYNC(connector->audio_latency[0]);
113 		else
114 			tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
115 	}
116 	WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
117 }
118 
119 void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
120 	u8 *sadb, int sad_count)
121 {
122 	struct radeon_device *rdev = encoder->dev->dev_private;
123 	u32 tmp;
124 
125 	/* program the speaker allocation */
126 	tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
127 	tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
128 	/* set HDMI mode */
129 	tmp |= HDMI_CONNECTION;
130 	if (sad_count)
131 		tmp |= SPEAKER_ALLOCATION(sadb[0]);
132 	else
133 		tmp |= SPEAKER_ALLOCATION(5); /* stereo */
134 	WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
135 }
136 
137 void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
138 	u8 *sadb, int sad_count)
139 {
140 	struct radeon_device *rdev = encoder->dev->dev_private;
141 	u32 tmp;
142 
143 	/* program the speaker allocation */
144 	tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
145 	tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
146 	/* set DP mode */
147 	tmp |= DP_CONNECTION;
148 	if (sad_count)
149 		tmp |= SPEAKER_ALLOCATION(sadb[0]);
150 	else
151 		tmp |= SPEAKER_ALLOCATION(5); /* stereo */
152 	WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
153 }
154 
155 void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder,
156 	struct cea_sad *sads, int sad_count)
157 {
158 	int i;
159 	struct radeon_device *rdev = encoder->dev->dev_private;
160 	static const u16 eld_reg_to_type[][2] = {
161 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
162 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
163 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
164 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
165 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
166 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
167 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
168 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
169 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
170 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
171 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
172 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
173 	};
174 
175 	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
176 		u32 value = 0;
177 		u8 stereo_freqs = 0;
178 		int max_channels = -1;
179 		int j;
180 
181 		for (j = 0; j < sad_count; j++) {
182 			struct cea_sad *sad = &sads[j];
183 
184 			if (sad->format == eld_reg_to_type[i][1]) {
185 				if (sad->channels > max_channels) {
186 					value = MAX_CHANNELS(sad->channels) |
187 						DESCRIPTOR_BYTE_2(sad->byte2) |
188 						SUPPORTED_FREQUENCIES(sad->freq);
189 					max_channels = sad->channels;
190 				}
191 
192 				if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
193 					stereo_freqs |= sad->freq;
194 				else
195 					break;
196 			}
197 		}
198 
199 		value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
200 
201 		WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value);
202 	}
203 }
204 
205 /*
206  * build a AVI Info Frame
207  */
208 void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset,
209 			      unsigned char *buffer, size_t size)
210 {
211 	uint8_t *frame = buffer + 3;
212 
213 	WREG32(AFMT_AVI_INFO0 + offset,
214 		frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
215 	WREG32(AFMT_AVI_INFO1 + offset,
216 		frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
217 	WREG32(AFMT_AVI_INFO2 + offset,
218 		frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
219 	WREG32(AFMT_AVI_INFO3 + offset,
220 		frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24));
221 
222 	WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
223 		 HDMI_AVI_INFO_LINE(2),	/* anything other than 0 */
224 		 ~HDMI_AVI_INFO_LINE_MASK);
225 }
226 
227 void dce4_hdmi_audio_set_dto(struct radeon_device *rdev,
228 	struct radeon_crtc *crtc, unsigned int clock)
229 {
230 	unsigned int max_ratio = clock / 24000;
231 	u32 dto_phase;
232 	u32 wallclock_ratio;
233 	u32 value;
234 
235 	if (max_ratio >= 8) {
236 		dto_phase = 192 * 1000;
237 		wallclock_ratio = 3;
238 	} else if (max_ratio >= 4) {
239 		dto_phase = 96 * 1000;
240 		wallclock_ratio = 2;
241 	} else if (max_ratio >= 2) {
242 		dto_phase = 48 * 1000;
243 		wallclock_ratio = 1;
244 	} else {
245 		dto_phase = 24 * 1000;
246 		wallclock_ratio = 0;
247 	}
248 
249 	value = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
250 	value |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
251 	value &= ~DCCG_AUDIO_DTO1_USE_512FBR_DTO;
252 	WREG32(DCCG_AUDIO_DTO0_CNTL, value);
253 
254 	/* Two dtos; generally use dto0 for HDMI */
255 	value = 0;
256 
257 	if (crtc)
258 		value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
259 
260 	WREG32(DCCG_AUDIO_DTO_SOURCE, value);
261 
262 	/* Express [24MHz / target pixel clock] as an exact rational
263 	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
264 	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
265 	 */
266 	WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
267 	WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
268 }
269 
270 void dce4_dp_audio_set_dto(struct radeon_device *rdev,
271 			   struct radeon_crtc *crtc, unsigned int clock)
272 {
273 	u32 value;
274 
275 	value = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
276 	value |= DCCG_AUDIO_DTO1_USE_512FBR_DTO;
277 	WREG32(DCCG_AUDIO_DTO1_CNTL, value);
278 
279 	/* Two dtos; generally use dto1 for DP */
280 	value = 0;
281 	value |= DCCG_AUDIO_DTO_SEL;
282 
283 	if (crtc)
284 		value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
285 
286 	WREG32(DCCG_AUDIO_DTO_SOURCE, value);
287 
288 	/* Express [24MHz / target pixel clock] as an exact rational
289 	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
290 	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
291 	 */
292 	if (ASIC_IS_DCE41(rdev)) {
293 		unsigned int div = (RREG32(DCE41_DENTIST_DISPCLK_CNTL) &
294 			DENTIST_DPREFCLK_WDIVIDER_MASK) >>
295 			DENTIST_DPREFCLK_WDIVIDER_SHIFT;
296 		div = radeon_audio_decode_dfs_div(div);
297 
298 		if (div)
299 			clock = 100 * clock / div;
300 	}
301 
302 	WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
303 	WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
304 }
305 
306 void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset)
307 {
308 	struct drm_device *dev = encoder->dev;
309 	struct radeon_device *rdev = dev->dev_private;
310 
311 	WREG32(HDMI_VBI_PACKET_CONTROL + offset,
312 		HDMI_NULL_SEND |	/* send null packets when required */
313 		HDMI_GC_SEND |		/* send general control packets */
314 		HDMI_GC_CONT);		/* send general control packets every frame */
315 }
316 
317 void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, u32 offset, int bpc)
318 {
319 	struct drm_device *dev = encoder->dev;
320 	struct radeon_device *rdev = dev->dev_private;
321 	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
322 	uint32_t val;
323 
324 	val = RREG32(HDMI_CONTROL + offset);
325 	val &= ~HDMI_DEEP_COLOR_ENABLE;
326 	val &= ~HDMI_DEEP_COLOR_DEPTH_MASK;
327 
328 	switch (bpc) {
329 		case 0:
330 		case 6:
331 		case 8:
332 		case 16:
333 		default:
334 			DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
335 					 connector->name, bpc);
336 			break;
337 		case 10:
338 			val |= HDMI_DEEP_COLOR_ENABLE;
339 			val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR);
340 			DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
341 					 connector->name);
342 			break;
343 		case 12:
344 			val |= HDMI_DEEP_COLOR_ENABLE;
345 			val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR);
346 			DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
347 					 connector->name);
348 			break;
349 	}
350 
351 	WREG32(HDMI_CONTROL + offset, val);
352 }
353 
354 void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset)
355 {
356 	struct drm_device *dev = encoder->dev;
357 	struct radeon_device *rdev = dev->dev_private;
358 
359 	WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
360 		AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
361 
362 	WREG32(AFMT_60958_0 + offset,
363 		AFMT_60958_CS_CHANNEL_NUMBER_L(1));
364 
365 	WREG32(AFMT_60958_1 + offset,
366 		AFMT_60958_CS_CHANNEL_NUMBER_R(2));
367 
368 	WREG32(AFMT_60958_2 + offset,
369 		AFMT_60958_CS_CHANNEL_NUMBER_2(3) |
370 		AFMT_60958_CS_CHANNEL_NUMBER_3(4) |
371 		AFMT_60958_CS_CHANNEL_NUMBER_4(5) |
372 		AFMT_60958_CS_CHANNEL_NUMBER_5(6) |
373 		AFMT_60958_CS_CHANNEL_NUMBER_6(7) |
374 		AFMT_60958_CS_CHANNEL_NUMBER_7(8));
375 
376 	WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
377 		AFMT_AUDIO_CHANNEL_ENABLE(0xff));
378 
379 	WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
380 	       HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
381 	       HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
382 
383 	/* allow 60958 channel status and send audio packets fields to be updated */
384 	WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
385 		  AFMT_RESET_FIFO_WHEN_AUDIO_DIS | AFMT_60958_CS_UPDATE);
386 }
387 
388 
389 void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)
390 {
391 	struct drm_device *dev = encoder->dev;
392 	struct radeon_device *rdev = dev->dev_private;
393 
394 	if (mute)
395 		WREG32_OR(HDMI_GC + offset, HDMI_GC_AVMUTE);
396 	else
397 		WREG32_AND(HDMI_GC + offset, ~HDMI_GC_AVMUTE);
398 }
399 
400 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
401 {
402 	struct drm_device *dev = encoder->dev;
403 	struct radeon_device *rdev = dev->dev_private;
404 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
405 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
406 
407 	if (!dig || !dig->afmt)
408 		return;
409 
410 	if (enable) {
411 		struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
412 
413 		if (connector && drm_detect_monitor_audio(radeon_connector_edid(connector))) {
414 			WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,
415 			       HDMI_AVI_INFO_SEND | /* enable AVI info frames */
416 			       HDMI_AVI_INFO_CONT | /* required for audio info values to be updated */
417 			       HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
418 			       HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
419 			WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
420 				  AFMT_AUDIO_SAMPLE_SEND);
421 		} else {
422 			WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,
423 			       HDMI_AVI_INFO_SEND | /* enable AVI info frames */
424 			       HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */
425 			WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
426 				   ~AFMT_AUDIO_SAMPLE_SEND);
427 		}
428 	} else {
429 		WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
430 			   ~AFMT_AUDIO_SAMPLE_SEND);
431 		WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0);
432 	}
433 
434 	dig->afmt->enabled = enable;
435 
436 	DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
437 		  enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
438 }
439 
440 void evergreen_dp_enable(struct drm_encoder *encoder, bool enable)
441 {
442 	struct drm_device *dev = encoder->dev;
443 	struct radeon_device *rdev = dev->dev_private;
444 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
445 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
446 	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
447 
448 	if (!dig || !dig->afmt)
449 		return;
450 
451 	if (enable && connector &&
452 	    drm_detect_monitor_audio(radeon_connector_edid(connector))) {
453 		struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
454 		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
455 		struct radeon_connector_atom_dig *dig_connector;
456 		uint32_t val;
457 
458 		WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
459 			  AFMT_AUDIO_SAMPLE_SEND);
460 
461 		WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset,
462 		       EVERGREEN_DP_SEC_TIMESTAMP_MODE(1));
463 
464 		if (!ASIC_IS_DCE6(rdev) && radeon_connector->con_priv) {
465 			dig_connector = radeon_connector->con_priv;
466 			val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset);
467 			val &= ~EVERGREEN_DP_SEC_N_BASE_MULTIPLE(0xf);
468 
469 			if (dig_connector->dp_clock == 162000)
470 				val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(3);
471 			else
472 				val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(5);
473 
474 			WREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset, val);
475 		}
476 
477 		WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset,
478 			EVERGREEN_DP_SEC_ASP_ENABLE |		/* Audio packet transmission */
479 			EVERGREEN_DP_SEC_ATP_ENABLE |		/* Audio timestamp packet transmission */
480 			EVERGREEN_DP_SEC_AIP_ENABLE |		/* Audio infoframe packet transmission */
481 			EVERGREEN_DP_SEC_STREAM_ENABLE);	/* Master enable for secondary stream engine */
482 	} else {
483 		WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0);
484 		WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
485 			   ~AFMT_AUDIO_SAMPLE_SEND);
486 	}
487 
488 	dig->afmt->enabled = enable;
489 }
490