1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/hdmi.h> 24 #include <drm/drmP.h> 25 #include "radeon.h" 26 #include "sid.h" 27 28 static u32 dce6_endpoint_rreg(struct radeon_device *rdev, 29 u32 block_offset, u32 reg) 30 { 31 unsigned long flags; 32 u32 r; 33 34 spin_lock_irqsave(&rdev->end_idx_lock, flags); 35 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 36 r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset); 37 spin_unlock_irqrestore(&rdev->end_idx_lock, flags); 38 39 return r; 40 } 41 42 static void dce6_endpoint_wreg(struct radeon_device *rdev, 43 u32 block_offset, u32 reg, u32 v) 44 { 45 unsigned long flags; 46 47 spin_lock_irqsave(&rdev->end_idx_lock, flags); 48 if (ASIC_IS_DCE8(rdev)) 49 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 50 else 51 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, 52 AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg)); 53 WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v); 54 spin_unlock_irqrestore(&rdev->end_idx_lock, flags); 55 } 56 57 #define RREG32_ENDPOINT(block, reg) dce6_endpoint_rreg(rdev, (block), (reg)) 58 #define WREG32_ENDPOINT(block, reg, v) dce6_endpoint_wreg(rdev, (block), (reg), (v)) 59 60 61 static void dce6_afmt_get_connected_pins(struct radeon_device *rdev) 62 { 63 int i; 64 u32 offset, tmp; 65 66 for (i = 0; i < rdev->audio.num_pins; i++) { 67 offset = rdev->audio.pin[i].offset; 68 tmp = RREG32_ENDPOINT(offset, 69 AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 70 if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1) 71 rdev->audio.pin[i].connected = false; 72 else 73 rdev->audio.pin[i].connected = true; 74 } 75 } 76 77 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev) 78 { 79 int i; 80 81 dce6_afmt_get_connected_pins(rdev); 82 83 for (i = 0; i < rdev->audio.num_pins; i++) { 84 if (rdev->audio.pin[i].connected) 85 return &rdev->audio.pin[i]; 86 } 87 DRM_ERROR("No connected audio pins found!\n"); 88 return NULL; 89 } 90 91 void dce6_afmt_select_pin(struct drm_encoder *encoder) 92 { 93 struct radeon_device *rdev = encoder->dev->dev_private; 94 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 95 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 96 u32 offset = dig->afmt->offset; 97 98 if (!dig->afmt->pin) 99 return; 100 101 WREG32(AFMT_AUDIO_SRC_CONTROL + offset, 102 AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id)); 103 } 104 105 void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder) 106 { 107 struct radeon_device *rdev = encoder->dev->dev_private; 108 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 109 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 110 struct drm_connector *connector; 111 struct radeon_connector *radeon_connector = NULL; 112 u32 offset, tmp; 113 u8 *sadb; 114 int sad_count; 115 116 if (!dig->afmt->pin) 117 return; 118 119 offset = dig->afmt->pin->offset; 120 121 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 122 if (connector->encoder == encoder) 123 radeon_connector = to_radeon_connector(connector); 124 } 125 126 if (!radeon_connector) { 127 DRM_ERROR("Couldn't find encoder's connector\n"); 128 return; 129 } 130 131 sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb); 132 if (sad_count < 0) { 133 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 134 return; 135 } 136 137 /* program the speaker allocation */ 138 tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 139 tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); 140 /* set HDMI mode */ 141 tmp |= HDMI_CONNECTION; 142 if (sad_count) 143 tmp |= SPEAKER_ALLOCATION(sadb[0]); 144 else 145 tmp |= SPEAKER_ALLOCATION(5); /* stereo */ 146 WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 147 148 kfree(sadb); 149 } 150 151 void dce6_afmt_write_sad_regs(struct drm_encoder *encoder) 152 { 153 struct radeon_device *rdev = encoder->dev->dev_private; 154 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 155 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 156 u32 offset; 157 struct drm_connector *connector; 158 struct radeon_connector *radeon_connector = NULL; 159 struct cea_sad *sads; 160 int i, sad_count; 161 162 static const u16 eld_reg_to_type[][2] = { 163 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 164 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 165 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 166 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 167 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 168 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 169 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 170 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 171 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 172 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 173 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 174 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 175 }; 176 177 if (!dig->afmt->pin) 178 return; 179 180 offset = dig->afmt->pin->offset; 181 182 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 183 if (connector->encoder == encoder) 184 radeon_connector = to_radeon_connector(connector); 185 } 186 187 if (!radeon_connector) { 188 DRM_ERROR("Couldn't find encoder's connector\n"); 189 return; 190 } 191 192 sad_count = drm_edid_to_sad(radeon_connector->edid, &sads); 193 if (sad_count < 0) { 194 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 195 return; 196 } 197 BUG_ON(!sads); 198 199 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 200 u32 value = 0; 201 int j; 202 203 for (j = 0; j < sad_count; j++) { 204 struct cea_sad *sad = &sads[j]; 205 206 if (sad->format == eld_reg_to_type[i][1]) { 207 value = MAX_CHANNELS(sad->channels) | 208 DESCRIPTOR_BYTE_2(sad->byte2) | 209 SUPPORTED_FREQUENCIES(sad->freq); 210 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 211 value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq); 212 break; 213 } 214 } 215 WREG32_ENDPOINT(offset, eld_reg_to_type[i][0], value); 216 } 217 218 kfree(sads); 219 } 220 221 static int dce6_audio_chipset_supported(struct radeon_device *rdev) 222 { 223 return !ASIC_IS_NODCE(rdev); 224 } 225 226 static void dce6_audio_enable(struct radeon_device *rdev, 227 struct r600_audio_pin *pin, 228 bool enable) 229 { 230 WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL, 231 AUDIO_ENABLED); 232 DRM_INFO("%s audio %d support\n", enable ? "Enabling" : "Disabling", pin->id); 233 } 234 235 static const u32 pin_offsets[7] = 236 { 237 (0x5e00 - 0x5e00), 238 (0x5e18 - 0x5e00), 239 (0x5e30 - 0x5e00), 240 (0x5e48 - 0x5e00), 241 (0x5e60 - 0x5e00), 242 (0x5e78 - 0x5e00), 243 (0x5e90 - 0x5e00), 244 }; 245 246 int dce6_audio_init(struct radeon_device *rdev) 247 { 248 int i; 249 250 if (!radeon_audio || !dce6_audio_chipset_supported(rdev)) 251 return 0; 252 253 rdev->audio.enabled = true; 254 255 if (ASIC_IS_DCE8(rdev)) 256 rdev->audio.num_pins = 7; 257 else 258 rdev->audio.num_pins = 6; 259 260 for (i = 0; i < rdev->audio.num_pins; i++) { 261 rdev->audio.pin[i].channels = -1; 262 rdev->audio.pin[i].rate = -1; 263 rdev->audio.pin[i].bits_per_sample = -1; 264 rdev->audio.pin[i].status_bits = 0; 265 rdev->audio.pin[i].category_code = 0; 266 rdev->audio.pin[i].connected = false; 267 rdev->audio.pin[i].offset = pin_offsets[i]; 268 rdev->audio.pin[i].id = i; 269 dce6_audio_enable(rdev, &rdev->audio.pin[i], true); 270 } 271 272 return 0; 273 } 274 275 void dce6_audio_fini(struct radeon_device *rdev) 276 { 277 int i; 278 279 if (!rdev->audio.enabled) 280 return; 281 282 for (i = 0; i < rdev->audio.num_pins; i++) 283 dce6_audio_enable(rdev, &rdev->audio.pin[i], false); 284 285 rdev->audio.enabled = false; 286 } 287