1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/hdmi.h> 24 #include <drm/drmP.h> 25 #include "radeon.h" 26 #include "radeon_audio.h" 27 #include "sid.h" 28 29 u32 dce6_endpoint_rreg(struct radeon_device *rdev, 30 u32 block_offset, u32 reg) 31 { 32 unsigned long flags; 33 u32 r; 34 35 spin_lock_irqsave(&rdev->end_idx_lock, flags); 36 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 37 r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset); 38 spin_unlock_irqrestore(&rdev->end_idx_lock, flags); 39 40 return r; 41 } 42 43 void dce6_endpoint_wreg(struct radeon_device *rdev, 44 u32 block_offset, u32 reg, u32 v) 45 { 46 unsigned long flags; 47 48 spin_lock_irqsave(&rdev->end_idx_lock, flags); 49 if (ASIC_IS_DCE8(rdev)) 50 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 51 else 52 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, 53 AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg)); 54 WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v); 55 spin_unlock_irqrestore(&rdev->end_idx_lock, flags); 56 } 57 58 static void dce6_afmt_get_connected_pins(struct radeon_device *rdev) 59 { 60 int i; 61 u32 offset, tmp; 62 63 for (i = 0; i < rdev->audio.num_pins; i++) { 64 offset = rdev->audio.pin[i].offset; 65 tmp = RREG32_ENDPOINT(offset, 66 AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 67 if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1) 68 rdev->audio.pin[i].connected = false; 69 else 70 rdev->audio.pin[i].connected = true; 71 } 72 } 73 74 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev) 75 { 76 int i; 77 78 dce6_afmt_get_connected_pins(rdev); 79 80 for (i = 0; i < rdev->audio.num_pins; i++) { 81 if (rdev->audio.pin[i].connected) 82 return &rdev->audio.pin[i]; 83 } 84 DRM_ERROR("No connected audio pins found!\n"); 85 return NULL; 86 } 87 88 void dce6_afmt_select_pin(struct drm_encoder *encoder) 89 { 90 struct radeon_device *rdev = encoder->dev->dev_private; 91 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 92 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 93 u32 offset; 94 95 if (!dig || !dig->afmt || !dig->afmt->pin) 96 return; 97 98 offset = dig->afmt->offset; 99 100 WREG32(AFMT_AUDIO_SRC_CONTROL + offset, 101 AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id)); 102 } 103 104 void dce6_afmt_write_latency_fields(struct drm_encoder *encoder, 105 struct drm_connector *connector, struct drm_display_mode *mode) 106 { 107 struct radeon_device *rdev = encoder->dev->dev_private; 108 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 109 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 110 u32 tmp = 0, offset; 111 112 if (!dig || !dig->afmt || !dig->afmt->pin) 113 return; 114 115 offset = dig->afmt->pin->offset; 116 117 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 118 if (connector->latency_present[1]) 119 tmp = VIDEO_LIPSYNC(connector->video_latency[1]) | 120 AUDIO_LIPSYNC(connector->audio_latency[1]); 121 else 122 tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0); 123 } else { 124 if (connector->latency_present[0]) 125 tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | 126 AUDIO_LIPSYNC(connector->audio_latency[0]); 127 else 128 tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0); 129 } 130 WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 131 } 132 133 void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder, 134 u8 *sadb, int sad_count) 135 { 136 struct radeon_device *rdev = encoder->dev->dev_private; 137 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 138 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 139 u32 offset, tmp; 140 141 if (!dig || !dig->afmt || !dig->afmt->pin) 142 return; 143 144 offset = dig->afmt->pin->offset; 145 146 /* program the speaker allocation */ 147 tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 148 tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); 149 /* set HDMI mode */ 150 tmp |= HDMI_CONNECTION; 151 if (sad_count) 152 tmp |= SPEAKER_ALLOCATION(sadb[0]); 153 else 154 tmp |= SPEAKER_ALLOCATION(5); /* stereo */ 155 WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 156 } 157 158 void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder, 159 u8 *sadb, int sad_count) 160 { 161 struct radeon_device *rdev = encoder->dev->dev_private; 162 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 163 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 164 u32 offset, tmp; 165 166 if (!dig || !dig->afmt || !dig->afmt->pin) 167 return; 168 169 offset = dig->afmt->pin->offset; 170 171 /* program the speaker allocation */ 172 tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 173 tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK); 174 /* set DP mode */ 175 tmp |= DP_CONNECTION; 176 if (sad_count) 177 tmp |= SPEAKER_ALLOCATION(sadb[0]); 178 else 179 tmp |= SPEAKER_ALLOCATION(5); /* stereo */ 180 WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 181 } 182 183 void dce6_afmt_write_sad_regs(struct drm_encoder *encoder, 184 struct cea_sad *sads, int sad_count) 185 { 186 u32 offset; 187 int i; 188 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 189 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 190 struct radeon_device *rdev = encoder->dev->dev_private; 191 static const u16 eld_reg_to_type[][2] = { 192 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 193 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 194 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 195 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 196 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 197 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 198 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 199 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 200 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 201 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 202 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 203 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 204 }; 205 206 if (!dig || !dig->afmt || !dig->afmt->pin) 207 return; 208 209 offset = dig->afmt->pin->offset; 210 211 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 212 u32 value = 0; 213 u8 stereo_freqs = 0; 214 int max_channels = -1; 215 int j; 216 217 for (j = 0; j < sad_count; j++) { 218 struct cea_sad *sad = &sads[j]; 219 220 if (sad->format == eld_reg_to_type[i][1]) { 221 if (sad->channels > max_channels) { 222 value = MAX_CHANNELS(sad->channels) | 223 DESCRIPTOR_BYTE_2(sad->byte2) | 224 SUPPORTED_FREQUENCIES(sad->freq); 225 max_channels = sad->channels; 226 } 227 228 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 229 stereo_freqs |= sad->freq; 230 else 231 break; 232 } 233 } 234 235 value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); 236 237 WREG32_ENDPOINT(offset, eld_reg_to_type[i][0], value); 238 } 239 } 240 241 void dce6_audio_enable(struct radeon_device *rdev, 242 struct r600_audio_pin *pin, 243 u8 enable_mask) 244 { 245 if (!pin) 246 return; 247 248 WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 249 enable_mask ? AUDIO_ENABLED : 0); 250 } 251 252 void dce6_audio_fini(struct radeon_device *rdev) 253 { 254 int i; 255 256 if (!rdev->audio.enabled) 257 return; 258 259 for (i = 0; i < rdev->audio.num_pins; i++) 260 radeon_audio_enable(rdev, &rdev->audio.pin[i], false); 261 262 rdev->audio.enabled = false; 263 } 264