1b530602fSAlex Deucher /* 2b530602fSAlex Deucher * Copyright 2013 Advanced Micro Devices, Inc. 3b530602fSAlex Deucher * 4b530602fSAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5b530602fSAlex Deucher * copy of this software and associated documentation files (the "Software"), 6b530602fSAlex Deucher * to deal in the Software without restriction, including without limitation 7b530602fSAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8b530602fSAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9b530602fSAlex Deucher * Software is furnished to do so, subject to the following conditions: 10b530602fSAlex Deucher * 11b530602fSAlex Deucher * The above copyright notice and this permission notice shall be included in 12b530602fSAlex Deucher * all copies or substantial portions of the Software. 13b530602fSAlex Deucher * 14b530602fSAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15b530602fSAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16b530602fSAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17b530602fSAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18b530602fSAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19b530602fSAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20b530602fSAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21b530602fSAlex Deucher * 22b530602fSAlex Deucher */ 23b530602fSAlex Deucher #include <linux/hdmi.h> 24b530602fSAlex Deucher #include <drm/drmP.h> 25b530602fSAlex Deucher #include "radeon.h" 26b530602fSAlex Deucher #include "sid.h" 27b530602fSAlex Deucher 28b530602fSAlex Deucher static u32 dce6_endpoint_rreg(struct radeon_device *rdev, 29b530602fSAlex Deucher u32 block_offset, u32 reg) 30b530602fSAlex Deucher { 310a5b7b0bSAlex Deucher unsigned long flags; 32b530602fSAlex Deucher u32 r; 33b530602fSAlex Deucher 340a5b7b0bSAlex Deucher spin_lock_irqsave(&rdev->end_idx_lock, flags); 35b530602fSAlex Deucher WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 36b530602fSAlex Deucher r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset); 370a5b7b0bSAlex Deucher spin_unlock_irqrestore(&rdev->end_idx_lock, flags); 380a5b7b0bSAlex Deucher 39b530602fSAlex Deucher return r; 40b530602fSAlex Deucher } 41b530602fSAlex Deucher 42b530602fSAlex Deucher static void dce6_endpoint_wreg(struct radeon_device *rdev, 43b530602fSAlex Deucher u32 block_offset, u32 reg, u32 v) 44b530602fSAlex Deucher { 450a5b7b0bSAlex Deucher unsigned long flags; 460a5b7b0bSAlex Deucher 470a5b7b0bSAlex Deucher spin_lock_irqsave(&rdev->end_idx_lock, flags); 48b530602fSAlex Deucher if (ASIC_IS_DCE8(rdev)) 49b530602fSAlex Deucher WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 50b530602fSAlex Deucher else 51b530602fSAlex Deucher WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, 52b530602fSAlex Deucher AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg)); 53b530602fSAlex Deucher WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v); 540a5b7b0bSAlex Deucher spin_unlock_irqrestore(&rdev->end_idx_lock, flags); 55b530602fSAlex Deucher } 56b530602fSAlex Deucher 57b530602fSAlex Deucher #define RREG32_ENDPOINT(block, reg) dce6_endpoint_rreg(rdev, (block), (reg)) 58b530602fSAlex Deucher #define WREG32_ENDPOINT(block, reg, v) dce6_endpoint_wreg(rdev, (block), (reg), (v)) 59b530602fSAlex Deucher 60b530602fSAlex Deucher 61b530602fSAlex Deucher static void dce6_afmt_get_connected_pins(struct radeon_device *rdev) 62b530602fSAlex Deucher { 63b530602fSAlex Deucher int i; 64b530602fSAlex Deucher u32 offset, tmp; 65b530602fSAlex Deucher 66b530602fSAlex Deucher for (i = 0; i < rdev->audio.num_pins; i++) { 67b530602fSAlex Deucher offset = rdev->audio.pin[i].offset; 68b530602fSAlex Deucher tmp = RREG32_ENDPOINT(offset, 69b530602fSAlex Deucher AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 70b530602fSAlex Deucher if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1) 71b530602fSAlex Deucher rdev->audio.pin[i].connected = false; 72b530602fSAlex Deucher else 73b530602fSAlex Deucher rdev->audio.pin[i].connected = true; 74b530602fSAlex Deucher } 75b530602fSAlex Deucher } 76b530602fSAlex Deucher 77b530602fSAlex Deucher struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev) 78b530602fSAlex Deucher { 79b530602fSAlex Deucher int i; 80b530602fSAlex Deucher 81b530602fSAlex Deucher dce6_afmt_get_connected_pins(rdev); 82b530602fSAlex Deucher 83b530602fSAlex Deucher for (i = 0; i < rdev->audio.num_pins; i++) { 84b530602fSAlex Deucher if (rdev->audio.pin[i].connected) 85b530602fSAlex Deucher return &rdev->audio.pin[i]; 86b530602fSAlex Deucher } 87b530602fSAlex Deucher DRM_ERROR("No connected audio pins found!\n"); 88b530602fSAlex Deucher return NULL; 89b530602fSAlex Deucher } 90b530602fSAlex Deucher 91b530602fSAlex Deucher void dce6_afmt_select_pin(struct drm_encoder *encoder) 92b530602fSAlex Deucher { 93b530602fSAlex Deucher struct radeon_device *rdev = encoder->dev->dev_private; 94b530602fSAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 95b530602fSAlex Deucher struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 96b530602fSAlex Deucher u32 offset = dig->afmt->offset; 97b530602fSAlex Deucher 98b530602fSAlex Deucher if (!dig->afmt->pin) 99b530602fSAlex Deucher return; 100b530602fSAlex Deucher 1017cc0a3d8SAlex Deucher WREG32(AFMT_AUDIO_SRC_CONTROL + offset, 1027cc0a3d8SAlex Deucher AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id)); 103b530602fSAlex Deucher } 104b530602fSAlex Deucher 105b1880258SAlex Deucher void dce6_afmt_write_latency_fields(struct drm_encoder *encoder, 106b1880258SAlex Deucher struct drm_display_mode *mode) 107b1880258SAlex Deucher { 108b1880258SAlex Deucher struct radeon_device *rdev = encoder->dev->dev_private; 109b1880258SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 110b1880258SAlex Deucher struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 111b1880258SAlex Deucher struct drm_connector *connector; 112b1880258SAlex Deucher struct radeon_connector *radeon_connector = NULL; 113b1880258SAlex Deucher u32 tmp = 0, offset; 114b1880258SAlex Deucher 115b1880258SAlex Deucher if (!dig->afmt->pin) 116b1880258SAlex Deucher return; 117b1880258SAlex Deucher 118b1880258SAlex Deucher offset = dig->afmt->pin->offset; 119b1880258SAlex Deucher 120b1880258SAlex Deucher list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 121b1880258SAlex Deucher if (connector->encoder == encoder) { 122b1880258SAlex Deucher radeon_connector = to_radeon_connector(connector); 123b1880258SAlex Deucher break; 124b1880258SAlex Deucher } 125b1880258SAlex Deucher } 126b1880258SAlex Deucher 127b1880258SAlex Deucher if (!radeon_connector) { 128b1880258SAlex Deucher DRM_ERROR("Couldn't find encoder's connector\n"); 129b1880258SAlex Deucher return; 130b1880258SAlex Deucher } 131b1880258SAlex Deucher 132b1880258SAlex Deucher if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 133b1880258SAlex Deucher if (connector->latency_present[1]) 134b1880258SAlex Deucher tmp = VIDEO_LIPSYNC(connector->video_latency[1]) | 135b1880258SAlex Deucher AUDIO_LIPSYNC(connector->audio_latency[1]); 136b1880258SAlex Deucher else 137b1880258SAlex Deucher tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); 138b1880258SAlex Deucher } else { 139b1880258SAlex Deucher if (connector->latency_present[0]) 140b1880258SAlex Deucher tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | 141b1880258SAlex Deucher AUDIO_LIPSYNC(connector->audio_latency[0]); 142b1880258SAlex Deucher else 143b1880258SAlex Deucher tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); 144b1880258SAlex Deucher } 145b1880258SAlex Deucher WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 146b1880258SAlex Deucher } 147b1880258SAlex Deucher 1486159b65aSRafał Miłecki void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder) 1496159b65aSRafał Miłecki { 1506159b65aSRafał Miłecki struct radeon_device *rdev = encoder->dev->dev_private; 1516159b65aSRafał Miłecki struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1526159b65aSRafał Miłecki struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1536159b65aSRafał Miłecki struct drm_connector *connector; 1546159b65aSRafał Miłecki struct radeon_connector *radeon_connector = NULL; 1556159b65aSRafał Miłecki u32 offset, tmp; 1566159b65aSRafał Miłecki u8 *sadb; 1576159b65aSRafał Miłecki int sad_count; 1586159b65aSRafał Miłecki 159555b1b65SAlex Deucher /* XXX: setting this register causes hangs on some asics */ 160555b1b65SAlex Deucher return; 161555b1b65SAlex Deucher 1626159b65aSRafał Miłecki if (!dig->afmt->pin) 1636159b65aSRafał Miłecki return; 1646159b65aSRafał Miłecki 1656159b65aSRafał Miłecki offset = dig->afmt->pin->offset; 1666159b65aSRafał Miłecki 1676159b65aSRafał Miłecki list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1686159b65aSRafał Miłecki if (connector->encoder == encoder) 1696159b65aSRafał Miłecki radeon_connector = to_radeon_connector(connector); 1706159b65aSRafał Miłecki } 1716159b65aSRafał Miłecki 1726159b65aSRafał Miłecki if (!radeon_connector) { 1736159b65aSRafał Miłecki DRM_ERROR("Couldn't find encoder's connector\n"); 1746159b65aSRafał Miłecki return; 1756159b65aSRafał Miłecki } 1766159b65aSRafał Miłecki 1776159b65aSRafał Miłecki sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb); 1786159b65aSRafał Miłecki if (sad_count < 0) { 1796159b65aSRafał Miłecki DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1806159b65aSRafał Miłecki return; 1816159b65aSRafał Miłecki } 1826159b65aSRafał Miłecki 1836159b65aSRafał Miłecki /* program the speaker allocation */ 1846159b65aSRafał Miłecki tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1856159b65aSRafał Miłecki tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); 1866159b65aSRafał Miłecki /* set HDMI mode */ 1876159b65aSRafał Miłecki tmp |= HDMI_CONNECTION; 1886159b65aSRafał Miłecki if (sad_count) 1896159b65aSRafał Miłecki tmp |= SPEAKER_ALLOCATION(sadb[0]); 1906159b65aSRafał Miłecki else 1916159b65aSRafał Miłecki tmp |= SPEAKER_ALLOCATION(5); /* stereo */ 1926159b65aSRafał Miłecki WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1936159b65aSRafał Miłecki 1946159b65aSRafał Miłecki kfree(sadb); 1956159b65aSRafał Miłecki } 1966159b65aSRafał Miłecki 197b530602fSAlex Deucher void dce6_afmt_write_sad_regs(struct drm_encoder *encoder) 198b530602fSAlex Deucher { 199b530602fSAlex Deucher struct radeon_device *rdev = encoder->dev->dev_private; 200b530602fSAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 201b530602fSAlex Deucher struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2026159b65aSRafał Miłecki u32 offset; 203b530602fSAlex Deucher struct drm_connector *connector; 204b530602fSAlex Deucher struct radeon_connector *radeon_connector = NULL; 205b530602fSAlex Deucher struct cea_sad *sads; 2066159b65aSRafał Miłecki int i, sad_count; 207b530602fSAlex Deucher 208b530602fSAlex Deucher static const u16 eld_reg_to_type[][2] = { 209b530602fSAlex Deucher { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 210b530602fSAlex Deucher { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 211b530602fSAlex Deucher { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 212b530602fSAlex Deucher { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 213b530602fSAlex Deucher { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 214b530602fSAlex Deucher { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 215b530602fSAlex Deucher { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 216b530602fSAlex Deucher { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 217b530602fSAlex Deucher { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 218b530602fSAlex Deucher { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 219b530602fSAlex Deucher { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 220b530602fSAlex Deucher { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 221b530602fSAlex Deucher }; 222b530602fSAlex Deucher 223b530602fSAlex Deucher if (!dig->afmt->pin) 224b530602fSAlex Deucher return; 225b530602fSAlex Deucher 226b530602fSAlex Deucher offset = dig->afmt->pin->offset; 227b530602fSAlex Deucher 228b530602fSAlex Deucher list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 229b530602fSAlex Deucher if (connector->encoder == encoder) 230b530602fSAlex Deucher radeon_connector = to_radeon_connector(connector); 231b530602fSAlex Deucher } 232b530602fSAlex Deucher 233b530602fSAlex Deucher if (!radeon_connector) { 234b530602fSAlex Deucher DRM_ERROR("Couldn't find encoder's connector\n"); 235b530602fSAlex Deucher return; 236b530602fSAlex Deucher } 237b530602fSAlex Deucher 238b530602fSAlex Deucher sad_count = drm_edid_to_sad(radeon_connector->edid, &sads); 239b530602fSAlex Deucher if (sad_count < 0) { 240b530602fSAlex Deucher DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 241b530602fSAlex Deucher return; 242b530602fSAlex Deucher } 243b530602fSAlex Deucher BUG_ON(!sads); 244b530602fSAlex Deucher 245b530602fSAlex Deucher for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 246b530602fSAlex Deucher u32 value = 0; 2470f57bca9SAnssi Hannula u8 stereo_freqs = 0; 2480f57bca9SAnssi Hannula int max_channels = -1; 249b530602fSAlex Deucher int j; 250b530602fSAlex Deucher 251b530602fSAlex Deucher for (j = 0; j < sad_count; j++) { 252b530602fSAlex Deucher struct cea_sad *sad = &sads[j]; 253b530602fSAlex Deucher 254b530602fSAlex Deucher if (sad->format == eld_reg_to_type[i][1]) { 2550f57bca9SAnssi Hannula if (sad->channels > max_channels) { 256b530602fSAlex Deucher value = MAX_CHANNELS(sad->channels) | 257b530602fSAlex Deucher DESCRIPTOR_BYTE_2(sad->byte2) | 258b530602fSAlex Deucher SUPPORTED_FREQUENCIES(sad->freq); 2590f57bca9SAnssi Hannula max_channels = sad->channels; 2600f57bca9SAnssi Hannula } 2610f57bca9SAnssi Hannula 262b530602fSAlex Deucher if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 2630f57bca9SAnssi Hannula stereo_freqs |= sad->freq; 2640f57bca9SAnssi Hannula else 265b530602fSAlex Deucher break; 266b530602fSAlex Deucher } 267b530602fSAlex Deucher } 2680f57bca9SAnssi Hannula 2690f57bca9SAnssi Hannula value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); 2700f57bca9SAnssi Hannula 271b530602fSAlex Deucher WREG32_ENDPOINT(offset, eld_reg_to_type[i][0], value); 272b530602fSAlex Deucher } 273b530602fSAlex Deucher 274b530602fSAlex Deucher kfree(sads); 275b530602fSAlex Deucher } 276b530602fSAlex Deucher 277b530602fSAlex Deucher static int dce6_audio_chipset_supported(struct radeon_device *rdev) 278b530602fSAlex Deucher { 279b530602fSAlex Deucher return !ASIC_IS_NODCE(rdev); 280b530602fSAlex Deucher } 281b530602fSAlex Deucher 282b530602fSAlex Deucher static void dce6_audio_enable(struct radeon_device *rdev, 283b530602fSAlex Deucher struct r600_audio_pin *pin, 284b530602fSAlex Deucher bool enable) 285b530602fSAlex Deucher { 286b530602fSAlex Deucher WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL, 287b530602fSAlex Deucher AUDIO_ENABLED); 288b530602fSAlex Deucher DRM_INFO("%s audio %d support\n", enable ? "Enabling" : "Disabling", pin->id); 289b530602fSAlex Deucher } 290b530602fSAlex Deucher 291b530602fSAlex Deucher static const u32 pin_offsets[7] = 292b530602fSAlex Deucher { 293b530602fSAlex Deucher (0x5e00 - 0x5e00), 294b530602fSAlex Deucher (0x5e18 - 0x5e00), 295b530602fSAlex Deucher (0x5e30 - 0x5e00), 296b530602fSAlex Deucher (0x5e48 - 0x5e00), 297b530602fSAlex Deucher (0x5e60 - 0x5e00), 298b530602fSAlex Deucher (0x5e78 - 0x5e00), 299b530602fSAlex Deucher (0x5e90 - 0x5e00), 300b530602fSAlex Deucher }; 301b530602fSAlex Deucher 302b530602fSAlex Deucher int dce6_audio_init(struct radeon_device *rdev) 303b530602fSAlex Deucher { 304b530602fSAlex Deucher int i; 305b530602fSAlex Deucher 306b530602fSAlex Deucher if (!radeon_audio || !dce6_audio_chipset_supported(rdev)) 307b530602fSAlex Deucher return 0; 308b530602fSAlex Deucher 309b530602fSAlex Deucher rdev->audio.enabled = true; 310b530602fSAlex Deucher 311b530602fSAlex Deucher if (ASIC_IS_DCE8(rdev)) 312b530602fSAlex Deucher rdev->audio.num_pins = 7; 313b530602fSAlex Deucher else 314b530602fSAlex Deucher rdev->audio.num_pins = 6; 315b530602fSAlex Deucher 316b530602fSAlex Deucher for (i = 0; i < rdev->audio.num_pins; i++) { 317b530602fSAlex Deucher rdev->audio.pin[i].channels = -1; 318b530602fSAlex Deucher rdev->audio.pin[i].rate = -1; 319b530602fSAlex Deucher rdev->audio.pin[i].bits_per_sample = -1; 320b530602fSAlex Deucher rdev->audio.pin[i].status_bits = 0; 321b530602fSAlex Deucher rdev->audio.pin[i].category_code = 0; 322b530602fSAlex Deucher rdev->audio.pin[i].connected = false; 323b530602fSAlex Deucher rdev->audio.pin[i].offset = pin_offsets[i]; 324b530602fSAlex Deucher rdev->audio.pin[i].id = i; 325b530602fSAlex Deucher dce6_audio_enable(rdev, &rdev->audio.pin[i], true); 326b530602fSAlex Deucher } 327b530602fSAlex Deucher 328b530602fSAlex Deucher return 0; 329b530602fSAlex Deucher } 330b530602fSAlex Deucher 331b530602fSAlex Deucher void dce6_audio_fini(struct radeon_device *rdev) 332b530602fSAlex Deucher { 333b530602fSAlex Deucher int i; 334b530602fSAlex Deucher 335b530602fSAlex Deucher if (!rdev->audio.enabled) 336b530602fSAlex Deucher return; 337b530602fSAlex Deucher 338b530602fSAlex Deucher for (i = 0; i < rdev->audio.num_pins; i++) 339b530602fSAlex Deucher dce6_audio_enable(rdev, &rdev->audio.pin[i], false); 340b530602fSAlex Deucher 341b530602fSAlex Deucher rdev->audio.enabled = false; 342b530602fSAlex Deucher } 343