1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * Copyright 2014 Rafał Miłecki 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #include <linux/hdmi.h> 24 #include <drm/drmP.h> 25 #include "radeon.h" 26 #include "radeon_asic.h" 27 #include "radeon_audio.h" 28 #include "r600d.h" 29 30 void dce3_2_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder, 31 u8 *sadb, int sad_count) 32 { 33 struct radeon_device *rdev = encoder->dev->dev_private; 34 u32 tmp; 35 36 /* program the speaker allocation */ 37 tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); 38 tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); 39 /* set HDMI mode */ 40 tmp |= HDMI_CONNECTION; 41 if (sad_count) 42 tmp |= SPEAKER_ALLOCATION(sadb[0]); 43 else 44 tmp |= SPEAKER_ALLOCATION(5); /* stereo */ 45 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); 46 } 47 48 void dce3_2_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder, 49 u8 *sadb, int sad_count) 50 { 51 struct radeon_device *rdev = encoder->dev->dev_private; 52 u32 tmp; 53 54 /* program the speaker allocation */ 55 tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); 56 tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK); 57 /* set DP mode */ 58 tmp |= DP_CONNECTION; 59 if (sad_count) 60 tmp |= SPEAKER_ALLOCATION(sadb[0]); 61 else 62 tmp |= SPEAKER_ALLOCATION(5); /* stereo */ 63 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); 64 } 65 66 void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder, 67 struct cea_sad *sads, int sad_count) 68 { 69 int i; 70 struct radeon_device *rdev = encoder->dev->dev_private; 71 static const u16 eld_reg_to_type[][2] = { 72 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 73 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 74 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 75 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 76 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 77 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 78 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 79 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 80 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 81 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 82 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 83 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 84 }; 85 86 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 87 u32 value = 0; 88 u8 stereo_freqs = 0; 89 int max_channels = -1; 90 int j; 91 92 for (j = 0; j < sad_count; j++) { 93 struct cea_sad *sad = &sads[j]; 94 95 if (sad->format == eld_reg_to_type[i][1]) { 96 if (sad->channels > max_channels) { 97 value = MAX_CHANNELS(sad->channels) | 98 DESCRIPTOR_BYTE_2(sad->byte2) | 99 SUPPORTED_FREQUENCIES(sad->freq); 100 max_channels = sad->channels; 101 } 102 103 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 104 stereo_freqs |= sad->freq; 105 else 106 break; 107 } 108 } 109 110 value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); 111 112 WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value); 113 } 114 } 115 116 /* 117 * update the info frames with the data from the current display mode 118 */ 119 void dce3_1_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) 120 { 121 struct drm_device *dev = encoder->dev; 122 struct radeon_device *rdev = dev->dev_private; 123 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 124 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 125 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 126 struct hdmi_avi_infoframe frame; 127 uint32_t offset; 128 ssize_t err; 129 130 if (!dig || !dig->afmt) 131 return; 132 133 /* Silent, r600_hdmi_enable will raise WARN for us */ 134 if (!dig->afmt->enabled) 135 return; 136 offset = dig->afmt->offset; 137 138 /* disable audio prior to setting up hw */ 139 dig->afmt->pin = radeon_audio_get_pin(encoder); 140 r600_audio_enable(rdev, dig->afmt->pin, 0); 141 142 r600_audio_set_dto(encoder, mode->clock); 143 144 WREG32(HDMI0_VBI_PACKET_CONTROL + offset, 145 HDMI0_NULL_SEND); /* send null packets when required */ 146 147 WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000); 148 149 if (ASIC_IS_DCE32(rdev)) { 150 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, 151 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ 152 HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ 153 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, 154 AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */ 155 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ 156 } else { 157 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, 158 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */ 159 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ 160 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */ 161 HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ 162 } 163 164 if (ASIC_IS_DCE32(rdev)) { 165 radeon_audio_write_speaker_allocation(encoder); 166 radeon_audio_write_sad_regs(encoder); 167 } 168 169 WREG32(HDMI0_ACR_PACKET_CONTROL + offset, 170 HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */ 171 HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ 172 173 WREG32(HDMI0_VBI_PACKET_CONTROL + offset, 174 HDMI0_NULL_SEND | /* send null packets when required */ 175 HDMI0_GC_SEND | /* send general control packets */ 176 HDMI0_GC_CONT); /* send general control packets every frame */ 177 178 /* TODO: HDMI0_AUDIO_INFO_UPDATE */ 179 WREG32(HDMI0_INFOFRAME_CONTROL0 + offset, 180 HDMI0_AVI_INFO_SEND | /* enable AVI info frames */ 181 HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */ 182 HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ 183 HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */ 184 185 WREG32(HDMI0_INFOFRAME_CONTROL1 + offset, 186 HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */ 187 HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */ 188 189 WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */ 190 191 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 192 if (err < 0) { 193 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 194 return; 195 } 196 197 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 198 if (err < 0) { 199 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 200 return; 201 } 202 203 r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 204 r600_hdmi_update_ACR(encoder, mode->clock); 205 206 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ 207 WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF); 208 WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF); 209 WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001); 210 WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001); 211 212 r600_hdmi_audio_workaround(encoder); 213 214 /* enable audio after to setting up hw */ 215 r600_audio_enable(rdev, dig->afmt->pin, 0xf); 216 } 217