1 /* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #ifndef CIK_H 25 #define CIK_H 26 27 #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 28 29 #define CIK_RB_BITMAP_WIDTH_PER_SH 2 30 31 /* SMC IND registers */ 32 #define GENERAL_PWRMGT 0xC0200000 33 # define GPU_COUNTER_CLK (1 << 15) 34 35 #define CG_CLKPIN_CNTL 0xC05001A0 36 # define XTALIN_DIVIDE (1 << 1) 37 38 #define PCIE_INDEX 0x38 39 #define PCIE_DATA 0x3C 40 41 #define VGA_HDP_CONTROL 0x328 42 #define VGA_MEMORY_DISABLE (1 << 4) 43 44 #define DMIF_ADDR_CALC 0xC00 45 46 #define SRBM_GFX_CNTL 0xE44 47 #define PIPEID(x) ((x) << 0) 48 #define MEID(x) ((x) << 2) 49 #define VMID(x) ((x) << 4) 50 #define QUEUEID(x) ((x) << 8) 51 52 #define SRBM_STATUS2 0xE4C 53 #define SDMA_BUSY (1 << 5) 54 #define SDMA1_BUSY (1 << 6) 55 #define SRBM_STATUS 0xE50 56 #define UVD_RQ_PENDING (1 << 1) 57 #define GRBM_RQ_PENDING (1 << 5) 58 #define VMC_BUSY (1 << 8) 59 #define MCB_BUSY (1 << 9) 60 #define MCB_NON_DISPLAY_BUSY (1 << 10) 61 #define MCC_BUSY (1 << 11) 62 #define MCD_BUSY (1 << 12) 63 #define SEM_BUSY (1 << 14) 64 #define IH_BUSY (1 << 17) 65 #define UVD_BUSY (1 << 19) 66 67 #define SRBM_SOFT_RESET 0xE60 68 #define SOFT_RESET_BIF (1 << 1) 69 #define SOFT_RESET_R0PLL (1 << 4) 70 #define SOFT_RESET_DC (1 << 5) 71 #define SOFT_RESET_SDMA1 (1 << 6) 72 #define SOFT_RESET_GRBM (1 << 8) 73 #define SOFT_RESET_HDP (1 << 9) 74 #define SOFT_RESET_IH (1 << 10) 75 #define SOFT_RESET_MC (1 << 11) 76 #define SOFT_RESET_ROM (1 << 14) 77 #define SOFT_RESET_SEM (1 << 15) 78 #define SOFT_RESET_VMC (1 << 17) 79 #define SOFT_RESET_SDMA (1 << 20) 80 #define SOFT_RESET_TST (1 << 21) 81 #define SOFT_RESET_REGBB (1 << 22) 82 #define SOFT_RESET_ORB (1 << 23) 83 #define SOFT_RESET_VCE (1 << 24) 84 85 #define VM_L2_CNTL 0x1400 86 #define ENABLE_L2_CACHE (1 << 0) 87 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 88 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) 89 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) 90 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 91 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 92 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) 93 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) 94 #define VM_L2_CNTL2 0x1404 95 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 96 #define INVALIDATE_L2_CACHE (1 << 1) 97 #define INVALIDATE_CACHE_MODE(x) ((x) << 26) 98 #define INVALIDATE_PTE_AND_PDE_CACHES 0 99 #define INVALIDATE_ONLY_PTE_CACHES 1 100 #define INVALIDATE_ONLY_PDE_CACHES 2 101 #define VM_L2_CNTL3 0x1408 102 #define BANK_SELECT(x) ((x) << 0) 103 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) 104 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 105 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 106 #define VM_L2_STATUS 0x140C 107 #define L2_BUSY (1 << 0) 108 #define VM_CONTEXT0_CNTL 0x1410 109 #define ENABLE_CONTEXT (1 << 0) 110 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 111 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 112 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 113 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 114 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 115 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 116 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 117 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 118 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 119 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 120 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 121 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 122 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 123 #define VM_CONTEXT1_CNTL 0x1414 124 #define VM_CONTEXT0_CNTL2 0x1430 125 #define VM_CONTEXT1_CNTL2 0x1434 126 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438 127 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c 128 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440 129 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444 130 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448 131 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c 132 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450 133 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454 134 135 #define VM_INVALIDATE_REQUEST 0x1478 136 #define VM_INVALIDATE_RESPONSE 0x147c 137 138 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 139 #define PROTECTIONS_MASK (0xf << 0) 140 #define PROTECTIONS_SHIFT 0 141 /* bit 0: range 142 * bit 1: pde0 143 * bit 2: valid 144 * bit 3: read 145 * bit 4: write 146 */ 147 #define MEMORY_CLIENT_ID_MASK (0xff << 12) 148 #define MEMORY_CLIENT_ID_SHIFT 12 149 #define MEMORY_CLIENT_RW_MASK (1 << 24) 150 #define MEMORY_CLIENT_RW_SHIFT 24 151 #define FAULT_VMID_MASK (0xf << 25) 152 #define FAULT_VMID_SHIFT 25 153 154 #define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x14E4 155 156 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 157 158 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 159 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 160 161 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 162 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540 163 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544 164 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548 165 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c 166 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550 167 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554 168 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558 169 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 170 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560 171 172 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 173 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580 174 175 #define MC_SHARED_CHMAP 0x2004 176 #define NOOFCHAN_SHIFT 12 177 #define NOOFCHAN_MASK 0x0000f000 178 #define MC_SHARED_CHREMAP 0x2008 179 180 #define CHUB_CONTROL 0x1864 181 #define BYPASS_VM (1 << 0) 182 183 #define MC_VM_FB_LOCATION 0x2024 184 #define MC_VM_AGP_TOP 0x2028 185 #define MC_VM_AGP_BOT 0x202C 186 #define MC_VM_AGP_BASE 0x2030 187 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 188 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 189 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 190 191 #define MC_VM_MX_L1_TLB_CNTL 0x2064 192 #define ENABLE_L1_TLB (1 << 0) 193 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 194 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 195 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 196 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 197 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 198 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 199 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 200 #define MC_VM_FB_OFFSET 0x2068 201 202 #define MC_SHARED_BLACKOUT_CNTL 0x20ac 203 204 #define MC_ARB_RAMCFG 0x2760 205 #define NOOFBANK_SHIFT 0 206 #define NOOFBANK_MASK 0x00000003 207 #define NOOFRANK_SHIFT 2 208 #define NOOFRANK_MASK 0x00000004 209 #define NOOFROWS_SHIFT 3 210 #define NOOFROWS_MASK 0x00000038 211 #define NOOFCOLS_SHIFT 6 212 #define NOOFCOLS_MASK 0x000000C0 213 #define CHANSIZE_SHIFT 8 214 #define CHANSIZE_MASK 0x00000100 215 #define NOOFGROUPS_SHIFT 12 216 #define NOOFGROUPS_MASK 0x00001000 217 218 #define MC_SEQ_SUP_CNTL 0x28c8 219 #define RUN_MASK (1 << 0) 220 #define MC_SEQ_SUP_PGM 0x28cc 221 222 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8 223 #define TRAIN_DONE_D0 (1 << 30) 224 #define TRAIN_DONE_D1 (1 << 31) 225 226 #define MC_IO_PAD_CNTL_D0 0x29d0 227 #define MEM_FALL_OUT_CMD (1 << 8) 228 229 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 230 #define MC_SEQ_IO_DEBUG_DATA 0x2a48 231 232 #define HDP_HOST_PATH_CNTL 0x2C00 233 #define HDP_NONSURFACE_BASE 0x2C04 234 #define HDP_NONSURFACE_INFO 0x2C08 235 #define HDP_NONSURFACE_SIZE 0x2C0C 236 237 #define HDP_ADDR_CONFIG 0x2F48 238 #define HDP_MISC_CNTL 0x2F4C 239 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 240 241 #define IH_RB_CNTL 0x3e00 242 # define IH_RB_ENABLE (1 << 0) 243 # define IH_RB_SIZE(x) ((x) << 1) /* log2 */ 244 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 245 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 246 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 247 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 248 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 249 #define IH_RB_BASE 0x3e04 250 #define IH_RB_RPTR 0x3e08 251 #define IH_RB_WPTR 0x3e0c 252 # define RB_OVERFLOW (1 << 0) 253 # define WPTR_OFFSET_MASK 0x3fffc 254 #define IH_RB_WPTR_ADDR_HI 0x3e10 255 #define IH_RB_WPTR_ADDR_LO 0x3e14 256 #define IH_CNTL 0x3e18 257 # define ENABLE_INTR (1 << 0) 258 # define IH_MC_SWAP(x) ((x) << 1) 259 # define IH_MC_SWAP_NONE 0 260 # define IH_MC_SWAP_16BIT 1 261 # define IH_MC_SWAP_32BIT 2 262 # define IH_MC_SWAP_64BIT 3 263 # define RPTR_REARM (1 << 4) 264 # define MC_WRREQ_CREDIT(x) ((x) << 15) 265 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 266 # define MC_VMID(x) ((x) << 25) 267 268 #define CONFIG_MEMSIZE 0x5428 269 270 #define INTERRUPT_CNTL 0x5468 271 # define IH_DUMMY_RD_OVERRIDE (1 << 0) 272 # define IH_DUMMY_RD_EN (1 << 1) 273 # define IH_REQ_NONSNOOP_EN (1 << 3) 274 # define GEN_IH_INT_EN (1 << 8) 275 #define INTERRUPT_CNTL2 0x546c 276 277 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 278 279 #define BIF_FB_EN 0x5490 280 #define FB_READ_EN (1 << 0) 281 #define FB_WRITE_EN (1 << 1) 282 283 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 284 285 #define GPU_HDP_FLUSH_REQ 0x54DC 286 #define GPU_HDP_FLUSH_DONE 0x54E0 287 #define CP0 (1 << 0) 288 #define CP1 (1 << 1) 289 #define CP2 (1 << 2) 290 #define CP3 (1 << 3) 291 #define CP4 (1 << 4) 292 #define CP5 (1 << 5) 293 #define CP6 (1 << 6) 294 #define CP7 (1 << 7) 295 #define CP8 (1 << 8) 296 #define CP9 (1 << 9) 297 #define SDMA0 (1 << 10) 298 #define SDMA1 (1 << 11) 299 300 /* 0x6b04, 0x7704, 0x10304, 0x10f04, 0x11b04, 0x12704 */ 301 #define LB_MEMORY_CTRL 0x6b04 302 #define LB_MEMORY_SIZE(x) ((x) << 0) 303 #define LB_MEMORY_CONFIG(x) ((x) << 20) 304 305 #define DPG_WATERMARK_MASK_CONTROL 0x6cc8 306 # define LATENCY_WATERMARK_MASK(x) ((x) << 8) 307 #define DPG_PIPE_LATENCY_CONTROL 0x6ccc 308 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 309 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 310 311 /* 0x6b24, 0x7724, 0x10324, 0x10f24, 0x11b24, 0x12724 */ 312 #define LB_VLINE_STATUS 0x6b24 313 # define VLINE_OCCURRED (1 << 0) 314 # define VLINE_ACK (1 << 4) 315 # define VLINE_STAT (1 << 12) 316 # define VLINE_INTERRUPT (1 << 16) 317 # define VLINE_INTERRUPT_TYPE (1 << 17) 318 /* 0x6b2c, 0x772c, 0x1032c, 0x10f2c, 0x11b2c, 0x1272c */ 319 #define LB_VBLANK_STATUS 0x6b2c 320 # define VBLANK_OCCURRED (1 << 0) 321 # define VBLANK_ACK (1 << 4) 322 # define VBLANK_STAT (1 << 12) 323 # define VBLANK_INTERRUPT (1 << 16) 324 # define VBLANK_INTERRUPT_TYPE (1 << 17) 325 326 /* 0x6b20, 0x7720, 0x10320, 0x10f20, 0x11b20, 0x12720 */ 327 #define LB_INTERRUPT_MASK 0x6b20 328 # define VBLANK_INTERRUPT_MASK (1 << 0) 329 # define VLINE_INTERRUPT_MASK (1 << 4) 330 # define VLINE2_INTERRUPT_MASK (1 << 8) 331 332 #define DISP_INTERRUPT_STATUS 0x60f4 333 # define LB_D1_VLINE_INTERRUPT (1 << 2) 334 # define LB_D1_VBLANK_INTERRUPT (1 << 3) 335 # define DC_HPD1_INTERRUPT (1 << 17) 336 # define DC_HPD1_RX_INTERRUPT (1 << 18) 337 # define DACA_AUTODETECT_INTERRUPT (1 << 22) 338 # define DACB_AUTODETECT_INTERRUPT (1 << 23) 339 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 340 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 341 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 342 # define LB_D2_VLINE_INTERRUPT (1 << 2) 343 # define LB_D2_VBLANK_INTERRUPT (1 << 3) 344 # define DC_HPD2_INTERRUPT (1 << 17) 345 # define DC_HPD2_RX_INTERRUPT (1 << 18) 346 # define DISP_TIMER_INTERRUPT (1 << 24) 347 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 348 # define LB_D3_VLINE_INTERRUPT (1 << 2) 349 # define LB_D3_VBLANK_INTERRUPT (1 << 3) 350 # define DC_HPD3_INTERRUPT (1 << 17) 351 # define DC_HPD3_RX_INTERRUPT (1 << 18) 352 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 353 # define LB_D4_VLINE_INTERRUPT (1 << 2) 354 # define LB_D4_VBLANK_INTERRUPT (1 << 3) 355 # define DC_HPD4_INTERRUPT (1 << 17) 356 # define DC_HPD4_RX_INTERRUPT (1 << 18) 357 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 358 # define LB_D5_VLINE_INTERRUPT (1 << 2) 359 # define LB_D5_VBLANK_INTERRUPT (1 << 3) 360 # define DC_HPD5_INTERRUPT (1 << 17) 361 # define DC_HPD5_RX_INTERRUPT (1 << 18) 362 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 363 # define LB_D6_VLINE_INTERRUPT (1 << 2) 364 # define LB_D6_VBLANK_INTERRUPT (1 << 3) 365 # define DC_HPD6_INTERRUPT (1 << 17) 366 # define DC_HPD6_RX_INTERRUPT (1 << 18) 367 #define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780 368 369 #define DAC_AUTODETECT_INT_CONTROL 0x67c8 370 371 #define DC_HPD1_INT_STATUS 0x601c 372 #define DC_HPD2_INT_STATUS 0x6028 373 #define DC_HPD3_INT_STATUS 0x6034 374 #define DC_HPD4_INT_STATUS 0x6040 375 #define DC_HPD5_INT_STATUS 0x604c 376 #define DC_HPD6_INT_STATUS 0x6058 377 # define DC_HPDx_INT_STATUS (1 << 0) 378 # define DC_HPDx_SENSE (1 << 1) 379 # define DC_HPDx_SENSE_DELAYED (1 << 4) 380 # define DC_HPDx_RX_INT_STATUS (1 << 8) 381 382 #define DC_HPD1_INT_CONTROL 0x6020 383 #define DC_HPD2_INT_CONTROL 0x602c 384 #define DC_HPD3_INT_CONTROL 0x6038 385 #define DC_HPD4_INT_CONTROL 0x6044 386 #define DC_HPD5_INT_CONTROL 0x6050 387 #define DC_HPD6_INT_CONTROL 0x605c 388 # define DC_HPDx_INT_ACK (1 << 0) 389 # define DC_HPDx_INT_POLARITY (1 << 8) 390 # define DC_HPDx_INT_EN (1 << 16) 391 # define DC_HPDx_RX_INT_ACK (1 << 20) 392 # define DC_HPDx_RX_INT_EN (1 << 24) 393 394 #define DC_HPD1_CONTROL 0x6024 395 #define DC_HPD2_CONTROL 0x6030 396 #define DC_HPD3_CONTROL 0x603c 397 #define DC_HPD4_CONTROL 0x6048 398 #define DC_HPD5_CONTROL 0x6054 399 #define DC_HPD6_CONTROL 0x6060 400 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 401 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 402 # define DC_HPDx_EN (1 << 28) 403 404 #define GRBM_CNTL 0x8000 405 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 406 407 #define GRBM_STATUS2 0x8008 408 #define ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000F 409 #define ME0PIPE1_CF_RQ_PENDING (1 << 4) 410 #define ME0PIPE1_PF_RQ_PENDING (1 << 5) 411 #define ME1PIPE0_RQ_PENDING (1 << 6) 412 #define ME1PIPE1_RQ_PENDING (1 << 7) 413 #define ME1PIPE2_RQ_PENDING (1 << 8) 414 #define ME1PIPE3_RQ_PENDING (1 << 9) 415 #define ME2PIPE0_RQ_PENDING (1 << 10) 416 #define ME2PIPE1_RQ_PENDING (1 << 11) 417 #define ME2PIPE2_RQ_PENDING (1 << 12) 418 #define ME2PIPE3_RQ_PENDING (1 << 13) 419 #define RLC_RQ_PENDING (1 << 14) 420 #define RLC_BUSY (1 << 24) 421 #define TC_BUSY (1 << 25) 422 #define CPF_BUSY (1 << 28) 423 #define CPC_BUSY (1 << 29) 424 #define CPG_BUSY (1 << 30) 425 426 #define GRBM_STATUS 0x8010 427 #define ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000F 428 #define SRBM_RQ_PENDING (1 << 5) 429 #define ME0PIPE0_CF_RQ_PENDING (1 << 7) 430 #define ME0PIPE0_PF_RQ_PENDING (1 << 8) 431 #define GDS_DMA_RQ_PENDING (1 << 9) 432 #define DB_CLEAN (1 << 12) 433 #define CB_CLEAN (1 << 13) 434 #define TA_BUSY (1 << 14) 435 #define GDS_BUSY (1 << 15) 436 #define WD_BUSY_NO_DMA (1 << 16) 437 #define VGT_BUSY (1 << 17) 438 #define IA_BUSY_NO_DMA (1 << 18) 439 #define IA_BUSY (1 << 19) 440 #define SX_BUSY (1 << 20) 441 #define WD_BUSY (1 << 21) 442 #define SPI_BUSY (1 << 22) 443 #define BCI_BUSY (1 << 23) 444 #define SC_BUSY (1 << 24) 445 #define PA_BUSY (1 << 25) 446 #define DB_BUSY (1 << 26) 447 #define CP_COHERENCY_BUSY (1 << 28) 448 #define CP_BUSY (1 << 29) 449 #define CB_BUSY (1 << 30) 450 #define GUI_ACTIVE (1 << 31) 451 #define GRBM_STATUS_SE0 0x8014 452 #define GRBM_STATUS_SE1 0x8018 453 #define GRBM_STATUS_SE2 0x8038 454 #define GRBM_STATUS_SE3 0x803C 455 #define SE_DB_CLEAN (1 << 1) 456 #define SE_CB_CLEAN (1 << 2) 457 #define SE_BCI_BUSY (1 << 22) 458 #define SE_VGT_BUSY (1 << 23) 459 #define SE_PA_BUSY (1 << 24) 460 #define SE_TA_BUSY (1 << 25) 461 #define SE_SX_BUSY (1 << 26) 462 #define SE_SPI_BUSY (1 << 27) 463 #define SE_SC_BUSY (1 << 29) 464 #define SE_DB_BUSY (1 << 30) 465 #define SE_CB_BUSY (1 << 31) 466 467 #define GRBM_SOFT_RESET 0x8020 468 #define SOFT_RESET_CP (1 << 0) /* All CP blocks */ 469 #define SOFT_RESET_RLC (1 << 2) /* RLC */ 470 #define SOFT_RESET_GFX (1 << 16) /* GFX */ 471 #define SOFT_RESET_CPF (1 << 17) /* CP fetcher shared by gfx and compute */ 472 #define SOFT_RESET_CPC (1 << 18) /* CP Compute (MEC1/2) */ 473 #define SOFT_RESET_CPG (1 << 19) /* CP GFX (PFP, ME, CE) */ 474 475 #define GRBM_INT_CNTL 0x8060 476 # define RDERR_INT_ENABLE (1 << 0) 477 # define GUI_IDLE_INT_ENABLE (1 << 19) 478 479 #define CP_CPC_STATUS 0x8210 480 #define CP_CPC_BUSY_STAT 0x8214 481 #define CP_CPC_STALLED_STAT1 0x8218 482 #define CP_CPF_STATUS 0x821c 483 #define CP_CPF_BUSY_STAT 0x8220 484 #define CP_CPF_STALLED_STAT1 0x8224 485 486 #define CP_MEC_CNTL 0x8234 487 #define MEC_ME2_HALT (1 << 28) 488 #define MEC_ME1_HALT (1 << 30) 489 490 #define CP_MEC_CNTL 0x8234 491 #define MEC_ME2_HALT (1 << 28) 492 #define MEC_ME1_HALT (1 << 30) 493 494 #define CP_STALLED_STAT3 0x8670 495 #define CP_STALLED_STAT1 0x8674 496 #define CP_STALLED_STAT2 0x8678 497 498 #define CP_STAT 0x8680 499 500 #define CP_ME_CNTL 0x86D8 501 #define CP_CE_HALT (1 << 24) 502 #define CP_PFP_HALT (1 << 26) 503 #define CP_ME_HALT (1 << 28) 504 505 #define CP_RB0_RPTR 0x8700 506 #define CP_RB_WPTR_DELAY 0x8704 507 508 #define CP_MEQ_THRESHOLDS 0x8764 509 #define MEQ1_START(x) ((x) << 0) 510 #define MEQ2_START(x) ((x) << 8) 511 512 #define VGT_VTX_VECT_EJECT_REG 0x88B0 513 514 #define VGT_CACHE_INVALIDATION 0x88C4 515 #define CACHE_INVALIDATION(x) ((x) << 0) 516 #define VC_ONLY 0 517 #define TC_ONLY 1 518 #define VC_AND_TC 2 519 #define AUTO_INVLD_EN(x) ((x) << 6) 520 #define NO_AUTO 0 521 #define ES_AUTO 1 522 #define GS_AUTO 2 523 #define ES_AND_GS_AUTO 3 524 525 #define VGT_GS_VERTEX_REUSE 0x88D4 526 527 #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc 528 #define INACTIVE_CUS_MASK 0xFFFF0000 529 #define INACTIVE_CUS_SHIFT 16 530 #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 531 532 #define PA_CL_ENHANCE 0x8A14 533 #define CLIP_VTX_REORDER_ENA (1 << 0) 534 #define NUM_CLIP_SEQ(x) ((x) << 1) 535 536 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 537 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 538 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 539 540 #define PA_SC_FIFO_SIZE 0x8BCC 541 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) 542 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) 543 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) 544 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) 545 546 #define PA_SC_ENHANCE 0x8BF0 547 #define ENABLE_PA_SC_OUT_OF_ORDER (1 << 0) 548 #define DISABLE_PA_SC_GUIDANCE (1 << 13) 549 550 #define SQ_CONFIG 0x8C00 551 552 #define SH_MEM_BASES 0x8C28 553 /* if PTR32, these are the bases for scratch and lds */ 554 #define PRIVATE_BASE(x) ((x) << 0) /* scratch */ 555 #define SHARED_BASE(x) ((x) << 16) /* LDS */ 556 #define SH_MEM_APE1_BASE 0x8C2C 557 /* if PTR32, this is the base location of GPUVM */ 558 #define SH_MEM_APE1_LIMIT 0x8C30 559 /* if PTR32, this is the upper limit of GPUVM */ 560 #define SH_MEM_CONFIG 0x8C34 561 #define PTR32 (1 << 0) 562 #define ALIGNMENT_MODE(x) ((x) << 2) 563 #define SH_MEM_ALIGNMENT_MODE_DWORD 0 564 #define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1 565 #define SH_MEM_ALIGNMENT_MODE_STRICT 2 566 #define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3 567 #define DEFAULT_MTYPE(x) ((x) << 4) 568 #define APE1_MTYPE(x) ((x) << 7) 569 570 #define SX_DEBUG_1 0x9060 571 572 #define SPI_CONFIG_CNTL 0x9100 573 574 #define SPI_CONFIG_CNTL_1 0x913C 575 #define VTX_DONE_DELAY(x) ((x) << 0) 576 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 577 578 #define TA_CNTL_AUX 0x9508 579 580 #define DB_DEBUG 0x9830 581 #define DB_DEBUG2 0x9834 582 #define DB_DEBUG3 0x9838 583 584 #define CC_RB_BACKEND_DISABLE 0x98F4 585 #define BACKEND_DISABLE(x) ((x) << 16) 586 #define GB_ADDR_CONFIG 0x98F8 587 #define NUM_PIPES(x) ((x) << 0) 588 #define NUM_PIPES_MASK 0x00000007 589 #define NUM_PIPES_SHIFT 0 590 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 591 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 592 #define PIPE_INTERLEAVE_SIZE_SHIFT 4 593 #define NUM_SHADER_ENGINES(x) ((x) << 12) 594 #define NUM_SHADER_ENGINES_MASK 0x00003000 595 #define NUM_SHADER_ENGINES_SHIFT 12 596 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 597 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 598 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 599 #define ROW_SIZE(x) ((x) << 28) 600 #define ROW_SIZE_MASK 0x30000000 601 #define ROW_SIZE_SHIFT 28 602 603 #define GB_TILE_MODE0 0x9910 604 # define ARRAY_MODE(x) ((x) << 2) 605 # define ARRAY_LINEAR_GENERAL 0 606 # define ARRAY_LINEAR_ALIGNED 1 607 # define ARRAY_1D_TILED_THIN1 2 608 # define ARRAY_2D_TILED_THIN1 4 609 # define ARRAY_PRT_TILED_THIN1 5 610 # define ARRAY_PRT_2D_TILED_THIN1 6 611 # define PIPE_CONFIG(x) ((x) << 6) 612 # define ADDR_SURF_P2 0 613 # define ADDR_SURF_P4_8x16 4 614 # define ADDR_SURF_P4_16x16 5 615 # define ADDR_SURF_P4_16x32 6 616 # define ADDR_SURF_P4_32x32 7 617 # define ADDR_SURF_P8_16x16_8x16 8 618 # define ADDR_SURF_P8_16x32_8x16 9 619 # define ADDR_SURF_P8_32x32_8x16 10 620 # define ADDR_SURF_P8_16x32_16x16 11 621 # define ADDR_SURF_P8_32x32_16x16 12 622 # define ADDR_SURF_P8_32x32_16x32 13 623 # define ADDR_SURF_P8_32x64_32x32 14 624 # define TILE_SPLIT(x) ((x) << 11) 625 # define ADDR_SURF_TILE_SPLIT_64B 0 626 # define ADDR_SURF_TILE_SPLIT_128B 1 627 # define ADDR_SURF_TILE_SPLIT_256B 2 628 # define ADDR_SURF_TILE_SPLIT_512B 3 629 # define ADDR_SURF_TILE_SPLIT_1KB 4 630 # define ADDR_SURF_TILE_SPLIT_2KB 5 631 # define ADDR_SURF_TILE_SPLIT_4KB 6 632 # define MICRO_TILE_MODE_NEW(x) ((x) << 22) 633 # define ADDR_SURF_DISPLAY_MICRO_TILING 0 634 # define ADDR_SURF_THIN_MICRO_TILING 1 635 # define ADDR_SURF_DEPTH_MICRO_TILING 2 636 # define ADDR_SURF_ROTATED_MICRO_TILING 3 637 # define SAMPLE_SPLIT(x) ((x) << 25) 638 # define ADDR_SURF_SAMPLE_SPLIT_1 0 639 # define ADDR_SURF_SAMPLE_SPLIT_2 1 640 # define ADDR_SURF_SAMPLE_SPLIT_4 2 641 # define ADDR_SURF_SAMPLE_SPLIT_8 3 642 643 #define GB_MACROTILE_MODE0 0x9990 644 # define BANK_WIDTH(x) ((x) << 0) 645 # define ADDR_SURF_BANK_WIDTH_1 0 646 # define ADDR_SURF_BANK_WIDTH_2 1 647 # define ADDR_SURF_BANK_WIDTH_4 2 648 # define ADDR_SURF_BANK_WIDTH_8 3 649 # define BANK_HEIGHT(x) ((x) << 2) 650 # define ADDR_SURF_BANK_HEIGHT_1 0 651 # define ADDR_SURF_BANK_HEIGHT_2 1 652 # define ADDR_SURF_BANK_HEIGHT_4 2 653 # define ADDR_SURF_BANK_HEIGHT_8 3 654 # define MACRO_TILE_ASPECT(x) ((x) << 4) 655 # define ADDR_SURF_MACRO_ASPECT_1 0 656 # define ADDR_SURF_MACRO_ASPECT_2 1 657 # define ADDR_SURF_MACRO_ASPECT_4 2 658 # define ADDR_SURF_MACRO_ASPECT_8 3 659 # define NUM_BANKS(x) ((x) << 6) 660 # define ADDR_SURF_2_BANK 0 661 # define ADDR_SURF_4_BANK 1 662 # define ADDR_SURF_8_BANK 2 663 # define ADDR_SURF_16_BANK 3 664 665 #define CB_HW_CONTROL 0x9A10 666 667 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 668 #define BACKEND_DISABLE_MASK 0x00FF0000 669 #define BACKEND_DISABLE_SHIFT 16 670 671 #define TCP_CHAN_STEER_LO 0xac0c 672 #define TCP_CHAN_STEER_HI 0xac10 673 674 #define TC_CFG_L1_LOAD_POLICY0 0xAC68 675 #define TC_CFG_L1_LOAD_POLICY1 0xAC6C 676 #define TC_CFG_L1_STORE_POLICY 0xAC70 677 #define TC_CFG_L2_LOAD_POLICY0 0xAC74 678 #define TC_CFG_L2_LOAD_POLICY1 0xAC78 679 #define TC_CFG_L2_STORE_POLICY0 0xAC7C 680 #define TC_CFG_L2_STORE_POLICY1 0xAC80 681 #define TC_CFG_L2_ATOMIC_POLICY 0xAC84 682 #define TC_CFG_L1_VOLATILE 0xAC88 683 #define TC_CFG_L2_VOLATILE 0xAC8C 684 685 #define CP_RB0_BASE 0xC100 686 #define CP_RB0_CNTL 0xC104 687 #define RB_BUFSZ(x) ((x) << 0) 688 #define RB_BLKSZ(x) ((x) << 8) 689 #define BUF_SWAP_32BIT (2 << 16) 690 #define RB_NO_UPDATE (1 << 27) 691 #define RB_RPTR_WR_ENA (1 << 31) 692 693 #define CP_RB0_RPTR_ADDR 0xC10C 694 #define RB_RPTR_SWAP_32BIT (2 << 0) 695 #define CP_RB0_RPTR_ADDR_HI 0xC110 696 #define CP_RB0_WPTR 0xC114 697 698 #define CP_DEVICE_ID 0xC12C 699 #define CP_ENDIAN_SWAP 0xC140 700 #define CP_RB_VMID 0xC144 701 702 #define CP_PFP_UCODE_ADDR 0xC150 703 #define CP_PFP_UCODE_DATA 0xC154 704 #define CP_ME_RAM_RADDR 0xC158 705 #define CP_ME_RAM_WADDR 0xC15C 706 #define CP_ME_RAM_DATA 0xC160 707 708 #define CP_CE_UCODE_ADDR 0xC168 709 #define CP_CE_UCODE_DATA 0xC16C 710 #define CP_MEC_ME1_UCODE_ADDR 0xC170 711 #define CP_MEC_ME1_UCODE_DATA 0xC174 712 #define CP_MEC_ME2_UCODE_ADDR 0xC178 713 #define CP_MEC_ME2_UCODE_DATA 0xC17C 714 715 #define CP_INT_CNTL_RING0 0xC1A8 716 # define CNTX_BUSY_INT_ENABLE (1 << 19) 717 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 718 # define PRIV_INSTR_INT_ENABLE (1 << 22) 719 # define PRIV_REG_INT_ENABLE (1 << 23) 720 # define TIME_STAMP_INT_ENABLE (1 << 26) 721 # define CP_RINGID2_INT_ENABLE (1 << 29) 722 # define CP_RINGID1_INT_ENABLE (1 << 30) 723 # define CP_RINGID0_INT_ENABLE (1 << 31) 724 725 #define CP_INT_STATUS_RING0 0xC1B4 726 # define PRIV_INSTR_INT_STAT (1 << 22) 727 # define PRIV_REG_INT_STAT (1 << 23) 728 # define TIME_STAMP_INT_STAT (1 << 26) 729 # define CP_RINGID2_INT_STAT (1 << 29) 730 # define CP_RINGID1_INT_STAT (1 << 30) 731 # define CP_RINGID0_INT_STAT (1 << 31) 732 733 #define CP_CPF_DEBUG 0xC200 734 735 #define CP_PQ_WPTR_POLL_CNTL 0xC20C 736 #define WPTR_POLL_EN (1 << 31) 737 738 #define CP_ME1_PIPE0_INT_CNTL 0xC214 739 #define CP_ME1_PIPE1_INT_CNTL 0xC218 740 #define CP_ME1_PIPE2_INT_CNTL 0xC21C 741 #define CP_ME1_PIPE3_INT_CNTL 0xC220 742 #define CP_ME2_PIPE0_INT_CNTL 0xC224 743 #define CP_ME2_PIPE1_INT_CNTL 0xC228 744 #define CP_ME2_PIPE2_INT_CNTL 0xC22C 745 #define CP_ME2_PIPE3_INT_CNTL 0xC230 746 # define DEQUEUE_REQUEST_INT_ENABLE (1 << 13) 747 # define WRM_POLL_TIMEOUT_INT_ENABLE (1 << 17) 748 # define PRIV_REG_INT_ENABLE (1 << 23) 749 # define TIME_STAMP_INT_ENABLE (1 << 26) 750 # define GENERIC2_INT_ENABLE (1 << 29) 751 # define GENERIC1_INT_ENABLE (1 << 30) 752 # define GENERIC0_INT_ENABLE (1 << 31) 753 #define CP_ME1_PIPE0_INT_STATUS 0xC214 754 #define CP_ME1_PIPE1_INT_STATUS 0xC218 755 #define CP_ME1_PIPE2_INT_STATUS 0xC21C 756 #define CP_ME1_PIPE3_INT_STATUS 0xC220 757 #define CP_ME2_PIPE0_INT_STATUS 0xC224 758 #define CP_ME2_PIPE1_INT_STATUS 0xC228 759 #define CP_ME2_PIPE2_INT_STATUS 0xC22C 760 #define CP_ME2_PIPE3_INT_STATUS 0xC230 761 # define DEQUEUE_REQUEST_INT_STATUS (1 << 13) 762 # define WRM_POLL_TIMEOUT_INT_STATUS (1 << 17) 763 # define PRIV_REG_INT_STATUS (1 << 23) 764 # define TIME_STAMP_INT_STATUS (1 << 26) 765 # define GENERIC2_INT_STATUS (1 << 29) 766 # define GENERIC1_INT_STATUS (1 << 30) 767 # define GENERIC0_INT_STATUS (1 << 31) 768 769 #define CP_MAX_CONTEXT 0xC2B8 770 771 #define CP_RB0_BASE_HI 0xC2C4 772 773 #define RLC_CNTL 0xC300 774 # define RLC_ENABLE (1 << 0) 775 776 #define RLC_MC_CNTL 0xC30C 777 778 #define RLC_LB_CNTR_MAX 0xC348 779 780 #define RLC_LB_CNTL 0xC364 781 782 #define RLC_LB_CNTR_INIT 0xC36C 783 784 #define RLC_SAVE_AND_RESTORE_BASE 0xC374 785 #define RLC_DRIVER_DMA_STATUS 0xC378 786 787 #define RLC_GPM_UCODE_ADDR 0xC388 788 #define RLC_GPM_UCODE_DATA 0xC38C 789 #define RLC_GPU_CLOCK_COUNT_LSB 0xC390 790 #define RLC_GPU_CLOCK_COUNT_MSB 0xC394 791 #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC398 792 #define RLC_UCODE_CNTL 0xC39C 793 794 #define RLC_CGCG_CGLS_CTRL 0xC424 795 796 #define RLC_LB_INIT_CU_MASK 0xC43C 797 798 #define RLC_LB_PARAMS 0xC444 799 800 #define RLC_SERDES_CU_MASTER_BUSY 0xC484 801 #define RLC_SERDES_NONCU_MASTER_BUSY 0xC488 802 # define SE_MASTER_BUSY_MASK 0x0000ffff 803 # define GC_MASTER_BUSY (1 << 16) 804 # define TC0_MASTER_BUSY (1 << 17) 805 # define TC1_MASTER_BUSY (1 << 18) 806 807 #define RLC_GPM_SCRATCH_ADDR 0xC4B0 808 #define RLC_GPM_SCRATCH_DATA 0xC4B4 809 810 #define CP_HPD_EOP_BASE_ADDR 0xC904 811 #define CP_HPD_EOP_BASE_ADDR_HI 0xC908 812 #define CP_HPD_EOP_VMID 0xC90C 813 #define CP_HPD_EOP_CONTROL 0xC910 814 #define EOP_SIZE(x) ((x) << 0) 815 #define EOP_SIZE_MASK (0x3f << 0) 816 #define CP_MQD_BASE_ADDR 0xC914 817 #define CP_MQD_BASE_ADDR_HI 0xC918 818 #define CP_HQD_ACTIVE 0xC91C 819 #define CP_HQD_VMID 0xC920 820 821 #define CP_HQD_PQ_BASE 0xC934 822 #define CP_HQD_PQ_BASE_HI 0xC938 823 #define CP_HQD_PQ_RPTR 0xC93C 824 #define CP_HQD_PQ_RPTR_REPORT_ADDR 0xC940 825 #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI 0xC944 826 #define CP_HQD_PQ_WPTR_POLL_ADDR 0xC948 827 #define CP_HQD_PQ_WPTR_POLL_ADDR_HI 0xC94C 828 #define CP_HQD_PQ_DOORBELL_CONTROL 0xC950 829 #define DOORBELL_OFFSET(x) ((x) << 2) 830 #define DOORBELL_OFFSET_MASK (0x1fffff << 2) 831 #define DOORBELL_SOURCE (1 << 28) 832 #define DOORBELL_SCHD_HIT (1 << 29) 833 #define DOORBELL_EN (1 << 30) 834 #define DOORBELL_HIT (1 << 31) 835 #define CP_HQD_PQ_WPTR 0xC954 836 #define CP_HQD_PQ_CONTROL 0xC958 837 #define QUEUE_SIZE(x) ((x) << 0) 838 #define QUEUE_SIZE_MASK (0x3f << 0) 839 #define RPTR_BLOCK_SIZE(x) ((x) << 8) 840 #define RPTR_BLOCK_SIZE_MASK (0x3f << 8) 841 #define PQ_VOLATILE (1 << 26) 842 #define NO_UPDATE_RPTR (1 << 27) 843 #define UNORD_DISPATCH (1 << 28) 844 #define ROQ_PQ_IB_FLIP (1 << 29) 845 #define PRIV_STATE (1 << 30) 846 #define KMD_QUEUE (1 << 31) 847 848 #define CP_HQD_DEQUEUE_REQUEST 0xC974 849 850 #define CP_MQD_CONTROL 0xC99C 851 #define MQD_VMID(x) ((x) << 0) 852 #define MQD_VMID_MASK (0xf << 0) 853 854 #define PA_SC_RASTER_CONFIG 0x28350 855 # define RASTER_CONFIG_RB_MAP_0 0 856 # define RASTER_CONFIG_RB_MAP_1 1 857 # define RASTER_CONFIG_RB_MAP_2 2 858 # define RASTER_CONFIG_RB_MAP_3 3 859 860 #define VGT_EVENT_INITIATOR 0x28a90 861 # define SAMPLE_STREAMOUTSTATS1 (1 << 0) 862 # define SAMPLE_STREAMOUTSTATS2 (2 << 0) 863 # define SAMPLE_STREAMOUTSTATS3 (3 << 0) 864 # define CACHE_FLUSH_TS (4 << 0) 865 # define CACHE_FLUSH (6 << 0) 866 # define CS_PARTIAL_FLUSH (7 << 0) 867 # define VGT_STREAMOUT_RESET (10 << 0) 868 # define END_OF_PIPE_INCR_DE (11 << 0) 869 # define END_OF_PIPE_IB_END (12 << 0) 870 # define RST_PIX_CNT (13 << 0) 871 # define VS_PARTIAL_FLUSH (15 << 0) 872 # define PS_PARTIAL_FLUSH (16 << 0) 873 # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0) 874 # define ZPASS_DONE (21 << 0) 875 # define CACHE_FLUSH_AND_INV_EVENT (22 << 0) 876 # define PERFCOUNTER_START (23 << 0) 877 # define PERFCOUNTER_STOP (24 << 0) 878 # define PIPELINESTAT_START (25 << 0) 879 # define PIPELINESTAT_STOP (26 << 0) 880 # define PERFCOUNTER_SAMPLE (27 << 0) 881 # define SAMPLE_PIPELINESTAT (30 << 0) 882 # define SO_VGT_STREAMOUT_FLUSH (31 << 0) 883 # define SAMPLE_STREAMOUTSTATS (32 << 0) 884 # define RESET_VTX_CNT (33 << 0) 885 # define VGT_FLUSH (36 << 0) 886 # define BOTTOM_OF_PIPE_TS (40 << 0) 887 # define DB_CACHE_FLUSH_AND_INV (42 << 0) 888 # define FLUSH_AND_INV_DB_DATA_TS (43 << 0) 889 # define FLUSH_AND_INV_DB_META (44 << 0) 890 # define FLUSH_AND_INV_CB_DATA_TS (45 << 0) 891 # define FLUSH_AND_INV_CB_META (46 << 0) 892 # define CS_DONE (47 << 0) 893 # define PS_DONE (48 << 0) 894 # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0) 895 # define THREAD_TRACE_START (51 << 0) 896 # define THREAD_TRACE_STOP (52 << 0) 897 # define THREAD_TRACE_FLUSH (54 << 0) 898 # define THREAD_TRACE_FINISH (55 << 0) 899 # define PIXEL_PIPE_STAT_CONTROL (56 << 0) 900 # define PIXEL_PIPE_STAT_DUMP (57 << 0) 901 # define PIXEL_PIPE_STAT_RESET (58 << 0) 902 903 #define SCRATCH_REG0 0x30100 904 #define SCRATCH_REG1 0x30104 905 #define SCRATCH_REG2 0x30108 906 #define SCRATCH_REG3 0x3010C 907 #define SCRATCH_REG4 0x30110 908 #define SCRATCH_REG5 0x30114 909 #define SCRATCH_REG6 0x30118 910 #define SCRATCH_REG7 0x3011C 911 912 #define SCRATCH_UMSK 0x30140 913 #define SCRATCH_ADDR 0x30144 914 915 #define CP_SEM_WAIT_TIMER 0x301BC 916 917 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x301C8 918 919 #define CP_WAIT_REG_MEM_TIMEOUT 0x301D0 920 921 #define GRBM_GFX_INDEX 0x30800 922 #define INSTANCE_INDEX(x) ((x) << 0) 923 #define SH_INDEX(x) ((x) << 8) 924 #define SE_INDEX(x) ((x) << 16) 925 #define SH_BROADCAST_WRITES (1 << 29) 926 #define INSTANCE_BROADCAST_WRITES (1 << 30) 927 #define SE_BROADCAST_WRITES (1 << 31) 928 929 #define VGT_ESGS_RING_SIZE 0x30900 930 #define VGT_GSVS_RING_SIZE 0x30904 931 #define VGT_PRIMITIVE_TYPE 0x30908 932 #define VGT_INDEX_TYPE 0x3090C 933 934 #define VGT_NUM_INDICES 0x30930 935 #define VGT_NUM_INSTANCES 0x30934 936 #define VGT_TF_RING_SIZE 0x30938 937 #define VGT_HS_OFFCHIP_PARAM 0x3093C 938 #define VGT_TF_MEMORY_BASE 0x30940 939 940 #define PA_SU_LINE_STIPPLE_VALUE 0x30a00 941 #define PA_SC_LINE_STIPPLE_STATE 0x30a04 942 943 #define SQC_CACHES 0x30d20 944 945 #define CP_PERFMON_CNTL 0x36020 946 947 #define CGTS_TCC_DISABLE 0x3c00c 948 #define CGTS_USER_TCC_DISABLE 0x3c010 949 #define TCC_DISABLE_MASK 0xFFFF0000 950 #define TCC_DISABLE_SHIFT 16 951 952 #define CB_CGTT_SCLK_CTRL 0x3c2a0 953 954 /* 955 * PM4 956 */ 957 #define PACKET_TYPE0 0 958 #define PACKET_TYPE1 1 959 #define PACKET_TYPE2 2 960 #define PACKET_TYPE3 3 961 962 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 963 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 964 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 965 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 966 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 967 (((reg) >> 2) & 0xFFFF) | \ 968 ((n) & 0x3FFF) << 16) 969 #define CP_PACKET2 0x80000000 970 #define PACKET2_PAD_SHIFT 0 971 #define PACKET2_PAD_MASK (0x3fffffff << 0) 972 973 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 974 975 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 976 (((op) & 0xFF) << 8) | \ 977 ((n) & 0x3FFF) << 16) 978 979 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 980 981 /* Packet 3 types */ 982 #define PACKET3_NOP 0x10 983 #define PACKET3_SET_BASE 0x11 984 #define PACKET3_BASE_INDEX(x) ((x) << 0) 985 #define CE_PARTITION_BASE 3 986 #define PACKET3_CLEAR_STATE 0x12 987 #define PACKET3_INDEX_BUFFER_SIZE 0x13 988 #define PACKET3_DISPATCH_DIRECT 0x15 989 #define PACKET3_DISPATCH_INDIRECT 0x16 990 #define PACKET3_ATOMIC_GDS 0x1D 991 #define PACKET3_ATOMIC_MEM 0x1E 992 #define PACKET3_OCCLUSION_QUERY 0x1F 993 #define PACKET3_SET_PREDICATION 0x20 994 #define PACKET3_REG_RMW 0x21 995 #define PACKET3_COND_EXEC 0x22 996 #define PACKET3_PRED_EXEC 0x23 997 #define PACKET3_DRAW_INDIRECT 0x24 998 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 999 #define PACKET3_INDEX_BASE 0x26 1000 #define PACKET3_DRAW_INDEX_2 0x27 1001 #define PACKET3_CONTEXT_CONTROL 0x28 1002 #define PACKET3_INDEX_TYPE 0x2A 1003 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 1004 #define PACKET3_DRAW_INDEX_AUTO 0x2D 1005 #define PACKET3_NUM_INSTANCES 0x2F 1006 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 1007 #define PACKET3_INDIRECT_BUFFER_CONST 0x33 1008 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 1009 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 1010 #define PACKET3_DRAW_PREAMBLE 0x36 1011 #define PACKET3_WRITE_DATA 0x37 1012 #define WRITE_DATA_DST_SEL(x) ((x) << 8) 1013 /* 0 - register 1014 * 1 - memory (sync - via GRBM) 1015 * 2 - gl2 1016 * 3 - gds 1017 * 4 - reserved 1018 * 5 - memory (async - direct) 1019 */ 1020 #define WR_ONE_ADDR (1 << 16) 1021 #define WR_CONFIRM (1 << 20) 1022 #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 1023 /* 0 - LRU 1024 * 1 - Stream 1025 */ 1026 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 1027 /* 0 - me 1028 * 1 - pfp 1029 * 2 - ce 1030 */ 1031 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 1032 #define PACKET3_MEM_SEMAPHORE 0x39 1033 # define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 1034 # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 1035 # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ 1036 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 1037 # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 1038 #define PACKET3_COPY_DW 0x3B 1039 #define PACKET3_WAIT_REG_MEM 0x3C 1040 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 1041 /* 0 - always 1042 * 1 - < 1043 * 2 - <= 1044 * 3 - == 1045 * 4 - != 1046 * 5 - >= 1047 * 6 - > 1048 */ 1049 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 1050 /* 0 - reg 1051 * 1 - mem 1052 */ 1053 #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 1054 /* 0 - wait_reg_mem 1055 * 1 - wr_wait_wr_reg 1056 */ 1057 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 1058 /* 0 - me 1059 * 1 - pfp 1060 */ 1061 #define PACKET3_INDIRECT_BUFFER 0x3F 1062 #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) 1063 #define INDIRECT_BUFFER_VALID (1 << 23) 1064 #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 1065 /* 0 - LRU 1066 * 1 - Stream 1067 * 2 - Bypass 1068 */ 1069 #define PACKET3_COPY_DATA 0x40 1070 #define PACKET3_PFP_SYNC_ME 0x42 1071 #define PACKET3_SURFACE_SYNC 0x43 1072 # define PACKET3_DEST_BASE_0_ENA (1 << 0) 1073 # define PACKET3_DEST_BASE_1_ENA (1 << 1) 1074 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1075 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 1076 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 1077 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 1078 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 1079 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 1080 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 1081 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 1082 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 1083 # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) 1084 # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ 1085 # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ 1086 # define PACKET3_DEST_BASE_2_ENA (1 << 19) 1087 # define PACKET3_DEST_BASE_3_ENA (1 << 21) 1088 # define PACKET3_TCL1_ACTION_ENA (1 << 22) 1089 # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ 1090 # define PACKET3_CB_ACTION_ENA (1 << 25) 1091 # define PACKET3_DB_ACTION_ENA (1 << 26) 1092 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 1093 # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) 1094 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 1095 #define PACKET3_COND_WRITE 0x45 1096 #define PACKET3_EVENT_WRITE 0x46 1097 #define EVENT_TYPE(x) ((x) << 0) 1098 #define EVENT_INDEX(x) ((x) << 8) 1099 /* 0 - any non-TS event 1100 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 1101 * 2 - SAMPLE_PIPELINESTAT 1102 * 3 - SAMPLE_STREAMOUTSTAT* 1103 * 4 - *S_PARTIAL_FLUSH 1104 * 5 - EOP events 1105 * 6 - EOS events 1106 */ 1107 #define PACKET3_EVENT_WRITE_EOP 0x47 1108 #define EOP_TCL1_VOL_ACTION_EN (1 << 12) 1109 #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ 1110 #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ 1111 #define EOP_TCL1_ACTION_EN (1 << 16) 1112 #define EOP_TC_ACTION_EN (1 << 17) /* L2 */ 1113 #define EOP_CACHE_POLICY(x) ((x) << 25) 1114 /* 0 - LRU 1115 * 1 - Stream 1116 * 2 - Bypass 1117 */ 1118 #define EOP_TCL2_VOLATILE (1 << 27) 1119 #define DATA_SEL(x) ((x) << 29) 1120 /* 0 - discard 1121 * 1 - send low 32bit data 1122 * 2 - send 64bit data 1123 * 3 - send 64bit GPU counter value 1124 * 4 - send 64bit sys counter value 1125 */ 1126 #define INT_SEL(x) ((x) << 24) 1127 /* 0 - none 1128 * 1 - interrupt only (DATA_SEL = 0) 1129 * 2 - interrupt when data write is confirmed 1130 */ 1131 #define DST_SEL(x) ((x) << 16) 1132 /* 0 - MC 1133 * 1 - TC/L2 1134 */ 1135 #define PACKET3_EVENT_WRITE_EOS 0x48 1136 #define PACKET3_RELEASE_MEM 0x49 1137 #define PACKET3_PREAMBLE_CNTL 0x4A 1138 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 1139 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 1140 #define PACKET3_DMA_DATA 0x50 1141 #define PACKET3_AQUIRE_MEM 0x58 1142 #define PACKET3_REWIND 0x59 1143 #define PACKET3_LOAD_UCONFIG_REG 0x5E 1144 #define PACKET3_LOAD_SH_REG 0x5F 1145 #define PACKET3_LOAD_CONFIG_REG 0x60 1146 #define PACKET3_LOAD_CONTEXT_REG 0x61 1147 #define PACKET3_SET_CONFIG_REG 0x68 1148 #define PACKET3_SET_CONFIG_REG_START 0x00008000 1149 #define PACKET3_SET_CONFIG_REG_END 0x0000b000 1150 #define PACKET3_SET_CONTEXT_REG 0x69 1151 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 1152 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 1153 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 1154 #define PACKET3_SET_SH_REG 0x76 1155 #define PACKET3_SET_SH_REG_START 0x0000b000 1156 #define PACKET3_SET_SH_REG_END 0x0000c000 1157 #define PACKET3_SET_SH_REG_OFFSET 0x77 1158 #define PACKET3_SET_QUEUE_REG 0x78 1159 #define PACKET3_SET_UCONFIG_REG 0x79 1160 #define PACKET3_SET_UCONFIG_REG_START 0x00030000 1161 #define PACKET3_SET_UCONFIG_REG_END 0x00031000 1162 #define PACKET3_SCRATCH_RAM_WRITE 0x7D 1163 #define PACKET3_SCRATCH_RAM_READ 0x7E 1164 #define PACKET3_LOAD_CONST_RAM 0x80 1165 #define PACKET3_WRITE_CONST_RAM 0x81 1166 #define PACKET3_DUMP_CONST_RAM 0x83 1167 #define PACKET3_INCREMENT_CE_COUNTER 0x84 1168 #define PACKET3_INCREMENT_DE_COUNTER 0x85 1169 #define PACKET3_WAIT_ON_CE_COUNTER 0x86 1170 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 1171 #define PACKET3_SWITCH_BUFFER 0x8B 1172 1173 /* SDMA - first instance at 0xd000, second at 0xd800 */ 1174 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ 1175 #define SDMA1_REGISTER_OFFSET 0x800 /* not a register */ 1176 1177 #define SDMA0_UCODE_ADDR 0xD000 1178 #define SDMA0_UCODE_DATA 0xD004 1179 1180 #define SDMA0_CNTL 0xD010 1181 # define TRAP_ENABLE (1 << 0) 1182 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 1183 # define SEM_WAIT_INT_ENABLE (1 << 2) 1184 # define DATA_SWAP_ENABLE (1 << 3) 1185 # define FENCE_SWAP_ENABLE (1 << 4) 1186 # define AUTO_CTXSW_ENABLE (1 << 18) 1187 # define CTXEMPTY_INT_ENABLE (1 << 28) 1188 1189 #define SDMA0_TILING_CONFIG 0xD018 1190 1191 #define SDMA0_SEM_INCOMPLETE_TIMER_CNTL 0xD020 1192 #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0xD024 1193 1194 #define SDMA0_STATUS_REG 0xd034 1195 # define SDMA_IDLE (1 << 0) 1196 1197 #define SDMA0_ME_CNTL 0xD048 1198 # define SDMA_HALT (1 << 0) 1199 1200 #define SDMA0_GFX_RB_CNTL 0xD200 1201 # define SDMA_RB_ENABLE (1 << 0) 1202 # define SDMA_RB_SIZE(x) ((x) << 1) /* log2 */ 1203 # define SDMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 1204 # define SDMA_RPTR_WRITEBACK_ENABLE (1 << 12) 1205 # define SDMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 1206 # define SDMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 1207 #define SDMA0_GFX_RB_BASE 0xD204 1208 #define SDMA0_GFX_RB_BASE_HI 0xD208 1209 #define SDMA0_GFX_RB_RPTR 0xD20C 1210 #define SDMA0_GFX_RB_WPTR 0xD210 1211 1212 #define SDMA0_GFX_RB_RPTR_ADDR_HI 0xD220 1213 #define SDMA0_GFX_RB_RPTR_ADDR_LO 0xD224 1214 #define SDMA0_GFX_IB_CNTL 0xD228 1215 # define SDMA_IB_ENABLE (1 << 0) 1216 # define SDMA_IB_SWAP_ENABLE (1 << 4) 1217 # define SDMA_SWITCH_INSIDE_IB (1 << 8) 1218 # define SDMA_CMD_VMID(x) ((x) << 16) 1219 1220 #define SDMA0_GFX_VIRTUAL_ADDR 0xD29C 1221 #define SDMA0_GFX_APE1_CNTL 0xD2A0 1222 1223 #define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \ 1224 (((sub_op) & 0xFF) << 8) | \ 1225 (((op) & 0xFF) << 0)) 1226 /* sDMA opcodes */ 1227 #define SDMA_OPCODE_NOP 0 1228 #define SDMA_OPCODE_COPY 1 1229 # define SDMA_COPY_SUB_OPCODE_LINEAR 0 1230 # define SDMA_COPY_SUB_OPCODE_TILED 1 1231 # define SDMA_COPY_SUB_OPCODE_SOA 3 1232 # define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4 1233 # define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5 1234 # define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6 1235 #define SDMA_OPCODE_WRITE 2 1236 # define SDMA_WRITE_SUB_OPCODE_LINEAR 0 1237 # define SDMA_WRTIE_SUB_OPCODE_TILED 1 1238 #define SDMA_OPCODE_INDIRECT_BUFFER 4 1239 #define SDMA_OPCODE_FENCE 5 1240 #define SDMA_OPCODE_TRAP 6 1241 #define SDMA_OPCODE_SEMAPHORE 7 1242 # define SDMA_SEMAPHORE_EXTRA_O (1 << 13) 1243 /* 0 - increment 1244 * 1 - write 1 1245 */ 1246 # define SDMA_SEMAPHORE_EXTRA_S (1 << 14) 1247 /* 0 - wait 1248 * 1 - signal 1249 */ 1250 # define SDMA_SEMAPHORE_EXTRA_M (1 << 15) 1251 /* mailbox */ 1252 #define SDMA_OPCODE_POLL_REG_MEM 8 1253 # define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10) 1254 /* 0 - wait_reg_mem 1255 * 1 - wr_wait_wr_reg 1256 */ 1257 # define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12) 1258 /* 0 - always 1259 * 1 - < 1260 * 2 - <= 1261 * 3 - == 1262 * 4 - != 1263 * 5 - >= 1264 * 6 - > 1265 */ 1266 # define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15) 1267 /* 0 = register 1268 * 1 = memory 1269 */ 1270 #define SDMA_OPCODE_COND_EXEC 9 1271 #define SDMA_OPCODE_CONSTANT_FILL 11 1272 # define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14) 1273 /* 0 = byte fill 1274 * 2 = DW fill 1275 */ 1276 #define SDMA_OPCODE_GENERATE_PTE_PDE 12 1277 #define SDMA_OPCODE_TIMESTAMP 13 1278 # define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0 1279 # define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1 1280 # define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2 1281 #define SDMA_OPCODE_SRBM_WRITE 14 1282 # define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12) 1283 /* byte mask */ 1284 1285 /* UVD */ 1286 1287 #define UVD_UDEC_ADDR_CONFIG 0xef4c 1288 #define UVD_UDEC_DB_ADDR_CONFIG 0xef50 1289 #define UVD_UDEC_DBW_ADDR_CONFIG 0xef54 1290 1291 #define UVD_LMI_EXT40_ADDR 0xf498 1292 #define UVD_LMI_ADDR_EXT 0xf594 1293 #define UVD_VCPU_CACHE_OFFSET0 0xf608 1294 #define UVD_VCPU_CACHE_SIZE0 0xf60c 1295 #define UVD_VCPU_CACHE_OFFSET1 0xf610 1296 #define UVD_VCPU_CACHE_SIZE1 0xf614 1297 #define UVD_VCPU_CACHE_OFFSET2 0xf618 1298 #define UVD_VCPU_CACHE_SIZE2 0xf61c 1299 1300 #define UVD_RBC_RB_RPTR 0xf690 1301 #define UVD_RBC_RB_WPTR 0xf694 1302 1303 /* UVD clocks */ 1304 1305 #define CG_DCLK_CNTL 0xC050009C 1306 # define DCLK_DIVIDER_MASK 0x7f 1307 # define DCLK_DIR_CNTL_EN (1 << 8) 1308 #define CG_DCLK_STATUS 0xC05000A0 1309 # define DCLK_STATUS (1 << 0) 1310 #define CG_VCLK_CNTL 0xC05000A4 1311 #define CG_VCLK_STATUS 0xC05000A8 1312 1313 #endif 1314