1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "radeon.h" 27 #include "radeon_asic.h" 28 #include "radeon_trace.h" 29 #include "cikd.h" 30 31 /* sdma */ 32 #define CIK_SDMA_UCODE_SIZE 1050 33 #define CIK_SDMA_UCODE_VERSION 64 34 35 u32 cik_gpu_check_soft_reset(struct radeon_device *rdev); 36 37 /* 38 * sDMA - System DMA 39 * Starting with CIK, the GPU has new asynchronous 40 * DMA engines. These engines are used for compute 41 * and gfx. There are two DMA engines (SDMA0, SDMA1) 42 * and each one supports 1 ring buffer used for gfx 43 * and 2 queues used for compute. 44 * 45 * The programming model is very similar to the CP 46 * (ring buffer, IBs, etc.), but sDMA has it's own 47 * packet format that is different from the PM4 format 48 * used by the CP. sDMA supports copying data, writing 49 * embedded data, solid fills, and a number of other 50 * things. It also has support for tiling/detiling of 51 * buffers. 52 */ 53 54 /** 55 * cik_sdma_get_rptr - get the current read pointer 56 * 57 * @rdev: radeon_device pointer 58 * @ring: radeon ring pointer 59 * 60 * Get the current rptr from the hardware (CIK+). 61 */ 62 uint32_t cik_sdma_get_rptr(struct radeon_device *rdev, 63 struct radeon_ring *ring) 64 { 65 u32 rptr, reg; 66 67 if (rdev->wb.enabled) { 68 rptr = rdev->wb.wb[ring->rptr_offs/4]; 69 } else { 70 if (ring->idx == R600_RING_TYPE_DMA_INDEX) 71 reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET; 72 else 73 reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET; 74 75 rptr = RREG32(reg); 76 } 77 78 return (rptr & 0x3fffc) >> 2; 79 } 80 81 /** 82 * cik_sdma_get_wptr - get the current write pointer 83 * 84 * @rdev: radeon_device pointer 85 * @ring: radeon ring pointer 86 * 87 * Get the current wptr from the hardware (CIK+). 88 */ 89 uint32_t cik_sdma_get_wptr(struct radeon_device *rdev, 90 struct radeon_ring *ring) 91 { 92 u32 reg; 93 94 if (ring->idx == R600_RING_TYPE_DMA_INDEX) 95 reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; 96 else 97 reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; 98 99 return (RREG32(reg) & 0x3fffc) >> 2; 100 } 101 102 /** 103 * cik_sdma_set_wptr - commit the write pointer 104 * 105 * @rdev: radeon_device pointer 106 * @ring: radeon ring pointer 107 * 108 * Write the wptr back to the hardware (CIK+). 109 */ 110 void cik_sdma_set_wptr(struct radeon_device *rdev, 111 struct radeon_ring *ring) 112 { 113 u32 reg; 114 115 if (ring->idx == R600_RING_TYPE_DMA_INDEX) 116 reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; 117 else 118 reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; 119 120 WREG32(reg, (ring->wptr << 2) & 0x3fffc); 121 } 122 123 /** 124 * cik_sdma_ring_ib_execute - Schedule an IB on the DMA engine 125 * 126 * @rdev: radeon_device pointer 127 * @ib: IB object to schedule 128 * 129 * Schedule an IB in the DMA ring (CIK). 130 */ 131 void cik_sdma_ring_ib_execute(struct radeon_device *rdev, 132 struct radeon_ib *ib) 133 { 134 struct radeon_ring *ring = &rdev->ring[ib->ring]; 135 u32 extra_bits = (ib->vm ? ib->vm->id : 0) & 0xf; 136 137 if (rdev->wb.enabled) { 138 u32 next_rptr = ring->wptr + 5; 139 while ((next_rptr & 7) != 4) 140 next_rptr++; 141 next_rptr += 4; 142 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); 143 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 144 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); 145 radeon_ring_write(ring, 1); /* number of DWs to follow */ 146 radeon_ring_write(ring, next_rptr); 147 } 148 149 /* IB packet must end on a 8 DW boundary */ 150 while ((ring->wptr & 7) != 4) 151 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); 152 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); 153 radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ 154 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); 155 radeon_ring_write(ring, ib->length_dw); 156 157 } 158 159 /** 160 * cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring 161 * 162 * @rdev: radeon_device pointer 163 * @ridx: radeon ring index 164 * 165 * Emit an hdp flush packet on the requested DMA ring. 166 */ 167 static void cik_sdma_hdp_flush_ring_emit(struct radeon_device *rdev, 168 int ridx) 169 { 170 struct radeon_ring *ring = &rdev->ring[ridx]; 171 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | 172 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ 173 u32 ref_and_mask; 174 175 if (ridx == R600_RING_TYPE_DMA_INDEX) 176 ref_and_mask = SDMA0; 177 else 178 ref_and_mask = SDMA1; 179 180 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); 181 radeon_ring_write(ring, GPU_HDP_FLUSH_DONE); 182 radeon_ring_write(ring, GPU_HDP_FLUSH_REQ); 183 radeon_ring_write(ring, ref_and_mask); /* reference */ 184 radeon_ring_write(ring, ref_and_mask); /* mask */ 185 radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ 186 } 187 188 /** 189 * cik_sdma_fence_ring_emit - emit a fence on the DMA ring 190 * 191 * @rdev: radeon_device pointer 192 * @fence: radeon fence object 193 * 194 * Add a DMA fence packet to the ring to write 195 * the fence seq number and DMA trap packet to generate 196 * an interrupt if needed (CIK). 197 */ 198 void cik_sdma_fence_ring_emit(struct radeon_device *rdev, 199 struct radeon_fence *fence) 200 { 201 struct radeon_ring *ring = &rdev->ring[fence->ring]; 202 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 203 204 /* write the fence */ 205 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); 206 radeon_ring_write(ring, lower_32_bits(addr)); 207 radeon_ring_write(ring, upper_32_bits(addr)); 208 radeon_ring_write(ring, fence->seq); 209 /* generate an interrupt */ 210 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); 211 /* flush HDP */ 212 cik_sdma_hdp_flush_ring_emit(rdev, fence->ring); 213 } 214 215 /** 216 * cik_sdma_semaphore_ring_emit - emit a semaphore on the dma ring 217 * 218 * @rdev: radeon_device pointer 219 * @ring: radeon_ring structure holding ring information 220 * @semaphore: radeon semaphore object 221 * @emit_wait: wait or signal semaphore 222 * 223 * Add a DMA semaphore packet to the ring wait on or signal 224 * other rings (CIK). 225 */ 226 bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev, 227 struct radeon_ring *ring, 228 struct radeon_semaphore *semaphore, 229 bool emit_wait) 230 { 231 u64 addr = semaphore->gpu_addr; 232 u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S; 233 234 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits)); 235 radeon_ring_write(ring, addr & 0xfffffff8); 236 radeon_ring_write(ring, upper_32_bits(addr)); 237 238 return true; 239 } 240 241 /** 242 * cik_sdma_gfx_stop - stop the gfx async dma engines 243 * 244 * @rdev: radeon_device pointer 245 * 246 * Stop the gfx async dma ring buffers (CIK). 247 */ 248 static void cik_sdma_gfx_stop(struct radeon_device *rdev) 249 { 250 u32 rb_cntl, reg_offset; 251 int i; 252 253 if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) || 254 (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX)) 255 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 256 257 for (i = 0; i < 2; i++) { 258 if (i == 0) 259 reg_offset = SDMA0_REGISTER_OFFSET; 260 else 261 reg_offset = SDMA1_REGISTER_OFFSET; 262 rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset); 263 rb_cntl &= ~SDMA_RB_ENABLE; 264 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); 265 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0); 266 } 267 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false; 268 rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false; 269 } 270 271 /** 272 * cik_sdma_rlc_stop - stop the compute async dma engines 273 * 274 * @rdev: radeon_device pointer 275 * 276 * Stop the compute async dma queues (CIK). 277 */ 278 static void cik_sdma_rlc_stop(struct radeon_device *rdev) 279 { 280 /* XXX todo */ 281 } 282 283 /** 284 * cik_sdma_enable - stop the async dma engines 285 * 286 * @rdev: radeon_device pointer 287 * @enable: enable/disable the DMA MEs. 288 * 289 * Halt or unhalt the async dma engines (CIK). 290 */ 291 void cik_sdma_enable(struct radeon_device *rdev, bool enable) 292 { 293 u32 me_cntl, reg_offset; 294 int i; 295 296 if (enable == false) { 297 cik_sdma_gfx_stop(rdev); 298 cik_sdma_rlc_stop(rdev); 299 } 300 301 for (i = 0; i < 2; i++) { 302 if (i == 0) 303 reg_offset = SDMA0_REGISTER_OFFSET; 304 else 305 reg_offset = SDMA1_REGISTER_OFFSET; 306 me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset); 307 if (enable) 308 me_cntl &= ~SDMA_HALT; 309 else 310 me_cntl |= SDMA_HALT; 311 WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl); 312 } 313 } 314 315 /** 316 * cik_sdma_gfx_resume - setup and start the async dma engines 317 * 318 * @rdev: radeon_device pointer 319 * 320 * Set up the gfx DMA ring buffers and enable them (CIK). 321 * Returns 0 for success, error for failure. 322 */ 323 static int cik_sdma_gfx_resume(struct radeon_device *rdev) 324 { 325 struct radeon_ring *ring; 326 u32 rb_cntl, ib_cntl; 327 u32 rb_bufsz; 328 u32 reg_offset, wb_offset; 329 int i, r; 330 331 for (i = 0; i < 2; i++) { 332 if (i == 0) { 333 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 334 reg_offset = SDMA0_REGISTER_OFFSET; 335 wb_offset = R600_WB_DMA_RPTR_OFFSET; 336 } else { 337 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; 338 reg_offset = SDMA1_REGISTER_OFFSET; 339 wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET; 340 } 341 342 WREG32(SDMA0_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0); 343 WREG32(SDMA0_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0); 344 345 /* Set ring buffer size in dwords */ 346 rb_bufsz = order_base_2(ring->ring_size / 4); 347 rb_cntl = rb_bufsz << 1; 348 #ifdef __BIG_ENDIAN 349 rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE; 350 #endif 351 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); 352 353 /* Initialize the ring buffer's read and write pointers */ 354 WREG32(SDMA0_GFX_RB_RPTR + reg_offset, 0); 355 WREG32(SDMA0_GFX_RB_WPTR + reg_offset, 0); 356 357 /* set the wb address whether it's enabled or not */ 358 WREG32(SDMA0_GFX_RB_RPTR_ADDR_HI + reg_offset, 359 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 360 WREG32(SDMA0_GFX_RB_RPTR_ADDR_LO + reg_offset, 361 ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); 362 363 if (rdev->wb.enabled) 364 rb_cntl |= SDMA_RPTR_WRITEBACK_ENABLE; 365 366 WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8); 367 WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40); 368 369 ring->wptr = 0; 370 WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2); 371 372 /* enable DMA RB */ 373 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE); 374 375 ib_cntl = SDMA_IB_ENABLE; 376 #ifdef __BIG_ENDIAN 377 ib_cntl |= SDMA_IB_SWAP_ENABLE; 378 #endif 379 /* enable DMA IBs */ 380 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, ib_cntl); 381 382 ring->ready = true; 383 384 r = radeon_ring_test(rdev, ring->idx, ring); 385 if (r) { 386 ring->ready = false; 387 return r; 388 } 389 } 390 391 if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) || 392 (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX)) 393 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 394 395 return 0; 396 } 397 398 /** 399 * cik_sdma_rlc_resume - setup and start the async dma engines 400 * 401 * @rdev: radeon_device pointer 402 * 403 * Set up the compute DMA queues and enable them (CIK). 404 * Returns 0 for success, error for failure. 405 */ 406 static int cik_sdma_rlc_resume(struct radeon_device *rdev) 407 { 408 /* XXX todo */ 409 return 0; 410 } 411 412 /** 413 * cik_sdma_load_microcode - load the sDMA ME ucode 414 * 415 * @rdev: radeon_device pointer 416 * 417 * Loads the sDMA0/1 ucode. 418 * Returns 0 for success, -EINVAL if the ucode is not available. 419 */ 420 static int cik_sdma_load_microcode(struct radeon_device *rdev) 421 { 422 const __be32 *fw_data; 423 int i; 424 425 if (!rdev->sdma_fw) 426 return -EINVAL; 427 428 /* halt the MEs */ 429 cik_sdma_enable(rdev, false); 430 431 /* sdma0 */ 432 fw_data = (const __be32 *)rdev->sdma_fw->data; 433 WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); 434 for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++) 435 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++)); 436 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); 437 438 /* sdma1 */ 439 fw_data = (const __be32 *)rdev->sdma_fw->data; 440 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); 441 for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++) 442 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++)); 443 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); 444 445 WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); 446 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); 447 return 0; 448 } 449 450 /** 451 * cik_sdma_resume - setup and start the async dma engines 452 * 453 * @rdev: radeon_device pointer 454 * 455 * Set up the DMA engines and enable them (CIK). 456 * Returns 0 for success, error for failure. 457 */ 458 int cik_sdma_resume(struct radeon_device *rdev) 459 { 460 int r; 461 462 /* Reset dma */ 463 WREG32(SRBM_SOFT_RESET, SOFT_RESET_SDMA | SOFT_RESET_SDMA1); 464 RREG32(SRBM_SOFT_RESET); 465 udelay(50); 466 WREG32(SRBM_SOFT_RESET, 0); 467 RREG32(SRBM_SOFT_RESET); 468 469 r = cik_sdma_load_microcode(rdev); 470 if (r) 471 return r; 472 473 /* unhalt the MEs */ 474 cik_sdma_enable(rdev, true); 475 476 /* start the gfx rings and rlc compute queues */ 477 r = cik_sdma_gfx_resume(rdev); 478 if (r) 479 return r; 480 r = cik_sdma_rlc_resume(rdev); 481 if (r) 482 return r; 483 484 return 0; 485 } 486 487 /** 488 * cik_sdma_fini - tear down the async dma engines 489 * 490 * @rdev: radeon_device pointer 491 * 492 * Stop the async dma engines and free the rings (CIK). 493 */ 494 void cik_sdma_fini(struct radeon_device *rdev) 495 { 496 /* halt the MEs */ 497 cik_sdma_enable(rdev, false); 498 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]); 499 radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]); 500 /* XXX - compute dma queue tear down */ 501 } 502 503 /** 504 * cik_copy_dma - copy pages using the DMA engine 505 * 506 * @rdev: radeon_device pointer 507 * @src_offset: src GPU address 508 * @dst_offset: dst GPU address 509 * @num_gpu_pages: number of GPU pages to xfer 510 * @fence: radeon fence object 511 * 512 * Copy GPU paging using the DMA engine (CIK). 513 * Used by the radeon ttm implementation to move pages if 514 * registered as the asic copy callback. 515 */ 516 int cik_copy_dma(struct radeon_device *rdev, 517 uint64_t src_offset, uint64_t dst_offset, 518 unsigned num_gpu_pages, 519 struct radeon_fence **fence) 520 { 521 struct radeon_semaphore *sem = NULL; 522 int ring_index = rdev->asic->copy.dma_ring_index; 523 struct radeon_ring *ring = &rdev->ring[ring_index]; 524 u32 size_in_bytes, cur_size_in_bytes; 525 int i, num_loops; 526 int r = 0; 527 528 r = radeon_semaphore_create(rdev, &sem); 529 if (r) { 530 DRM_ERROR("radeon: moving bo (%d).\n", r); 531 return r; 532 } 533 534 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); 535 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff); 536 r = radeon_ring_lock(rdev, ring, num_loops * 7 + 14); 537 if (r) { 538 DRM_ERROR("radeon: moving bo (%d).\n", r); 539 radeon_semaphore_free(rdev, &sem, NULL); 540 return r; 541 } 542 543 radeon_semaphore_sync_to(sem, *fence); 544 radeon_semaphore_sync_rings(rdev, sem, ring->idx); 545 546 for (i = 0; i < num_loops; i++) { 547 cur_size_in_bytes = size_in_bytes; 548 if (cur_size_in_bytes > 0x1fffff) 549 cur_size_in_bytes = 0x1fffff; 550 size_in_bytes -= cur_size_in_bytes; 551 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0)); 552 radeon_ring_write(ring, cur_size_in_bytes); 553 radeon_ring_write(ring, 0); /* src/dst endian swap */ 554 radeon_ring_write(ring, lower_32_bits(src_offset)); 555 radeon_ring_write(ring, upper_32_bits(src_offset)); 556 radeon_ring_write(ring, lower_32_bits(dst_offset)); 557 radeon_ring_write(ring, upper_32_bits(dst_offset)); 558 src_offset += cur_size_in_bytes; 559 dst_offset += cur_size_in_bytes; 560 } 561 562 r = radeon_fence_emit(rdev, fence, ring->idx); 563 if (r) { 564 radeon_ring_unlock_undo(rdev, ring); 565 radeon_semaphore_free(rdev, &sem, NULL); 566 return r; 567 } 568 569 radeon_ring_unlock_commit(rdev, ring); 570 radeon_semaphore_free(rdev, &sem, *fence); 571 572 return r; 573 } 574 575 /** 576 * cik_sdma_ring_test - simple async dma engine test 577 * 578 * @rdev: radeon_device pointer 579 * @ring: radeon_ring structure holding ring information 580 * 581 * Test the DMA engine by writing using it to write an 582 * value to memory. (CIK). 583 * Returns 0 for success, error for failure. 584 */ 585 int cik_sdma_ring_test(struct radeon_device *rdev, 586 struct radeon_ring *ring) 587 { 588 unsigned i; 589 int r; 590 void __iomem *ptr = (void *)rdev->vram_scratch.ptr; 591 u32 tmp; 592 593 if (!ptr) { 594 DRM_ERROR("invalid vram scratch pointer\n"); 595 return -EINVAL; 596 } 597 598 tmp = 0xCAFEDEAD; 599 writel(tmp, ptr); 600 601 r = radeon_ring_lock(rdev, ring, 5); 602 if (r) { 603 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r); 604 return r; 605 } 606 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); 607 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc); 608 radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr)); 609 radeon_ring_write(ring, 1); /* number of DWs to follow */ 610 radeon_ring_write(ring, 0xDEADBEEF); 611 radeon_ring_unlock_commit(rdev, ring); 612 613 for (i = 0; i < rdev->usec_timeout; i++) { 614 tmp = readl(ptr); 615 if (tmp == 0xDEADBEEF) 616 break; 617 DRM_UDELAY(1); 618 } 619 620 if (i < rdev->usec_timeout) { 621 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 622 } else { 623 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n", 624 ring->idx, tmp); 625 r = -EINVAL; 626 } 627 return r; 628 } 629 630 /** 631 * cik_sdma_ib_test - test an IB on the DMA engine 632 * 633 * @rdev: radeon_device pointer 634 * @ring: radeon_ring structure holding ring information 635 * 636 * Test a simple IB in the DMA ring (CIK). 637 * Returns 0 on success, error on failure. 638 */ 639 int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 640 { 641 struct radeon_ib ib; 642 unsigned i; 643 int r; 644 void __iomem *ptr = (void *)rdev->vram_scratch.ptr; 645 u32 tmp = 0; 646 647 if (!ptr) { 648 DRM_ERROR("invalid vram scratch pointer\n"); 649 return -EINVAL; 650 } 651 652 tmp = 0xCAFEDEAD; 653 writel(tmp, ptr); 654 655 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 656 if (r) { 657 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 658 return r; 659 } 660 661 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 662 ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc; 663 ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr); 664 ib.ptr[3] = 1; 665 ib.ptr[4] = 0xDEADBEEF; 666 ib.length_dw = 5; 667 668 r = radeon_ib_schedule(rdev, &ib, NULL); 669 if (r) { 670 radeon_ib_free(rdev, &ib); 671 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 672 return r; 673 } 674 r = radeon_fence_wait(ib.fence, false); 675 if (r) { 676 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 677 return r; 678 } 679 for (i = 0; i < rdev->usec_timeout; i++) { 680 tmp = readl(ptr); 681 if (tmp == 0xDEADBEEF) 682 break; 683 DRM_UDELAY(1); 684 } 685 if (i < rdev->usec_timeout) { 686 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 687 } else { 688 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp); 689 r = -EINVAL; 690 } 691 radeon_ib_free(rdev, &ib); 692 return r; 693 } 694 695 /** 696 * cik_sdma_is_lockup - Check if the DMA engine is locked up 697 * 698 * @rdev: radeon_device pointer 699 * @ring: radeon_ring structure holding ring information 700 * 701 * Check if the async DMA engine is locked up (CIK). 702 * Returns true if the engine appears to be locked up, false if not. 703 */ 704 bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 705 { 706 u32 reset_mask = cik_gpu_check_soft_reset(rdev); 707 u32 mask; 708 709 if (ring->idx == R600_RING_TYPE_DMA_INDEX) 710 mask = RADEON_RESET_DMA; 711 else 712 mask = RADEON_RESET_DMA1; 713 714 if (!(reset_mask & mask)) { 715 radeon_ring_lockup_update(rdev, ring); 716 return false; 717 } 718 return radeon_ring_test_lockup(rdev, ring); 719 } 720 721 /** 722 * cik_sdma_vm_set_page - update the page tables using sDMA 723 * 724 * @rdev: radeon_device pointer 725 * @ib: indirect buffer to fill with commands 726 * @pe: addr of the page entry 727 * @addr: dst addr to write into pe 728 * @count: number of page entries to update 729 * @incr: increase next addr by incr bytes 730 * @flags: access flags 731 * 732 * Update the page tables using sDMA (CIK). 733 */ 734 void cik_sdma_vm_set_page(struct radeon_device *rdev, 735 struct radeon_ib *ib, 736 uint64_t pe, 737 uint64_t addr, unsigned count, 738 uint32_t incr, uint32_t flags) 739 { 740 uint64_t value; 741 unsigned ndw; 742 743 trace_radeon_vm_set_page(pe, addr, count, incr, flags); 744 745 if (flags == R600_PTE_GART) { 746 uint64_t src = rdev->gart.table_addr + (addr >> 12) * 8; 747 while (count) { 748 unsigned bytes = count * 8; 749 if (bytes > 0x1FFFF8) 750 bytes = 0x1FFFF8; 751 752 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 753 ib->ptr[ib->length_dw++] = bytes; 754 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 755 ib->ptr[ib->length_dw++] = lower_32_bits(src); 756 ib->ptr[ib->length_dw++] = upper_32_bits(src); 757 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 758 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 759 760 pe += bytes; 761 src += bytes; 762 count -= bytes / 8; 763 } 764 } else if (flags & R600_PTE_SYSTEM) { 765 while (count) { 766 ndw = count * 2; 767 if (ndw > 0xFFFFE) 768 ndw = 0xFFFFE; 769 770 /* for non-physically contiguous pages (system) */ 771 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 772 ib->ptr[ib->length_dw++] = pe; 773 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 774 ib->ptr[ib->length_dw++] = ndw; 775 for (; ndw > 0; ndw -= 2, --count, pe += 8) { 776 value = radeon_vm_map_gart(rdev, addr); 777 value &= 0xFFFFFFFFFFFFF000ULL; 778 addr += incr; 779 value |= flags; 780 ib->ptr[ib->length_dw++] = value; 781 ib->ptr[ib->length_dw++] = upper_32_bits(value); 782 } 783 } 784 } else { 785 while (count) { 786 ndw = count; 787 if (ndw > 0x7FFFF) 788 ndw = 0x7FFFF; 789 790 if (flags & R600_PTE_VALID) 791 value = addr; 792 else 793 value = 0; 794 /* for physically contiguous pages (vram) */ 795 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0); 796 ib->ptr[ib->length_dw++] = pe; /* dst addr */ 797 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 798 ib->ptr[ib->length_dw++] = flags; /* mask */ 799 ib->ptr[ib->length_dw++] = 0; 800 ib->ptr[ib->length_dw++] = value; /* value */ 801 ib->ptr[ib->length_dw++] = upper_32_bits(value); 802 ib->ptr[ib->length_dw++] = incr; /* increment size */ 803 ib->ptr[ib->length_dw++] = 0; 804 ib->ptr[ib->length_dw++] = ndw; /* number of entries */ 805 pe += ndw * 8; 806 addr += ndw * incr; 807 count -= ndw; 808 } 809 } 810 while (ib->length_dw & 0x7) 811 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0); 812 } 813 814 /** 815 * cik_dma_vm_flush - cik vm flush using sDMA 816 * 817 * @rdev: radeon_device pointer 818 * 819 * Update the page table base and flush the VM TLB 820 * using sDMA (CIK). 821 */ 822 void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) 823 { 824 struct radeon_ring *ring = &rdev->ring[ridx]; 825 826 if (vm == NULL) 827 return; 828 829 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 830 if (vm->id < 8) { 831 radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2); 832 } else { 833 radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2); 834 } 835 radeon_ring_write(ring, vm->pd_gpu_addr >> 12); 836 837 /* update SH_MEM_* regs */ 838 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 839 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); 840 radeon_ring_write(ring, VMID(vm->id)); 841 842 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 843 radeon_ring_write(ring, SH_MEM_BASES >> 2); 844 radeon_ring_write(ring, 0); 845 846 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 847 radeon_ring_write(ring, SH_MEM_CONFIG >> 2); 848 radeon_ring_write(ring, 0); 849 850 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 851 radeon_ring_write(ring, SH_MEM_APE1_BASE >> 2); 852 radeon_ring_write(ring, 1); 853 854 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 855 radeon_ring_write(ring, SH_MEM_APE1_LIMIT >> 2); 856 radeon_ring_write(ring, 0); 857 858 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 859 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); 860 radeon_ring_write(ring, VMID(0)); 861 862 /* flush HDP */ 863 cik_sdma_hdp_flush_ring_emit(rdev, ridx); 864 865 /* flush TLB */ 866 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 867 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); 868 radeon_ring_write(ring, 1 << vm->id); 869 } 870 871