1 /* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #ifndef __CIK_REG_H__ 25 #define __CIK_REG_H__ 26 27 #define CIK_DIDT_IND_INDEX 0xca00 28 #define CIK_DIDT_IND_DATA 0xca04 29 30 #define CIK_DC_GPIO_HPD_MASK 0x65b0 31 #define CIK_DC_GPIO_HPD_A 0x65b4 32 #define CIK_DC_GPIO_HPD_EN 0x65b8 33 #define CIK_DC_GPIO_HPD_Y 0x65bc 34 35 #define CIK_GRPH_CONTROL 0x6804 36 # define CIK_GRPH_DEPTH(x) (((x) & 0x3) << 0) 37 # define CIK_GRPH_DEPTH_8BPP 0 38 # define CIK_GRPH_DEPTH_16BPP 1 39 # define CIK_GRPH_DEPTH_32BPP 2 40 # define CIK_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2) 41 # define CIK_ADDR_SURF_2_BANK 0 42 # define CIK_ADDR_SURF_4_BANK 1 43 # define CIK_ADDR_SURF_8_BANK 2 44 # define CIK_ADDR_SURF_16_BANK 3 45 # define CIK_GRPH_Z(x) (((x) & 0x3) << 4) 46 # define CIK_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6) 47 # define CIK_ADDR_SURF_BANK_WIDTH_1 0 48 # define CIK_ADDR_SURF_BANK_WIDTH_2 1 49 # define CIK_ADDR_SURF_BANK_WIDTH_4 2 50 # define CIK_ADDR_SURF_BANK_WIDTH_8 3 51 # define CIK_GRPH_FORMAT(x) (((x) & 0x7) << 8) 52 /* 8 BPP */ 53 # define CIK_GRPH_FORMAT_INDEXED 0 54 /* 16 BPP */ 55 # define CIK_GRPH_FORMAT_ARGB1555 0 56 # define CIK_GRPH_FORMAT_ARGB565 1 57 # define CIK_GRPH_FORMAT_ARGB4444 2 58 # define CIK_GRPH_FORMAT_AI88 3 59 # define CIK_GRPH_FORMAT_MONO16 4 60 # define CIK_GRPH_FORMAT_BGRA5551 5 61 /* 32 BPP */ 62 # define CIK_GRPH_FORMAT_ARGB8888 0 63 # define CIK_GRPH_FORMAT_ARGB2101010 1 64 # define CIK_GRPH_FORMAT_32BPP_DIG 2 65 # define CIK_GRPH_FORMAT_8B_ARGB2101010 3 66 # define CIK_GRPH_FORMAT_BGRA1010102 4 67 # define CIK_GRPH_FORMAT_8B_BGRA1010102 5 68 # define CIK_GRPH_FORMAT_RGB111110 6 69 # define CIK_GRPH_FORMAT_BGR101111 7 70 # define CIK_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11) 71 # define CIK_ADDR_SURF_BANK_HEIGHT_1 0 72 # define CIK_ADDR_SURF_BANK_HEIGHT_2 1 73 # define CIK_ADDR_SURF_BANK_HEIGHT_4 2 74 # define CIK_ADDR_SURF_BANK_HEIGHT_8 3 75 # define CIK_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13) 76 # define CIK_ADDR_SURF_TILE_SPLIT_64B 0 77 # define CIK_ADDR_SURF_TILE_SPLIT_128B 1 78 # define CIK_ADDR_SURF_TILE_SPLIT_256B 2 79 # define CIK_ADDR_SURF_TILE_SPLIT_512B 3 80 # define CIK_ADDR_SURF_TILE_SPLIT_1KB 4 81 # define CIK_ADDR_SURF_TILE_SPLIT_2KB 5 82 # define CIK_ADDR_SURF_TILE_SPLIT_4KB 6 83 # define CIK_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18) 84 # define CIK_ADDR_SURF_MACRO_TILE_ASPECT_1 0 85 # define CIK_ADDR_SURF_MACRO_TILE_ASPECT_2 1 86 # define CIK_ADDR_SURF_MACRO_TILE_ASPECT_4 2 87 # define CIK_ADDR_SURF_MACRO_TILE_ASPECT_8 3 88 # define CIK_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20) 89 # define CIK_GRPH_ARRAY_LINEAR_GENERAL 0 90 # define CIK_GRPH_ARRAY_LINEAR_ALIGNED 1 91 # define CIK_GRPH_ARRAY_1D_TILED_THIN1 2 92 # define CIK_GRPH_ARRAY_2D_TILED_THIN1 4 93 # define CIK_GRPH_PIPE_CONFIG(x) (((x) & 0x1f) << 24) 94 # define CIK_ADDR_SURF_P2 0 95 # define CIK_ADDR_SURF_P4_8x16 4 96 # define CIK_ADDR_SURF_P4_16x16 5 97 # define CIK_ADDR_SURF_P4_16x32 6 98 # define CIK_ADDR_SURF_P4_32x32 7 99 # define CIK_ADDR_SURF_P8_16x16_8x16 8 100 # define CIK_ADDR_SURF_P8_16x32_8x16 9 101 # define CIK_ADDR_SURF_P8_32x32_8x16 10 102 # define CIK_ADDR_SURF_P8_16x32_16x16 11 103 # define CIK_ADDR_SURF_P8_32x32_16x16 12 104 # define CIK_ADDR_SURF_P8_32x32_16x32 13 105 # define CIK_ADDR_SURF_P8_32x64_32x32 14 106 # define CIK_GRPH_MICRO_TILE_MODE(x) (((x) & 0x7) << 29) 107 # define CIK_DISPLAY_MICRO_TILING 0 108 # define CIK_THIN_MICRO_TILING 1 109 # define CIK_DEPTH_MICRO_TILING 2 110 # define CIK_ROTATED_MICRO_TILING 4 111 112 /* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */ 113 #define CIK_CUR_CONTROL 0x6998 114 # define CIK_CURSOR_EN (1 << 0) 115 # define CIK_CURSOR_MODE(x) (((x) & 0x3) << 8) 116 # define CIK_CURSOR_MONO 0 117 # define CIK_CURSOR_24_1 1 118 # define CIK_CURSOR_24_8_PRE_MULT 2 119 # define CIK_CURSOR_24_8_UNPRE_MULT 3 120 # define CIK_CURSOR_2X_MAGNIFY (1 << 16) 121 # define CIK_CURSOR_FORCE_MC_ON (1 << 20) 122 # define CIK_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24) 123 # define CIK_CURSOR_URGENT_ALWAYS 0 124 # define CIK_CURSOR_URGENT_1_8 1 125 # define CIK_CURSOR_URGENT_1_4 2 126 # define CIK_CURSOR_URGENT_3_8 3 127 # define CIK_CURSOR_URGENT_1_2 4 128 #define CIK_CUR_SURFACE_ADDRESS 0x699c 129 # define CIK_CUR_SURFACE_ADDRESS_MASK 0xfffff000 130 #define CIK_CUR_SIZE 0x69a0 131 #define CIK_CUR_SURFACE_ADDRESS_HIGH 0x69a4 132 #define CIK_CUR_POSITION 0x69a8 133 #define CIK_CUR_HOT_SPOT 0x69ac 134 #define CIK_CUR_COLOR1 0x69b0 135 #define CIK_CUR_COLOR2 0x69b4 136 #define CIK_CUR_UPDATE 0x69b8 137 # define CIK_CURSOR_UPDATE_PENDING (1 << 0) 138 # define CIK_CURSOR_UPDATE_TAKEN (1 << 1) 139 # define CIK_CURSOR_UPDATE_LOCK (1 << 16) 140 # define CIK_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24) 141 142 #define CIK_ALPHA_CONTROL 0x6af0 143 # define CIK_CURSOR_ALPHA_BLND_ENA (1 << 1) 144 145 #define CIK_LB_DATA_FORMAT 0x6b00 146 # define CIK_INTERLEAVE_EN (1 << 3) 147 148 #define CIK_LB_DESKTOP_HEIGHT 0x6b0c 149 150 #define CP_HQD_IQ_RPTR 0xC970u 151 #define AQL_ENABLE (1U << 0) 152 153 #define IDLE (1 << 2) 154 155 struct cik_mqd { 156 uint32_t header; 157 uint32_t compute_dispatch_initiator; 158 uint32_t compute_dim_x; 159 uint32_t compute_dim_y; 160 uint32_t compute_dim_z; 161 uint32_t compute_start_x; 162 uint32_t compute_start_y; 163 uint32_t compute_start_z; 164 uint32_t compute_num_thread_x; 165 uint32_t compute_num_thread_y; 166 uint32_t compute_num_thread_z; 167 uint32_t compute_pipelinestat_enable; 168 uint32_t compute_perfcount_enable; 169 uint32_t compute_pgm_lo; 170 uint32_t compute_pgm_hi; 171 uint32_t compute_tba_lo; 172 uint32_t compute_tba_hi; 173 uint32_t compute_tma_lo; 174 uint32_t compute_tma_hi; 175 uint32_t compute_pgm_rsrc1; 176 uint32_t compute_pgm_rsrc2; 177 uint32_t compute_vmid; 178 uint32_t compute_resource_limits; 179 uint32_t compute_static_thread_mgmt_se0; 180 uint32_t compute_static_thread_mgmt_se1; 181 uint32_t compute_tmpring_size; 182 uint32_t compute_static_thread_mgmt_se2; 183 uint32_t compute_static_thread_mgmt_se3; 184 uint32_t compute_restart_x; 185 uint32_t compute_restart_y; 186 uint32_t compute_restart_z; 187 uint32_t compute_thread_trace_enable; 188 uint32_t compute_misc_reserved; 189 uint32_t compute_user_data_0; 190 uint32_t compute_user_data_1; 191 uint32_t compute_user_data_2; 192 uint32_t compute_user_data_3; 193 uint32_t compute_user_data_4; 194 uint32_t compute_user_data_5; 195 uint32_t compute_user_data_6; 196 uint32_t compute_user_data_7; 197 uint32_t compute_user_data_8; 198 uint32_t compute_user_data_9; 199 uint32_t compute_user_data_10; 200 uint32_t compute_user_data_11; 201 uint32_t compute_user_data_12; 202 uint32_t compute_user_data_13; 203 uint32_t compute_user_data_14; 204 uint32_t compute_user_data_15; 205 uint32_t cp_compute_csinvoc_count_lo; 206 uint32_t cp_compute_csinvoc_count_hi; 207 uint32_t cp_mqd_base_addr_lo; 208 uint32_t cp_mqd_base_addr_hi; 209 uint32_t cp_hqd_active; 210 uint32_t cp_hqd_vmid; 211 uint32_t cp_hqd_persistent_state; 212 uint32_t cp_hqd_pipe_priority; 213 uint32_t cp_hqd_queue_priority; 214 uint32_t cp_hqd_quantum; 215 uint32_t cp_hqd_pq_base_lo; 216 uint32_t cp_hqd_pq_base_hi; 217 uint32_t cp_hqd_pq_rptr; 218 uint32_t cp_hqd_pq_rptr_report_addr_lo; 219 uint32_t cp_hqd_pq_rptr_report_addr_hi; 220 uint32_t cp_hqd_pq_wptr_poll_addr_lo; 221 uint32_t cp_hqd_pq_wptr_poll_addr_hi; 222 uint32_t cp_hqd_pq_doorbell_control; 223 uint32_t cp_hqd_pq_wptr; 224 uint32_t cp_hqd_pq_control; 225 uint32_t cp_hqd_ib_base_addr_lo; 226 uint32_t cp_hqd_ib_base_addr_hi; 227 uint32_t cp_hqd_ib_rptr; 228 uint32_t cp_hqd_ib_control; 229 uint32_t cp_hqd_iq_timer; 230 uint32_t cp_hqd_iq_rptr; 231 uint32_t cp_hqd_dequeue_request; 232 uint32_t cp_hqd_dma_offload; 233 uint32_t cp_hqd_sema_cmd; 234 uint32_t cp_hqd_msg_type; 235 uint32_t cp_hqd_atomic0_preop_lo; 236 uint32_t cp_hqd_atomic0_preop_hi; 237 uint32_t cp_hqd_atomic1_preop_lo; 238 uint32_t cp_hqd_atomic1_preop_hi; 239 uint32_t cp_hqd_hq_status0; 240 uint32_t cp_hqd_hq_control0; 241 uint32_t cp_mqd_control; 242 uint32_t cp_mqd_query_time_lo; 243 uint32_t cp_mqd_query_time_hi; 244 uint32_t cp_mqd_connect_start_time_lo; 245 uint32_t cp_mqd_connect_start_time_hi; 246 uint32_t cp_mqd_connect_end_time_lo; 247 uint32_t cp_mqd_connect_end_time_hi; 248 uint32_t cp_mqd_connect_end_wf_count; 249 uint32_t cp_mqd_connect_end_pq_rptr; 250 uint32_t cp_mqd_connect_end_pq_wptr; 251 uint32_t cp_mqd_connect_end_ib_rptr; 252 uint32_t reserved_96; 253 uint32_t reserved_97; 254 uint32_t reserved_98; 255 uint32_t reserved_99; 256 uint32_t iqtimer_pkt_header; 257 uint32_t iqtimer_pkt_dw0; 258 uint32_t iqtimer_pkt_dw1; 259 uint32_t iqtimer_pkt_dw2; 260 uint32_t iqtimer_pkt_dw3; 261 uint32_t iqtimer_pkt_dw4; 262 uint32_t iqtimer_pkt_dw5; 263 uint32_t iqtimer_pkt_dw6; 264 uint32_t reserved_108; 265 uint32_t reserved_109; 266 uint32_t reserved_110; 267 uint32_t reserved_111; 268 uint32_t queue_doorbell_id0; 269 uint32_t queue_doorbell_id1; 270 uint32_t queue_doorbell_id2; 271 uint32_t queue_doorbell_id3; 272 uint32_t queue_doorbell_id4; 273 uint32_t queue_doorbell_id5; 274 uint32_t queue_doorbell_id6; 275 uint32_t queue_doorbell_id7; 276 uint32_t queue_doorbell_id8; 277 uint32_t queue_doorbell_id9; 278 uint32_t queue_doorbell_id10; 279 uint32_t queue_doorbell_id11; 280 uint32_t queue_doorbell_id12; 281 uint32_t queue_doorbell_id13; 282 uint32_t queue_doorbell_id14; 283 uint32_t queue_doorbell_id15; 284 }; 285 286 #endif 287