1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 #include <linux/seq_file.h> 27 28 #include "atom.h" 29 #include "ci_dpm.h" 30 #include "cikd.h" 31 #include "r600_dpm.h" 32 #include "radeon.h" 33 #include "radeon_asic.h" 34 #include "radeon_ucode.h" 35 36 #define MC_CG_ARB_FREQ_F0 0x0a 37 #define MC_CG_ARB_FREQ_F1 0x0b 38 #define MC_CG_ARB_FREQ_F2 0x0c 39 #define MC_CG_ARB_FREQ_F3 0x0d 40 41 #define SMC_RAM_END 0x40000 42 43 #define VOLTAGE_SCALE 4 44 #define VOLTAGE_VID_OFFSET_SCALE1 625 45 #define VOLTAGE_VID_OFFSET_SCALE2 100 46 47 static const struct ci_pt_defaults defaults_hawaii_xt = 48 { 49 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000, 50 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 }, 51 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 } 52 }; 53 54 static const struct ci_pt_defaults defaults_hawaii_pro = 55 { 56 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062, 57 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 }, 58 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 } 59 }; 60 61 static const struct ci_pt_defaults defaults_bonaire_xt = 62 { 63 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000, 64 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 }, 65 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } 66 }; 67 68 static const struct ci_pt_defaults defaults_saturn_xt = 69 { 70 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000, 71 { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D }, 72 { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 } 73 }; 74 75 static const struct ci_pt_config_reg didt_config_ci[] = 76 { 77 { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 78 { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 79 { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 80 { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 81 { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 82 { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 83 { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 84 { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 85 { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 86 { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 87 { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 88 { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 89 { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, 90 { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, 91 { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, 92 { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 93 { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 94 { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 95 { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 96 { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 97 { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 98 { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 99 { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 100 { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 101 { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 102 { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 103 { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 104 { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 105 { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 106 { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 107 { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, 108 { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, 109 { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, 110 { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 111 { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 112 { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 113 { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 114 { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 115 { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 116 { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 117 { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 118 { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 119 { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 120 { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 121 { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 122 { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 123 { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 124 { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 125 { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, 126 { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, 127 { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, 128 { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 129 { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 130 { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 131 { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 132 { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 133 { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 134 { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 135 { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 136 { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 137 { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 138 { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 139 { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 140 { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 141 { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 142 { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 143 { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, 144 { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, 145 { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, 146 { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 147 { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 148 { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 149 { 0xFFFFFFFF } 150 }; 151 152 extern u8 rv770_get_memory_module_index(struct radeon_device *rdev); 153 extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev, 154 u32 arb_freq_src, u32 arb_freq_dest); 155 extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock); 156 extern u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode); 157 extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 158 u32 max_voltage_steps, 159 struct atom_voltage_table *voltage_table); 160 extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev); 161 extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev); 162 extern int ci_mc_load_microcode(struct radeon_device *rdev); 163 extern void cik_update_cg(struct radeon_device *rdev, 164 u32 block, bool enable); 165 166 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev, 167 struct atom_voltage_table_entry *voltage_table, 168 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd); 169 static int ci_set_power_limit(struct radeon_device *rdev, u32 n); 170 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev, 171 u32 target_tdp); 172 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate); 173 174 static PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg); 175 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 176 PPSMC_Msg msg, u32 parameter); 177 178 static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev); 179 static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev); 180 181 static struct ci_power_info *ci_get_pi(struct radeon_device *rdev) 182 { 183 struct ci_power_info *pi = rdev->pm.dpm.priv; 184 185 return pi; 186 } 187 188 static struct ci_ps *ci_get_ps(struct radeon_ps *rps) 189 { 190 struct ci_ps *ps = rps->ps_priv; 191 192 return ps; 193 } 194 195 static void ci_initialize_powertune_defaults(struct radeon_device *rdev) 196 { 197 struct ci_power_info *pi = ci_get_pi(rdev); 198 199 switch (rdev->pdev->device) { 200 case 0x6649: 201 case 0x6650: 202 case 0x6651: 203 case 0x6658: 204 case 0x665C: 205 case 0x665D: 206 default: 207 pi->powertune_defaults = &defaults_bonaire_xt; 208 break; 209 case 0x6640: 210 case 0x6641: 211 case 0x6646: 212 case 0x6647: 213 pi->powertune_defaults = &defaults_saturn_xt; 214 break; 215 case 0x67B8: 216 case 0x67B0: 217 pi->powertune_defaults = &defaults_hawaii_xt; 218 break; 219 case 0x67BA: 220 case 0x67B1: 221 pi->powertune_defaults = &defaults_hawaii_pro; 222 break; 223 case 0x67A0: 224 case 0x67A1: 225 case 0x67A2: 226 case 0x67A8: 227 case 0x67A9: 228 case 0x67AA: 229 case 0x67B9: 230 case 0x67BE: 231 pi->powertune_defaults = &defaults_bonaire_xt; 232 break; 233 } 234 235 pi->dte_tj_offset = 0; 236 237 pi->caps_power_containment = true; 238 pi->caps_cac = false; 239 pi->caps_sq_ramping = false; 240 pi->caps_db_ramping = false; 241 pi->caps_td_ramping = false; 242 pi->caps_tcp_ramping = false; 243 244 if (pi->caps_power_containment) { 245 pi->caps_cac = true; 246 if (rdev->family == CHIP_HAWAII) 247 pi->enable_bapm_feature = false; 248 else 249 pi->enable_bapm_feature = true; 250 pi->enable_tdc_limit_feature = true; 251 pi->enable_pkg_pwr_tracking_feature = true; 252 } 253 } 254 255 static u8 ci_convert_to_vid(u16 vddc) 256 { 257 return (6200 - (vddc * VOLTAGE_SCALE)) / 25; 258 } 259 260 static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev) 261 { 262 struct ci_power_info *pi = ci_get_pi(rdev); 263 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; 264 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; 265 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2; 266 u32 i; 267 268 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL) 269 return -EINVAL; 270 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8) 271 return -EINVAL; 272 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count != 273 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) 274 return -EINVAL; 275 276 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) { 277 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { 278 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1); 279 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2); 280 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3); 281 } else { 282 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc); 283 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage); 284 } 285 } 286 return 0; 287 } 288 289 static int ci_populate_vddc_vid(struct radeon_device *rdev) 290 { 291 struct ci_power_info *pi = ci_get_pi(rdev); 292 u8 *vid = pi->smc_powertune_table.VddCVid; 293 u32 i; 294 295 if (pi->vddc_voltage_table.count > 8) 296 return -EINVAL; 297 298 for (i = 0; i < pi->vddc_voltage_table.count; i++) 299 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value); 300 301 return 0; 302 } 303 304 static int ci_populate_svi_load_line(struct radeon_device *rdev) 305 { 306 struct ci_power_info *pi = ci_get_pi(rdev); 307 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; 308 309 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en; 310 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc; 311 pi->smc_powertune_table.SviLoadLineTrimVddC = 3; 312 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0; 313 314 return 0; 315 } 316 317 static int ci_populate_tdc_limit(struct radeon_device *rdev) 318 { 319 struct ci_power_info *pi = ci_get_pi(rdev); 320 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; 321 u16 tdc_limit; 322 323 tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256; 324 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit); 325 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc = 326 pt_defaults->tdc_vddc_throttle_release_limit_perc; 327 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt; 328 329 return 0; 330 } 331 332 static int ci_populate_dw8(struct radeon_device *rdev) 333 { 334 struct ci_power_info *pi = ci_get_pi(rdev); 335 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; 336 int ret; 337 338 ret = ci_read_smc_sram_dword(rdev, 339 SMU7_FIRMWARE_HEADER_LOCATION + 340 offsetof(SMU7_Firmware_Header, PmFuseTable) + 341 offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl), 342 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl, 343 pi->sram_end); 344 if (ret) 345 return -EINVAL; 346 else 347 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl; 348 349 return 0; 350 } 351 352 static int ci_populate_fuzzy_fan(struct radeon_device *rdev) 353 { 354 struct ci_power_info *pi = ci_get_pi(rdev); 355 356 if ((rdev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) || 357 (rdev->pm.dpm.fan.fan_output_sensitivity == 0)) 358 rdev->pm.dpm.fan.fan_output_sensitivity = 359 rdev->pm.dpm.fan.default_fan_output_sensitivity; 360 361 pi->smc_powertune_table.FuzzyFan_PwmSetDelta = 362 cpu_to_be16(rdev->pm.dpm.fan.fan_output_sensitivity); 363 364 return 0; 365 } 366 367 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev) 368 { 369 struct ci_power_info *pi = ci_get_pi(rdev); 370 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; 371 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; 372 int i, min, max; 373 374 min = max = hi_vid[0]; 375 for (i = 0; i < 8; i++) { 376 if (0 != hi_vid[i]) { 377 if (min > hi_vid[i]) 378 min = hi_vid[i]; 379 if (max < hi_vid[i]) 380 max = hi_vid[i]; 381 } 382 383 if (0 != lo_vid[i]) { 384 if (min > lo_vid[i]) 385 min = lo_vid[i]; 386 if (max < lo_vid[i]) 387 max = lo_vid[i]; 388 } 389 } 390 391 if ((min == 0) || (max == 0)) 392 return -EINVAL; 393 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max; 394 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min; 395 396 return 0; 397 } 398 399 static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev) 400 { 401 struct ci_power_info *pi = ci_get_pi(rdev); 402 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd; 403 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd; 404 struct radeon_cac_tdp_table *cac_tdp_table = 405 rdev->pm.dpm.dyn_state.cac_tdp_table; 406 407 hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256; 408 lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256; 409 410 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd); 411 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd); 412 413 return 0; 414 } 415 416 static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev) 417 { 418 struct ci_power_info *pi = ci_get_pi(rdev); 419 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; 420 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; 421 struct radeon_cac_tdp_table *cac_tdp_table = 422 rdev->pm.dpm.dyn_state.cac_tdp_table; 423 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 424 int i, j, k; 425 const u16 *def1; 426 const u16 *def2; 427 428 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256; 429 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256; 430 431 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; 432 dpm_table->GpuTjMax = 433 (u8)(pi->thermal_temp_setting.temperature_high / 1000); 434 dpm_table->GpuTjHyst = 8; 435 436 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base; 437 438 if (ppm) { 439 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000); 440 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256); 441 } else { 442 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0); 443 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0); 444 } 445 446 dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient); 447 def1 = pt_defaults->bapmti_r; 448 def2 = pt_defaults->bapmti_rc; 449 450 for (i = 0; i < SMU7_DTE_ITERATIONS; i++) { 451 for (j = 0; j < SMU7_DTE_SOURCES; j++) { 452 for (k = 0; k < SMU7_DTE_SINKS; k++) { 453 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1); 454 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2); 455 def1++; 456 def2++; 457 } 458 } 459 } 460 461 return 0; 462 } 463 464 static int ci_populate_pm_base(struct radeon_device *rdev) 465 { 466 struct ci_power_info *pi = ci_get_pi(rdev); 467 u32 pm_fuse_table_offset; 468 int ret; 469 470 if (pi->caps_power_containment) { 471 ret = ci_read_smc_sram_dword(rdev, 472 SMU7_FIRMWARE_HEADER_LOCATION + 473 offsetof(SMU7_Firmware_Header, PmFuseTable), 474 &pm_fuse_table_offset, pi->sram_end); 475 if (ret) 476 return ret; 477 ret = ci_populate_bapm_vddc_vid_sidd(rdev); 478 if (ret) 479 return ret; 480 ret = ci_populate_vddc_vid(rdev); 481 if (ret) 482 return ret; 483 ret = ci_populate_svi_load_line(rdev); 484 if (ret) 485 return ret; 486 ret = ci_populate_tdc_limit(rdev); 487 if (ret) 488 return ret; 489 ret = ci_populate_dw8(rdev); 490 if (ret) 491 return ret; 492 ret = ci_populate_fuzzy_fan(rdev); 493 if (ret) 494 return ret; 495 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev); 496 if (ret) 497 return ret; 498 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev); 499 if (ret) 500 return ret; 501 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset, 502 (u8 *)&pi->smc_powertune_table, 503 sizeof(SMU7_Discrete_PmFuses), pi->sram_end); 504 if (ret) 505 return ret; 506 } 507 508 return 0; 509 } 510 511 static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable) 512 { 513 struct ci_power_info *pi = ci_get_pi(rdev); 514 u32 data; 515 516 if (pi->caps_sq_ramping) { 517 data = RREG32_DIDT(DIDT_SQ_CTRL0); 518 if (enable) 519 data |= DIDT_CTRL_EN; 520 else 521 data &= ~DIDT_CTRL_EN; 522 WREG32_DIDT(DIDT_SQ_CTRL0, data); 523 } 524 525 if (pi->caps_db_ramping) { 526 data = RREG32_DIDT(DIDT_DB_CTRL0); 527 if (enable) 528 data |= DIDT_CTRL_EN; 529 else 530 data &= ~DIDT_CTRL_EN; 531 WREG32_DIDT(DIDT_DB_CTRL0, data); 532 } 533 534 if (pi->caps_td_ramping) { 535 data = RREG32_DIDT(DIDT_TD_CTRL0); 536 if (enable) 537 data |= DIDT_CTRL_EN; 538 else 539 data &= ~DIDT_CTRL_EN; 540 WREG32_DIDT(DIDT_TD_CTRL0, data); 541 } 542 543 if (pi->caps_tcp_ramping) { 544 data = RREG32_DIDT(DIDT_TCP_CTRL0); 545 if (enable) 546 data |= DIDT_CTRL_EN; 547 else 548 data &= ~DIDT_CTRL_EN; 549 WREG32_DIDT(DIDT_TCP_CTRL0, data); 550 } 551 } 552 553 static int ci_program_pt_config_registers(struct radeon_device *rdev, 554 const struct ci_pt_config_reg *cac_config_regs) 555 { 556 const struct ci_pt_config_reg *config_regs = cac_config_regs; 557 u32 data; 558 u32 cache = 0; 559 560 if (config_regs == NULL) 561 return -EINVAL; 562 563 while (config_regs->offset != 0xFFFFFFFF) { 564 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) { 565 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask); 566 } else { 567 switch (config_regs->type) { 568 case CISLANDS_CONFIGREG_SMC_IND: 569 data = RREG32_SMC(config_regs->offset); 570 break; 571 case CISLANDS_CONFIGREG_DIDT_IND: 572 data = RREG32_DIDT(config_regs->offset); 573 break; 574 default: 575 data = RREG32(config_regs->offset << 2); 576 break; 577 } 578 579 data &= ~config_regs->mask; 580 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 581 data |= cache; 582 583 switch (config_regs->type) { 584 case CISLANDS_CONFIGREG_SMC_IND: 585 WREG32_SMC(config_regs->offset, data); 586 break; 587 case CISLANDS_CONFIGREG_DIDT_IND: 588 WREG32_DIDT(config_regs->offset, data); 589 break; 590 default: 591 WREG32(config_regs->offset << 2, data); 592 break; 593 } 594 cache = 0; 595 } 596 config_regs++; 597 } 598 return 0; 599 } 600 601 static int ci_enable_didt(struct radeon_device *rdev, bool enable) 602 { 603 struct ci_power_info *pi = ci_get_pi(rdev); 604 int ret; 605 606 if (pi->caps_sq_ramping || pi->caps_db_ramping || 607 pi->caps_td_ramping || pi->caps_tcp_ramping) { 608 cik_enter_rlc_safe_mode(rdev); 609 610 if (enable) { 611 ret = ci_program_pt_config_registers(rdev, didt_config_ci); 612 if (ret) { 613 cik_exit_rlc_safe_mode(rdev); 614 return ret; 615 } 616 } 617 618 ci_do_enable_didt(rdev, enable); 619 620 cik_exit_rlc_safe_mode(rdev); 621 } 622 623 return 0; 624 } 625 626 static int ci_enable_power_containment(struct radeon_device *rdev, bool enable) 627 { 628 struct ci_power_info *pi = ci_get_pi(rdev); 629 PPSMC_Result smc_result; 630 int ret = 0; 631 632 if (enable) { 633 pi->power_containment_features = 0; 634 if (pi->caps_power_containment) { 635 if (pi->enable_bapm_feature) { 636 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 637 if (smc_result != PPSMC_Result_OK) 638 ret = -EINVAL; 639 else 640 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM; 641 } 642 643 if (pi->enable_tdc_limit_feature) { 644 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable); 645 if (smc_result != PPSMC_Result_OK) 646 ret = -EINVAL; 647 else 648 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit; 649 } 650 651 if (pi->enable_pkg_pwr_tracking_feature) { 652 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable); 653 if (smc_result != PPSMC_Result_OK) { 654 ret = -EINVAL; 655 } else { 656 struct radeon_cac_tdp_table *cac_tdp_table = 657 rdev->pm.dpm.dyn_state.cac_tdp_table; 658 u32 default_pwr_limit = 659 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256); 660 661 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit; 662 663 ci_set_power_limit(rdev, default_pwr_limit); 664 } 665 } 666 } 667 } else { 668 if (pi->caps_power_containment && pi->power_containment_features) { 669 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit) 670 ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable); 671 672 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM) 673 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 674 675 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) 676 ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable); 677 pi->power_containment_features = 0; 678 } 679 } 680 681 return ret; 682 } 683 684 static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable) 685 { 686 struct ci_power_info *pi = ci_get_pi(rdev); 687 PPSMC_Result smc_result; 688 int ret = 0; 689 690 if (pi->caps_cac) { 691 if (enable) { 692 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 693 if (smc_result != PPSMC_Result_OK) { 694 ret = -EINVAL; 695 pi->cac_enabled = false; 696 } else { 697 pi->cac_enabled = true; 698 } 699 } else if (pi->cac_enabled) { 700 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 701 pi->cac_enabled = false; 702 } 703 } 704 705 return ret; 706 } 707 708 static int ci_enable_thermal_based_sclk_dpm(struct radeon_device *rdev, 709 bool enable) 710 { 711 struct ci_power_info *pi = ci_get_pi(rdev); 712 PPSMC_Result smc_result = PPSMC_Result_OK; 713 714 if (pi->thermal_sclk_dpm_enabled) { 715 if (enable) 716 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_ENABLE_THERMAL_DPM); 717 else 718 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DISABLE_THERMAL_DPM); 719 } 720 721 if (smc_result == PPSMC_Result_OK) 722 return 0; 723 else 724 return -EINVAL; 725 } 726 727 static int ci_power_control_set_level(struct radeon_device *rdev) 728 { 729 struct ci_power_info *pi = ci_get_pi(rdev); 730 struct radeon_cac_tdp_table *cac_tdp_table = 731 rdev->pm.dpm.dyn_state.cac_tdp_table; 732 s32 adjust_percent; 733 s32 target_tdp; 734 int ret = 0; 735 bool adjust_polarity = false; /* ??? */ 736 737 if (pi->caps_power_containment) { 738 adjust_percent = adjust_polarity ? 739 rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment); 740 target_tdp = ((100 + adjust_percent) * 741 (s32)cac_tdp_table->configurable_tdp) / 100; 742 743 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp); 744 } 745 746 return ret; 747 } 748 749 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate) 750 { 751 struct ci_power_info *pi = ci_get_pi(rdev); 752 753 if (pi->uvd_power_gated == gate) 754 return; 755 756 pi->uvd_power_gated = gate; 757 758 ci_update_uvd_dpm(rdev, gate); 759 } 760 761 bool ci_dpm_vblank_too_short(struct radeon_device *rdev) 762 { 763 struct ci_power_info *pi = ci_get_pi(rdev); 764 u32 vblank_time = r600_dpm_get_vblank_time(rdev); 765 u32 switch_limit = pi->mem_gddr5 ? 450 : 300; 766 767 /* disable mclk switching if the refresh is >120Hz, even if the 768 * blanking period would allow it 769 */ 770 if (r600_dpm_get_vrefresh(rdev) > 120) 771 return true; 772 773 if (vblank_time < switch_limit) 774 return true; 775 else 776 return false; 777 778 } 779 780 static void ci_apply_state_adjust_rules(struct radeon_device *rdev, 781 struct radeon_ps *rps) 782 { 783 struct ci_ps *ps = ci_get_ps(rps); 784 struct ci_power_info *pi = ci_get_pi(rdev); 785 struct radeon_clock_and_voltage_limits *max_limits; 786 bool disable_mclk_switching; 787 u32 sclk, mclk; 788 int i; 789 790 if (rps->vce_active) { 791 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; 792 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; 793 } else { 794 rps->evclk = 0; 795 rps->ecclk = 0; 796 } 797 798 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 799 ci_dpm_vblank_too_short(rdev)) 800 disable_mclk_switching = true; 801 else 802 disable_mclk_switching = false; 803 804 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) 805 pi->battery_state = true; 806 else 807 pi->battery_state = false; 808 809 if (rdev->pm.dpm.ac_power) 810 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 811 else 812 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 813 814 if (rdev->pm.dpm.ac_power == false) { 815 for (i = 0; i < ps->performance_level_count; i++) { 816 if (ps->performance_levels[i].mclk > max_limits->mclk) 817 ps->performance_levels[i].mclk = max_limits->mclk; 818 if (ps->performance_levels[i].sclk > max_limits->sclk) 819 ps->performance_levels[i].sclk = max_limits->sclk; 820 } 821 } 822 823 /* XXX validate the min clocks required for display */ 824 825 if (disable_mclk_switching) { 826 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 827 sclk = ps->performance_levels[0].sclk; 828 } else { 829 mclk = ps->performance_levels[0].mclk; 830 sclk = ps->performance_levels[0].sclk; 831 } 832 833 if (rps->vce_active) { 834 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) 835 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; 836 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) 837 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; 838 } 839 840 ps->performance_levels[0].sclk = sclk; 841 ps->performance_levels[0].mclk = mclk; 842 843 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk) 844 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk; 845 846 if (disable_mclk_switching) { 847 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk) 848 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk; 849 } else { 850 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk) 851 ps->performance_levels[1].mclk = ps->performance_levels[0].mclk; 852 } 853 } 854 855 static int ci_thermal_set_temperature_range(struct radeon_device *rdev, 856 int min_temp, int max_temp) 857 { 858 int low_temp = 0 * 1000; 859 int high_temp = 255 * 1000; 860 u32 tmp; 861 862 if (low_temp < min_temp) 863 low_temp = min_temp; 864 if (high_temp > max_temp) 865 high_temp = max_temp; 866 if (high_temp < low_temp) { 867 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 868 return -EINVAL; 869 } 870 871 tmp = RREG32_SMC(CG_THERMAL_INT); 872 tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK); 873 tmp |= CI_DIG_THERM_INTH(high_temp / 1000) | 874 CI_DIG_THERM_INTL(low_temp / 1000); 875 WREG32_SMC(CG_THERMAL_INT, tmp); 876 877 #if 0 878 /* XXX: need to figure out how to handle this properly */ 879 tmp = RREG32_SMC(CG_THERMAL_CTRL); 880 tmp &= DIG_THERM_DPM_MASK; 881 tmp |= DIG_THERM_DPM(high_temp / 1000); 882 WREG32_SMC(CG_THERMAL_CTRL, tmp); 883 #endif 884 885 rdev->pm.dpm.thermal.min_temp = low_temp; 886 rdev->pm.dpm.thermal.max_temp = high_temp; 887 888 return 0; 889 } 890 891 static int ci_thermal_enable_alert(struct radeon_device *rdev, 892 bool enable) 893 { 894 u32 thermal_int = RREG32_SMC(CG_THERMAL_INT); 895 PPSMC_Result result; 896 897 if (enable) { 898 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 899 WREG32_SMC(CG_THERMAL_INT, thermal_int); 900 rdev->irq.dpm_thermal = false; 901 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Enable); 902 if (result != PPSMC_Result_OK) { 903 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 904 return -EINVAL; 905 } 906 } else { 907 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 908 WREG32_SMC(CG_THERMAL_INT, thermal_int); 909 rdev->irq.dpm_thermal = true; 910 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Disable); 911 if (result != PPSMC_Result_OK) { 912 DRM_DEBUG_KMS("Could not disable thermal interrupts.\n"); 913 return -EINVAL; 914 } 915 } 916 917 return 0; 918 } 919 920 static void ci_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) 921 { 922 struct ci_power_info *pi = ci_get_pi(rdev); 923 u32 tmp; 924 925 if (pi->fan_ctrl_is_in_default_mode) { 926 tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; 927 pi->fan_ctrl_default_mode = tmp; 928 tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; 929 pi->t_min = tmp; 930 pi->fan_ctrl_is_in_default_mode = false; 931 } 932 933 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK; 934 tmp |= TMIN(0); 935 WREG32_SMC(CG_FDO_CTRL2, tmp); 936 937 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 938 tmp |= FDO_PWM_MODE(mode); 939 WREG32_SMC(CG_FDO_CTRL2, tmp); 940 } 941 942 static int ci_thermal_setup_fan_table(struct radeon_device *rdev) 943 { 944 struct ci_power_info *pi = ci_get_pi(rdev); 945 SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; 946 u32 duty100; 947 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; 948 u16 fdo_min, slope1, slope2; 949 u32 reference_clock, tmp; 950 int ret; 951 u64 tmp64; 952 953 if (!pi->fan_table_start) { 954 rdev->pm.dpm.fan.ucode_fan_control = false; 955 return 0; 956 } 957 958 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 959 960 if (duty100 == 0) { 961 rdev->pm.dpm.fan.ucode_fan_control = false; 962 return 0; 963 } 964 965 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; 966 do_div(tmp64, 10000); 967 fdo_min = (u16)tmp64; 968 969 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; 970 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; 971 972 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; 973 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; 974 975 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); 976 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); 977 978 fan_table.TempMin = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); 979 fan_table.TempMed = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); 980 fan_table.TempMax = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); 981 982 fan_table.Slope1 = cpu_to_be16(slope1); 983 fan_table.Slope2 = cpu_to_be16(slope2); 984 985 fan_table.FdoMin = cpu_to_be16(fdo_min); 986 987 fan_table.HystDown = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); 988 989 fan_table.HystUp = cpu_to_be16(1); 990 991 fan_table.HystSlope = cpu_to_be16(1); 992 993 fan_table.TempRespLim = cpu_to_be16(5); 994 995 reference_clock = radeon_get_xclk(rdev); 996 997 fan_table.RefreshPeriod = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * 998 reference_clock) / 1600); 999 1000 fan_table.FdoMax = cpu_to_be16((u16)duty100); 1001 1002 tmp = (RREG32_SMC(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; 1003 fan_table.TempSrc = (uint8_t)tmp; 1004 1005 ret = ci_copy_bytes_to_smc(rdev, 1006 pi->fan_table_start, 1007 (u8 *)(&fan_table), 1008 sizeof(fan_table), 1009 pi->sram_end); 1010 1011 if (ret) { 1012 DRM_ERROR("Failed to load fan table to the SMC."); 1013 rdev->pm.dpm.fan.ucode_fan_control = false; 1014 } 1015 1016 return 0; 1017 } 1018 1019 static int ci_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev) 1020 { 1021 struct ci_power_info *pi = ci_get_pi(rdev); 1022 PPSMC_Result ret; 1023 1024 if (pi->caps_od_fuzzy_fan_control_support) { 1025 ret = ci_send_msg_to_smc_with_parameter(rdev, 1026 PPSMC_StartFanControl, 1027 FAN_CONTROL_FUZZY); 1028 if (ret != PPSMC_Result_OK) 1029 return -EINVAL; 1030 ret = ci_send_msg_to_smc_with_parameter(rdev, 1031 PPSMC_MSG_SetFanPwmMax, 1032 rdev->pm.dpm.fan.default_max_fan_pwm); 1033 if (ret != PPSMC_Result_OK) 1034 return -EINVAL; 1035 } else { 1036 ret = ci_send_msg_to_smc_with_parameter(rdev, 1037 PPSMC_StartFanControl, 1038 FAN_CONTROL_TABLE); 1039 if (ret != PPSMC_Result_OK) 1040 return -EINVAL; 1041 } 1042 1043 pi->fan_is_controlled_by_smc = true; 1044 return 0; 1045 } 1046 1047 static int ci_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev) 1048 { 1049 PPSMC_Result ret; 1050 struct ci_power_info *pi = ci_get_pi(rdev); 1051 1052 ret = ci_send_msg_to_smc(rdev, PPSMC_StopFanControl); 1053 if (ret == PPSMC_Result_OK) { 1054 pi->fan_is_controlled_by_smc = false; 1055 return 0; 1056 } else 1057 return -EINVAL; 1058 } 1059 1060 int ci_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, 1061 u32 *speed) 1062 { 1063 u32 duty, duty100; 1064 u64 tmp64; 1065 1066 if (rdev->pm.no_fan) 1067 return -ENOENT; 1068 1069 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 1070 duty = (RREG32_SMC(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT; 1071 1072 if (duty100 == 0) 1073 return -EINVAL; 1074 1075 tmp64 = (u64)duty * 100; 1076 do_div(tmp64, duty100); 1077 *speed = (u32)tmp64; 1078 1079 if (*speed > 100) 1080 *speed = 100; 1081 1082 return 0; 1083 } 1084 1085 int ci_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, 1086 u32 speed) 1087 { 1088 u32 tmp; 1089 u32 duty, duty100; 1090 u64 tmp64; 1091 struct ci_power_info *pi = ci_get_pi(rdev); 1092 1093 if (rdev->pm.no_fan) 1094 return -ENOENT; 1095 1096 if (pi->fan_is_controlled_by_smc) 1097 return -EINVAL; 1098 1099 if (speed > 100) 1100 return -EINVAL; 1101 1102 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 1103 1104 if (duty100 == 0) 1105 return -EINVAL; 1106 1107 tmp64 = (u64)speed * duty100; 1108 do_div(tmp64, 100); 1109 duty = (u32)tmp64; 1110 1111 tmp = RREG32_SMC(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; 1112 tmp |= FDO_STATIC_DUTY(duty); 1113 WREG32_SMC(CG_FDO_CTRL0, tmp); 1114 1115 return 0; 1116 } 1117 1118 void ci_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode) 1119 { 1120 if (mode) { 1121 /* stop auto-manage */ 1122 if (rdev->pm.dpm.fan.ucode_fan_control) 1123 ci_fan_ctrl_stop_smc_fan_control(rdev); 1124 ci_fan_ctrl_set_static_mode(rdev, mode); 1125 } else { 1126 /* restart auto-manage */ 1127 if (rdev->pm.dpm.fan.ucode_fan_control) 1128 ci_thermal_start_smc_fan_control(rdev); 1129 else 1130 ci_fan_ctrl_set_default_mode(rdev); 1131 } 1132 } 1133 1134 u32 ci_fan_ctrl_get_mode(struct radeon_device *rdev) 1135 { 1136 struct ci_power_info *pi = ci_get_pi(rdev); 1137 u32 tmp; 1138 1139 if (pi->fan_is_controlled_by_smc) 1140 return 0; 1141 1142 tmp = RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; 1143 return (tmp >> FDO_PWM_MODE_SHIFT); 1144 } 1145 1146 #if 0 1147 static int ci_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev, 1148 u32 *speed) 1149 { 1150 u32 tach_period; 1151 u32 xclk = radeon_get_xclk(rdev); 1152 1153 if (rdev->pm.no_fan) 1154 return -ENOENT; 1155 1156 if (rdev->pm.fan_pulses_per_revolution == 0) 1157 return -ENOENT; 1158 1159 tach_period = (RREG32_SMC(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; 1160 if (tach_period == 0) 1161 return -ENOENT; 1162 1163 *speed = 60 * xclk * 10000 / tach_period; 1164 1165 return 0; 1166 } 1167 1168 static int ci_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev, 1169 u32 speed) 1170 { 1171 u32 tach_period, tmp; 1172 u32 xclk = radeon_get_xclk(rdev); 1173 1174 if (rdev->pm.no_fan) 1175 return -ENOENT; 1176 1177 if (rdev->pm.fan_pulses_per_revolution == 0) 1178 return -ENOENT; 1179 1180 if ((speed < rdev->pm.fan_min_rpm) || 1181 (speed > rdev->pm.fan_max_rpm)) 1182 return -EINVAL; 1183 1184 if (rdev->pm.dpm.fan.ucode_fan_control) 1185 ci_fan_ctrl_stop_smc_fan_control(rdev); 1186 1187 tach_period = 60 * xclk * 10000 / (8 * speed); 1188 tmp = RREG32_SMC(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; 1189 tmp |= TARGET_PERIOD(tach_period); 1190 WREG32_SMC(CG_TACH_CTRL, tmp); 1191 1192 ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM); 1193 1194 return 0; 1195 } 1196 #endif 1197 1198 static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev) 1199 { 1200 struct ci_power_info *pi = ci_get_pi(rdev); 1201 u32 tmp; 1202 1203 if (!pi->fan_ctrl_is_in_default_mode) { 1204 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 1205 tmp |= FDO_PWM_MODE(pi->fan_ctrl_default_mode); 1206 WREG32_SMC(CG_FDO_CTRL2, tmp); 1207 1208 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK; 1209 tmp |= TMIN(pi->t_min); 1210 WREG32_SMC(CG_FDO_CTRL2, tmp); 1211 pi->fan_ctrl_is_in_default_mode = true; 1212 } 1213 } 1214 1215 static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev) 1216 { 1217 if (rdev->pm.dpm.fan.ucode_fan_control) { 1218 ci_fan_ctrl_start_smc_fan_control(rdev); 1219 ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); 1220 } 1221 } 1222 1223 static void ci_thermal_initialize(struct radeon_device *rdev) 1224 { 1225 u32 tmp; 1226 1227 if (rdev->pm.fan_pulses_per_revolution) { 1228 tmp = RREG32_SMC(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK; 1229 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1); 1230 WREG32_SMC(CG_TACH_CTRL, tmp); 1231 } 1232 1233 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; 1234 tmp |= TACH_PWM_RESP_RATE(0x28); 1235 WREG32_SMC(CG_FDO_CTRL2, tmp); 1236 } 1237 1238 static int ci_thermal_start_thermal_controller(struct radeon_device *rdev) 1239 { 1240 int ret; 1241 1242 ci_thermal_initialize(rdev); 1243 ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 1244 if (ret) 1245 return ret; 1246 ret = ci_thermal_enable_alert(rdev, true); 1247 if (ret) 1248 return ret; 1249 if (rdev->pm.dpm.fan.ucode_fan_control) { 1250 ret = ci_thermal_setup_fan_table(rdev); 1251 if (ret) 1252 return ret; 1253 ci_thermal_start_smc_fan_control(rdev); 1254 } 1255 1256 return 0; 1257 } 1258 1259 static void ci_thermal_stop_thermal_controller(struct radeon_device *rdev) 1260 { 1261 if (!rdev->pm.no_fan) 1262 ci_fan_ctrl_set_default_mode(rdev); 1263 } 1264 1265 #if 0 1266 static int ci_read_smc_soft_register(struct radeon_device *rdev, 1267 u16 reg_offset, u32 *value) 1268 { 1269 struct ci_power_info *pi = ci_get_pi(rdev); 1270 1271 return ci_read_smc_sram_dword(rdev, 1272 pi->soft_regs_start + reg_offset, 1273 value, pi->sram_end); 1274 } 1275 #endif 1276 1277 static int ci_write_smc_soft_register(struct radeon_device *rdev, 1278 u16 reg_offset, u32 value) 1279 { 1280 struct ci_power_info *pi = ci_get_pi(rdev); 1281 1282 return ci_write_smc_sram_dword(rdev, 1283 pi->soft_regs_start + reg_offset, 1284 value, pi->sram_end); 1285 } 1286 1287 static void ci_init_fps_limits(struct radeon_device *rdev) 1288 { 1289 struct ci_power_info *pi = ci_get_pi(rdev); 1290 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; 1291 1292 if (pi->caps_fps) { 1293 u16 tmp; 1294 1295 tmp = 45; 1296 table->FpsHighT = cpu_to_be16(tmp); 1297 1298 tmp = 30; 1299 table->FpsLowT = cpu_to_be16(tmp); 1300 } 1301 } 1302 1303 static int ci_update_sclk_t(struct radeon_device *rdev) 1304 { 1305 struct ci_power_info *pi = ci_get_pi(rdev); 1306 int ret = 0; 1307 u32 low_sclk_interrupt_t = 0; 1308 1309 if (pi->caps_sclk_throttle_low_notification) { 1310 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); 1311 1312 ret = ci_copy_bytes_to_smc(rdev, 1313 pi->dpm_table_start + 1314 offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT), 1315 (u8 *)&low_sclk_interrupt_t, 1316 sizeof(u32), pi->sram_end); 1317 1318 } 1319 1320 return ret; 1321 } 1322 1323 static void ci_get_leakage_voltages(struct radeon_device *rdev) 1324 { 1325 struct ci_power_info *pi = ci_get_pi(rdev); 1326 u16 leakage_id, virtual_voltage_id; 1327 u16 vddc, vddci; 1328 int i; 1329 1330 pi->vddc_leakage.count = 0; 1331 pi->vddci_leakage.count = 0; 1332 1333 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { 1334 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) { 1335 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; 1336 if (radeon_atom_get_voltage_evv(rdev, virtual_voltage_id, &vddc) != 0) 1337 continue; 1338 if (vddc != 0 && vddc != virtual_voltage_id) { 1339 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; 1340 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; 1341 pi->vddc_leakage.count++; 1342 } 1343 } 1344 } else if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) { 1345 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) { 1346 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; 1347 if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci, 1348 virtual_voltage_id, 1349 leakage_id) == 0) { 1350 if (vddc != 0 && vddc != virtual_voltage_id) { 1351 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; 1352 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; 1353 pi->vddc_leakage.count++; 1354 } 1355 if (vddci != 0 && vddci != virtual_voltage_id) { 1356 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci; 1357 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id; 1358 pi->vddci_leakage.count++; 1359 } 1360 } 1361 } 1362 } 1363 } 1364 1365 static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 1366 { 1367 struct ci_power_info *pi = ci_get_pi(rdev); 1368 bool want_thermal_protection; 1369 u32 tmp; 1370 1371 switch (sources) { 1372 case 0: 1373 default: 1374 want_thermal_protection = false; 1375 break; 1376 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 1377 want_thermal_protection = true; 1378 break; 1379 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 1380 want_thermal_protection = true; 1381 break; 1382 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 1383 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 1384 want_thermal_protection = true; 1385 break; 1386 } 1387 1388 if (want_thermal_protection) { 1389 tmp = RREG32_SMC(GENERAL_PWRMGT); 1390 if (pi->thermal_protection) 1391 tmp &= ~THERMAL_PROTECTION_DIS; 1392 else 1393 tmp |= THERMAL_PROTECTION_DIS; 1394 WREG32_SMC(GENERAL_PWRMGT, tmp); 1395 } else { 1396 tmp = RREG32_SMC(GENERAL_PWRMGT); 1397 tmp |= THERMAL_PROTECTION_DIS; 1398 WREG32_SMC(GENERAL_PWRMGT, tmp); 1399 } 1400 } 1401 1402 static void ci_enable_auto_throttle_source(struct radeon_device *rdev, 1403 enum radeon_dpm_auto_throttle_src source, 1404 bool enable) 1405 { 1406 struct ci_power_info *pi = ci_get_pi(rdev); 1407 1408 if (enable) { 1409 if (!(pi->active_auto_throttle_sources & (1 << source))) { 1410 pi->active_auto_throttle_sources |= 1 << source; 1411 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 1412 } 1413 } else { 1414 if (pi->active_auto_throttle_sources & (1 << source)) { 1415 pi->active_auto_throttle_sources &= ~(1 << source); 1416 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 1417 } 1418 } 1419 } 1420 1421 static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev) 1422 { 1423 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) 1424 ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt); 1425 } 1426 1427 static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev) 1428 { 1429 struct ci_power_info *pi = ci_get_pi(rdev); 1430 PPSMC_Result smc_result; 1431 1432 if (!pi->need_update_smu7_dpm_table) 1433 return 0; 1434 1435 if ((!pi->sclk_dpm_key_disabled) && 1436 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { 1437 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel); 1438 if (smc_result != PPSMC_Result_OK) 1439 return -EINVAL; 1440 } 1441 1442 if ((!pi->mclk_dpm_key_disabled) && 1443 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { 1444 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel); 1445 if (smc_result != PPSMC_Result_OK) 1446 return -EINVAL; 1447 } 1448 1449 pi->need_update_smu7_dpm_table = 0; 1450 return 0; 1451 } 1452 1453 static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable) 1454 { 1455 struct ci_power_info *pi = ci_get_pi(rdev); 1456 PPSMC_Result smc_result; 1457 1458 if (enable) { 1459 if (!pi->sclk_dpm_key_disabled) { 1460 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable); 1461 if (smc_result != PPSMC_Result_OK) 1462 return -EINVAL; 1463 } 1464 1465 if (!pi->mclk_dpm_key_disabled) { 1466 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable); 1467 if (smc_result != PPSMC_Result_OK) 1468 return -EINVAL; 1469 1470 WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN); 1471 1472 WREG32_SMC(LCAC_MC0_CNTL, 0x05); 1473 WREG32_SMC(LCAC_MC1_CNTL, 0x05); 1474 WREG32_SMC(LCAC_CPL_CNTL, 0x100005); 1475 1476 udelay(10); 1477 1478 WREG32_SMC(LCAC_MC0_CNTL, 0x400005); 1479 WREG32_SMC(LCAC_MC1_CNTL, 0x400005); 1480 WREG32_SMC(LCAC_CPL_CNTL, 0x500005); 1481 } 1482 } else { 1483 if (!pi->sclk_dpm_key_disabled) { 1484 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable); 1485 if (smc_result != PPSMC_Result_OK) 1486 return -EINVAL; 1487 } 1488 1489 if (!pi->mclk_dpm_key_disabled) { 1490 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable); 1491 if (smc_result != PPSMC_Result_OK) 1492 return -EINVAL; 1493 } 1494 } 1495 1496 return 0; 1497 } 1498 1499 static int ci_start_dpm(struct radeon_device *rdev) 1500 { 1501 struct ci_power_info *pi = ci_get_pi(rdev); 1502 PPSMC_Result smc_result; 1503 int ret; 1504 u32 tmp; 1505 1506 tmp = RREG32_SMC(GENERAL_PWRMGT); 1507 tmp |= GLOBAL_PWRMGT_EN; 1508 WREG32_SMC(GENERAL_PWRMGT, tmp); 1509 1510 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 1511 tmp |= DYNAMIC_PM_EN; 1512 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 1513 1514 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000); 1515 1516 WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN); 1517 1518 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable); 1519 if (smc_result != PPSMC_Result_OK) 1520 return -EINVAL; 1521 1522 ret = ci_enable_sclk_mclk_dpm(rdev, true); 1523 if (ret) 1524 return ret; 1525 1526 if (!pi->pcie_dpm_key_disabled) { 1527 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable); 1528 if (smc_result != PPSMC_Result_OK) 1529 return -EINVAL; 1530 } 1531 1532 return 0; 1533 } 1534 1535 static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev) 1536 { 1537 struct ci_power_info *pi = ci_get_pi(rdev); 1538 PPSMC_Result smc_result; 1539 1540 if (!pi->need_update_smu7_dpm_table) 1541 return 0; 1542 1543 if ((!pi->sclk_dpm_key_disabled) && 1544 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { 1545 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel); 1546 if (smc_result != PPSMC_Result_OK) 1547 return -EINVAL; 1548 } 1549 1550 if ((!pi->mclk_dpm_key_disabled) && 1551 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { 1552 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel); 1553 if (smc_result != PPSMC_Result_OK) 1554 return -EINVAL; 1555 } 1556 1557 return 0; 1558 } 1559 1560 static int ci_stop_dpm(struct radeon_device *rdev) 1561 { 1562 struct ci_power_info *pi = ci_get_pi(rdev); 1563 PPSMC_Result smc_result; 1564 int ret; 1565 u32 tmp; 1566 1567 tmp = RREG32_SMC(GENERAL_PWRMGT); 1568 tmp &= ~GLOBAL_PWRMGT_EN; 1569 WREG32_SMC(GENERAL_PWRMGT, tmp); 1570 1571 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 1572 tmp &= ~DYNAMIC_PM_EN; 1573 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 1574 1575 if (!pi->pcie_dpm_key_disabled) { 1576 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable); 1577 if (smc_result != PPSMC_Result_OK) 1578 return -EINVAL; 1579 } 1580 1581 ret = ci_enable_sclk_mclk_dpm(rdev, false); 1582 if (ret) 1583 return ret; 1584 1585 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable); 1586 if (smc_result != PPSMC_Result_OK) 1587 return -EINVAL; 1588 1589 return 0; 1590 } 1591 1592 static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable) 1593 { 1594 u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 1595 1596 if (enable) 1597 tmp &= ~SCLK_PWRMGT_OFF; 1598 else 1599 tmp |= SCLK_PWRMGT_OFF; 1600 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 1601 } 1602 1603 #if 0 1604 static int ci_notify_hw_of_power_source(struct radeon_device *rdev, 1605 bool ac_power) 1606 { 1607 struct ci_power_info *pi = ci_get_pi(rdev); 1608 struct radeon_cac_tdp_table *cac_tdp_table = 1609 rdev->pm.dpm.dyn_state.cac_tdp_table; 1610 u32 power_limit; 1611 1612 if (ac_power) 1613 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256); 1614 else 1615 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256); 1616 1617 ci_set_power_limit(rdev, power_limit); 1618 1619 if (pi->caps_automatic_dc_transition) { 1620 if (ac_power) 1621 ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC); 1622 else 1623 ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp); 1624 } 1625 1626 return 0; 1627 } 1628 #endif 1629 1630 static PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg) 1631 { 1632 u32 tmp; 1633 int i; 1634 1635 if (!ci_is_smc_running(rdev)) 1636 return PPSMC_Result_Failed; 1637 1638 WREG32(SMC_MESSAGE_0, msg); 1639 1640 for (i = 0; i < rdev->usec_timeout; i++) { 1641 tmp = RREG32(SMC_RESP_0); 1642 if (tmp != 0) 1643 break; 1644 udelay(1); 1645 } 1646 tmp = RREG32(SMC_RESP_0); 1647 1648 return (PPSMC_Result)tmp; 1649 } 1650 1651 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 1652 PPSMC_Msg msg, u32 parameter) 1653 { 1654 WREG32(SMC_MSG_ARG_0, parameter); 1655 return ci_send_msg_to_smc(rdev, msg); 1656 } 1657 1658 static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev, 1659 PPSMC_Msg msg, u32 *parameter) 1660 { 1661 PPSMC_Result smc_result; 1662 1663 smc_result = ci_send_msg_to_smc(rdev, msg); 1664 1665 if ((smc_result == PPSMC_Result_OK) && parameter) 1666 *parameter = RREG32(SMC_MSG_ARG_0); 1667 1668 return smc_result; 1669 } 1670 1671 static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n) 1672 { 1673 struct ci_power_info *pi = ci_get_pi(rdev); 1674 1675 if (!pi->sclk_dpm_key_disabled) { 1676 PPSMC_Result smc_result = 1677 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n); 1678 if (smc_result != PPSMC_Result_OK) 1679 return -EINVAL; 1680 } 1681 1682 return 0; 1683 } 1684 1685 static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n) 1686 { 1687 struct ci_power_info *pi = ci_get_pi(rdev); 1688 1689 if (!pi->mclk_dpm_key_disabled) { 1690 PPSMC_Result smc_result = 1691 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n); 1692 if (smc_result != PPSMC_Result_OK) 1693 return -EINVAL; 1694 } 1695 1696 return 0; 1697 } 1698 1699 static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n) 1700 { 1701 struct ci_power_info *pi = ci_get_pi(rdev); 1702 1703 if (!pi->pcie_dpm_key_disabled) { 1704 PPSMC_Result smc_result = 1705 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n); 1706 if (smc_result != PPSMC_Result_OK) 1707 return -EINVAL; 1708 } 1709 1710 return 0; 1711 } 1712 1713 static int ci_set_power_limit(struct radeon_device *rdev, u32 n) 1714 { 1715 struct ci_power_info *pi = ci_get_pi(rdev); 1716 1717 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) { 1718 PPSMC_Result smc_result = 1719 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n); 1720 if (smc_result != PPSMC_Result_OK) 1721 return -EINVAL; 1722 } 1723 1724 return 0; 1725 } 1726 1727 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev, 1728 u32 target_tdp) 1729 { 1730 PPSMC_Result smc_result = 1731 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp); 1732 if (smc_result != PPSMC_Result_OK) 1733 return -EINVAL; 1734 return 0; 1735 } 1736 1737 #if 0 1738 static int ci_set_boot_state(struct radeon_device *rdev) 1739 { 1740 return ci_enable_sclk_mclk_dpm(rdev, false); 1741 } 1742 #endif 1743 1744 static u32 ci_get_average_sclk_freq(struct radeon_device *rdev) 1745 { 1746 u32 sclk_freq; 1747 PPSMC_Result smc_result = 1748 ci_send_msg_to_smc_return_parameter(rdev, 1749 PPSMC_MSG_API_GetSclkFrequency, 1750 &sclk_freq); 1751 if (smc_result != PPSMC_Result_OK) 1752 sclk_freq = 0; 1753 1754 return sclk_freq; 1755 } 1756 1757 static u32 ci_get_average_mclk_freq(struct radeon_device *rdev) 1758 { 1759 u32 mclk_freq; 1760 PPSMC_Result smc_result = 1761 ci_send_msg_to_smc_return_parameter(rdev, 1762 PPSMC_MSG_API_GetMclkFrequency, 1763 &mclk_freq); 1764 if (smc_result != PPSMC_Result_OK) 1765 mclk_freq = 0; 1766 1767 return mclk_freq; 1768 } 1769 1770 static void ci_dpm_start_smc(struct radeon_device *rdev) 1771 { 1772 int i; 1773 1774 ci_program_jump_on_start(rdev); 1775 ci_start_smc_clock(rdev); 1776 ci_start_smc(rdev); 1777 for (i = 0; i < rdev->usec_timeout; i++) { 1778 if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED) 1779 break; 1780 } 1781 } 1782 1783 static void ci_dpm_stop_smc(struct radeon_device *rdev) 1784 { 1785 ci_reset_smc(rdev); 1786 ci_stop_smc_clock(rdev); 1787 } 1788 1789 static int ci_process_firmware_header(struct radeon_device *rdev) 1790 { 1791 struct ci_power_info *pi = ci_get_pi(rdev); 1792 u32 tmp; 1793 int ret; 1794 1795 ret = ci_read_smc_sram_dword(rdev, 1796 SMU7_FIRMWARE_HEADER_LOCATION + 1797 offsetof(SMU7_Firmware_Header, DpmTable), 1798 &tmp, pi->sram_end); 1799 if (ret) 1800 return ret; 1801 1802 pi->dpm_table_start = tmp; 1803 1804 ret = ci_read_smc_sram_dword(rdev, 1805 SMU7_FIRMWARE_HEADER_LOCATION + 1806 offsetof(SMU7_Firmware_Header, SoftRegisters), 1807 &tmp, pi->sram_end); 1808 if (ret) 1809 return ret; 1810 1811 pi->soft_regs_start = tmp; 1812 1813 ret = ci_read_smc_sram_dword(rdev, 1814 SMU7_FIRMWARE_HEADER_LOCATION + 1815 offsetof(SMU7_Firmware_Header, mcRegisterTable), 1816 &tmp, pi->sram_end); 1817 if (ret) 1818 return ret; 1819 1820 pi->mc_reg_table_start = tmp; 1821 1822 ret = ci_read_smc_sram_dword(rdev, 1823 SMU7_FIRMWARE_HEADER_LOCATION + 1824 offsetof(SMU7_Firmware_Header, FanTable), 1825 &tmp, pi->sram_end); 1826 if (ret) 1827 return ret; 1828 1829 pi->fan_table_start = tmp; 1830 1831 ret = ci_read_smc_sram_dword(rdev, 1832 SMU7_FIRMWARE_HEADER_LOCATION + 1833 offsetof(SMU7_Firmware_Header, mcArbDramTimingTable), 1834 &tmp, pi->sram_end); 1835 if (ret) 1836 return ret; 1837 1838 pi->arb_table_start = tmp; 1839 1840 return 0; 1841 } 1842 1843 static void ci_read_clock_registers(struct radeon_device *rdev) 1844 { 1845 struct ci_power_info *pi = ci_get_pi(rdev); 1846 1847 pi->clock_registers.cg_spll_func_cntl = 1848 RREG32_SMC(CG_SPLL_FUNC_CNTL); 1849 pi->clock_registers.cg_spll_func_cntl_2 = 1850 RREG32_SMC(CG_SPLL_FUNC_CNTL_2); 1851 pi->clock_registers.cg_spll_func_cntl_3 = 1852 RREG32_SMC(CG_SPLL_FUNC_CNTL_3); 1853 pi->clock_registers.cg_spll_func_cntl_4 = 1854 RREG32_SMC(CG_SPLL_FUNC_CNTL_4); 1855 pi->clock_registers.cg_spll_spread_spectrum = 1856 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM); 1857 pi->clock_registers.cg_spll_spread_spectrum_2 = 1858 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2); 1859 pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 1860 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 1861 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 1862 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 1863 pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 1864 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 1865 pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 1866 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 1867 pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 1868 } 1869 1870 static void ci_init_sclk_t(struct radeon_device *rdev) 1871 { 1872 struct ci_power_info *pi = ci_get_pi(rdev); 1873 1874 pi->low_sclk_interrupt_t = 0; 1875 } 1876 1877 static void ci_enable_thermal_protection(struct radeon_device *rdev, 1878 bool enable) 1879 { 1880 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); 1881 1882 if (enable) 1883 tmp &= ~THERMAL_PROTECTION_DIS; 1884 else 1885 tmp |= THERMAL_PROTECTION_DIS; 1886 WREG32_SMC(GENERAL_PWRMGT, tmp); 1887 } 1888 1889 static void ci_enable_acpi_power_management(struct radeon_device *rdev) 1890 { 1891 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); 1892 1893 tmp |= STATIC_PM_EN; 1894 1895 WREG32_SMC(GENERAL_PWRMGT, tmp); 1896 } 1897 1898 #if 0 1899 static int ci_enter_ulp_state(struct radeon_device *rdev) 1900 { 1901 1902 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 1903 1904 udelay(25000); 1905 1906 return 0; 1907 } 1908 1909 static int ci_exit_ulp_state(struct radeon_device *rdev) 1910 { 1911 int i; 1912 1913 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 1914 1915 udelay(7000); 1916 1917 for (i = 0; i < rdev->usec_timeout; i++) { 1918 if (RREG32(SMC_RESP_0) == 1) 1919 break; 1920 udelay(1000); 1921 } 1922 1923 return 0; 1924 } 1925 #endif 1926 1927 static int ci_notify_smc_display_change(struct radeon_device *rdev, 1928 bool has_display) 1929 { 1930 PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 1931 1932 return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL; 1933 } 1934 1935 static int ci_enable_ds_master_switch(struct radeon_device *rdev, 1936 bool enable) 1937 { 1938 struct ci_power_info *pi = ci_get_pi(rdev); 1939 1940 if (enable) { 1941 if (pi->caps_sclk_ds) { 1942 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK) 1943 return -EINVAL; 1944 } else { 1945 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK) 1946 return -EINVAL; 1947 } 1948 } else { 1949 if (pi->caps_sclk_ds) { 1950 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK) 1951 return -EINVAL; 1952 } 1953 } 1954 1955 return 0; 1956 } 1957 1958 static void ci_program_display_gap(struct radeon_device *rdev) 1959 { 1960 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL); 1961 u32 pre_vbi_time_in_us; 1962 u32 frame_time_in_us; 1963 u32 ref_clock = rdev->clock.spll.reference_freq; 1964 u32 refresh_rate = r600_dpm_get_vrefresh(rdev); 1965 u32 vblank_time = r600_dpm_get_vblank_time(rdev); 1966 1967 tmp &= ~DISP_GAP_MASK; 1968 if (rdev->pm.dpm.new_active_crtc_count > 0) 1969 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 1970 else 1971 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE); 1972 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp); 1973 1974 if (refresh_rate == 0) 1975 refresh_rate = 60; 1976 if (vblank_time == 0xffffffff) 1977 vblank_time = 500; 1978 frame_time_in_us = 1000000 / refresh_rate; 1979 pre_vbi_time_in_us = 1980 frame_time_in_us - 200 - vblank_time; 1981 tmp = pre_vbi_time_in_us * (ref_clock / 100); 1982 1983 WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp); 1984 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64); 1985 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us)); 1986 1987 1988 ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1)); 1989 1990 } 1991 1992 static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 1993 { 1994 struct ci_power_info *pi = ci_get_pi(rdev); 1995 u32 tmp; 1996 1997 if (enable) { 1998 if (pi->caps_sclk_ss_support) { 1999 tmp = RREG32_SMC(GENERAL_PWRMGT); 2000 tmp |= DYN_SPREAD_SPECTRUM_EN; 2001 WREG32_SMC(GENERAL_PWRMGT, tmp); 2002 } 2003 } else { 2004 tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM); 2005 tmp &= ~SSEN; 2006 WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp); 2007 2008 tmp = RREG32_SMC(GENERAL_PWRMGT); 2009 tmp &= ~DYN_SPREAD_SPECTRUM_EN; 2010 WREG32_SMC(GENERAL_PWRMGT, tmp); 2011 } 2012 } 2013 2014 static void ci_program_sstp(struct radeon_device *rdev) 2015 { 2016 WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 2017 } 2018 2019 static void ci_enable_display_gap(struct radeon_device *rdev) 2020 { 2021 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL); 2022 2023 tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK); 2024 tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 2025 DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK)); 2026 2027 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp); 2028 } 2029 2030 static void ci_program_vc(struct radeon_device *rdev) 2031 { 2032 u32 tmp; 2033 2034 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 2035 tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT); 2036 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 2037 2038 WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0); 2039 WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1); 2040 WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2); 2041 WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3); 2042 WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4); 2043 WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5); 2044 WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6); 2045 WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7); 2046 } 2047 2048 static void ci_clear_vc(struct radeon_device *rdev) 2049 { 2050 u32 tmp; 2051 2052 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 2053 tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT); 2054 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 2055 2056 WREG32_SMC(CG_FTV_0, 0); 2057 WREG32_SMC(CG_FTV_1, 0); 2058 WREG32_SMC(CG_FTV_2, 0); 2059 WREG32_SMC(CG_FTV_3, 0); 2060 WREG32_SMC(CG_FTV_4, 0); 2061 WREG32_SMC(CG_FTV_5, 0); 2062 WREG32_SMC(CG_FTV_6, 0); 2063 WREG32_SMC(CG_FTV_7, 0); 2064 } 2065 2066 static int ci_upload_firmware(struct radeon_device *rdev) 2067 { 2068 struct ci_power_info *pi = ci_get_pi(rdev); 2069 int i, ret; 2070 2071 for (i = 0; i < rdev->usec_timeout; i++) { 2072 if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE) 2073 break; 2074 } 2075 WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1); 2076 2077 ci_stop_smc_clock(rdev); 2078 ci_reset_smc(rdev); 2079 2080 ret = ci_load_smc_ucode(rdev, pi->sram_end); 2081 2082 return ret; 2083 2084 } 2085 2086 static int ci_get_svi2_voltage_table(struct radeon_device *rdev, 2087 struct radeon_clock_voltage_dependency_table *voltage_dependency_table, 2088 struct atom_voltage_table *voltage_table) 2089 { 2090 u32 i; 2091 2092 if (voltage_dependency_table == NULL) 2093 return -EINVAL; 2094 2095 voltage_table->mask_low = 0; 2096 voltage_table->phase_delay = 0; 2097 2098 voltage_table->count = voltage_dependency_table->count; 2099 for (i = 0; i < voltage_table->count; i++) { 2100 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 2101 voltage_table->entries[i].smio_low = 0; 2102 } 2103 2104 return 0; 2105 } 2106 2107 static int ci_construct_voltage_tables(struct radeon_device *rdev) 2108 { 2109 struct ci_power_info *pi = ci_get_pi(rdev); 2110 int ret; 2111 2112 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { 2113 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 2114 VOLTAGE_OBJ_GPIO_LUT, 2115 &pi->vddc_voltage_table); 2116 if (ret) 2117 return ret; 2118 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { 2119 ret = ci_get_svi2_voltage_table(rdev, 2120 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 2121 &pi->vddc_voltage_table); 2122 if (ret) 2123 return ret; 2124 } 2125 2126 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC) 2127 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC, 2128 &pi->vddc_voltage_table); 2129 2130 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { 2131 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 2132 VOLTAGE_OBJ_GPIO_LUT, 2133 &pi->vddci_voltage_table); 2134 if (ret) 2135 return ret; 2136 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { 2137 ret = ci_get_svi2_voltage_table(rdev, 2138 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 2139 &pi->vddci_voltage_table); 2140 if (ret) 2141 return ret; 2142 } 2143 2144 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI) 2145 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI, 2146 &pi->vddci_voltage_table); 2147 2148 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { 2149 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 2150 VOLTAGE_OBJ_GPIO_LUT, 2151 &pi->mvdd_voltage_table); 2152 if (ret) 2153 return ret; 2154 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { 2155 ret = ci_get_svi2_voltage_table(rdev, 2156 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, 2157 &pi->mvdd_voltage_table); 2158 if (ret) 2159 return ret; 2160 } 2161 2162 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD) 2163 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD, 2164 &pi->mvdd_voltage_table); 2165 2166 return 0; 2167 } 2168 2169 static void ci_populate_smc_voltage_table(struct radeon_device *rdev, 2170 struct atom_voltage_table_entry *voltage_table, 2171 SMU7_Discrete_VoltageLevel *smc_voltage_table) 2172 { 2173 int ret; 2174 2175 ret = ci_get_std_voltage_value_sidd(rdev, voltage_table, 2176 &smc_voltage_table->StdVoltageHiSidd, 2177 &smc_voltage_table->StdVoltageLoSidd); 2178 2179 if (ret) { 2180 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE; 2181 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE; 2182 } 2183 2184 smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE); 2185 smc_voltage_table->StdVoltageHiSidd = 2186 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd); 2187 smc_voltage_table->StdVoltageLoSidd = 2188 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd); 2189 } 2190 2191 static int ci_populate_smc_vddc_table(struct radeon_device *rdev, 2192 SMU7_Discrete_DpmTable *table) 2193 { 2194 struct ci_power_info *pi = ci_get_pi(rdev); 2195 unsigned int count; 2196 2197 table->VddcLevelCount = pi->vddc_voltage_table.count; 2198 for (count = 0; count < table->VddcLevelCount; count++) { 2199 ci_populate_smc_voltage_table(rdev, 2200 &pi->vddc_voltage_table.entries[count], 2201 &table->VddcLevel[count]); 2202 2203 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) 2204 table->VddcLevel[count].Smio |= 2205 pi->vddc_voltage_table.entries[count].smio_low; 2206 else 2207 table->VddcLevel[count].Smio = 0; 2208 } 2209 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount); 2210 2211 return 0; 2212 } 2213 2214 static int ci_populate_smc_vddci_table(struct radeon_device *rdev, 2215 SMU7_Discrete_DpmTable *table) 2216 { 2217 unsigned int count; 2218 struct ci_power_info *pi = ci_get_pi(rdev); 2219 2220 table->VddciLevelCount = pi->vddci_voltage_table.count; 2221 for (count = 0; count < table->VddciLevelCount; count++) { 2222 ci_populate_smc_voltage_table(rdev, 2223 &pi->vddci_voltage_table.entries[count], 2224 &table->VddciLevel[count]); 2225 2226 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) 2227 table->VddciLevel[count].Smio |= 2228 pi->vddci_voltage_table.entries[count].smio_low; 2229 else 2230 table->VddciLevel[count].Smio = 0; 2231 } 2232 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount); 2233 2234 return 0; 2235 } 2236 2237 static int ci_populate_smc_mvdd_table(struct radeon_device *rdev, 2238 SMU7_Discrete_DpmTable *table) 2239 { 2240 struct ci_power_info *pi = ci_get_pi(rdev); 2241 unsigned int count; 2242 2243 table->MvddLevelCount = pi->mvdd_voltage_table.count; 2244 for (count = 0; count < table->MvddLevelCount; count++) { 2245 ci_populate_smc_voltage_table(rdev, 2246 &pi->mvdd_voltage_table.entries[count], 2247 &table->MvddLevel[count]); 2248 2249 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) 2250 table->MvddLevel[count].Smio |= 2251 pi->mvdd_voltage_table.entries[count].smio_low; 2252 else 2253 table->MvddLevel[count].Smio = 0; 2254 } 2255 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount); 2256 2257 return 0; 2258 } 2259 2260 static int ci_populate_smc_voltage_tables(struct radeon_device *rdev, 2261 SMU7_Discrete_DpmTable *table) 2262 { 2263 int ret; 2264 2265 ret = ci_populate_smc_vddc_table(rdev, table); 2266 if (ret) 2267 return ret; 2268 2269 ret = ci_populate_smc_vddci_table(rdev, table); 2270 if (ret) 2271 return ret; 2272 2273 ret = ci_populate_smc_mvdd_table(rdev, table); 2274 if (ret) 2275 return ret; 2276 2277 return 0; 2278 } 2279 2280 static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 2281 SMU7_Discrete_VoltageLevel *voltage) 2282 { 2283 struct ci_power_info *pi = ci_get_pi(rdev); 2284 u32 i = 0; 2285 2286 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) { 2287 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) { 2288 if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) { 2289 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value; 2290 break; 2291 } 2292 } 2293 2294 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count) 2295 return -EINVAL; 2296 } 2297 2298 return -EINVAL; 2299 } 2300 2301 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev, 2302 struct atom_voltage_table_entry *voltage_table, 2303 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd) 2304 { 2305 u16 v_index, idx; 2306 bool voltage_found = false; 2307 *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE; 2308 *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE; 2309 2310 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 2311 return -EINVAL; 2312 2313 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 2314 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 2315 if (voltage_table->value == 2316 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 2317 voltage_found = true; 2318 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 2319 idx = v_index; 2320 else 2321 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; 2322 *std_voltage_lo_sidd = 2323 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; 2324 *std_voltage_hi_sidd = 2325 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; 2326 break; 2327 } 2328 } 2329 2330 if (!voltage_found) { 2331 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 2332 if (voltage_table->value <= 2333 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 2334 voltage_found = true; 2335 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 2336 idx = v_index; 2337 else 2338 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; 2339 *std_voltage_lo_sidd = 2340 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; 2341 *std_voltage_hi_sidd = 2342 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; 2343 break; 2344 } 2345 } 2346 } 2347 } 2348 2349 return 0; 2350 } 2351 2352 static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev, 2353 const struct radeon_phase_shedding_limits_table *limits, 2354 u32 sclk, 2355 u32 *phase_shedding) 2356 { 2357 unsigned int i; 2358 2359 *phase_shedding = 1; 2360 2361 for (i = 0; i < limits->count; i++) { 2362 if (sclk < limits->entries[i].sclk) { 2363 *phase_shedding = i; 2364 break; 2365 } 2366 } 2367 } 2368 2369 static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev, 2370 const struct radeon_phase_shedding_limits_table *limits, 2371 u32 mclk, 2372 u32 *phase_shedding) 2373 { 2374 unsigned int i; 2375 2376 *phase_shedding = 1; 2377 2378 for (i = 0; i < limits->count; i++) { 2379 if (mclk < limits->entries[i].mclk) { 2380 *phase_shedding = i; 2381 break; 2382 } 2383 } 2384 } 2385 2386 static int ci_init_arb_table_index(struct radeon_device *rdev) 2387 { 2388 struct ci_power_info *pi = ci_get_pi(rdev); 2389 u32 tmp; 2390 int ret; 2391 2392 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start, 2393 &tmp, pi->sram_end); 2394 if (ret) 2395 return ret; 2396 2397 tmp &= 0x00FFFFFF; 2398 tmp |= MC_CG_ARB_FREQ_F1 << 24; 2399 2400 return ci_write_smc_sram_dword(rdev, pi->arb_table_start, 2401 tmp, pi->sram_end); 2402 } 2403 2404 static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev, 2405 struct radeon_clock_voltage_dependency_table *allowed_clock_voltage_table, 2406 u32 clock, u32 *voltage) 2407 { 2408 u32 i = 0; 2409 2410 if (allowed_clock_voltage_table->count == 0) 2411 return -EINVAL; 2412 2413 for (i = 0; i < allowed_clock_voltage_table->count; i++) { 2414 if (allowed_clock_voltage_table->entries[i].clk >= clock) { 2415 *voltage = allowed_clock_voltage_table->entries[i].v; 2416 return 0; 2417 } 2418 } 2419 2420 *voltage = allowed_clock_voltage_table->entries[i-1].v; 2421 2422 return 0; 2423 } 2424 2425 static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev, 2426 u32 sclk, u32 min_sclk_in_sr) 2427 { 2428 u32 i; 2429 u32 tmp; 2430 u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ? 2431 min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK; 2432 2433 if (sclk < min) 2434 return 0; 2435 2436 for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { 2437 tmp = sclk / (1 << i); 2438 if (tmp >= min || i == 0) 2439 break; 2440 } 2441 2442 return (u8)i; 2443 } 2444 2445 static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 2446 { 2447 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 2448 } 2449 2450 static int ci_reset_to_default(struct radeon_device *rdev) 2451 { 2452 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 2453 0 : -EINVAL; 2454 } 2455 2456 static int ci_force_switch_to_arb_f0(struct radeon_device *rdev) 2457 { 2458 u32 tmp; 2459 2460 tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8; 2461 2462 if (tmp == MC_CG_ARB_FREQ_F0) 2463 return 0; 2464 2465 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 2466 } 2467 2468 static void ci_register_patching_mc_arb(struct radeon_device *rdev, 2469 const u32 engine_clock, 2470 const u32 memory_clock, 2471 u32 *dram_timimg2) 2472 { 2473 bool patch; 2474 u32 tmp, tmp2; 2475 2476 tmp = RREG32(MC_SEQ_MISC0); 2477 patch = ((tmp & 0x0000f00) == 0x300) ? true : false; 2478 2479 if (patch && 2480 ((rdev->pdev->device == 0x67B0) || 2481 (rdev->pdev->device == 0x67B1))) { 2482 if ((memory_clock > 100000) && (memory_clock <= 125000)) { 2483 tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff; 2484 *dram_timimg2 &= ~0x00ff0000; 2485 *dram_timimg2 |= tmp2 << 16; 2486 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) { 2487 tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff; 2488 *dram_timimg2 &= ~0x00ff0000; 2489 *dram_timimg2 |= tmp2 << 16; 2490 } 2491 } 2492 } 2493 2494 2495 static int ci_populate_memory_timing_parameters(struct radeon_device *rdev, 2496 u32 sclk, 2497 u32 mclk, 2498 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs) 2499 { 2500 u32 dram_timing; 2501 u32 dram_timing2; 2502 u32 burst_time; 2503 2504 radeon_atom_set_engine_dram_timings(rdev, sclk, mclk); 2505 2506 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 2507 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 2508 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 2509 2510 ci_register_patching_mc_arb(rdev, sclk, mclk, &dram_timing2); 2511 2512 arb_regs->McArbDramTiming = cpu_to_be32(dram_timing); 2513 arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2); 2514 arb_regs->McArbBurstTime = (u8)burst_time; 2515 2516 return 0; 2517 } 2518 2519 static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev) 2520 { 2521 struct ci_power_info *pi = ci_get_pi(rdev); 2522 SMU7_Discrete_MCArbDramTimingTable arb_regs; 2523 u32 i, j; 2524 int ret = 0; 2525 2526 memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable)); 2527 2528 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { 2529 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { 2530 ret = ci_populate_memory_timing_parameters(rdev, 2531 pi->dpm_table.sclk_table.dpm_levels[i].value, 2532 pi->dpm_table.mclk_table.dpm_levels[j].value, 2533 &arb_regs.entries[i][j]); 2534 if (ret) 2535 break; 2536 } 2537 } 2538 2539 if (ret == 0) 2540 ret = ci_copy_bytes_to_smc(rdev, 2541 pi->arb_table_start, 2542 (u8 *)&arb_regs, 2543 sizeof(SMU7_Discrete_MCArbDramTimingTable), 2544 pi->sram_end); 2545 2546 return ret; 2547 } 2548 2549 static int ci_program_memory_timing_parameters(struct radeon_device *rdev) 2550 { 2551 struct ci_power_info *pi = ci_get_pi(rdev); 2552 2553 if (pi->need_update_smu7_dpm_table == 0) 2554 return 0; 2555 2556 return ci_do_program_memory_timing_parameters(rdev); 2557 } 2558 2559 static void ci_populate_smc_initial_state(struct radeon_device *rdev, 2560 struct radeon_ps *radeon_boot_state) 2561 { 2562 struct ci_ps *boot_state = ci_get_ps(radeon_boot_state); 2563 struct ci_power_info *pi = ci_get_pi(rdev); 2564 u32 level = 0; 2565 2566 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) { 2567 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >= 2568 boot_state->performance_levels[0].sclk) { 2569 pi->smc_state_table.GraphicsBootLevel = level; 2570 break; 2571 } 2572 } 2573 2574 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) { 2575 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >= 2576 boot_state->performance_levels[0].mclk) { 2577 pi->smc_state_table.MemoryBootLevel = level; 2578 break; 2579 } 2580 } 2581 } 2582 2583 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table) 2584 { 2585 u32 i; 2586 u32 mask_value = 0; 2587 2588 for (i = dpm_table->count; i > 0; i--) { 2589 mask_value = mask_value << 1; 2590 if (dpm_table->dpm_levels[i-1].enabled) 2591 mask_value |= 0x1; 2592 else 2593 mask_value &= 0xFFFFFFFE; 2594 } 2595 2596 return mask_value; 2597 } 2598 2599 static void ci_populate_smc_link_level(struct radeon_device *rdev, 2600 SMU7_Discrete_DpmTable *table) 2601 { 2602 struct ci_power_info *pi = ci_get_pi(rdev); 2603 struct ci_dpm_table *dpm_table = &pi->dpm_table; 2604 u32 i; 2605 2606 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) { 2607 table->LinkLevel[i].PcieGenSpeed = 2608 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value; 2609 table->LinkLevel[i].PcieLaneCount = 2610 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); 2611 table->LinkLevel[i].EnabledForActivity = 1; 2612 table->LinkLevel[i].DownT = cpu_to_be32(5); 2613 table->LinkLevel[i].UpT = cpu_to_be32(30); 2614 } 2615 2616 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; 2617 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = 2618 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); 2619 } 2620 2621 static int ci_populate_smc_uvd_level(struct radeon_device *rdev, 2622 SMU7_Discrete_DpmTable *table) 2623 { 2624 u32 count; 2625 struct atom_clock_dividers dividers; 2626 int ret = -EINVAL; 2627 2628 table->UvdLevelCount = 2629 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count; 2630 2631 for (count = 0; count < table->UvdLevelCount; count++) { 2632 table->UvdLevel[count].VclkFrequency = 2633 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk; 2634 table->UvdLevel[count].DclkFrequency = 2635 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk; 2636 table->UvdLevel[count].MinVddc = 2637 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; 2638 table->UvdLevel[count].MinVddcPhases = 1; 2639 2640 ret = radeon_atom_get_clock_dividers(rdev, 2641 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2642 table->UvdLevel[count].VclkFrequency, false, ÷rs); 2643 if (ret) 2644 return ret; 2645 2646 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider; 2647 2648 ret = radeon_atom_get_clock_dividers(rdev, 2649 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2650 table->UvdLevel[count].DclkFrequency, false, ÷rs); 2651 if (ret) 2652 return ret; 2653 2654 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider; 2655 2656 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency); 2657 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency); 2658 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc); 2659 } 2660 2661 return ret; 2662 } 2663 2664 static int ci_populate_smc_vce_level(struct radeon_device *rdev, 2665 SMU7_Discrete_DpmTable *table) 2666 { 2667 u32 count; 2668 struct atom_clock_dividers dividers; 2669 int ret = -EINVAL; 2670 2671 table->VceLevelCount = 2672 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count; 2673 2674 for (count = 0; count < table->VceLevelCount; count++) { 2675 table->VceLevel[count].Frequency = 2676 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk; 2677 table->VceLevel[count].MinVoltage = 2678 (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; 2679 table->VceLevel[count].MinPhases = 1; 2680 2681 ret = radeon_atom_get_clock_dividers(rdev, 2682 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2683 table->VceLevel[count].Frequency, false, ÷rs); 2684 if (ret) 2685 return ret; 2686 2687 table->VceLevel[count].Divider = (u8)dividers.post_divider; 2688 2689 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency); 2690 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage); 2691 } 2692 2693 return ret; 2694 2695 } 2696 2697 static int ci_populate_smc_acp_level(struct radeon_device *rdev, 2698 SMU7_Discrete_DpmTable *table) 2699 { 2700 u32 count; 2701 struct atom_clock_dividers dividers; 2702 int ret = -EINVAL; 2703 2704 table->AcpLevelCount = (u8) 2705 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count); 2706 2707 for (count = 0; count < table->AcpLevelCount; count++) { 2708 table->AcpLevel[count].Frequency = 2709 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk; 2710 table->AcpLevel[count].MinVoltage = 2711 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v; 2712 table->AcpLevel[count].MinPhases = 1; 2713 2714 ret = radeon_atom_get_clock_dividers(rdev, 2715 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2716 table->AcpLevel[count].Frequency, false, ÷rs); 2717 if (ret) 2718 return ret; 2719 2720 table->AcpLevel[count].Divider = (u8)dividers.post_divider; 2721 2722 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency); 2723 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage); 2724 } 2725 2726 return ret; 2727 } 2728 2729 static int ci_populate_smc_samu_level(struct radeon_device *rdev, 2730 SMU7_Discrete_DpmTable *table) 2731 { 2732 u32 count; 2733 struct atom_clock_dividers dividers; 2734 int ret = -EINVAL; 2735 2736 table->SamuLevelCount = 2737 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count; 2738 2739 for (count = 0; count < table->SamuLevelCount; count++) { 2740 table->SamuLevel[count].Frequency = 2741 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk; 2742 table->SamuLevel[count].MinVoltage = 2743 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; 2744 table->SamuLevel[count].MinPhases = 1; 2745 2746 ret = radeon_atom_get_clock_dividers(rdev, 2747 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2748 table->SamuLevel[count].Frequency, false, ÷rs); 2749 if (ret) 2750 return ret; 2751 2752 table->SamuLevel[count].Divider = (u8)dividers.post_divider; 2753 2754 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency); 2755 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage); 2756 } 2757 2758 return ret; 2759 } 2760 2761 static int ci_calculate_mclk_params(struct radeon_device *rdev, 2762 u32 memory_clock, 2763 SMU7_Discrete_MemoryLevel *mclk, 2764 bool strobe_mode, 2765 bool dll_state_on) 2766 { 2767 struct ci_power_info *pi = ci_get_pi(rdev); 2768 u32 dll_cntl = pi->clock_registers.dll_cntl; 2769 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; 2770 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl; 2771 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl; 2772 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl; 2773 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1; 2774 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2; 2775 u32 mpll_ss1 = pi->clock_registers.mpll_ss1; 2776 u32 mpll_ss2 = pi->clock_registers.mpll_ss2; 2777 struct atom_mpll_param mpll_param; 2778 int ret; 2779 2780 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 2781 if (ret) 2782 return ret; 2783 2784 mpll_func_cntl &= ~BWCTRL_MASK; 2785 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 2786 2787 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 2788 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 2789 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 2790 2791 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 2792 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 2793 2794 if (pi->mem_gddr5) { 2795 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 2796 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 2797 YCLK_POST_DIV(mpll_param.post_div); 2798 } 2799 2800 if (pi->caps_mclk_ss_support) { 2801 struct radeon_atom_ss ss; 2802 u32 freq_nom; 2803 u32 tmp; 2804 u32 reference_clock = rdev->clock.mpll.reference_freq; 2805 2806 if (mpll_param.qdr == 1) 2807 freq_nom = memory_clock * 4 * (1 << mpll_param.post_div); 2808 else 2809 freq_nom = memory_clock * 2 * (1 << mpll_param.post_div); 2810 2811 tmp = (freq_nom / reference_clock); 2812 tmp = tmp * tmp; 2813 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 2814 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 2815 u32 clks = reference_clock * 5 / ss.rate; 2816 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 2817 2818 mpll_ss1 &= ~CLKV_MASK; 2819 mpll_ss1 |= CLKV(clkv); 2820 2821 mpll_ss2 &= ~CLKS_MASK; 2822 mpll_ss2 |= CLKS(clks); 2823 } 2824 } 2825 2826 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 2827 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 2828 2829 if (dll_state_on) 2830 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 2831 else 2832 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 2833 2834 mclk->MclkFrequency = memory_clock; 2835 mclk->MpllFuncCntl = mpll_func_cntl; 2836 mclk->MpllFuncCntl_1 = mpll_func_cntl_1; 2837 mclk->MpllFuncCntl_2 = mpll_func_cntl_2; 2838 mclk->MpllAdFuncCntl = mpll_ad_func_cntl; 2839 mclk->MpllDqFuncCntl = mpll_dq_func_cntl; 2840 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl; 2841 mclk->DllCntl = dll_cntl; 2842 mclk->MpllSs1 = mpll_ss1; 2843 mclk->MpllSs2 = mpll_ss2; 2844 2845 return 0; 2846 } 2847 2848 static int ci_populate_single_memory_level(struct radeon_device *rdev, 2849 u32 memory_clock, 2850 SMU7_Discrete_MemoryLevel *memory_level) 2851 { 2852 struct ci_power_info *pi = ci_get_pi(rdev); 2853 int ret; 2854 bool dll_state_on; 2855 2856 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) { 2857 ret = ci_get_dependency_volt_by_clk(rdev, 2858 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 2859 memory_clock, &memory_level->MinVddc); 2860 if (ret) 2861 return ret; 2862 } 2863 2864 if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) { 2865 ret = ci_get_dependency_volt_by_clk(rdev, 2866 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 2867 memory_clock, &memory_level->MinVddci); 2868 if (ret) 2869 return ret; 2870 } 2871 2872 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) { 2873 ret = ci_get_dependency_volt_by_clk(rdev, 2874 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, 2875 memory_clock, &memory_level->MinMvdd); 2876 if (ret) 2877 return ret; 2878 } 2879 2880 memory_level->MinVddcPhases = 1; 2881 2882 if (pi->vddc_phase_shed_control) 2883 ci_populate_phase_value_based_on_mclk(rdev, 2884 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 2885 memory_clock, 2886 &memory_level->MinVddcPhases); 2887 2888 memory_level->EnabledForThrottle = 1; 2889 memory_level->UpH = 0; 2890 memory_level->DownH = 100; 2891 memory_level->VoltageDownH = 0; 2892 memory_level->ActivityLevel = (u16)pi->mclk_activity_target; 2893 2894 memory_level->StutterEnable = false; 2895 memory_level->StrobeEnable = false; 2896 memory_level->EdcReadEnable = false; 2897 memory_level->EdcWriteEnable = false; 2898 memory_level->RttEnable = false; 2899 2900 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 2901 2902 if (pi->mclk_stutter_mode_threshold && 2903 (memory_clock <= pi->mclk_stutter_mode_threshold) && 2904 (pi->uvd_enabled == false) && 2905 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 2906 (rdev->pm.dpm.new_active_crtc_count <= 2)) 2907 memory_level->StutterEnable = true; 2908 2909 if (pi->mclk_strobe_mode_threshold && 2910 (memory_clock <= pi->mclk_strobe_mode_threshold)) 2911 memory_level->StrobeEnable = 1; 2912 2913 if (pi->mem_gddr5) { 2914 memory_level->StrobeRatio = 2915 si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable); 2916 if (pi->mclk_edc_enable_threshold && 2917 (memory_clock > pi->mclk_edc_enable_threshold)) 2918 memory_level->EdcReadEnable = true; 2919 2920 if (pi->mclk_edc_wr_enable_threshold && 2921 (memory_clock > pi->mclk_edc_wr_enable_threshold)) 2922 memory_level->EdcWriteEnable = true; 2923 2924 if (memory_level->StrobeEnable) { 2925 if (si_get_mclk_frequency_ratio(memory_clock, true) >= 2926 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 2927 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 2928 else 2929 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 2930 } else { 2931 dll_state_on = pi->dll_default_on; 2932 } 2933 } else { 2934 memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock); 2935 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 2936 } 2937 2938 ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on); 2939 if (ret) 2940 return ret; 2941 2942 memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE); 2943 memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases); 2944 memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE); 2945 memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE); 2946 2947 memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency); 2948 memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel); 2949 memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl); 2950 memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1); 2951 memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2); 2952 memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl); 2953 memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl); 2954 memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl); 2955 memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl); 2956 memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1); 2957 memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2); 2958 2959 return 0; 2960 } 2961 2962 static int ci_populate_smc_acpi_level(struct radeon_device *rdev, 2963 SMU7_Discrete_DpmTable *table) 2964 { 2965 struct ci_power_info *pi = ci_get_pi(rdev); 2966 struct atom_clock_dividers dividers; 2967 SMU7_Discrete_VoltageLevel voltage_level; 2968 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl; 2969 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2; 2970 u32 dll_cntl = pi->clock_registers.dll_cntl; 2971 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; 2972 int ret; 2973 2974 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; 2975 2976 if (pi->acpi_vddc) 2977 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE); 2978 else 2979 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE); 2980 2981 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; 2982 2983 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq; 2984 2985 ret = radeon_atom_get_clock_dividers(rdev, 2986 COMPUTE_GPUCLK_INPUT_FLAG_SCLK, 2987 table->ACPILevel.SclkFrequency, false, ÷rs); 2988 if (ret) 2989 return ret; 2990 2991 table->ACPILevel.SclkDid = (u8)dividers.post_divider; 2992 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 2993 table->ACPILevel.DeepSleepDivId = 0; 2994 2995 spll_func_cntl &= ~SPLL_PWRON; 2996 spll_func_cntl |= SPLL_RESET; 2997 2998 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 2999 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 3000 3001 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl; 3002 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2; 3003 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3; 3004 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4; 3005 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum; 3006 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2; 3007 table->ACPILevel.CcPwrDynRm = 0; 3008 table->ACPILevel.CcPwrDynRm1 = 0; 3009 3010 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags); 3011 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases); 3012 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency); 3013 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl); 3014 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2); 3015 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3); 3016 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4); 3017 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum); 3018 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2); 3019 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm); 3020 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1); 3021 3022 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc; 3023 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases; 3024 3025 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) { 3026 if (pi->acpi_vddci) 3027 table->MemoryACPILevel.MinVddci = 3028 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE); 3029 else 3030 table->MemoryACPILevel.MinVddci = 3031 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE); 3032 } 3033 3034 if (ci_populate_mvdd_value(rdev, 0, &voltage_level)) 3035 table->MemoryACPILevel.MinMvdd = 0; 3036 else 3037 table->MemoryACPILevel.MinMvdd = 3038 cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE); 3039 3040 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 3041 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 3042 3043 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 3044 3045 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl); 3046 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl); 3047 table->MemoryACPILevel.MpllAdFuncCntl = 3048 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl); 3049 table->MemoryACPILevel.MpllDqFuncCntl = 3050 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl); 3051 table->MemoryACPILevel.MpllFuncCntl = 3052 cpu_to_be32(pi->clock_registers.mpll_func_cntl); 3053 table->MemoryACPILevel.MpllFuncCntl_1 = 3054 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1); 3055 table->MemoryACPILevel.MpllFuncCntl_2 = 3056 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2); 3057 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1); 3058 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2); 3059 3060 table->MemoryACPILevel.EnabledForThrottle = 0; 3061 table->MemoryACPILevel.EnabledForActivity = 0; 3062 table->MemoryACPILevel.UpH = 0; 3063 table->MemoryACPILevel.DownH = 100; 3064 table->MemoryACPILevel.VoltageDownH = 0; 3065 table->MemoryACPILevel.ActivityLevel = 3066 cpu_to_be16((u16)pi->mclk_activity_target); 3067 3068 table->MemoryACPILevel.StutterEnable = false; 3069 table->MemoryACPILevel.StrobeEnable = false; 3070 table->MemoryACPILevel.EdcReadEnable = false; 3071 table->MemoryACPILevel.EdcWriteEnable = false; 3072 table->MemoryACPILevel.RttEnable = false; 3073 3074 return 0; 3075 } 3076 3077 3078 static int ci_enable_ulv(struct radeon_device *rdev, bool enable) 3079 { 3080 struct ci_power_info *pi = ci_get_pi(rdev); 3081 struct ci_ulv_parm *ulv = &pi->ulv; 3082 3083 if (ulv->supported) { 3084 if (enable) 3085 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 3086 0 : -EINVAL; 3087 else 3088 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 3089 0 : -EINVAL; 3090 } 3091 3092 return 0; 3093 } 3094 3095 static int ci_populate_ulv_level(struct radeon_device *rdev, 3096 SMU7_Discrete_Ulv *state) 3097 { 3098 struct ci_power_info *pi = ci_get_pi(rdev); 3099 u16 ulv_voltage = rdev->pm.dpm.backbias_response_time; 3100 3101 state->CcPwrDynRm = 0; 3102 state->CcPwrDynRm1 = 0; 3103 3104 if (ulv_voltage == 0) { 3105 pi->ulv.supported = false; 3106 return 0; 3107 } 3108 3109 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { 3110 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) 3111 state->VddcOffset = 0; 3112 else 3113 state->VddcOffset = 3114 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage; 3115 } else { 3116 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) 3117 state->VddcOffsetVid = 0; 3118 else 3119 state->VddcOffsetVid = (u8) 3120 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) * 3121 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1); 3122 } 3123 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1; 3124 3125 state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm); 3126 state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1); 3127 state->VddcOffset = cpu_to_be16(state->VddcOffset); 3128 3129 return 0; 3130 } 3131 3132 static int ci_calculate_sclk_params(struct radeon_device *rdev, 3133 u32 engine_clock, 3134 SMU7_Discrete_GraphicsLevel *sclk) 3135 { 3136 struct ci_power_info *pi = ci_get_pi(rdev); 3137 struct atom_clock_dividers dividers; 3138 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3; 3139 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4; 3140 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum; 3141 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2; 3142 u32 reference_clock = rdev->clock.spll.reference_freq; 3143 u32 reference_divider; 3144 u32 fbdiv; 3145 int ret; 3146 3147 ret = radeon_atom_get_clock_dividers(rdev, 3148 COMPUTE_GPUCLK_INPUT_FLAG_SCLK, 3149 engine_clock, false, ÷rs); 3150 if (ret) 3151 return ret; 3152 3153 reference_divider = 1 + dividers.ref_div; 3154 fbdiv = dividers.fb_div & 0x3FFFFFF; 3155 3156 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 3157 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 3158 spll_func_cntl_3 |= SPLL_DITHEN; 3159 3160 if (pi->caps_sclk_ss_support) { 3161 struct radeon_atom_ss ss; 3162 u32 vco_freq = engine_clock * dividers.post_div; 3163 3164 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 3165 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 3166 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 3167 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 3168 3169 cg_spll_spread_spectrum &= ~CLK_S_MASK; 3170 cg_spll_spread_spectrum |= CLK_S(clk_s); 3171 cg_spll_spread_spectrum |= SSEN; 3172 3173 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 3174 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 3175 } 3176 } 3177 3178 sclk->SclkFrequency = engine_clock; 3179 sclk->CgSpllFuncCntl3 = spll_func_cntl_3; 3180 sclk->CgSpllFuncCntl4 = spll_func_cntl_4; 3181 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum; 3182 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2; 3183 sclk->SclkDid = (u8)dividers.post_divider; 3184 3185 return 0; 3186 } 3187 3188 static int ci_populate_single_graphic_level(struct radeon_device *rdev, 3189 u32 engine_clock, 3190 u16 sclk_activity_level_t, 3191 SMU7_Discrete_GraphicsLevel *graphic_level) 3192 { 3193 struct ci_power_info *pi = ci_get_pi(rdev); 3194 int ret; 3195 3196 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level); 3197 if (ret) 3198 return ret; 3199 3200 ret = ci_get_dependency_volt_by_clk(rdev, 3201 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3202 engine_clock, &graphic_level->MinVddc); 3203 if (ret) 3204 return ret; 3205 3206 graphic_level->SclkFrequency = engine_clock; 3207 3208 graphic_level->Flags = 0; 3209 graphic_level->MinVddcPhases = 1; 3210 3211 if (pi->vddc_phase_shed_control) 3212 ci_populate_phase_value_based_on_sclk(rdev, 3213 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 3214 engine_clock, 3215 &graphic_level->MinVddcPhases); 3216 3217 graphic_level->ActivityLevel = sclk_activity_level_t; 3218 3219 graphic_level->CcPwrDynRm = 0; 3220 graphic_level->CcPwrDynRm1 = 0; 3221 graphic_level->EnabledForThrottle = 1; 3222 graphic_level->UpH = 0; 3223 graphic_level->DownH = 0; 3224 graphic_level->VoltageDownH = 0; 3225 graphic_level->PowerThrottle = 0; 3226 3227 if (pi->caps_sclk_ds) 3228 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev, 3229 engine_clock, 3230 CISLAND_MINIMUM_ENGINE_CLOCK); 3231 3232 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 3233 3234 graphic_level->Flags = cpu_to_be32(graphic_level->Flags); 3235 graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE); 3236 graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases); 3237 graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency); 3238 graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel); 3239 graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3); 3240 graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4); 3241 graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum); 3242 graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2); 3243 graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm); 3244 graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1); 3245 3246 return 0; 3247 } 3248 3249 static int ci_populate_all_graphic_levels(struct radeon_device *rdev) 3250 { 3251 struct ci_power_info *pi = ci_get_pi(rdev); 3252 struct ci_dpm_table *dpm_table = &pi->dpm_table; 3253 u32 level_array_address = pi->dpm_table_start + 3254 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel); 3255 u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) * 3256 SMU7_MAX_LEVELS_GRAPHICS; 3257 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; 3258 u32 i, ret; 3259 3260 memset(levels, 0, level_array_size); 3261 3262 for (i = 0; i < dpm_table->sclk_table.count; i++) { 3263 ret = ci_populate_single_graphic_level(rdev, 3264 dpm_table->sclk_table.dpm_levels[i].value, 3265 (u16)pi->activity_target[i], 3266 &pi->smc_state_table.GraphicsLevel[i]); 3267 if (ret) 3268 return ret; 3269 if (i > 1) 3270 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; 3271 if (i == (dpm_table->sclk_table.count - 1)) 3272 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = 3273 PPSMC_DISPLAY_WATERMARK_HIGH; 3274 } 3275 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; 3276 3277 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; 3278 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = 3279 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); 3280 3281 ret = ci_copy_bytes_to_smc(rdev, level_array_address, 3282 (u8 *)levels, level_array_size, 3283 pi->sram_end); 3284 if (ret) 3285 return ret; 3286 3287 return 0; 3288 } 3289 3290 static int ci_populate_ulv_state(struct radeon_device *rdev, 3291 SMU7_Discrete_Ulv *ulv_level) 3292 { 3293 return ci_populate_ulv_level(rdev, ulv_level); 3294 } 3295 3296 static int ci_populate_all_memory_levels(struct radeon_device *rdev) 3297 { 3298 struct ci_power_info *pi = ci_get_pi(rdev); 3299 struct ci_dpm_table *dpm_table = &pi->dpm_table; 3300 u32 level_array_address = pi->dpm_table_start + 3301 offsetof(SMU7_Discrete_DpmTable, MemoryLevel); 3302 u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) * 3303 SMU7_MAX_LEVELS_MEMORY; 3304 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel; 3305 u32 i, ret; 3306 3307 memset(levels, 0, level_array_size); 3308 3309 for (i = 0; i < dpm_table->mclk_table.count; i++) { 3310 if (dpm_table->mclk_table.dpm_levels[i].value == 0) 3311 return -EINVAL; 3312 ret = ci_populate_single_memory_level(rdev, 3313 dpm_table->mclk_table.dpm_levels[i].value, 3314 &pi->smc_state_table.MemoryLevel[i]); 3315 if (ret) 3316 return ret; 3317 } 3318 3319 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; 3320 3321 if ((dpm_table->mclk_table.count >= 2) && 3322 ((rdev->pdev->device == 0x67B0) || (rdev->pdev->device == 0x67B1))) { 3323 pi->smc_state_table.MemoryLevel[1].MinVddc = 3324 pi->smc_state_table.MemoryLevel[0].MinVddc; 3325 pi->smc_state_table.MemoryLevel[1].MinVddcPhases = 3326 pi->smc_state_table.MemoryLevel[0].MinVddcPhases; 3327 } 3328 3329 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F); 3330 3331 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; 3332 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = 3333 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); 3334 3335 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = 3336 PPSMC_DISPLAY_WATERMARK_HIGH; 3337 3338 ret = ci_copy_bytes_to_smc(rdev, level_array_address, 3339 (u8 *)levels, level_array_size, 3340 pi->sram_end); 3341 if (ret) 3342 return ret; 3343 3344 return 0; 3345 } 3346 3347 static void ci_reset_single_dpm_table(struct radeon_device *rdev, 3348 struct ci_single_dpm_table* dpm_table, 3349 u32 count) 3350 { 3351 u32 i; 3352 3353 dpm_table->count = count; 3354 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) 3355 dpm_table->dpm_levels[i].enabled = false; 3356 } 3357 3358 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table, 3359 u32 index, u32 pcie_gen, u32 pcie_lanes) 3360 { 3361 dpm_table->dpm_levels[index].value = pcie_gen; 3362 dpm_table->dpm_levels[index].param1 = pcie_lanes; 3363 dpm_table->dpm_levels[index].enabled = true; 3364 } 3365 3366 static int ci_setup_default_pcie_tables(struct radeon_device *rdev) 3367 { 3368 struct ci_power_info *pi = ci_get_pi(rdev); 3369 3370 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) 3371 return -EINVAL; 3372 3373 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) { 3374 pi->pcie_gen_powersaving = pi->pcie_gen_performance; 3375 pi->pcie_lane_powersaving = pi->pcie_lane_performance; 3376 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) { 3377 pi->pcie_gen_performance = pi->pcie_gen_powersaving; 3378 pi->pcie_lane_performance = pi->pcie_lane_powersaving; 3379 } 3380 3381 ci_reset_single_dpm_table(rdev, 3382 &pi->dpm_table.pcie_speed_table, 3383 SMU7_MAX_LEVELS_LINK); 3384 3385 if (rdev->family == CHIP_BONAIRE) 3386 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, 3387 pi->pcie_gen_powersaving.min, 3388 pi->pcie_lane_powersaving.max); 3389 else 3390 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, 3391 pi->pcie_gen_powersaving.min, 3392 pi->pcie_lane_powersaving.min); 3393 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1, 3394 pi->pcie_gen_performance.min, 3395 pi->pcie_lane_performance.min); 3396 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2, 3397 pi->pcie_gen_powersaving.min, 3398 pi->pcie_lane_powersaving.max); 3399 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3, 3400 pi->pcie_gen_performance.min, 3401 pi->pcie_lane_performance.max); 3402 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4, 3403 pi->pcie_gen_powersaving.max, 3404 pi->pcie_lane_powersaving.max); 3405 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5, 3406 pi->pcie_gen_performance.max, 3407 pi->pcie_lane_performance.max); 3408 3409 pi->dpm_table.pcie_speed_table.count = 6; 3410 3411 return 0; 3412 } 3413 3414 static int ci_setup_default_dpm_tables(struct radeon_device *rdev) 3415 { 3416 struct ci_power_info *pi = ci_get_pi(rdev); 3417 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table = 3418 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 3419 struct radeon_clock_voltage_dependency_table *allowed_mclk_table = 3420 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; 3421 struct radeon_cac_leakage_table *std_voltage_table = 3422 &rdev->pm.dpm.dyn_state.cac_leakage_table; 3423 u32 i; 3424 3425 if (allowed_sclk_vddc_table == NULL) 3426 return -EINVAL; 3427 if (allowed_sclk_vddc_table->count < 1) 3428 return -EINVAL; 3429 if (allowed_mclk_table == NULL) 3430 return -EINVAL; 3431 if (allowed_mclk_table->count < 1) 3432 return -EINVAL; 3433 3434 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table)); 3435 3436 ci_reset_single_dpm_table(rdev, 3437 &pi->dpm_table.sclk_table, 3438 SMU7_MAX_LEVELS_GRAPHICS); 3439 ci_reset_single_dpm_table(rdev, 3440 &pi->dpm_table.mclk_table, 3441 SMU7_MAX_LEVELS_MEMORY); 3442 ci_reset_single_dpm_table(rdev, 3443 &pi->dpm_table.vddc_table, 3444 SMU7_MAX_LEVELS_VDDC); 3445 ci_reset_single_dpm_table(rdev, 3446 &pi->dpm_table.vddci_table, 3447 SMU7_MAX_LEVELS_VDDCI); 3448 ci_reset_single_dpm_table(rdev, 3449 &pi->dpm_table.mvdd_table, 3450 SMU7_MAX_LEVELS_MVDD); 3451 3452 pi->dpm_table.sclk_table.count = 0; 3453 for (i = 0; i < allowed_sclk_vddc_table->count; i++) { 3454 if ((i == 0) || 3455 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != 3456 allowed_sclk_vddc_table->entries[i].clk)) { 3457 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = 3458 allowed_sclk_vddc_table->entries[i].clk; 3459 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = 3460 (i == 0) ? true : false; 3461 pi->dpm_table.sclk_table.count++; 3462 } 3463 } 3464 3465 pi->dpm_table.mclk_table.count = 0; 3466 for (i = 0; i < allowed_mclk_table->count; i++) { 3467 if ((i == 0) || 3468 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != 3469 allowed_mclk_table->entries[i].clk)) { 3470 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = 3471 allowed_mclk_table->entries[i].clk; 3472 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = 3473 (i == 0) ? true : false; 3474 pi->dpm_table.mclk_table.count++; 3475 } 3476 } 3477 3478 for (i = 0; i < allowed_sclk_vddc_table->count; i++) { 3479 pi->dpm_table.vddc_table.dpm_levels[i].value = 3480 allowed_sclk_vddc_table->entries[i].v; 3481 pi->dpm_table.vddc_table.dpm_levels[i].param1 = 3482 std_voltage_table->entries[i].leakage; 3483 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true; 3484 } 3485 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; 3486 3487 allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; 3488 if (allowed_mclk_table) { 3489 for (i = 0; i < allowed_mclk_table->count; i++) { 3490 pi->dpm_table.vddci_table.dpm_levels[i].value = 3491 allowed_mclk_table->entries[i].v; 3492 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true; 3493 } 3494 pi->dpm_table.vddci_table.count = allowed_mclk_table->count; 3495 } 3496 3497 allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk; 3498 if (allowed_mclk_table) { 3499 for (i = 0; i < allowed_mclk_table->count; i++) { 3500 pi->dpm_table.mvdd_table.dpm_levels[i].value = 3501 allowed_mclk_table->entries[i].v; 3502 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true; 3503 } 3504 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count; 3505 } 3506 3507 ci_setup_default_pcie_tables(rdev); 3508 3509 return 0; 3510 } 3511 3512 static int ci_find_boot_level(struct ci_single_dpm_table *table, 3513 u32 value, u32 *boot_level) 3514 { 3515 u32 i; 3516 int ret = -EINVAL; 3517 3518 for(i = 0; i < table->count; i++) { 3519 if (value == table->dpm_levels[i].value) { 3520 *boot_level = i; 3521 ret = 0; 3522 } 3523 } 3524 3525 return ret; 3526 } 3527 3528 static int ci_init_smc_table(struct radeon_device *rdev) 3529 { 3530 struct ci_power_info *pi = ci_get_pi(rdev); 3531 struct ci_ulv_parm *ulv = &pi->ulv; 3532 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 3533 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; 3534 int ret; 3535 3536 ret = ci_setup_default_dpm_tables(rdev); 3537 if (ret) 3538 return ret; 3539 3540 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) 3541 ci_populate_smc_voltage_tables(rdev, table); 3542 3543 ci_init_fps_limits(rdev); 3544 3545 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 3546 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 3547 3548 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 3549 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 3550 3551 if (pi->mem_gddr5) 3552 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 3553 3554 if (ulv->supported) { 3555 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv); 3556 if (ret) 3557 return ret; 3558 WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 3559 } 3560 3561 ret = ci_populate_all_graphic_levels(rdev); 3562 if (ret) 3563 return ret; 3564 3565 ret = ci_populate_all_memory_levels(rdev); 3566 if (ret) 3567 return ret; 3568 3569 ci_populate_smc_link_level(rdev, table); 3570 3571 ret = ci_populate_smc_acpi_level(rdev, table); 3572 if (ret) 3573 return ret; 3574 3575 ret = ci_populate_smc_vce_level(rdev, table); 3576 if (ret) 3577 return ret; 3578 3579 ret = ci_populate_smc_acp_level(rdev, table); 3580 if (ret) 3581 return ret; 3582 3583 ret = ci_populate_smc_samu_level(rdev, table); 3584 if (ret) 3585 return ret; 3586 3587 ret = ci_do_program_memory_timing_parameters(rdev); 3588 if (ret) 3589 return ret; 3590 3591 ret = ci_populate_smc_uvd_level(rdev, table); 3592 if (ret) 3593 return ret; 3594 3595 table->UvdBootLevel = 0; 3596 table->VceBootLevel = 0; 3597 table->AcpBootLevel = 0; 3598 table->SamuBootLevel = 0; 3599 table->GraphicsBootLevel = 0; 3600 table->MemoryBootLevel = 0; 3601 3602 ret = ci_find_boot_level(&pi->dpm_table.sclk_table, 3603 pi->vbios_boot_state.sclk_bootup_value, 3604 (u32 *)&pi->smc_state_table.GraphicsBootLevel); 3605 3606 ret = ci_find_boot_level(&pi->dpm_table.mclk_table, 3607 pi->vbios_boot_state.mclk_bootup_value, 3608 (u32 *)&pi->smc_state_table.MemoryBootLevel); 3609 3610 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value; 3611 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value; 3612 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value; 3613 3614 ci_populate_smc_initial_state(rdev, radeon_boot_state); 3615 3616 ret = ci_populate_bapm_parameters_in_dpm_table(rdev); 3617 if (ret) 3618 return ret; 3619 3620 table->UVDInterval = 1; 3621 table->VCEInterval = 1; 3622 table->ACPInterval = 1; 3623 table->SAMUInterval = 1; 3624 table->GraphicsVoltageChangeEnable = 1; 3625 table->GraphicsThermThrottleEnable = 1; 3626 table->GraphicsInterval = 1; 3627 table->VoltageInterval = 1; 3628 table->ThermalInterval = 1; 3629 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high * 3630 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000); 3631 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low * 3632 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000); 3633 table->MemoryVoltageChangeEnable = 1; 3634 table->MemoryInterval = 1; 3635 table->VoltageResponseTime = 0; 3636 table->VddcVddciDelta = 4000; 3637 table->PhaseResponseTime = 0; 3638 table->MemoryThermThrottleEnable = 1; 3639 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1; 3640 table->PCIeGenInterval = 1; 3641 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) 3642 table->SVI2Enable = 1; 3643 else 3644 table->SVI2Enable = 0; 3645 3646 table->ThermGpio = 17; 3647 table->SclkStepSize = 0x4000; 3648 3649 table->SystemFlags = cpu_to_be32(table->SystemFlags); 3650 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid); 3651 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase); 3652 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid); 3653 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid); 3654 table->SclkStepSize = cpu_to_be32(table->SclkStepSize); 3655 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh); 3656 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow); 3657 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta); 3658 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime); 3659 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime); 3660 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE); 3661 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE); 3662 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE); 3663 3664 ret = ci_copy_bytes_to_smc(rdev, 3665 pi->dpm_table_start + 3666 offsetof(SMU7_Discrete_DpmTable, SystemFlags), 3667 (u8 *)&table->SystemFlags, 3668 sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController), 3669 pi->sram_end); 3670 if (ret) 3671 return ret; 3672 3673 return 0; 3674 } 3675 3676 static void ci_trim_single_dpm_states(struct radeon_device *rdev, 3677 struct ci_single_dpm_table *dpm_table, 3678 u32 low_limit, u32 high_limit) 3679 { 3680 u32 i; 3681 3682 for (i = 0; i < dpm_table->count; i++) { 3683 if ((dpm_table->dpm_levels[i].value < low_limit) || 3684 (dpm_table->dpm_levels[i].value > high_limit)) 3685 dpm_table->dpm_levels[i].enabled = false; 3686 else 3687 dpm_table->dpm_levels[i].enabled = true; 3688 } 3689 } 3690 3691 static void ci_trim_pcie_dpm_states(struct radeon_device *rdev, 3692 u32 speed_low, u32 lanes_low, 3693 u32 speed_high, u32 lanes_high) 3694 { 3695 struct ci_power_info *pi = ci_get_pi(rdev); 3696 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table; 3697 u32 i, j; 3698 3699 for (i = 0; i < pcie_table->count; i++) { 3700 if ((pcie_table->dpm_levels[i].value < speed_low) || 3701 (pcie_table->dpm_levels[i].param1 < lanes_low) || 3702 (pcie_table->dpm_levels[i].value > speed_high) || 3703 (pcie_table->dpm_levels[i].param1 > lanes_high)) 3704 pcie_table->dpm_levels[i].enabled = false; 3705 else 3706 pcie_table->dpm_levels[i].enabled = true; 3707 } 3708 3709 for (i = 0; i < pcie_table->count; i++) { 3710 if (pcie_table->dpm_levels[i].enabled) { 3711 for (j = i + 1; j < pcie_table->count; j++) { 3712 if (pcie_table->dpm_levels[j].enabled) { 3713 if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) && 3714 (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1)) 3715 pcie_table->dpm_levels[j].enabled = false; 3716 } 3717 } 3718 } 3719 } 3720 } 3721 3722 static int ci_trim_dpm_states(struct radeon_device *rdev, 3723 struct radeon_ps *radeon_state) 3724 { 3725 struct ci_ps *state = ci_get_ps(radeon_state); 3726 struct ci_power_info *pi = ci_get_pi(rdev); 3727 u32 high_limit_count; 3728 3729 if (state->performance_level_count < 1) 3730 return -EINVAL; 3731 3732 if (state->performance_level_count == 1) 3733 high_limit_count = 0; 3734 else 3735 high_limit_count = 1; 3736 3737 ci_trim_single_dpm_states(rdev, 3738 &pi->dpm_table.sclk_table, 3739 state->performance_levels[0].sclk, 3740 state->performance_levels[high_limit_count].sclk); 3741 3742 ci_trim_single_dpm_states(rdev, 3743 &pi->dpm_table.mclk_table, 3744 state->performance_levels[0].mclk, 3745 state->performance_levels[high_limit_count].mclk); 3746 3747 ci_trim_pcie_dpm_states(rdev, 3748 state->performance_levels[0].pcie_gen, 3749 state->performance_levels[0].pcie_lane, 3750 state->performance_levels[high_limit_count].pcie_gen, 3751 state->performance_levels[high_limit_count].pcie_lane); 3752 3753 return 0; 3754 } 3755 3756 static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev) 3757 { 3758 struct radeon_clock_voltage_dependency_table *disp_voltage_table = 3759 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk; 3760 struct radeon_clock_voltage_dependency_table *vddc_table = 3761 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 3762 u32 requested_voltage = 0; 3763 u32 i; 3764 3765 if (disp_voltage_table == NULL) 3766 return -EINVAL; 3767 if (!disp_voltage_table->count) 3768 return -EINVAL; 3769 3770 for (i = 0; i < disp_voltage_table->count; i++) { 3771 if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk) 3772 requested_voltage = disp_voltage_table->entries[i].v; 3773 } 3774 3775 for (i = 0; i < vddc_table->count; i++) { 3776 if (requested_voltage <= vddc_table->entries[i].v) { 3777 requested_voltage = vddc_table->entries[i].v; 3778 return (ci_send_msg_to_smc_with_parameter(rdev, 3779 PPSMC_MSG_VddC_Request, 3780 requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ? 3781 0 : -EINVAL; 3782 } 3783 } 3784 3785 return -EINVAL; 3786 } 3787 3788 static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev) 3789 { 3790 struct ci_power_info *pi = ci_get_pi(rdev); 3791 PPSMC_Result result; 3792 3793 ci_apply_disp_minimum_voltage_request(rdev); 3794 3795 if (!pi->sclk_dpm_key_disabled) { 3796 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { 3797 result = ci_send_msg_to_smc_with_parameter(rdev, 3798 PPSMC_MSG_SCLKDPM_SetEnabledMask, 3799 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); 3800 if (result != PPSMC_Result_OK) 3801 return -EINVAL; 3802 } 3803 } 3804 3805 if (!pi->mclk_dpm_key_disabled) { 3806 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { 3807 result = ci_send_msg_to_smc_with_parameter(rdev, 3808 PPSMC_MSG_MCLKDPM_SetEnabledMask, 3809 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); 3810 if (result != PPSMC_Result_OK) 3811 return -EINVAL; 3812 } 3813 } 3814 #if 0 3815 if (!pi->pcie_dpm_key_disabled) { 3816 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { 3817 result = ci_send_msg_to_smc_with_parameter(rdev, 3818 PPSMC_MSG_PCIeDPM_SetEnabledMask, 3819 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); 3820 if (result != PPSMC_Result_OK) 3821 return -EINVAL; 3822 } 3823 } 3824 #endif 3825 return 0; 3826 } 3827 3828 static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev, 3829 struct radeon_ps *radeon_state) 3830 { 3831 struct ci_power_info *pi = ci_get_pi(rdev); 3832 struct ci_ps *state = ci_get_ps(radeon_state); 3833 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; 3834 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; 3835 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; 3836 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; 3837 u32 i; 3838 3839 pi->need_update_smu7_dpm_table = 0; 3840 3841 for (i = 0; i < sclk_table->count; i++) { 3842 if (sclk == sclk_table->dpm_levels[i].value) 3843 break; 3844 } 3845 3846 if (i >= sclk_table->count) { 3847 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; 3848 } else { 3849 /* XXX The current code always reprogrammed the sclk levels, 3850 * but we don't currently handle disp sclk requirements 3851 * so just skip it. 3852 */ 3853 if (CISLAND_MINIMUM_ENGINE_CLOCK != CISLAND_MINIMUM_ENGINE_CLOCK) 3854 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; 3855 } 3856 3857 for (i = 0; i < mclk_table->count; i++) { 3858 if (mclk == mclk_table->dpm_levels[i].value) 3859 break; 3860 } 3861 3862 if (i >= mclk_table->count) 3863 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; 3864 3865 if (rdev->pm.dpm.current_active_crtc_count != 3866 rdev->pm.dpm.new_active_crtc_count) 3867 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; 3868 } 3869 3870 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev, 3871 struct radeon_ps *radeon_state) 3872 { 3873 struct ci_power_info *pi = ci_get_pi(rdev); 3874 struct ci_ps *state = ci_get_ps(radeon_state); 3875 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; 3876 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; 3877 struct ci_dpm_table *dpm_table = &pi->dpm_table; 3878 int ret; 3879 3880 if (!pi->need_update_smu7_dpm_table) 3881 return 0; 3882 3883 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) 3884 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk; 3885 3886 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) 3887 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk; 3888 3889 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { 3890 ret = ci_populate_all_graphic_levels(rdev); 3891 if (ret) 3892 return ret; 3893 } 3894 3895 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { 3896 ret = ci_populate_all_memory_levels(rdev); 3897 if (ret) 3898 return ret; 3899 } 3900 3901 return 0; 3902 } 3903 3904 static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable) 3905 { 3906 struct ci_power_info *pi = ci_get_pi(rdev); 3907 const struct radeon_clock_and_voltage_limits *max_limits; 3908 int i; 3909 3910 if (rdev->pm.dpm.ac_power) 3911 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3912 else 3913 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3914 3915 if (enable) { 3916 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; 3917 3918 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) { 3919 if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { 3920 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i; 3921 3922 if (!pi->caps_uvd_dpm) 3923 break; 3924 } 3925 } 3926 3927 ci_send_msg_to_smc_with_parameter(rdev, 3928 PPSMC_MSG_UVDDPM_SetEnabledMask, 3929 pi->dpm_level_enable_mask.uvd_dpm_enable_mask); 3930 3931 if (pi->last_mclk_dpm_enable_mask & 0x1) { 3932 pi->uvd_enabled = true; 3933 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; 3934 ci_send_msg_to_smc_with_parameter(rdev, 3935 PPSMC_MSG_MCLKDPM_SetEnabledMask, 3936 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); 3937 } 3938 } else { 3939 if (pi->last_mclk_dpm_enable_mask & 0x1) { 3940 pi->uvd_enabled = false; 3941 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1; 3942 ci_send_msg_to_smc_with_parameter(rdev, 3943 PPSMC_MSG_MCLKDPM_SetEnabledMask, 3944 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); 3945 } 3946 } 3947 3948 return (ci_send_msg_to_smc(rdev, enable ? 3949 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ? 3950 0 : -EINVAL; 3951 } 3952 3953 static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable) 3954 { 3955 struct ci_power_info *pi = ci_get_pi(rdev); 3956 const struct radeon_clock_and_voltage_limits *max_limits; 3957 int i; 3958 3959 if (rdev->pm.dpm.ac_power) 3960 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3961 else 3962 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3963 3964 if (enable) { 3965 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0; 3966 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) { 3967 if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { 3968 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i; 3969 3970 if (!pi->caps_vce_dpm) 3971 break; 3972 } 3973 } 3974 3975 ci_send_msg_to_smc_with_parameter(rdev, 3976 PPSMC_MSG_VCEDPM_SetEnabledMask, 3977 pi->dpm_level_enable_mask.vce_dpm_enable_mask); 3978 } 3979 3980 return (ci_send_msg_to_smc(rdev, enable ? 3981 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ? 3982 0 : -EINVAL; 3983 } 3984 3985 #if 0 3986 static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable) 3987 { 3988 struct ci_power_info *pi = ci_get_pi(rdev); 3989 const struct radeon_clock_and_voltage_limits *max_limits; 3990 int i; 3991 3992 if (rdev->pm.dpm.ac_power) 3993 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3994 else 3995 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3996 3997 if (enable) { 3998 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0; 3999 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) { 4000 if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { 4001 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i; 4002 4003 if (!pi->caps_samu_dpm) 4004 break; 4005 } 4006 } 4007 4008 ci_send_msg_to_smc_with_parameter(rdev, 4009 PPSMC_MSG_SAMUDPM_SetEnabledMask, 4010 pi->dpm_level_enable_mask.samu_dpm_enable_mask); 4011 } 4012 return (ci_send_msg_to_smc(rdev, enable ? 4013 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ? 4014 0 : -EINVAL; 4015 } 4016 4017 static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable) 4018 { 4019 struct ci_power_info *pi = ci_get_pi(rdev); 4020 const struct radeon_clock_and_voltage_limits *max_limits; 4021 int i; 4022 4023 if (rdev->pm.dpm.ac_power) 4024 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 4025 else 4026 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 4027 4028 if (enable) { 4029 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0; 4030 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) { 4031 if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { 4032 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i; 4033 4034 if (!pi->caps_acp_dpm) 4035 break; 4036 } 4037 } 4038 4039 ci_send_msg_to_smc_with_parameter(rdev, 4040 PPSMC_MSG_ACPDPM_SetEnabledMask, 4041 pi->dpm_level_enable_mask.acp_dpm_enable_mask); 4042 } 4043 4044 return (ci_send_msg_to_smc(rdev, enable ? 4045 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ? 4046 0 : -EINVAL; 4047 } 4048 #endif 4049 4050 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate) 4051 { 4052 struct ci_power_info *pi = ci_get_pi(rdev); 4053 u32 tmp; 4054 4055 if (!gate) { 4056 if (pi->caps_uvd_dpm || 4057 (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0)) 4058 pi->smc_state_table.UvdBootLevel = 0; 4059 else 4060 pi->smc_state_table.UvdBootLevel = 4061 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; 4062 4063 tmp = RREG32_SMC(DPM_TABLE_475); 4064 tmp &= ~UvdBootLevel_MASK; 4065 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel); 4066 WREG32_SMC(DPM_TABLE_475, tmp); 4067 } 4068 4069 return ci_enable_uvd_dpm(rdev, !gate); 4070 } 4071 4072 static u8 ci_get_vce_boot_level(struct radeon_device *rdev) 4073 { 4074 u8 i; 4075 u32 min_evclk = 30000; /* ??? */ 4076 struct radeon_vce_clock_voltage_dependency_table *table = 4077 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 4078 4079 for (i = 0; i < table->count; i++) { 4080 if (table->entries[i].evclk >= min_evclk) 4081 return i; 4082 } 4083 4084 return table->count - 1; 4085 } 4086 4087 static int ci_update_vce_dpm(struct radeon_device *rdev, 4088 struct radeon_ps *radeon_new_state, 4089 struct radeon_ps *radeon_current_state) 4090 { 4091 struct ci_power_info *pi = ci_get_pi(rdev); 4092 int ret = 0; 4093 u32 tmp; 4094 4095 if (radeon_current_state->evclk != radeon_new_state->evclk) { 4096 if (radeon_new_state->evclk) { 4097 /* turn the clocks on when encoding */ 4098 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false); 4099 4100 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev); 4101 tmp = RREG32_SMC(DPM_TABLE_475); 4102 tmp &= ~VceBootLevel_MASK; 4103 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel); 4104 WREG32_SMC(DPM_TABLE_475, tmp); 4105 4106 ret = ci_enable_vce_dpm(rdev, true); 4107 } else { 4108 /* turn the clocks off when not encoding */ 4109 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true); 4110 4111 ret = ci_enable_vce_dpm(rdev, false); 4112 } 4113 } 4114 return ret; 4115 } 4116 4117 #if 0 4118 static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate) 4119 { 4120 return ci_enable_samu_dpm(rdev, gate); 4121 } 4122 4123 static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate) 4124 { 4125 struct ci_power_info *pi = ci_get_pi(rdev); 4126 u32 tmp; 4127 4128 if (!gate) { 4129 pi->smc_state_table.AcpBootLevel = 0; 4130 4131 tmp = RREG32_SMC(DPM_TABLE_475); 4132 tmp &= ~AcpBootLevel_MASK; 4133 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel); 4134 WREG32_SMC(DPM_TABLE_475, tmp); 4135 } 4136 4137 return ci_enable_acp_dpm(rdev, !gate); 4138 } 4139 #endif 4140 4141 static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev, 4142 struct radeon_ps *radeon_state) 4143 { 4144 struct ci_power_info *pi = ci_get_pi(rdev); 4145 int ret; 4146 4147 ret = ci_trim_dpm_states(rdev, radeon_state); 4148 if (ret) 4149 return ret; 4150 4151 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = 4152 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table); 4153 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = 4154 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table); 4155 pi->last_mclk_dpm_enable_mask = 4156 pi->dpm_level_enable_mask.mclk_dpm_enable_mask; 4157 if (pi->uvd_enabled) { 4158 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1) 4159 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; 4160 } 4161 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = 4162 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table); 4163 4164 return 0; 4165 } 4166 4167 static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev, 4168 u32 level_mask) 4169 { 4170 u32 level = 0; 4171 4172 while ((level_mask & (1 << level)) == 0) 4173 level++; 4174 4175 return level; 4176 } 4177 4178 4179 int ci_dpm_force_performance_level(struct radeon_device *rdev, 4180 enum radeon_dpm_forced_level level) 4181 { 4182 struct ci_power_info *pi = ci_get_pi(rdev); 4183 u32 tmp, levels, i; 4184 int ret; 4185 4186 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 4187 if ((!pi->pcie_dpm_key_disabled) && 4188 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { 4189 levels = 0; 4190 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask; 4191 while (tmp >>= 1) 4192 levels++; 4193 if (levels) { 4194 ret = ci_dpm_force_state_pcie(rdev, level); 4195 if (ret) 4196 return ret; 4197 for (i = 0; i < rdev->usec_timeout; i++) { 4198 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) & 4199 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT; 4200 if (tmp == levels) 4201 break; 4202 udelay(1); 4203 } 4204 } 4205 } 4206 if ((!pi->sclk_dpm_key_disabled) && 4207 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { 4208 levels = 0; 4209 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask; 4210 while (tmp >>= 1) 4211 levels++; 4212 if (levels) { 4213 ret = ci_dpm_force_state_sclk(rdev, levels); 4214 if (ret) 4215 return ret; 4216 for (i = 0; i < rdev->usec_timeout; i++) { 4217 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & 4218 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT; 4219 if (tmp == levels) 4220 break; 4221 udelay(1); 4222 } 4223 } 4224 } 4225 if ((!pi->mclk_dpm_key_disabled) && 4226 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { 4227 levels = 0; 4228 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask; 4229 while (tmp >>= 1) 4230 levels++; 4231 if (levels) { 4232 ret = ci_dpm_force_state_mclk(rdev, levels); 4233 if (ret) 4234 return ret; 4235 for (i = 0; i < rdev->usec_timeout; i++) { 4236 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & 4237 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT; 4238 if (tmp == levels) 4239 break; 4240 udelay(1); 4241 } 4242 } 4243 } 4244 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 4245 if ((!pi->sclk_dpm_key_disabled) && 4246 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { 4247 levels = ci_get_lowest_enabled_level(rdev, 4248 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); 4249 ret = ci_dpm_force_state_sclk(rdev, levels); 4250 if (ret) 4251 return ret; 4252 for (i = 0; i < rdev->usec_timeout; i++) { 4253 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & 4254 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT; 4255 if (tmp == levels) 4256 break; 4257 udelay(1); 4258 } 4259 } 4260 if ((!pi->mclk_dpm_key_disabled) && 4261 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { 4262 levels = ci_get_lowest_enabled_level(rdev, 4263 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); 4264 ret = ci_dpm_force_state_mclk(rdev, levels); 4265 if (ret) 4266 return ret; 4267 for (i = 0; i < rdev->usec_timeout; i++) { 4268 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & 4269 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT; 4270 if (tmp == levels) 4271 break; 4272 udelay(1); 4273 } 4274 } 4275 if ((!pi->pcie_dpm_key_disabled) && 4276 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { 4277 levels = ci_get_lowest_enabled_level(rdev, 4278 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); 4279 ret = ci_dpm_force_state_pcie(rdev, levels); 4280 if (ret) 4281 return ret; 4282 for (i = 0; i < rdev->usec_timeout; i++) { 4283 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) & 4284 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT; 4285 if (tmp == levels) 4286 break; 4287 udelay(1); 4288 } 4289 } 4290 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 4291 if (!pi->pcie_dpm_key_disabled) { 4292 PPSMC_Result smc_result; 4293 4294 smc_result = ci_send_msg_to_smc(rdev, 4295 PPSMC_MSG_PCIeDPM_UnForceLevel); 4296 if (smc_result != PPSMC_Result_OK) 4297 return -EINVAL; 4298 } 4299 ret = ci_upload_dpm_level_enable_mask(rdev); 4300 if (ret) 4301 return ret; 4302 } 4303 4304 rdev->pm.dpm.forced_level = level; 4305 4306 return 0; 4307 } 4308 4309 static int ci_set_mc_special_registers(struct radeon_device *rdev, 4310 struct ci_mc_reg_table *table) 4311 { 4312 struct ci_power_info *pi = ci_get_pi(rdev); 4313 u8 i, j, k; 4314 u32 temp_reg; 4315 4316 for (i = 0, j = table->last; i < table->last; i++) { 4317 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4318 return -EINVAL; 4319 switch(table->mc_reg_address[i].s1 << 2) { 4320 case MC_SEQ_MISC1: 4321 temp_reg = RREG32(MC_PMG_CMD_EMRS); 4322 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 4323 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 4324 for (k = 0; k < table->num_entries; k++) { 4325 table->mc_reg_table_entry[k].mc_data[j] = 4326 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 4327 } 4328 j++; 4329 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4330 return -EINVAL; 4331 4332 temp_reg = RREG32(MC_PMG_CMD_MRS); 4333 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 4334 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 4335 for (k = 0; k < table->num_entries; k++) { 4336 table->mc_reg_table_entry[k].mc_data[j] = 4337 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 4338 if (!pi->mem_gddr5) 4339 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 4340 } 4341 j++; 4342 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4343 return -EINVAL; 4344 4345 if (!pi->mem_gddr5) { 4346 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 4347 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 4348 for (k = 0; k < table->num_entries; k++) { 4349 table->mc_reg_table_entry[k].mc_data[j] = 4350 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 4351 } 4352 j++; 4353 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4354 return -EINVAL; 4355 } 4356 break; 4357 case MC_SEQ_RESERVE_M: 4358 temp_reg = RREG32(MC_PMG_CMD_MRS1); 4359 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 4360 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 4361 for (k = 0; k < table->num_entries; k++) { 4362 table->mc_reg_table_entry[k].mc_data[j] = 4363 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 4364 } 4365 j++; 4366 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4367 return -EINVAL; 4368 break; 4369 default: 4370 break; 4371 } 4372 4373 } 4374 4375 table->last = j; 4376 4377 return 0; 4378 } 4379 4380 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 4381 { 4382 bool result = true; 4383 4384 switch(in_reg) { 4385 case MC_SEQ_RAS_TIMING >> 2: 4386 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 4387 break; 4388 case MC_SEQ_DLL_STBY >> 2: 4389 *out_reg = MC_SEQ_DLL_STBY_LP >> 2; 4390 break; 4391 case MC_SEQ_G5PDX_CMD0 >> 2: 4392 *out_reg = MC_SEQ_G5PDX_CMD0_LP >> 2; 4393 break; 4394 case MC_SEQ_G5PDX_CMD1 >> 2: 4395 *out_reg = MC_SEQ_G5PDX_CMD1_LP >> 2; 4396 break; 4397 case MC_SEQ_G5PDX_CTRL >> 2: 4398 *out_reg = MC_SEQ_G5PDX_CTRL_LP >> 2; 4399 break; 4400 case MC_SEQ_CAS_TIMING >> 2: 4401 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 4402 break; 4403 case MC_SEQ_MISC_TIMING >> 2: 4404 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 4405 break; 4406 case MC_SEQ_MISC_TIMING2 >> 2: 4407 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 4408 break; 4409 case MC_SEQ_PMG_DVS_CMD >> 2: 4410 *out_reg = MC_SEQ_PMG_DVS_CMD_LP >> 2; 4411 break; 4412 case MC_SEQ_PMG_DVS_CTL >> 2: 4413 *out_reg = MC_SEQ_PMG_DVS_CTL_LP >> 2; 4414 break; 4415 case MC_SEQ_RD_CTL_D0 >> 2: 4416 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 4417 break; 4418 case MC_SEQ_RD_CTL_D1 >> 2: 4419 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 4420 break; 4421 case MC_SEQ_WR_CTL_D0 >> 2: 4422 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 4423 break; 4424 case MC_SEQ_WR_CTL_D1 >> 2: 4425 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 4426 break; 4427 case MC_PMG_CMD_EMRS >> 2: 4428 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 4429 break; 4430 case MC_PMG_CMD_MRS >> 2: 4431 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 4432 break; 4433 case MC_PMG_CMD_MRS1 >> 2: 4434 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 4435 break; 4436 case MC_SEQ_PMG_TIMING >> 2: 4437 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 4438 break; 4439 case MC_PMG_CMD_MRS2 >> 2: 4440 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 4441 break; 4442 case MC_SEQ_WR_CTL_2 >> 2: 4443 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 4444 break; 4445 default: 4446 result = false; 4447 break; 4448 } 4449 4450 return result; 4451 } 4452 4453 static void ci_set_valid_flag(struct ci_mc_reg_table *table) 4454 { 4455 u8 i, j; 4456 4457 for (i = 0; i < table->last; i++) { 4458 for (j = 1; j < table->num_entries; j++) { 4459 if (table->mc_reg_table_entry[j-1].mc_data[i] != 4460 table->mc_reg_table_entry[j].mc_data[i]) { 4461 table->valid_flag |= 1 << i; 4462 break; 4463 } 4464 } 4465 } 4466 } 4467 4468 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table) 4469 { 4470 u32 i; 4471 u16 address; 4472 4473 for (i = 0; i < table->last; i++) { 4474 table->mc_reg_address[i].s0 = 4475 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 4476 address : table->mc_reg_address[i].s1; 4477 } 4478 } 4479 4480 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table, 4481 struct ci_mc_reg_table *ci_table) 4482 { 4483 u8 i, j; 4484 4485 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4486 return -EINVAL; 4487 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 4488 return -EINVAL; 4489 4490 for (i = 0; i < table->last; i++) 4491 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 4492 4493 ci_table->last = table->last; 4494 4495 for (i = 0; i < table->num_entries; i++) { 4496 ci_table->mc_reg_table_entry[i].mclk_max = 4497 table->mc_reg_table_entry[i].mclk_max; 4498 for (j = 0; j < table->last; j++) 4499 ci_table->mc_reg_table_entry[i].mc_data[j] = 4500 table->mc_reg_table_entry[i].mc_data[j]; 4501 } 4502 ci_table->num_entries = table->num_entries; 4503 4504 return 0; 4505 } 4506 4507 static int ci_register_patching_mc_seq(struct radeon_device *rdev, 4508 struct ci_mc_reg_table *table) 4509 { 4510 u8 i, k; 4511 u32 tmp; 4512 bool patch; 4513 4514 tmp = RREG32(MC_SEQ_MISC0); 4515 patch = ((tmp & 0x0000f00) == 0x300) ? true : false; 4516 4517 if (patch && 4518 ((rdev->pdev->device == 0x67B0) || 4519 (rdev->pdev->device == 0x67B1))) { 4520 for (i = 0; i < table->last; i++) { 4521 if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4522 return -EINVAL; 4523 switch(table->mc_reg_address[i].s1 >> 2) { 4524 case MC_SEQ_MISC1: 4525 for (k = 0; k < table->num_entries; k++) { 4526 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || 4527 (table->mc_reg_table_entry[k].mclk_max == 137500)) 4528 table->mc_reg_table_entry[k].mc_data[i] = 4529 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) | 4530 0x00000007; 4531 } 4532 break; 4533 case MC_SEQ_WR_CTL_D0: 4534 for (k = 0; k < table->num_entries; k++) { 4535 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || 4536 (table->mc_reg_table_entry[k].mclk_max == 137500)) 4537 table->mc_reg_table_entry[k].mc_data[i] = 4538 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) | 4539 0x0000D0DD; 4540 } 4541 break; 4542 case MC_SEQ_WR_CTL_D1: 4543 for (k = 0; k < table->num_entries; k++) { 4544 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || 4545 (table->mc_reg_table_entry[k].mclk_max == 137500)) 4546 table->mc_reg_table_entry[k].mc_data[i] = 4547 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) | 4548 0x0000D0DD; 4549 } 4550 break; 4551 case MC_SEQ_WR_CTL_2: 4552 for (k = 0; k < table->num_entries; k++) { 4553 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || 4554 (table->mc_reg_table_entry[k].mclk_max == 137500)) 4555 table->mc_reg_table_entry[k].mc_data[i] = 0; 4556 } 4557 break; 4558 case MC_SEQ_CAS_TIMING: 4559 for (k = 0; k < table->num_entries; k++) { 4560 if (table->mc_reg_table_entry[k].mclk_max == 125000) 4561 table->mc_reg_table_entry[k].mc_data[i] = 4562 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) | 4563 0x000C0140; 4564 else if (table->mc_reg_table_entry[k].mclk_max == 137500) 4565 table->mc_reg_table_entry[k].mc_data[i] = 4566 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) | 4567 0x000C0150; 4568 } 4569 break; 4570 case MC_SEQ_MISC_TIMING: 4571 for (k = 0; k < table->num_entries; k++) { 4572 if (table->mc_reg_table_entry[k].mclk_max == 125000) 4573 table->mc_reg_table_entry[k].mc_data[i] = 4574 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) | 4575 0x00000030; 4576 else if (table->mc_reg_table_entry[k].mclk_max == 137500) 4577 table->mc_reg_table_entry[k].mc_data[i] = 4578 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) | 4579 0x00000035; 4580 } 4581 break; 4582 default: 4583 break; 4584 } 4585 } 4586 4587 WREG32(MC_SEQ_IO_DEBUG_INDEX, 3); 4588 tmp = RREG32(MC_SEQ_IO_DEBUG_DATA); 4589 tmp = (tmp & 0xFFF8FFFF) | (1 << 16); 4590 WREG32(MC_SEQ_IO_DEBUG_INDEX, 3); 4591 WREG32(MC_SEQ_IO_DEBUG_DATA, tmp); 4592 } 4593 4594 return 0; 4595 } 4596 4597 static int ci_initialize_mc_reg_table(struct radeon_device *rdev) 4598 { 4599 struct ci_power_info *pi = ci_get_pi(rdev); 4600 struct atom_mc_reg_table *table; 4601 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table; 4602 u8 module_index = rv770_get_memory_module_index(rdev); 4603 int ret; 4604 4605 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 4606 if (!table) 4607 return -ENOMEM; 4608 4609 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 4610 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 4611 WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY)); 4612 WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0)); 4613 WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1)); 4614 WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL)); 4615 WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD)); 4616 WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL)); 4617 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 4618 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 4619 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 4620 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 4621 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 4622 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 4623 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 4624 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 4625 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 4626 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 4627 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 4628 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 4629 4630 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 4631 if (ret) 4632 goto init_mc_done; 4633 4634 ret = ci_copy_vbios_mc_reg_table(table, ci_table); 4635 if (ret) 4636 goto init_mc_done; 4637 4638 ci_set_s0_mc_reg_index(ci_table); 4639 4640 ret = ci_register_patching_mc_seq(rdev, ci_table); 4641 if (ret) 4642 goto init_mc_done; 4643 4644 ret = ci_set_mc_special_registers(rdev, ci_table); 4645 if (ret) 4646 goto init_mc_done; 4647 4648 ci_set_valid_flag(ci_table); 4649 4650 init_mc_done: 4651 kfree(table); 4652 4653 return ret; 4654 } 4655 4656 static int ci_populate_mc_reg_addresses(struct radeon_device *rdev, 4657 SMU7_Discrete_MCRegisters *mc_reg_table) 4658 { 4659 struct ci_power_info *pi = ci_get_pi(rdev); 4660 u32 i, j; 4661 4662 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) { 4663 if (pi->mc_reg_table.valid_flag & (1 << j)) { 4664 if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4665 return -EINVAL; 4666 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0); 4667 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1); 4668 i++; 4669 } 4670 } 4671 4672 mc_reg_table->last = (u8)i; 4673 4674 return 0; 4675 } 4676 4677 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry, 4678 SMU7_Discrete_MCRegisterSet *data, 4679 u32 num_entries, u32 valid_flag) 4680 { 4681 u32 i, j; 4682 4683 for (i = 0, j = 0; j < num_entries; j++) { 4684 if (valid_flag & (1 << j)) { 4685 data->value[i] = cpu_to_be32(entry->mc_data[j]); 4686 i++; 4687 } 4688 } 4689 } 4690 4691 static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 4692 const u32 memory_clock, 4693 SMU7_Discrete_MCRegisterSet *mc_reg_table_data) 4694 { 4695 struct ci_power_info *pi = ci_get_pi(rdev); 4696 u32 i = 0; 4697 4698 for(i = 0; i < pi->mc_reg_table.num_entries; i++) { 4699 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 4700 break; 4701 } 4702 4703 if ((i == pi->mc_reg_table.num_entries) && (i > 0)) 4704 --i; 4705 4706 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i], 4707 mc_reg_table_data, pi->mc_reg_table.last, 4708 pi->mc_reg_table.valid_flag); 4709 } 4710 4711 static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 4712 SMU7_Discrete_MCRegisters *mc_reg_table) 4713 { 4714 struct ci_power_info *pi = ci_get_pi(rdev); 4715 u32 i; 4716 4717 for (i = 0; i < pi->dpm_table.mclk_table.count; i++) 4718 ci_convert_mc_reg_table_entry_to_smc(rdev, 4719 pi->dpm_table.mclk_table.dpm_levels[i].value, 4720 &mc_reg_table->data[i]); 4721 } 4722 4723 static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev) 4724 { 4725 struct ci_power_info *pi = ci_get_pi(rdev); 4726 int ret; 4727 4728 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); 4729 4730 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table); 4731 if (ret) 4732 return ret; 4733 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); 4734 4735 return ci_copy_bytes_to_smc(rdev, 4736 pi->mc_reg_table_start, 4737 (u8 *)&pi->smc_mc_reg_table, 4738 sizeof(SMU7_Discrete_MCRegisters), 4739 pi->sram_end); 4740 } 4741 4742 static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev) 4743 { 4744 struct ci_power_info *pi = ci_get_pi(rdev); 4745 4746 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) 4747 return 0; 4748 4749 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); 4750 4751 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); 4752 4753 return ci_copy_bytes_to_smc(rdev, 4754 pi->mc_reg_table_start + 4755 offsetof(SMU7_Discrete_MCRegisters, data[0]), 4756 (u8 *)&pi->smc_mc_reg_table.data[0], 4757 sizeof(SMU7_Discrete_MCRegisterSet) * 4758 pi->dpm_table.mclk_table.count, 4759 pi->sram_end); 4760 } 4761 4762 static void ci_enable_voltage_control(struct radeon_device *rdev) 4763 { 4764 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); 4765 4766 tmp |= VOLT_PWRMGT_EN; 4767 WREG32_SMC(GENERAL_PWRMGT, tmp); 4768 } 4769 4770 static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev, 4771 struct radeon_ps *radeon_state) 4772 { 4773 struct ci_ps *state = ci_get_ps(radeon_state); 4774 int i; 4775 u16 pcie_speed, max_speed = 0; 4776 4777 for (i = 0; i < state->performance_level_count; i++) { 4778 pcie_speed = state->performance_levels[i].pcie_gen; 4779 if (max_speed < pcie_speed) 4780 max_speed = pcie_speed; 4781 } 4782 4783 return max_speed; 4784 } 4785 4786 static u16 ci_get_current_pcie_speed(struct radeon_device *rdev) 4787 { 4788 u32 speed_cntl = 0; 4789 4790 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 4791 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 4792 4793 return (u16)speed_cntl; 4794 } 4795 4796 static int ci_get_current_pcie_lane_number(struct radeon_device *rdev) 4797 { 4798 u32 link_width = 0; 4799 4800 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK; 4801 link_width >>= LC_LINK_WIDTH_RD_SHIFT; 4802 4803 switch (link_width) { 4804 case RADEON_PCIE_LC_LINK_WIDTH_X1: 4805 return 1; 4806 case RADEON_PCIE_LC_LINK_WIDTH_X2: 4807 return 2; 4808 case RADEON_PCIE_LC_LINK_WIDTH_X4: 4809 return 4; 4810 case RADEON_PCIE_LC_LINK_WIDTH_X8: 4811 return 8; 4812 case RADEON_PCIE_LC_LINK_WIDTH_X12: 4813 /* not actually supported */ 4814 return 12; 4815 case RADEON_PCIE_LC_LINK_WIDTH_X0: 4816 case RADEON_PCIE_LC_LINK_WIDTH_X16: 4817 default: 4818 return 16; 4819 } 4820 } 4821 4822 static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev, 4823 struct radeon_ps *radeon_new_state, 4824 struct radeon_ps *radeon_current_state) 4825 { 4826 struct ci_power_info *pi = ci_get_pi(rdev); 4827 enum radeon_pcie_gen target_link_speed = 4828 ci_get_maximum_link_speed(rdev, radeon_new_state); 4829 enum radeon_pcie_gen current_link_speed; 4830 4831 if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 4832 current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state); 4833 else 4834 current_link_speed = pi->force_pcie_gen; 4835 4836 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 4837 pi->pspp_notify_required = false; 4838 if (target_link_speed > current_link_speed) { 4839 switch (target_link_speed) { 4840 #ifdef CONFIG_ACPI 4841 case RADEON_PCIE_GEN3: 4842 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 4843 break; 4844 pi->force_pcie_gen = RADEON_PCIE_GEN2; 4845 if (current_link_speed == RADEON_PCIE_GEN2) 4846 break; 4847 fallthrough; 4848 case RADEON_PCIE_GEN2: 4849 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 4850 break; 4851 #endif 4852 /* fall through */ 4853 default: 4854 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev); 4855 break; 4856 } 4857 } else { 4858 if (target_link_speed < current_link_speed) 4859 pi->pspp_notify_required = true; 4860 } 4861 } 4862 4863 static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 4864 struct radeon_ps *radeon_new_state, 4865 struct radeon_ps *radeon_current_state) 4866 { 4867 struct ci_power_info *pi = ci_get_pi(rdev); 4868 enum radeon_pcie_gen target_link_speed = 4869 ci_get_maximum_link_speed(rdev, radeon_new_state); 4870 u8 request; 4871 4872 if (pi->pspp_notify_required) { 4873 if (target_link_speed == RADEON_PCIE_GEN3) 4874 request = PCIE_PERF_REQ_PECI_GEN3; 4875 else if (target_link_speed == RADEON_PCIE_GEN2) 4876 request = PCIE_PERF_REQ_PECI_GEN2; 4877 else 4878 request = PCIE_PERF_REQ_PECI_GEN1; 4879 4880 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 4881 (ci_get_current_pcie_speed(rdev) > 0)) 4882 return; 4883 4884 #ifdef CONFIG_ACPI 4885 radeon_acpi_pcie_performance_request(rdev, request, false); 4886 #endif 4887 } 4888 } 4889 4890 static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev) 4891 { 4892 struct ci_power_info *pi = ci_get_pi(rdev); 4893 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table = 4894 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 4895 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddc_table = 4896 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; 4897 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddci_table = 4898 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; 4899 4900 if (allowed_sclk_vddc_table == NULL) 4901 return -EINVAL; 4902 if (allowed_sclk_vddc_table->count < 1) 4903 return -EINVAL; 4904 if (allowed_mclk_vddc_table == NULL) 4905 return -EINVAL; 4906 if (allowed_mclk_vddc_table->count < 1) 4907 return -EINVAL; 4908 if (allowed_mclk_vddci_table == NULL) 4909 return -EINVAL; 4910 if (allowed_mclk_vddci_table->count < 1) 4911 return -EINVAL; 4912 4913 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v; 4914 pi->max_vddc_in_pp_table = 4915 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; 4916 4917 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v; 4918 pi->max_vddci_in_pp_table = 4919 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v; 4920 4921 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = 4922 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; 4923 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = 4924 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; 4925 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = 4926 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; 4927 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = 4928 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v; 4929 4930 return 0; 4931 } 4932 4933 static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc) 4934 { 4935 struct ci_power_info *pi = ci_get_pi(rdev); 4936 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage; 4937 u32 leakage_index; 4938 4939 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) { 4940 if (leakage_table->leakage_id[leakage_index] == *vddc) { 4941 *vddc = leakage_table->actual_voltage[leakage_index]; 4942 break; 4943 } 4944 } 4945 } 4946 4947 static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci) 4948 { 4949 struct ci_power_info *pi = ci_get_pi(rdev); 4950 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage; 4951 u32 leakage_index; 4952 4953 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) { 4954 if (leakage_table->leakage_id[leakage_index] == *vddci) { 4955 *vddci = leakage_table->actual_voltage[leakage_index]; 4956 break; 4957 } 4958 } 4959 } 4960 4961 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev, 4962 struct radeon_clock_voltage_dependency_table *table) 4963 { 4964 u32 i; 4965 4966 if (table) { 4967 for (i = 0; i < table->count; i++) 4968 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); 4969 } 4970 } 4971 4972 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev, 4973 struct radeon_clock_voltage_dependency_table *table) 4974 { 4975 u32 i; 4976 4977 if (table) { 4978 for (i = 0; i < table->count; i++) 4979 ci_patch_with_vddci_leakage(rdev, &table->entries[i].v); 4980 } 4981 } 4982 4983 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev, 4984 struct radeon_vce_clock_voltage_dependency_table *table) 4985 { 4986 u32 i; 4987 4988 if (table) { 4989 for (i = 0; i < table->count; i++) 4990 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); 4991 } 4992 } 4993 4994 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev, 4995 struct radeon_uvd_clock_voltage_dependency_table *table) 4996 { 4997 u32 i; 4998 4999 if (table) { 5000 for (i = 0; i < table->count; i++) 5001 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); 5002 } 5003 } 5004 5005 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev, 5006 struct radeon_phase_shedding_limits_table *table) 5007 { 5008 u32 i; 5009 5010 if (table) { 5011 for (i = 0; i < table->count; i++) 5012 ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage); 5013 } 5014 } 5015 5016 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev, 5017 struct radeon_clock_and_voltage_limits *table) 5018 { 5019 if (table) { 5020 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc); 5021 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci); 5022 } 5023 } 5024 5025 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev, 5026 struct radeon_cac_leakage_table *table) 5027 { 5028 u32 i; 5029 5030 if (table) { 5031 for (i = 0; i < table->count; i++) 5032 ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc); 5033 } 5034 } 5035 5036 static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev) 5037 { 5038 5039 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 5040 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5041 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 5042 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5043 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 5044 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk); 5045 ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev, 5046 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5047 ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev, 5048 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table); 5049 ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev, 5050 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table); 5051 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 5052 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table); 5053 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 5054 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table); 5055 ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev, 5056 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table); 5057 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev, 5058 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac); 5059 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev, 5060 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc); 5061 ci_patch_cac_leakage_table_with_vddc_leakage(rdev, 5062 &rdev->pm.dpm.dyn_state.cac_leakage_table); 5063 5064 } 5065 5066 static void ci_get_memory_type(struct radeon_device *rdev) 5067 { 5068 struct ci_power_info *pi = ci_get_pi(rdev); 5069 u32 tmp; 5070 5071 tmp = RREG32(MC_SEQ_MISC0); 5072 5073 if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) == 5074 MC_SEQ_MISC0_GDDR5_VALUE) 5075 pi->mem_gddr5 = true; 5076 else 5077 pi->mem_gddr5 = false; 5078 5079 } 5080 5081 static void ci_update_current_ps(struct radeon_device *rdev, 5082 struct radeon_ps *rps) 5083 { 5084 struct ci_ps *new_ps = ci_get_ps(rps); 5085 struct ci_power_info *pi = ci_get_pi(rdev); 5086 5087 pi->current_rps = *rps; 5088 pi->current_ps = *new_ps; 5089 pi->current_rps.ps_priv = &pi->current_ps; 5090 } 5091 5092 static void ci_update_requested_ps(struct radeon_device *rdev, 5093 struct radeon_ps *rps) 5094 { 5095 struct ci_ps *new_ps = ci_get_ps(rps); 5096 struct ci_power_info *pi = ci_get_pi(rdev); 5097 5098 pi->requested_rps = *rps; 5099 pi->requested_ps = *new_ps; 5100 pi->requested_rps.ps_priv = &pi->requested_ps; 5101 } 5102 5103 int ci_dpm_pre_set_power_state(struct radeon_device *rdev) 5104 { 5105 struct ci_power_info *pi = ci_get_pi(rdev); 5106 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 5107 struct radeon_ps *new_ps = &requested_ps; 5108 5109 ci_update_requested_ps(rdev, new_ps); 5110 5111 ci_apply_state_adjust_rules(rdev, &pi->requested_rps); 5112 5113 return 0; 5114 } 5115 5116 void ci_dpm_post_set_power_state(struct radeon_device *rdev) 5117 { 5118 struct ci_power_info *pi = ci_get_pi(rdev); 5119 struct radeon_ps *new_ps = &pi->requested_rps; 5120 5121 ci_update_current_ps(rdev, new_ps); 5122 } 5123 5124 5125 void ci_dpm_setup_asic(struct radeon_device *rdev) 5126 { 5127 int r; 5128 5129 r = ci_mc_load_microcode(rdev); 5130 if (r) 5131 DRM_ERROR("Failed to load MC firmware!\n"); 5132 ci_read_clock_registers(rdev); 5133 ci_get_memory_type(rdev); 5134 ci_enable_acpi_power_management(rdev); 5135 ci_init_sclk_t(rdev); 5136 } 5137 5138 int ci_dpm_enable(struct radeon_device *rdev) 5139 { 5140 struct ci_power_info *pi = ci_get_pi(rdev); 5141 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5142 int ret; 5143 5144 if (ci_is_smc_running(rdev)) 5145 return -EINVAL; 5146 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) { 5147 ci_enable_voltage_control(rdev); 5148 ret = ci_construct_voltage_tables(rdev); 5149 if (ret) { 5150 DRM_ERROR("ci_construct_voltage_tables failed\n"); 5151 return ret; 5152 } 5153 } 5154 if (pi->caps_dynamic_ac_timing) { 5155 ret = ci_initialize_mc_reg_table(rdev); 5156 if (ret) 5157 pi->caps_dynamic_ac_timing = false; 5158 } 5159 if (pi->dynamic_ss) 5160 ci_enable_spread_spectrum(rdev, true); 5161 if (pi->thermal_protection) 5162 ci_enable_thermal_protection(rdev, true); 5163 ci_program_sstp(rdev); 5164 ci_enable_display_gap(rdev); 5165 ci_program_vc(rdev); 5166 ret = ci_upload_firmware(rdev); 5167 if (ret) { 5168 DRM_ERROR("ci_upload_firmware failed\n"); 5169 return ret; 5170 } 5171 ret = ci_process_firmware_header(rdev); 5172 if (ret) { 5173 DRM_ERROR("ci_process_firmware_header failed\n"); 5174 return ret; 5175 } 5176 ret = ci_initial_switch_from_arb_f0_to_f1(rdev); 5177 if (ret) { 5178 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n"); 5179 return ret; 5180 } 5181 ret = ci_init_smc_table(rdev); 5182 if (ret) { 5183 DRM_ERROR("ci_init_smc_table failed\n"); 5184 return ret; 5185 } 5186 ret = ci_init_arb_table_index(rdev); 5187 if (ret) { 5188 DRM_ERROR("ci_init_arb_table_index failed\n"); 5189 return ret; 5190 } 5191 if (pi->caps_dynamic_ac_timing) { 5192 ret = ci_populate_initial_mc_reg_table(rdev); 5193 if (ret) { 5194 DRM_ERROR("ci_populate_initial_mc_reg_table failed\n"); 5195 return ret; 5196 } 5197 } 5198 ret = ci_populate_pm_base(rdev); 5199 if (ret) { 5200 DRM_ERROR("ci_populate_pm_base failed\n"); 5201 return ret; 5202 } 5203 ci_dpm_start_smc(rdev); 5204 ci_enable_vr_hot_gpio_interrupt(rdev); 5205 ret = ci_notify_smc_display_change(rdev, false); 5206 if (ret) { 5207 DRM_ERROR("ci_notify_smc_display_change failed\n"); 5208 return ret; 5209 } 5210 ci_enable_sclk_control(rdev, true); 5211 ret = ci_enable_ulv(rdev, true); 5212 if (ret) { 5213 DRM_ERROR("ci_enable_ulv failed\n"); 5214 return ret; 5215 } 5216 ret = ci_enable_ds_master_switch(rdev, true); 5217 if (ret) { 5218 DRM_ERROR("ci_enable_ds_master_switch failed\n"); 5219 return ret; 5220 } 5221 ret = ci_start_dpm(rdev); 5222 if (ret) { 5223 DRM_ERROR("ci_start_dpm failed\n"); 5224 return ret; 5225 } 5226 ret = ci_enable_didt(rdev, true); 5227 if (ret) { 5228 DRM_ERROR("ci_enable_didt failed\n"); 5229 return ret; 5230 } 5231 ret = ci_enable_smc_cac(rdev, true); 5232 if (ret) { 5233 DRM_ERROR("ci_enable_smc_cac failed\n"); 5234 return ret; 5235 } 5236 ret = ci_enable_power_containment(rdev, true); 5237 if (ret) { 5238 DRM_ERROR("ci_enable_power_containment failed\n"); 5239 return ret; 5240 } 5241 5242 ret = ci_power_control_set_level(rdev); 5243 if (ret) { 5244 DRM_ERROR("ci_power_control_set_level failed\n"); 5245 return ret; 5246 } 5247 5248 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 5249 5250 ret = ci_enable_thermal_based_sclk_dpm(rdev, true); 5251 if (ret) { 5252 DRM_ERROR("ci_enable_thermal_based_sclk_dpm failed\n"); 5253 return ret; 5254 } 5255 5256 ci_thermal_start_thermal_controller(rdev); 5257 5258 ci_update_current_ps(rdev, boot_ps); 5259 5260 return 0; 5261 } 5262 5263 static int ci_set_temperature_range(struct radeon_device *rdev) 5264 { 5265 int ret; 5266 5267 ret = ci_thermal_enable_alert(rdev, false); 5268 if (ret) 5269 return ret; 5270 ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 5271 if (ret) 5272 return ret; 5273 ret = ci_thermal_enable_alert(rdev, true); 5274 if (ret) 5275 return ret; 5276 5277 return ret; 5278 } 5279 5280 int ci_dpm_late_enable(struct radeon_device *rdev) 5281 { 5282 int ret; 5283 5284 ret = ci_set_temperature_range(rdev); 5285 if (ret) 5286 return ret; 5287 5288 ci_dpm_powergate_uvd(rdev, true); 5289 5290 return 0; 5291 } 5292 5293 void ci_dpm_disable(struct radeon_device *rdev) 5294 { 5295 struct ci_power_info *pi = ci_get_pi(rdev); 5296 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5297 5298 ci_dpm_powergate_uvd(rdev, false); 5299 5300 if (!ci_is_smc_running(rdev)) 5301 return; 5302 5303 ci_thermal_stop_thermal_controller(rdev); 5304 5305 if (pi->thermal_protection) 5306 ci_enable_thermal_protection(rdev, false); 5307 ci_enable_power_containment(rdev, false); 5308 ci_enable_smc_cac(rdev, false); 5309 ci_enable_didt(rdev, false); 5310 ci_enable_spread_spectrum(rdev, false); 5311 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 5312 ci_stop_dpm(rdev); 5313 ci_enable_ds_master_switch(rdev, false); 5314 ci_enable_ulv(rdev, false); 5315 ci_clear_vc(rdev); 5316 ci_reset_to_default(rdev); 5317 ci_dpm_stop_smc(rdev); 5318 ci_force_switch_to_arb_f0(rdev); 5319 ci_enable_thermal_based_sclk_dpm(rdev, false); 5320 5321 ci_update_current_ps(rdev, boot_ps); 5322 } 5323 5324 int ci_dpm_set_power_state(struct radeon_device *rdev) 5325 { 5326 struct ci_power_info *pi = ci_get_pi(rdev); 5327 struct radeon_ps *new_ps = &pi->requested_rps; 5328 struct radeon_ps *old_ps = &pi->current_rps; 5329 int ret; 5330 5331 ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps); 5332 if (pi->pcie_performance_request) 5333 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 5334 ret = ci_freeze_sclk_mclk_dpm(rdev); 5335 if (ret) { 5336 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n"); 5337 return ret; 5338 } 5339 ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps); 5340 if (ret) { 5341 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n"); 5342 return ret; 5343 } 5344 ret = ci_generate_dpm_level_enable_mask(rdev, new_ps); 5345 if (ret) { 5346 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n"); 5347 return ret; 5348 } 5349 5350 ret = ci_update_vce_dpm(rdev, new_ps, old_ps); 5351 if (ret) { 5352 DRM_ERROR("ci_update_vce_dpm failed\n"); 5353 return ret; 5354 } 5355 5356 ret = ci_update_sclk_t(rdev); 5357 if (ret) { 5358 DRM_ERROR("ci_update_sclk_t failed\n"); 5359 return ret; 5360 } 5361 if (pi->caps_dynamic_ac_timing) { 5362 ret = ci_update_and_upload_mc_reg_table(rdev); 5363 if (ret) { 5364 DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n"); 5365 return ret; 5366 } 5367 } 5368 ret = ci_program_memory_timing_parameters(rdev); 5369 if (ret) { 5370 DRM_ERROR("ci_program_memory_timing_parameters failed\n"); 5371 return ret; 5372 } 5373 ret = ci_unfreeze_sclk_mclk_dpm(rdev); 5374 if (ret) { 5375 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n"); 5376 return ret; 5377 } 5378 ret = ci_upload_dpm_level_enable_mask(rdev); 5379 if (ret) { 5380 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n"); 5381 return ret; 5382 } 5383 if (pi->pcie_performance_request) 5384 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 5385 5386 return 0; 5387 } 5388 5389 #if 0 5390 void ci_dpm_reset_asic(struct radeon_device *rdev) 5391 { 5392 ci_set_boot_state(rdev); 5393 } 5394 #endif 5395 5396 void ci_dpm_display_configuration_changed(struct radeon_device *rdev) 5397 { 5398 ci_program_display_gap(rdev); 5399 } 5400 5401 union power_info { 5402 struct _ATOM_POWERPLAY_INFO info; 5403 struct _ATOM_POWERPLAY_INFO_V2 info_2; 5404 struct _ATOM_POWERPLAY_INFO_V3 info_3; 5405 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 5406 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 5407 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 5408 }; 5409 5410 union pplib_clock_info { 5411 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 5412 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 5413 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 5414 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 5415 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 5416 struct _ATOM_PPLIB_CI_CLOCK_INFO ci; 5417 }; 5418 5419 union pplib_power_state { 5420 struct _ATOM_PPLIB_STATE v1; 5421 struct _ATOM_PPLIB_STATE_V2 v2; 5422 }; 5423 5424 static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev, 5425 struct radeon_ps *rps, 5426 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 5427 u8 table_rev) 5428 { 5429 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 5430 rps->class = le16_to_cpu(non_clock_info->usClassification); 5431 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 5432 5433 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 5434 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 5435 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 5436 } else { 5437 rps->vclk = 0; 5438 rps->dclk = 0; 5439 } 5440 5441 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 5442 rdev->pm.dpm.boot_ps = rps; 5443 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 5444 rdev->pm.dpm.uvd_ps = rps; 5445 } 5446 5447 static void ci_parse_pplib_clock_info(struct radeon_device *rdev, 5448 struct radeon_ps *rps, int index, 5449 union pplib_clock_info *clock_info) 5450 { 5451 struct ci_power_info *pi = ci_get_pi(rdev); 5452 struct ci_ps *ps = ci_get_ps(rps); 5453 struct ci_pl *pl = &ps->performance_levels[index]; 5454 5455 ps->performance_level_count = index + 1; 5456 5457 pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); 5458 pl->sclk |= clock_info->ci.ucEngineClockHigh << 16; 5459 pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); 5460 pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16; 5461 5462 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 5463 pi->sys_pcie_mask, 5464 pi->vbios_boot_state.pcie_gen_bootup_value, 5465 clock_info->ci.ucPCIEGen); 5466 pl->pcie_lane = r600_get_pcie_lane_support(rdev, 5467 pi->vbios_boot_state.pcie_lane_bootup_value, 5468 le16_to_cpu(clock_info->ci.usPCIELane)); 5469 5470 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 5471 pi->acpi_pcie_gen = pl->pcie_gen; 5472 } 5473 5474 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) { 5475 pi->ulv.supported = true; 5476 pi->ulv.pl = *pl; 5477 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT; 5478 } 5479 5480 /* patch up boot state */ 5481 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 5482 pl->mclk = pi->vbios_boot_state.mclk_bootup_value; 5483 pl->sclk = pi->vbios_boot_state.sclk_bootup_value; 5484 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value; 5485 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value; 5486 } 5487 5488 switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { 5489 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: 5490 pi->use_pcie_powersaving_levels = true; 5491 if (pi->pcie_gen_powersaving.max < pl->pcie_gen) 5492 pi->pcie_gen_powersaving.max = pl->pcie_gen; 5493 if (pi->pcie_gen_powersaving.min > pl->pcie_gen) 5494 pi->pcie_gen_powersaving.min = pl->pcie_gen; 5495 if (pi->pcie_lane_powersaving.max < pl->pcie_lane) 5496 pi->pcie_lane_powersaving.max = pl->pcie_lane; 5497 if (pi->pcie_lane_powersaving.min > pl->pcie_lane) 5498 pi->pcie_lane_powersaving.min = pl->pcie_lane; 5499 break; 5500 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: 5501 pi->use_pcie_performance_levels = true; 5502 if (pi->pcie_gen_performance.max < pl->pcie_gen) 5503 pi->pcie_gen_performance.max = pl->pcie_gen; 5504 if (pi->pcie_gen_performance.min > pl->pcie_gen) 5505 pi->pcie_gen_performance.min = pl->pcie_gen; 5506 if (pi->pcie_lane_performance.max < pl->pcie_lane) 5507 pi->pcie_lane_performance.max = pl->pcie_lane; 5508 if (pi->pcie_lane_performance.min > pl->pcie_lane) 5509 pi->pcie_lane_performance.min = pl->pcie_lane; 5510 break; 5511 default: 5512 break; 5513 } 5514 } 5515 5516 static int ci_parse_power_table(struct radeon_device *rdev) 5517 { 5518 struct radeon_mode_info *mode_info = &rdev->mode_info; 5519 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 5520 union pplib_power_state *power_state; 5521 int i, j, k, non_clock_array_index, clock_array_index; 5522 union pplib_clock_info *clock_info; 5523 struct _StateArray *state_array; 5524 struct _ClockInfoArray *clock_info_array; 5525 struct _NonClockInfoArray *non_clock_info_array; 5526 union power_info *power_info; 5527 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 5528 u16 data_offset; 5529 u8 frev, crev; 5530 u8 *power_state_offset; 5531 struct ci_ps *ps; 5532 5533 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 5534 &frev, &crev, &data_offset)) 5535 return -EINVAL; 5536 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 5537 5538 state_array = (struct _StateArray *) 5539 (mode_info->atom_context->bios + data_offset + 5540 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 5541 clock_info_array = (struct _ClockInfoArray *) 5542 (mode_info->atom_context->bios + data_offset + 5543 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 5544 non_clock_info_array = (struct _NonClockInfoArray *) 5545 (mode_info->atom_context->bios + data_offset + 5546 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 5547 5548 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, 5549 sizeof(struct radeon_ps), 5550 GFP_KERNEL); 5551 if (!rdev->pm.dpm.ps) 5552 return -ENOMEM; 5553 power_state_offset = (u8 *)state_array->states; 5554 rdev->pm.dpm.num_ps = 0; 5555 for (i = 0; i < state_array->ucNumEntries; i++) { 5556 u8 *idx; 5557 power_state = (union pplib_power_state *)power_state_offset; 5558 non_clock_array_index = power_state->v2.nonClockInfoIndex; 5559 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 5560 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 5561 if (!rdev->pm.power_state[i].clock_info) 5562 return -EINVAL; 5563 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL); 5564 if (ps == NULL) 5565 return -ENOMEM; 5566 rdev->pm.dpm.ps[i].ps_priv = ps; 5567 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 5568 non_clock_info, 5569 non_clock_info_array->ucEntrySize); 5570 k = 0; 5571 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 5572 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 5573 clock_array_index = idx[j]; 5574 if (clock_array_index >= clock_info_array->ucNumEntries) 5575 continue; 5576 if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS) 5577 break; 5578 clock_info = (union pplib_clock_info *) 5579 ((u8 *)&clock_info_array->clockInfo[0] + 5580 (clock_array_index * clock_info_array->ucEntrySize)); 5581 ci_parse_pplib_clock_info(rdev, 5582 &rdev->pm.dpm.ps[i], k, 5583 clock_info); 5584 k++; 5585 } 5586 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 5587 rdev->pm.dpm.num_ps = i + 1; 5588 } 5589 5590 /* fill in the vce power states */ 5591 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { 5592 u32 sclk, mclk; 5593 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; 5594 clock_info = (union pplib_clock_info *) 5595 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 5596 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); 5597 sclk |= clock_info->ci.ucEngineClockHigh << 16; 5598 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); 5599 mclk |= clock_info->ci.ucMemoryClockHigh << 16; 5600 rdev->pm.dpm.vce_states[i].sclk = sclk; 5601 rdev->pm.dpm.vce_states[i].mclk = mclk; 5602 } 5603 5604 return 0; 5605 } 5606 5607 static int ci_get_vbios_boot_values(struct radeon_device *rdev, 5608 struct ci_vbios_boot_state *boot_state) 5609 { 5610 struct radeon_mode_info *mode_info = &rdev->mode_info; 5611 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 5612 ATOM_FIRMWARE_INFO_V2_2 *firmware_info; 5613 u8 frev, crev; 5614 u16 data_offset; 5615 5616 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 5617 &frev, &crev, &data_offset)) { 5618 firmware_info = 5619 (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios + 5620 data_offset); 5621 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage); 5622 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage); 5623 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage); 5624 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev); 5625 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev); 5626 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock); 5627 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock); 5628 5629 return 0; 5630 } 5631 return -EINVAL; 5632 } 5633 5634 void ci_dpm_fini(struct radeon_device *rdev) 5635 { 5636 int i; 5637 5638 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 5639 kfree(rdev->pm.dpm.ps[i].ps_priv); 5640 } 5641 kfree(rdev->pm.dpm.ps); 5642 kfree(rdev->pm.dpm.priv); 5643 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 5644 r600_free_extended_power_table(rdev); 5645 } 5646 5647 int ci_dpm_init(struct radeon_device *rdev) 5648 { 5649 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 5650 SMU7_Discrete_DpmTable *dpm_table; 5651 struct radeon_gpio_rec gpio; 5652 u16 data_offset, size; 5653 u8 frev, crev; 5654 struct ci_power_info *pi; 5655 enum pci_bus_speed speed_cap = PCI_SPEED_UNKNOWN; 5656 struct pci_dev *root = rdev->pdev->bus->self; 5657 int ret; 5658 5659 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL); 5660 if (pi == NULL) 5661 return -ENOMEM; 5662 rdev->pm.dpm.priv = pi; 5663 5664 if (!pci_is_root_bus(rdev->pdev->bus)) 5665 speed_cap = pcie_get_speed_cap(root); 5666 if (speed_cap == PCI_SPEED_UNKNOWN) { 5667 pi->sys_pcie_mask = 0; 5668 } else { 5669 if (speed_cap == PCIE_SPEED_8_0GT) 5670 pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | 5671 RADEON_PCIE_SPEED_50 | 5672 RADEON_PCIE_SPEED_80; 5673 else if (speed_cap == PCIE_SPEED_5_0GT) 5674 pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | 5675 RADEON_PCIE_SPEED_50; 5676 else 5677 pi->sys_pcie_mask = RADEON_PCIE_SPEED_25; 5678 } 5679 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5680 5681 pi->pcie_gen_performance.max = RADEON_PCIE_GEN1; 5682 pi->pcie_gen_performance.min = RADEON_PCIE_GEN3; 5683 pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1; 5684 pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3; 5685 5686 pi->pcie_lane_performance.max = 0; 5687 pi->pcie_lane_performance.min = 16; 5688 pi->pcie_lane_powersaving.max = 0; 5689 pi->pcie_lane_powersaving.min = 16; 5690 5691 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state); 5692 if (ret) { 5693 ci_dpm_fini(rdev); 5694 return ret; 5695 } 5696 5697 ret = r600_get_platform_caps(rdev); 5698 if (ret) { 5699 ci_dpm_fini(rdev); 5700 return ret; 5701 } 5702 5703 ret = r600_parse_extended_power_table(rdev); 5704 if (ret) { 5705 ci_dpm_fini(rdev); 5706 return ret; 5707 } 5708 5709 ret = ci_parse_power_table(rdev); 5710 if (ret) { 5711 ci_dpm_fini(rdev); 5712 return ret; 5713 } 5714 5715 pi->dll_default_on = false; 5716 pi->sram_end = SMC_RAM_END; 5717 5718 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT; 5719 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT; 5720 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT; 5721 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT; 5722 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT; 5723 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT; 5724 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT; 5725 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT; 5726 5727 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT; 5728 5729 pi->sclk_dpm_key_disabled = 0; 5730 pi->mclk_dpm_key_disabled = 0; 5731 pi->pcie_dpm_key_disabled = 0; 5732 pi->thermal_sclk_dpm_enabled = 0; 5733 5734 /* mclk dpm is unstable on some R7 260X cards with the old mc ucode */ 5735 if ((rdev->pdev->device == 0x6658) && 5736 (rdev->mc_fw->size == (BONAIRE_MC_UCODE_SIZE * 4))) { 5737 pi->mclk_dpm_key_disabled = 1; 5738 } 5739 5740 pi->caps_sclk_ds = true; 5741 5742 pi->mclk_strobe_mode_threshold = 40000; 5743 pi->mclk_stutter_mode_threshold = 40000; 5744 pi->mclk_edc_enable_threshold = 40000; 5745 pi->mclk_edc_wr_enable_threshold = 40000; 5746 5747 ci_initialize_powertune_defaults(rdev); 5748 5749 pi->caps_fps = false; 5750 5751 pi->caps_sclk_throttle_low_notification = false; 5752 5753 pi->caps_uvd_dpm = true; 5754 pi->caps_vce_dpm = true; 5755 5756 ci_get_leakage_voltages(rdev); 5757 ci_patch_dependency_tables_with_leakage(rdev); 5758 ci_set_private_data_variables_based_on_pptable(rdev); 5759 5760 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 5761 kcalloc(4, 5762 sizeof(struct radeon_clock_voltage_dependency_entry), 5763 GFP_KERNEL); 5764 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 5765 ci_dpm_fini(rdev); 5766 return -ENOMEM; 5767 } 5768 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 5769 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 5770 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 5771 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 5772 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 5773 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 5774 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 5775 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 5776 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 5777 5778 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 5779 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 5780 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 5781 5782 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 5783 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 5784 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 5785 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 5786 5787 if (rdev->family == CHIP_HAWAII) { 5788 pi->thermal_temp_setting.temperature_low = 94500; 5789 pi->thermal_temp_setting.temperature_high = 95000; 5790 pi->thermal_temp_setting.temperature_shutdown = 104000; 5791 } else { 5792 pi->thermal_temp_setting.temperature_low = 99500; 5793 pi->thermal_temp_setting.temperature_high = 100000; 5794 pi->thermal_temp_setting.temperature_shutdown = 104000; 5795 } 5796 5797 pi->uvd_enabled = false; 5798 5799 dpm_table = &pi->smc_state_table; 5800 5801 gpio = radeon_atombios_lookup_gpio(rdev, VDDC_VRHOT_GPIO_PINID); 5802 if (gpio.valid) { 5803 dpm_table->VRHotGpio = gpio.shift; 5804 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT; 5805 } else { 5806 dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN; 5807 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT; 5808 } 5809 5810 gpio = radeon_atombios_lookup_gpio(rdev, PP_AC_DC_SWITCH_GPIO_PINID); 5811 if (gpio.valid) { 5812 dpm_table->AcDcGpio = gpio.shift; 5813 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC; 5814 } else { 5815 dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN; 5816 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC; 5817 } 5818 5819 gpio = radeon_atombios_lookup_gpio(rdev, VDDC_PCC_GPIO_PINID); 5820 if (gpio.valid) { 5821 u32 tmp = RREG32_SMC(CNB_PWRMGT_CNTL); 5822 5823 switch (gpio.shift) { 5824 case 0: 5825 tmp &= ~GNB_SLOW_MODE_MASK; 5826 tmp |= GNB_SLOW_MODE(1); 5827 break; 5828 case 1: 5829 tmp &= ~GNB_SLOW_MODE_MASK; 5830 tmp |= GNB_SLOW_MODE(2); 5831 break; 5832 case 2: 5833 tmp |= GNB_SLOW; 5834 break; 5835 case 3: 5836 tmp |= FORCE_NB_PS1; 5837 break; 5838 case 4: 5839 tmp |= DPM_ENABLED; 5840 break; 5841 default: 5842 DRM_DEBUG("Invalid PCC GPIO: %u!\n", gpio.shift); 5843 break; 5844 } 5845 WREG32_SMC(CNB_PWRMGT_CNTL, tmp); 5846 } 5847 5848 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE; 5849 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE; 5850 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE; 5851 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT)) 5852 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; 5853 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) 5854 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; 5855 5856 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) { 5857 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) 5858 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; 5859 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2)) 5860 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; 5861 else 5862 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL; 5863 } 5864 5865 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) { 5866 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) 5867 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; 5868 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) 5869 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; 5870 else 5871 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL; 5872 } 5873 5874 pi->vddc_phase_shed_control = true; 5875 5876 #if defined(CONFIG_ACPI) 5877 pi->pcie_performance_request = 5878 radeon_acpi_is_pcie_performance_request_supported(rdev); 5879 #else 5880 pi->pcie_performance_request = false; 5881 #endif 5882 5883 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 5884 &frev, &crev, &data_offset)) { 5885 pi->caps_sclk_ss_support = true; 5886 pi->caps_mclk_ss_support = true; 5887 pi->dynamic_ss = true; 5888 } else { 5889 pi->caps_sclk_ss_support = false; 5890 pi->caps_mclk_ss_support = false; 5891 pi->dynamic_ss = true; 5892 } 5893 5894 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 5895 pi->thermal_protection = true; 5896 else 5897 pi->thermal_protection = false; 5898 5899 pi->caps_dynamic_ac_timing = true; 5900 5901 pi->uvd_power_gated = false; 5902 5903 /* make sure dc limits are valid */ 5904 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 5905 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 5906 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 5907 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 5908 5909 pi->fan_ctrl_is_in_default_mode = true; 5910 5911 return 0; 5912 } 5913 5914 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 5915 struct seq_file *m) 5916 { 5917 struct ci_power_info *pi = ci_get_pi(rdev); 5918 struct radeon_ps *rps = &pi->current_rps; 5919 u32 sclk = ci_get_average_sclk_freq(rdev); 5920 u32 mclk = ci_get_average_mclk_freq(rdev); 5921 5922 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis"); 5923 seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis"); 5924 seq_printf(m, "power level avg sclk: %u mclk: %u\n", 5925 sclk, mclk); 5926 } 5927 5928 void ci_dpm_print_power_state(struct radeon_device *rdev, 5929 struct radeon_ps *rps) 5930 { 5931 struct ci_ps *ps = ci_get_ps(rps); 5932 struct ci_pl *pl; 5933 int i; 5934 5935 r600_dpm_print_class_info(rps->class, rps->class2); 5936 r600_dpm_print_cap_info(rps->caps); 5937 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 5938 for (i = 0; i < ps->performance_level_count; i++) { 5939 pl = &ps->performance_levels[i]; 5940 printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n", 5941 i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane); 5942 } 5943 r600_dpm_print_ps_status(rdev, rps); 5944 } 5945 5946 u32 ci_dpm_get_current_sclk(struct radeon_device *rdev) 5947 { 5948 u32 sclk = ci_get_average_sclk_freq(rdev); 5949 5950 return sclk; 5951 } 5952 5953 u32 ci_dpm_get_current_mclk(struct radeon_device *rdev) 5954 { 5955 u32 mclk = ci_get_average_mclk_freq(rdev); 5956 5957 return mclk; 5958 } 5959 5960 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low) 5961 { 5962 struct ci_power_info *pi = ci_get_pi(rdev); 5963 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); 5964 5965 if (low) 5966 return requested_state->performance_levels[0].sclk; 5967 else 5968 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; 5969 } 5970 5971 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low) 5972 { 5973 struct ci_power_info *pi = ci_get_pi(rdev); 5974 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); 5975 5976 if (low) 5977 return requested_state->performance_levels[0].mclk; 5978 else 5979 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk; 5980 } 5981