1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __BTC_DPM_H__ 24 #define __BTC_DPM_H__ 25 26 #include "radeon.h" 27 #include "rv770_dpm.h" 28 29 #define BTC_RLP_UVD_DFLT 20 30 #define BTC_RMP_UVD_DFLT 50 31 #define BTC_LHP_UVD_DFLT 50 32 #define BTC_LMP_UVD_DFLT 20 33 #define BARTS_MGCGCGTSSMCTRL_DFLT 0x81944000 34 #define TURKS_MGCGCGTSSMCTRL_DFLT 0x6e944000 35 #define CAICOS_MGCGCGTSSMCTRL_DFLT 0x46944040 36 #define BTC_CGULVPARAMETER_DFLT 0x00040035 37 #define BTC_CGULVCONTROL_DFLT 0x00001450 38 39 extern u32 btc_valid_sclk[40]; 40 41 void btc_read_arb_registers(struct radeon_device *rdev); 42 void btc_program_mgcg_hw_sequence(struct radeon_device *rdev, 43 const u32 *sequence, u32 count); 44 void btc_skip_blacklist_clocks(struct radeon_device *rdev, 45 const u32 max_sclk, const u32 max_mclk, 46 u32 *sclk, u32 *mclk); 47 void btc_adjust_clock_combinations(struct radeon_device *rdev, 48 const struct radeon_clock_and_voltage_limits *max_limits, 49 struct rv7xx_pl *pl); 50 void btc_apply_voltage_dependency_rules(struct radeon_clock_voltage_dependency_table *table, 51 u32 clock, u16 max_voltage, u16 *voltage); 52 void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table, 53 u32 *max_clock); 54 void btc_apply_voltage_delta_rules(struct radeon_device *rdev, 55 u16 max_vddc, u16 max_vddci, 56 u16 *vddc, u16 *vddci); 57 bool btc_dpm_enabled(struct radeon_device *rdev); 58 int btc_reset_to_default(struct radeon_device *rdev); 59 void btc_notify_uvd_to_smc(struct radeon_device *rdev, 60 struct radeon_ps *radeon_new_state); 61 62 #endif 63