1 /* 2 * Copyright 2007-11 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_crtc_helper.h> 28 #include <drm/radeon_drm.h> 29 #include "radeon.h" 30 #include "radeon_audio.h" 31 #include "radeon_asic.h" 32 #include "atom.h" 33 #include <linux/backlight.h> 34 35 extern int atom_debug; 36 37 static u8 38 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev) 39 { 40 u8 backlight_level; 41 u32 bios_2_scratch; 42 43 if (rdev->family >= CHIP_R600) 44 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 45 else 46 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 47 48 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >> 49 ATOM_S2_CURRENT_BL_LEVEL_SHIFT); 50 51 return backlight_level; 52 } 53 54 static void 55 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev, 56 u8 backlight_level) 57 { 58 u32 bios_2_scratch; 59 60 if (rdev->family >= CHIP_R600) 61 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 62 else 63 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 64 65 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; 66 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) & 67 ATOM_S2_CURRENT_BL_LEVEL_MASK); 68 69 if (rdev->family >= CHIP_R600) 70 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 71 else 72 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 73 } 74 75 u8 76 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder) 77 { 78 struct drm_device *dev = radeon_encoder->base.dev; 79 struct radeon_device *rdev = dev->dev_private; 80 81 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 82 return 0; 83 84 return radeon_atom_get_backlight_level_from_reg(rdev); 85 } 86 87 void 88 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) 89 { 90 struct drm_encoder *encoder = &radeon_encoder->base; 91 struct drm_device *dev = radeon_encoder->base.dev; 92 struct radeon_device *rdev = dev->dev_private; 93 struct radeon_encoder_atom_dig *dig; 94 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 95 int index; 96 97 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 98 return; 99 100 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 101 radeon_encoder->enc_priv) { 102 dig = radeon_encoder->enc_priv; 103 dig->backlight_level = level; 104 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level); 105 106 switch (radeon_encoder->encoder_id) { 107 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 108 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 109 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 110 if (dig->backlight_level == 0) { 111 args.ucAction = ATOM_LCD_BLOFF; 112 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 113 } else { 114 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL; 115 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 116 args.ucAction = ATOM_LCD_BLON; 117 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 118 } 119 break; 120 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 121 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 122 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 123 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 124 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 125 if (dig->backlight_level == 0) 126 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 127 else { 128 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0); 129 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 130 } 131 break; 132 default: 133 break; 134 } 135 } 136 } 137 138 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 139 140 static u8 radeon_atom_bl_level(struct backlight_device *bd) 141 { 142 u8 level; 143 144 /* Convert brightness to hardware level */ 145 if (bd->props.brightness < 0) 146 level = 0; 147 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) 148 level = RADEON_MAX_BL_LEVEL; 149 else 150 level = bd->props.brightness; 151 152 return level; 153 } 154 155 static int radeon_atom_backlight_update_status(struct backlight_device *bd) 156 { 157 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 158 struct radeon_encoder *radeon_encoder = pdata->encoder; 159 160 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd)); 161 162 return 0; 163 } 164 165 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd) 166 { 167 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 168 struct radeon_encoder *radeon_encoder = pdata->encoder; 169 struct drm_device *dev = radeon_encoder->base.dev; 170 struct radeon_device *rdev = dev->dev_private; 171 172 return radeon_atom_get_backlight_level_from_reg(rdev); 173 } 174 175 static const struct backlight_ops radeon_atom_backlight_ops = { 176 .get_brightness = radeon_atom_backlight_get_brightness, 177 .update_status = radeon_atom_backlight_update_status, 178 }; 179 180 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 181 struct drm_connector *drm_connector) 182 { 183 struct drm_device *dev = radeon_encoder->base.dev; 184 struct radeon_device *rdev = dev->dev_private; 185 struct backlight_device *bd; 186 struct backlight_properties props; 187 struct radeon_backlight_privdata *pdata; 188 struct radeon_encoder_atom_dig *dig; 189 char bl_name[16]; 190 191 /* Mac laptops with multiple GPUs use the gmux driver for backlight 192 * so don't register a backlight device 193 */ 194 if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && 195 (rdev->pdev->device == 0x6741)) 196 return; 197 198 if (!radeon_encoder->enc_priv) 199 return; 200 201 if (!rdev->is_atom_bios) 202 return; 203 204 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 205 return; 206 207 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL); 208 if (!pdata) { 209 DRM_ERROR("Memory allocation failed\n"); 210 goto error; 211 } 212 213 memset(&props, 0, sizeof(props)); 214 props.max_brightness = RADEON_MAX_BL_LEVEL; 215 props.type = BACKLIGHT_RAW; 216 snprintf(bl_name, sizeof(bl_name), 217 "radeon_bl%d", dev->primary->index); 218 bd = backlight_device_register(bl_name, drm_connector->kdev, 219 pdata, &radeon_atom_backlight_ops, &props); 220 if (IS_ERR(bd)) { 221 DRM_ERROR("Backlight registration failed\n"); 222 goto error; 223 } 224 225 pdata->encoder = radeon_encoder; 226 227 dig = radeon_encoder->enc_priv; 228 dig->bl_dev = bd; 229 230 bd->props.brightness = radeon_atom_backlight_get_brightness(bd); 231 /* Set a reasonable default here if the level is 0 otherwise 232 * fbdev will attempt to turn the backlight on after console 233 * unblanking and it will try and restore 0 which turns the backlight 234 * off again. 235 */ 236 if (bd->props.brightness == 0) 237 bd->props.brightness = RADEON_MAX_BL_LEVEL; 238 bd->props.power = FB_BLANK_UNBLANK; 239 backlight_update_status(bd); 240 241 DRM_INFO("radeon atom DIG backlight initialized\n"); 242 rdev->mode_info.bl_encoder = radeon_encoder; 243 244 return; 245 246 error: 247 kfree(pdata); 248 return; 249 } 250 251 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder) 252 { 253 struct drm_device *dev = radeon_encoder->base.dev; 254 struct radeon_device *rdev = dev->dev_private; 255 struct backlight_device *bd = NULL; 256 struct radeon_encoder_atom_dig *dig; 257 258 if (!radeon_encoder->enc_priv) 259 return; 260 261 if (!rdev->is_atom_bios) 262 return; 263 264 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 265 return; 266 267 dig = radeon_encoder->enc_priv; 268 bd = dig->bl_dev; 269 dig->bl_dev = NULL; 270 271 if (bd) { 272 struct radeon_legacy_backlight_privdata *pdata; 273 274 pdata = bl_get_data(bd); 275 backlight_device_unregister(bd); 276 kfree(pdata); 277 278 DRM_INFO("radeon atom LVDS backlight unloaded\n"); 279 } 280 } 281 282 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ 283 284 void radeon_atom_backlight_init(struct radeon_encoder *encoder) 285 { 286 } 287 288 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder) 289 { 290 } 291 292 #endif 293 294 /* evil but including atombios.h is much worse */ 295 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 296 struct drm_display_mode *mode); 297 298 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 299 const struct drm_display_mode *mode, 300 struct drm_display_mode *adjusted_mode) 301 { 302 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 303 struct drm_device *dev = encoder->dev; 304 struct radeon_device *rdev = dev->dev_private; 305 306 /* set the active encoder to connector routing */ 307 radeon_encoder_set_active_device(encoder); 308 drm_mode_set_crtcinfo(adjusted_mode, 0); 309 310 /* hw bug */ 311 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) 312 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) 313 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; 314 315 /* vertical FP must be at least 1 */ 316 if (mode->crtc_vsync_start == mode->crtc_vdisplay) 317 adjusted_mode->crtc_vsync_start++; 318 319 /* get the native mode for scaling */ 320 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { 321 radeon_panel_mode_fixup(encoder, adjusted_mode); 322 } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 323 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 324 if (tv_dac) { 325 if (tv_dac->tv_std == TV_STD_NTSC || 326 tv_dac->tv_std == TV_STD_NTSC_J || 327 tv_dac->tv_std == TV_STD_PAL_M) 328 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); 329 else 330 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); 331 } 332 } else if (radeon_encoder->rmx_type != RMX_OFF) { 333 radeon_panel_mode_fixup(encoder, adjusted_mode); 334 } 335 336 if (ASIC_IS_DCE3(rdev) && 337 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 338 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) { 339 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 340 radeon_dp_set_link_config(connector, adjusted_mode); 341 } 342 343 return true; 344 } 345 346 static void 347 atombios_dac_setup(struct drm_encoder *encoder, int action) 348 { 349 struct drm_device *dev = encoder->dev; 350 struct radeon_device *rdev = dev->dev_private; 351 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 352 DAC_ENCODER_CONTROL_PS_ALLOCATION args; 353 int index = 0; 354 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 355 356 memset(&args, 0, sizeof(args)); 357 358 switch (radeon_encoder->encoder_id) { 359 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 360 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 361 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); 362 break; 363 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 364 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 365 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); 366 break; 367 } 368 369 args.ucAction = action; 370 371 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) 372 args.ucDacStandard = ATOM_DAC1_PS2; 373 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 374 args.ucDacStandard = ATOM_DAC1_CV; 375 else { 376 switch (dac_info->tv_std) { 377 case TV_STD_PAL: 378 case TV_STD_PAL_M: 379 case TV_STD_SCART_PAL: 380 case TV_STD_SECAM: 381 case TV_STD_PAL_CN: 382 args.ucDacStandard = ATOM_DAC1_PAL; 383 break; 384 case TV_STD_NTSC: 385 case TV_STD_NTSC_J: 386 case TV_STD_PAL_60: 387 default: 388 args.ucDacStandard = ATOM_DAC1_NTSC; 389 break; 390 } 391 } 392 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 393 394 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 395 396 } 397 398 static void 399 atombios_tv_setup(struct drm_encoder *encoder, int action) 400 { 401 struct drm_device *dev = encoder->dev; 402 struct radeon_device *rdev = dev->dev_private; 403 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 404 TV_ENCODER_CONTROL_PS_ALLOCATION args; 405 int index = 0; 406 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 407 408 memset(&args, 0, sizeof(args)); 409 410 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); 411 412 args.sTVEncoder.ucAction = action; 413 414 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 415 args.sTVEncoder.ucTvStandard = ATOM_TV_CV; 416 else { 417 switch (dac_info->tv_std) { 418 case TV_STD_NTSC: 419 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 420 break; 421 case TV_STD_PAL: 422 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; 423 break; 424 case TV_STD_PAL_M: 425 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; 426 break; 427 case TV_STD_PAL_60: 428 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; 429 break; 430 case TV_STD_NTSC_J: 431 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; 432 break; 433 case TV_STD_SCART_PAL: 434 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ 435 break; 436 case TV_STD_SECAM: 437 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; 438 break; 439 case TV_STD_PAL_CN: 440 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; 441 break; 442 default: 443 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 444 break; 445 } 446 } 447 448 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 449 450 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 451 452 } 453 454 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) 455 { 456 int bpc = 8; 457 458 if (encoder->crtc) { 459 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 460 bpc = radeon_crtc->bpc; 461 } 462 463 switch (bpc) { 464 case 0: 465 return PANEL_BPC_UNDEFINE; 466 case 6: 467 return PANEL_6BIT_PER_COLOR; 468 case 8: 469 default: 470 return PANEL_8BIT_PER_COLOR; 471 case 10: 472 return PANEL_10BIT_PER_COLOR; 473 case 12: 474 return PANEL_12BIT_PER_COLOR; 475 case 16: 476 return PANEL_16BIT_PER_COLOR; 477 } 478 } 479 480 union dvo_encoder_control { 481 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; 482 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; 483 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; 484 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4; 485 }; 486 487 void 488 atombios_dvo_setup(struct drm_encoder *encoder, int action) 489 { 490 struct drm_device *dev = encoder->dev; 491 struct radeon_device *rdev = dev->dev_private; 492 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 493 union dvo_encoder_control args; 494 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 495 uint8_t frev, crev; 496 497 memset(&args, 0, sizeof(args)); 498 499 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 500 return; 501 502 /* some R4xx chips have the wrong frev */ 503 if (rdev->family <= CHIP_RV410) 504 frev = 1; 505 506 switch (frev) { 507 case 1: 508 switch (crev) { 509 case 1: 510 /* R4xx, R5xx */ 511 args.ext_tmds.sXTmdsEncoder.ucEnable = action; 512 513 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 514 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; 515 516 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; 517 break; 518 case 2: 519 /* RS600/690/740 */ 520 args.dvo.sDVOEncoder.ucAction = action; 521 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 522 /* DFP1, CRT1, TV1 depending on the type of port */ 523 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; 524 525 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 526 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; 527 break; 528 case 3: 529 /* R6xx */ 530 args.dvo_v3.ucAction = action; 531 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 532 args.dvo_v3.ucDVOConfig = 0; /* XXX */ 533 break; 534 case 4: 535 /* DCE8 */ 536 args.dvo_v4.ucAction = action; 537 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 538 args.dvo_v4.ucDVOConfig = 0; /* XXX */ 539 args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 540 break; 541 default: 542 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 543 break; 544 } 545 break; 546 default: 547 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 548 break; 549 } 550 551 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 552 } 553 554 union lvds_encoder_control { 555 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; 556 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; 557 }; 558 559 void 560 atombios_digital_setup(struct drm_encoder *encoder, int action) 561 { 562 struct drm_device *dev = encoder->dev; 563 struct radeon_device *rdev = dev->dev_private; 564 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 565 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 566 union lvds_encoder_control args; 567 int index = 0; 568 int hdmi_detected = 0; 569 uint8_t frev, crev; 570 571 if (!dig) 572 return; 573 574 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 575 hdmi_detected = 1; 576 577 memset(&args, 0, sizeof(args)); 578 579 switch (radeon_encoder->encoder_id) { 580 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 581 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 582 break; 583 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 584 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 585 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); 586 break; 587 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 588 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 589 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 590 else 591 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); 592 break; 593 } 594 595 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 596 return; 597 598 switch (frev) { 599 case 1: 600 case 2: 601 switch (crev) { 602 case 1: 603 args.v1.ucMisc = 0; 604 args.v1.ucAction = action; 605 if (hdmi_detected) 606 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 607 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 608 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 609 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 610 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 611 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 612 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 613 } else { 614 if (dig->linkb) 615 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 616 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 617 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 618 /*if (pScrn->rgbBits == 8) */ 619 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 620 } 621 break; 622 case 2: 623 case 3: 624 args.v2.ucMisc = 0; 625 args.v2.ucAction = action; 626 if (crev == 3) { 627 if (dig->coherent_mode) 628 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; 629 } 630 if (hdmi_detected) 631 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 632 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 633 args.v2.ucTruncate = 0; 634 args.v2.ucSpatial = 0; 635 args.v2.ucTemporal = 0; 636 args.v2.ucFRC = 0; 637 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 638 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 639 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 640 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { 641 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 642 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 643 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 644 } 645 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { 646 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 647 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 648 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 649 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) 650 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 651 } 652 } else { 653 if (dig->linkb) 654 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 655 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 656 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 657 } 658 break; 659 default: 660 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 661 break; 662 } 663 break; 664 default: 665 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 666 break; 667 } 668 669 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 670 } 671 672 int 673 atombios_get_encoder_mode(struct drm_encoder *encoder) 674 { 675 struct drm_device *dev = encoder->dev; 676 struct radeon_device *rdev = dev->dev_private; 677 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 678 struct drm_connector *connector; 679 struct radeon_connector *radeon_connector; 680 struct radeon_connector_atom_dig *dig_connector; 681 struct radeon_encoder_atom_dig *dig_enc; 682 683 if (radeon_encoder_is_digital(encoder)) { 684 dig_enc = radeon_encoder->enc_priv; 685 if (dig_enc->active_mst_links) 686 return ATOM_ENCODER_MODE_DP_MST; 687 } 688 if (radeon_encoder->is_mst_encoder || radeon_encoder->offset) 689 return ATOM_ENCODER_MODE_DP_MST; 690 /* dp bridges are always DP */ 691 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) 692 return ATOM_ENCODER_MODE_DP; 693 694 /* DVO is always DVO */ 695 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) || 696 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) 697 return ATOM_ENCODER_MODE_DVO; 698 699 connector = radeon_get_connector_for_encoder(encoder); 700 /* if we don't have an active device yet, just use one of 701 * the connectors tied to the encoder. 702 */ 703 if (!connector) 704 connector = radeon_get_connector_for_encoder_init(encoder); 705 radeon_connector = to_radeon_connector(connector); 706 707 switch (connector->connector_type) { 708 case DRM_MODE_CONNECTOR_DVII: 709 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 710 if (radeon_audio != 0) { 711 if (radeon_connector->use_digital && 712 (radeon_connector->audio == RADEON_AUDIO_ENABLE)) 713 return ATOM_ENCODER_MODE_HDMI; 714 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 715 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 716 return ATOM_ENCODER_MODE_HDMI; 717 else if (radeon_connector->use_digital) 718 return ATOM_ENCODER_MODE_DVI; 719 else 720 return ATOM_ENCODER_MODE_CRT; 721 } else if (radeon_connector->use_digital) { 722 return ATOM_ENCODER_MODE_DVI; 723 } else { 724 return ATOM_ENCODER_MODE_CRT; 725 } 726 break; 727 case DRM_MODE_CONNECTOR_DVID: 728 case DRM_MODE_CONNECTOR_HDMIA: 729 default: 730 if (radeon_audio != 0) { 731 if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 732 return ATOM_ENCODER_MODE_HDMI; 733 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 734 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 735 return ATOM_ENCODER_MODE_HDMI; 736 else 737 return ATOM_ENCODER_MODE_DVI; 738 } else { 739 return ATOM_ENCODER_MODE_DVI; 740 } 741 break; 742 case DRM_MODE_CONNECTOR_LVDS: 743 return ATOM_ENCODER_MODE_LVDS; 744 break; 745 case DRM_MODE_CONNECTOR_DisplayPort: 746 dig_connector = radeon_connector->con_priv; 747 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 748 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 749 if (radeon_audio != 0 && 750 drm_detect_monitor_audio(radeon_connector_edid(connector)) && 751 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev)) 752 return ATOM_ENCODER_MODE_DP_AUDIO; 753 return ATOM_ENCODER_MODE_DP; 754 } else if (radeon_audio != 0) { 755 if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 756 return ATOM_ENCODER_MODE_HDMI; 757 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 758 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 759 return ATOM_ENCODER_MODE_HDMI; 760 else 761 return ATOM_ENCODER_MODE_DVI; 762 } else { 763 return ATOM_ENCODER_MODE_DVI; 764 } 765 break; 766 case DRM_MODE_CONNECTOR_eDP: 767 if (radeon_audio != 0 && 768 drm_detect_monitor_audio(radeon_connector_edid(connector)) && 769 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev)) 770 return ATOM_ENCODER_MODE_DP_AUDIO; 771 return ATOM_ENCODER_MODE_DP; 772 case DRM_MODE_CONNECTOR_DVIA: 773 case DRM_MODE_CONNECTOR_VGA: 774 return ATOM_ENCODER_MODE_CRT; 775 break; 776 case DRM_MODE_CONNECTOR_Composite: 777 case DRM_MODE_CONNECTOR_SVIDEO: 778 case DRM_MODE_CONNECTOR_9PinDIN: 779 /* fix me */ 780 return ATOM_ENCODER_MODE_TV; 781 /*return ATOM_ENCODER_MODE_CV;*/ 782 break; 783 } 784 } 785 786 /* 787 * DIG Encoder/Transmitter Setup 788 * 789 * DCE 3.0/3.1 790 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. 791 * Supports up to 3 digital outputs 792 * - 2 DIG encoder blocks. 793 * DIG1 can drive UNIPHY link A or link B 794 * DIG2 can drive UNIPHY link B or LVTMA 795 * 796 * DCE 3.2 797 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). 798 * Supports up to 5 digital outputs 799 * - 2 DIG encoder blocks. 800 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 801 * 802 * DCE 4.0/5.0/6.0 803 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 804 * Supports up to 6 digital outputs 805 * - 6 DIG encoder blocks. 806 * - DIG to PHY mapping is hardcoded 807 * DIG1 drives UNIPHY0 link A, A+B 808 * DIG2 drives UNIPHY0 link B 809 * DIG3 drives UNIPHY1 link A, A+B 810 * DIG4 drives UNIPHY1 link B 811 * DIG5 drives UNIPHY2 link A, A+B 812 * DIG6 drives UNIPHY2 link B 813 * 814 * DCE 4.1 815 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 816 * Supports up to 6 digital outputs 817 * - 2 DIG encoder blocks. 818 * llano 819 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 820 * ontario 821 * DIG1 drives UNIPHY0/1/2 link A 822 * DIG2 drives UNIPHY0/1/2 link B 823 * 824 * Routing 825 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) 826 * Examples: 827 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI 828 * crtc1 -> dig1 -> UNIPHY0 link B -> DP 829 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS 830 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI 831 */ 832 833 union dig_encoder_control { 834 DIG_ENCODER_CONTROL_PS_ALLOCATION v1; 835 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; 836 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; 837 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; 838 }; 839 840 void 841 atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override) 842 { 843 struct drm_device *dev = encoder->dev; 844 struct radeon_device *rdev = dev->dev_private; 845 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 846 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 847 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 848 union dig_encoder_control args; 849 int index = 0; 850 uint8_t frev, crev; 851 int dp_clock = 0; 852 int dp_lane_count = 0; 853 int hpd_id = RADEON_HPD_NONE; 854 855 if (connector) { 856 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 857 struct radeon_connector_atom_dig *dig_connector = 858 radeon_connector->con_priv; 859 860 dp_clock = dig_connector->dp_clock; 861 dp_lane_count = dig_connector->dp_lane_count; 862 hpd_id = radeon_connector->hpd.hpd; 863 } 864 865 /* no dig encoder assigned */ 866 if (dig->dig_encoder == -1) 867 return; 868 869 memset(&args, 0, sizeof(args)); 870 871 if (ASIC_IS_DCE4(rdev)) 872 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); 873 else { 874 if (dig->dig_encoder) 875 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 876 else 877 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 878 } 879 880 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 881 return; 882 883 switch (frev) { 884 case 1: 885 switch (crev) { 886 case 1: 887 args.v1.ucAction = action; 888 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 889 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 890 args.v3.ucPanelMode = panel_mode; 891 else 892 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 893 894 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 895 args.v1.ucLaneNum = dp_lane_count; 896 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 897 args.v1.ucLaneNum = 8; 898 else 899 args.v1.ucLaneNum = 4; 900 901 switch (radeon_encoder->encoder_id) { 902 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 903 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; 904 break; 905 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 906 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 907 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; 908 break; 909 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 910 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; 911 break; 912 } 913 if (dig->linkb) 914 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 915 else 916 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 917 918 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) 919 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 920 921 break; 922 case 2: 923 case 3: 924 args.v3.ucAction = action; 925 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 926 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 927 args.v3.ucPanelMode = panel_mode; 928 else 929 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); 930 931 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) 932 args.v3.ucLaneNum = dp_lane_count; 933 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 934 args.v3.ucLaneNum = 8; 935 else 936 args.v3.ucLaneNum = 4; 937 938 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000)) 939 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 940 if (enc_override != -1) 941 args.v3.acConfig.ucDigSel = enc_override; 942 else 943 args.v3.acConfig.ucDigSel = dig->dig_encoder; 944 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder); 945 break; 946 case 4: 947 args.v4.ucAction = action; 948 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 949 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 950 args.v4.ucPanelMode = panel_mode; 951 else 952 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder); 953 954 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) 955 args.v4.ucLaneNum = dp_lane_count; 956 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 957 args.v4.ucLaneNum = 8; 958 else 959 args.v4.ucLaneNum = 4; 960 961 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) { 962 if (dp_clock == 540000) 963 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; 964 else if (dp_clock == 324000) 965 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ; 966 else if (dp_clock == 270000) 967 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; 968 else 969 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ; 970 } 971 972 if (enc_override != -1) 973 args.v4.acConfig.ucDigSel = enc_override; 974 else 975 args.v4.acConfig.ucDigSel = dig->dig_encoder; 976 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 977 if (hpd_id == RADEON_HPD_NONE) 978 args.v4.ucHPD_ID = 0; 979 else 980 args.v4.ucHPD_ID = hpd_id + 1; 981 break; 982 default: 983 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 984 break; 985 } 986 break; 987 default: 988 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 989 break; 990 } 991 992 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 993 994 } 995 996 void 997 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) 998 { 999 atombios_dig_encoder_setup2(encoder, action, panel_mode, -1); 1000 } 1001 1002 union dig_transmitter_control { 1003 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; 1004 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; 1005 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; 1006 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; 1007 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; 1008 }; 1009 1010 void 1011 atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe) 1012 { 1013 struct drm_device *dev = encoder->dev; 1014 struct radeon_device *rdev = dev->dev_private; 1015 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1016 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1017 struct drm_connector *connector; 1018 union dig_transmitter_control args; 1019 int index = 0; 1020 uint8_t frev, crev; 1021 bool is_dp = false; 1022 int pll_id = 0; 1023 int dp_clock = 0; 1024 int dp_lane_count = 0; 1025 int connector_object_id = 0; 1026 int igp_lane_info = 0; 1027 int dig_encoder = dig->dig_encoder; 1028 int hpd_id = RADEON_HPD_NONE; 1029 1030 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1031 connector = radeon_get_connector_for_encoder_init(encoder); 1032 /* just needed to avoid bailing in the encoder check. the encoder 1033 * isn't used for init 1034 */ 1035 dig_encoder = 0; 1036 } else 1037 connector = radeon_get_connector_for_encoder(encoder); 1038 1039 if (connector) { 1040 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1041 struct radeon_connector_atom_dig *dig_connector = 1042 radeon_connector->con_priv; 1043 1044 hpd_id = radeon_connector->hpd.hpd; 1045 dp_clock = dig_connector->dp_clock; 1046 dp_lane_count = dig_connector->dp_lane_count; 1047 connector_object_id = 1048 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1049 igp_lane_info = dig_connector->igp_lane_info; 1050 } 1051 1052 if (encoder->crtc) { 1053 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1054 pll_id = radeon_crtc->pll_id; 1055 } 1056 1057 /* no dig encoder assigned */ 1058 if (dig_encoder == -1) 1059 return; 1060 1061 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))) 1062 is_dp = true; 1063 1064 memset(&args, 0, sizeof(args)); 1065 1066 switch (radeon_encoder->encoder_id) { 1067 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1068 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1069 break; 1070 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1071 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1072 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1073 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1074 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1075 break; 1076 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1077 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); 1078 break; 1079 } 1080 1081 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1082 return; 1083 1084 switch (frev) { 1085 case 1: 1086 switch (crev) { 1087 case 1: 1088 args.v1.ucAction = action; 1089 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1090 args.v1.usInitInfo = cpu_to_le16(connector_object_id); 1091 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1092 args.v1.asMode.ucLaneSel = lane_num; 1093 args.v1.asMode.ucLaneSet = lane_set; 1094 } else { 1095 if (is_dp) 1096 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10); 1097 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1098 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1099 else 1100 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1101 } 1102 1103 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 1104 1105 if (dig_encoder) 1106 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 1107 else 1108 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; 1109 1110 if ((rdev->flags & RADEON_IS_IGP) && 1111 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { 1112 if (is_dp || 1113 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) { 1114 if (igp_lane_info & 0x1) 1115 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 1116 else if (igp_lane_info & 0x2) 1117 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; 1118 else if (igp_lane_info & 0x4) 1119 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; 1120 else if (igp_lane_info & 0x8) 1121 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; 1122 } else { 1123 if (igp_lane_info & 0x3) 1124 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; 1125 else if (igp_lane_info & 0xc) 1126 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; 1127 } 1128 } 1129 1130 if (dig->linkb) 1131 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; 1132 else 1133 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; 1134 1135 if (is_dp) 1136 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1137 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1138 if (dig->coherent_mode) 1139 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1140 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1141 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; 1142 } 1143 break; 1144 case 2: 1145 args.v2.ucAction = action; 1146 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1147 args.v2.usInitInfo = cpu_to_le16(connector_object_id); 1148 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1149 args.v2.asMode.ucLaneSel = lane_num; 1150 args.v2.asMode.ucLaneSet = lane_set; 1151 } else { 1152 if (is_dp) 1153 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10); 1154 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1155 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1156 else 1157 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1158 } 1159 1160 args.v2.acConfig.ucEncoderSel = dig_encoder; 1161 if (dig->linkb) 1162 args.v2.acConfig.ucLinkSel = 1; 1163 1164 switch (radeon_encoder->encoder_id) { 1165 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1166 args.v2.acConfig.ucTransmitterSel = 0; 1167 break; 1168 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1169 args.v2.acConfig.ucTransmitterSel = 1; 1170 break; 1171 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1172 args.v2.acConfig.ucTransmitterSel = 2; 1173 break; 1174 } 1175 1176 if (is_dp) { 1177 args.v2.acConfig.fCoherentMode = 1; 1178 args.v2.acConfig.fDPConnector = 1; 1179 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1180 if (dig->coherent_mode) 1181 args.v2.acConfig.fCoherentMode = 1; 1182 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1183 args.v2.acConfig.fDualLinkConnector = 1; 1184 } 1185 break; 1186 case 3: 1187 args.v3.ucAction = action; 1188 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1189 args.v3.usInitInfo = cpu_to_le16(connector_object_id); 1190 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1191 args.v3.asMode.ucLaneSel = lane_num; 1192 args.v3.asMode.ucLaneSet = lane_set; 1193 } else { 1194 if (is_dp) 1195 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10); 1196 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1197 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1198 else 1199 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1200 } 1201 1202 if (is_dp) 1203 args.v3.ucLaneNum = dp_lane_count; 1204 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1205 args.v3.ucLaneNum = 8; 1206 else 1207 args.v3.ucLaneNum = 4; 1208 1209 if (dig->linkb) 1210 args.v3.acConfig.ucLinkSel = 1; 1211 if (dig_encoder & 1) 1212 args.v3.acConfig.ucEncoderSel = 1; 1213 1214 /* Select the PLL for the PHY 1215 * DP PHY should be clocked from external src if there is 1216 * one. 1217 */ 1218 /* On DCE4, if there is an external clock, it generates the DP ref clock */ 1219 if (is_dp && rdev->clock.dp_extclk) 1220 args.v3.acConfig.ucRefClkSource = 2; /* external src */ 1221 else 1222 args.v3.acConfig.ucRefClkSource = pll_id; 1223 1224 switch (radeon_encoder->encoder_id) { 1225 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1226 args.v3.acConfig.ucTransmitterSel = 0; 1227 break; 1228 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1229 args.v3.acConfig.ucTransmitterSel = 1; 1230 break; 1231 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1232 args.v3.acConfig.ucTransmitterSel = 2; 1233 break; 1234 } 1235 1236 if (is_dp) 1237 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1238 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1239 if (dig->coherent_mode) 1240 args.v3.acConfig.fCoherentMode = 1; 1241 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1242 args.v3.acConfig.fDualLinkConnector = 1; 1243 } 1244 break; 1245 case 4: 1246 args.v4.ucAction = action; 1247 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1248 args.v4.usInitInfo = cpu_to_le16(connector_object_id); 1249 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1250 args.v4.asMode.ucLaneSel = lane_num; 1251 args.v4.asMode.ucLaneSet = lane_set; 1252 } else { 1253 if (is_dp) 1254 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10); 1255 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1256 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1257 else 1258 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1259 } 1260 1261 if (is_dp) 1262 args.v4.ucLaneNum = dp_lane_count; 1263 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1264 args.v4.ucLaneNum = 8; 1265 else 1266 args.v4.ucLaneNum = 4; 1267 1268 if (dig->linkb) 1269 args.v4.acConfig.ucLinkSel = 1; 1270 if (dig_encoder & 1) 1271 args.v4.acConfig.ucEncoderSel = 1; 1272 1273 /* Select the PLL for the PHY 1274 * DP PHY should be clocked from external src if there is 1275 * one. 1276 */ 1277 /* On DCE5 DCPLL usually generates the DP ref clock */ 1278 if (is_dp) { 1279 if (rdev->clock.dp_extclk) 1280 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; 1281 else 1282 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; 1283 } else 1284 args.v4.acConfig.ucRefClkSource = pll_id; 1285 1286 switch (radeon_encoder->encoder_id) { 1287 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1288 args.v4.acConfig.ucTransmitterSel = 0; 1289 break; 1290 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1291 args.v4.acConfig.ucTransmitterSel = 1; 1292 break; 1293 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1294 args.v4.acConfig.ucTransmitterSel = 2; 1295 break; 1296 } 1297 1298 if (is_dp) 1299 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1300 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1301 if (dig->coherent_mode) 1302 args.v4.acConfig.fCoherentMode = 1; 1303 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1304 args.v4.acConfig.fDualLinkConnector = 1; 1305 } 1306 break; 1307 case 5: 1308 args.v5.ucAction = action; 1309 if (is_dp) 1310 args.v5.usSymClock = cpu_to_le16(dp_clock / 10); 1311 else 1312 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1313 1314 switch (radeon_encoder->encoder_id) { 1315 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1316 if (dig->linkb) 1317 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; 1318 else 1319 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; 1320 break; 1321 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1322 if (dig->linkb) 1323 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; 1324 else 1325 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; 1326 break; 1327 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1328 if (dig->linkb) 1329 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; 1330 else 1331 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; 1332 break; 1333 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1334 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG; 1335 break; 1336 } 1337 if (is_dp) 1338 args.v5.ucLaneNum = dp_lane_count; 1339 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1340 args.v5.ucLaneNum = 8; 1341 else 1342 args.v5.ucLaneNum = 4; 1343 args.v5.ucConnObjId = connector_object_id; 1344 args.v5.ucDigMode = atombios_get_encoder_mode(encoder); 1345 1346 if (is_dp && rdev->clock.dp_extclk) 1347 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK; 1348 else 1349 args.v5.asConfig.ucPhyClkSrcId = pll_id; 1350 1351 if (is_dp) 1352 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ 1353 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1354 if (dig->coherent_mode) 1355 args.v5.asConfig.ucCoherentMode = 1; 1356 } 1357 if (hpd_id == RADEON_HPD_NONE) 1358 args.v5.asConfig.ucHPDSel = 0; 1359 else 1360 args.v5.asConfig.ucHPDSel = hpd_id + 1; 1361 args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder); 1362 args.v5.ucDPLaneSet = lane_set; 1363 break; 1364 default: 1365 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1366 break; 1367 } 1368 break; 1369 default: 1370 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1371 break; 1372 } 1373 1374 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1375 } 1376 1377 void 1378 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) 1379 { 1380 atombios_dig_transmitter_setup2(encoder, action, lane_num, lane_set, -1); 1381 } 1382 1383 bool 1384 atombios_set_edp_panel_power(struct drm_connector *connector, int action) 1385 { 1386 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1387 struct drm_device *dev = radeon_connector->base.dev; 1388 struct radeon_device *rdev = dev->dev_private; 1389 union dig_transmitter_control args; 1390 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1391 uint8_t frev, crev; 1392 1393 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) 1394 goto done; 1395 1396 if (!ASIC_IS_DCE4(rdev)) 1397 goto done; 1398 1399 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && 1400 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) 1401 goto done; 1402 1403 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1404 goto done; 1405 1406 memset(&args, 0, sizeof(args)); 1407 1408 args.v1.ucAction = action; 1409 1410 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1411 1412 /* wait for the panel to power up */ 1413 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { 1414 int i; 1415 1416 for (i = 0; i < 300; i++) { 1417 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) 1418 return true; 1419 mdelay(1); 1420 } 1421 return false; 1422 } 1423 done: 1424 return true; 1425 } 1426 1427 union external_encoder_control { 1428 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; 1429 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; 1430 }; 1431 1432 static void 1433 atombios_external_encoder_setup(struct drm_encoder *encoder, 1434 struct drm_encoder *ext_encoder, 1435 int action) 1436 { 1437 struct drm_device *dev = encoder->dev; 1438 struct radeon_device *rdev = dev->dev_private; 1439 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1440 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); 1441 union external_encoder_control args; 1442 struct drm_connector *connector; 1443 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); 1444 u8 frev, crev; 1445 int dp_clock = 0; 1446 int dp_lane_count = 0; 1447 int connector_object_id = 0; 1448 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1449 1450 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1451 connector = radeon_get_connector_for_encoder_init(encoder); 1452 else 1453 connector = radeon_get_connector_for_encoder(encoder); 1454 1455 if (connector) { 1456 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1457 struct radeon_connector_atom_dig *dig_connector = 1458 radeon_connector->con_priv; 1459 1460 dp_clock = dig_connector->dp_clock; 1461 dp_lane_count = dig_connector->dp_lane_count; 1462 connector_object_id = 1463 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1464 } 1465 1466 memset(&args, 0, sizeof(args)); 1467 1468 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1469 return; 1470 1471 switch (frev) { 1472 case 1: 1473 /* no params on frev 1 */ 1474 break; 1475 case 2: 1476 switch (crev) { 1477 case 1: 1478 case 2: 1479 args.v1.sDigEncoder.ucAction = action; 1480 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1481 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1482 1483 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) { 1484 if (dp_clock == 270000) 1485 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 1486 args.v1.sDigEncoder.ucLaneNum = dp_lane_count; 1487 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1488 args.v1.sDigEncoder.ucLaneNum = 8; 1489 else 1490 args.v1.sDigEncoder.ucLaneNum = 4; 1491 break; 1492 case 3: 1493 args.v3.sExtEncoder.ucAction = action; 1494 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1495 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); 1496 else 1497 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1498 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1499 1500 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { 1501 if (dp_clock == 270000) 1502 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 1503 else if (dp_clock == 540000) 1504 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; 1505 args.v3.sExtEncoder.ucLaneNum = dp_lane_count; 1506 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1507 args.v3.sExtEncoder.ucLaneNum = 8; 1508 else 1509 args.v3.sExtEncoder.ucLaneNum = 4; 1510 switch (ext_enum) { 1511 case GRAPH_OBJECT_ENUM_ID1: 1512 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; 1513 break; 1514 case GRAPH_OBJECT_ENUM_ID2: 1515 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; 1516 break; 1517 case GRAPH_OBJECT_ENUM_ID3: 1518 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; 1519 break; 1520 } 1521 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder); 1522 break; 1523 default: 1524 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1525 return; 1526 } 1527 break; 1528 default: 1529 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1530 return; 1531 } 1532 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1533 } 1534 1535 static void 1536 atombios_yuv_setup(struct drm_encoder *encoder, bool enable) 1537 { 1538 struct drm_device *dev = encoder->dev; 1539 struct radeon_device *rdev = dev->dev_private; 1540 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1541 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1542 ENABLE_YUV_PS_ALLOCATION args; 1543 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); 1544 uint32_t temp, reg; 1545 1546 memset(&args, 0, sizeof(args)); 1547 1548 if (rdev->family >= CHIP_R600) 1549 reg = R600_BIOS_3_SCRATCH; 1550 else 1551 reg = RADEON_BIOS_3_SCRATCH; 1552 1553 /* XXX: fix up scratch reg handling */ 1554 temp = RREG32(reg); 1555 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1556 WREG32(reg, (ATOM_S3_TV1_ACTIVE | 1557 (radeon_crtc->crtc_id << 18))); 1558 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1559 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); 1560 else 1561 WREG32(reg, 0); 1562 1563 if (enable) 1564 args.ucEnable = ATOM_ENABLE; 1565 args.ucCRTC = radeon_crtc->crtc_id; 1566 1567 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1568 1569 WREG32(reg, temp); 1570 } 1571 1572 static void 1573 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode) 1574 { 1575 struct drm_device *dev = encoder->dev; 1576 struct radeon_device *rdev = dev->dev_private; 1577 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1578 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 1579 int index = 0; 1580 1581 memset(&args, 0, sizeof(args)); 1582 1583 switch (radeon_encoder->encoder_id) { 1584 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1585 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1586 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); 1587 break; 1588 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1589 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1590 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1591 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1592 break; 1593 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1594 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1595 break; 1596 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1597 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1598 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1599 else 1600 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); 1601 break; 1602 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1603 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1604 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1605 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1606 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1607 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1608 else 1609 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 1610 break; 1611 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1612 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1613 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1614 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1615 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1616 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1617 else 1618 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 1619 break; 1620 default: 1621 return; 1622 } 1623 1624 switch (mode) { 1625 case DRM_MODE_DPMS_ON: 1626 args.ucAction = ATOM_ENABLE; 1627 /* workaround for DVOOutputControl on some RS690 systems */ 1628 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { 1629 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); 1630 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); 1631 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1632 WREG32(RADEON_BIOS_3_SCRATCH, reg); 1633 } else 1634 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1635 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1636 if (rdev->mode_info.bl_encoder) { 1637 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1638 1639 atombios_set_backlight_level(radeon_encoder, dig->backlight_level); 1640 } else { 1641 args.ucAction = ATOM_LCD_BLON; 1642 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1643 } 1644 } 1645 break; 1646 case DRM_MODE_DPMS_STANDBY: 1647 case DRM_MODE_DPMS_SUSPEND: 1648 case DRM_MODE_DPMS_OFF: 1649 args.ucAction = ATOM_DISABLE; 1650 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1651 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1652 args.ucAction = ATOM_LCD_BLOFF; 1653 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1654 } 1655 break; 1656 } 1657 } 1658 1659 static void 1660 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 1661 { 1662 struct drm_device *dev = encoder->dev; 1663 struct radeon_device *rdev = dev->dev_private; 1664 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1665 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1666 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1667 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1668 struct radeon_connector *radeon_connector = NULL; 1669 struct radeon_connector_atom_dig *radeon_dig_connector = NULL; 1670 bool travis_quirk = false; 1671 1672 if (connector) { 1673 radeon_connector = to_radeon_connector(connector); 1674 radeon_dig_connector = radeon_connector->con_priv; 1675 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 1676 ENCODER_OBJECT_ID_TRAVIS) && 1677 (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 1678 !ASIC_IS_DCE5(rdev)) 1679 travis_quirk = true; 1680 } 1681 1682 switch (mode) { 1683 case DRM_MODE_DPMS_ON: 1684 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 1685 if (!connector) 1686 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 1687 else 1688 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector); 1689 1690 /* setup and enable the encoder */ 1691 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1692 atombios_dig_encoder_setup(encoder, 1693 ATOM_ENCODER_CMD_SETUP_PANEL_MODE, 1694 dig->panel_mode); 1695 if (ext_encoder) { 1696 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) 1697 atombios_external_encoder_setup(encoder, ext_encoder, 1698 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); 1699 } 1700 } else if (ASIC_IS_DCE4(rdev)) { 1701 /* setup and enable the encoder */ 1702 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1703 } else { 1704 /* setup and enable the encoder and transmitter */ 1705 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); 1706 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1707 } 1708 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1709 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1710 atombios_set_edp_panel_power(connector, 1711 ATOM_TRANSMITTER_ACTION_POWER_ON); 1712 radeon_dig_connector->edp_on = true; 1713 } 1714 } 1715 /* enable the transmitter */ 1716 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1717 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1718 /* DP_SET_POWER_D0 is set in radeon_dp_link_train */ 1719 radeon_dp_link_train(encoder, connector); 1720 if (ASIC_IS_DCE4(rdev)) 1721 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); 1722 } 1723 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1724 if (rdev->mode_info.bl_encoder) 1725 atombios_set_backlight_level(radeon_encoder, dig->backlight_level); 1726 else 1727 atombios_dig_transmitter_setup(encoder, 1728 ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 1729 } 1730 if (ext_encoder) 1731 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1732 break; 1733 case DRM_MODE_DPMS_STANDBY: 1734 case DRM_MODE_DPMS_SUSPEND: 1735 case DRM_MODE_DPMS_OFF: 1736 1737 /* don't power off encoders with active MST links */ 1738 if (dig->active_mst_links) 1739 return; 1740 1741 if (ASIC_IS_DCE4(rdev)) { 1742 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) 1743 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1744 } 1745 if (ext_encoder) 1746 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); 1747 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1748 atombios_dig_transmitter_setup(encoder, 1749 ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 1750 1751 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && 1752 connector && !travis_quirk) 1753 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); 1754 if (ASIC_IS_DCE4(rdev)) { 1755 /* disable the transmitter */ 1756 atombios_dig_transmitter_setup(encoder, 1757 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1758 } else { 1759 /* disable the encoder and transmitter */ 1760 atombios_dig_transmitter_setup(encoder, 1761 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1762 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); 1763 } 1764 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1765 if (travis_quirk) 1766 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); 1767 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1768 atombios_set_edp_panel_power(connector, 1769 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1770 radeon_dig_connector->edp_on = false; 1771 } 1772 } 1773 break; 1774 } 1775 } 1776 1777 static void 1778 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 1779 { 1780 struct drm_device *dev = encoder->dev; 1781 struct radeon_device *rdev = dev->dev_private; 1782 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1783 int encoder_mode = atombios_get_encoder_mode(encoder); 1784 1785 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", 1786 radeon_encoder->encoder_id, mode, radeon_encoder->devices, 1787 radeon_encoder->active_device); 1788 1789 if ((radeon_audio != 0) && 1790 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) || 1791 ENCODER_MODE_IS_DP(encoder_mode))) 1792 radeon_audio_dpms(encoder, mode); 1793 1794 switch (radeon_encoder->encoder_id) { 1795 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1796 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1797 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1798 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1799 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1800 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1801 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1802 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1803 radeon_atom_encoder_dpms_avivo(encoder, mode); 1804 break; 1805 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1806 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1807 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1808 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1809 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1810 radeon_atom_encoder_dpms_dig(encoder, mode); 1811 break; 1812 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1813 if (ASIC_IS_DCE5(rdev)) { 1814 switch (mode) { 1815 case DRM_MODE_DPMS_ON: 1816 atombios_dvo_setup(encoder, ATOM_ENABLE); 1817 break; 1818 case DRM_MODE_DPMS_STANDBY: 1819 case DRM_MODE_DPMS_SUSPEND: 1820 case DRM_MODE_DPMS_OFF: 1821 atombios_dvo_setup(encoder, ATOM_DISABLE); 1822 break; 1823 } 1824 } else if (ASIC_IS_DCE3(rdev)) 1825 radeon_atom_encoder_dpms_dig(encoder, mode); 1826 else 1827 radeon_atom_encoder_dpms_avivo(encoder, mode); 1828 break; 1829 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1830 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1831 if (ASIC_IS_DCE5(rdev)) { 1832 switch (mode) { 1833 case DRM_MODE_DPMS_ON: 1834 atombios_dac_setup(encoder, ATOM_ENABLE); 1835 break; 1836 case DRM_MODE_DPMS_STANDBY: 1837 case DRM_MODE_DPMS_SUSPEND: 1838 case DRM_MODE_DPMS_OFF: 1839 atombios_dac_setup(encoder, ATOM_DISABLE); 1840 break; 1841 } 1842 } else 1843 radeon_atom_encoder_dpms_avivo(encoder, mode); 1844 break; 1845 default: 1846 return; 1847 } 1848 1849 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1850 1851 } 1852 1853 union crtc_source_param { 1854 SELECT_CRTC_SOURCE_PS_ALLOCATION v1; 1855 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; 1856 }; 1857 1858 static void 1859 atombios_set_encoder_crtc_source(struct drm_encoder *encoder) 1860 { 1861 struct drm_device *dev = encoder->dev; 1862 struct radeon_device *rdev = dev->dev_private; 1863 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1864 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1865 union crtc_source_param args; 1866 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 1867 uint8_t frev, crev; 1868 struct radeon_encoder_atom_dig *dig; 1869 1870 memset(&args, 0, sizeof(args)); 1871 1872 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1873 return; 1874 1875 switch (frev) { 1876 case 1: 1877 switch (crev) { 1878 case 1: 1879 default: 1880 if (ASIC_IS_AVIVO(rdev)) 1881 args.v1.ucCRTC = radeon_crtc->crtc_id; 1882 else { 1883 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { 1884 args.v1.ucCRTC = radeon_crtc->crtc_id; 1885 } else { 1886 args.v1.ucCRTC = radeon_crtc->crtc_id << 2; 1887 } 1888 } 1889 switch (radeon_encoder->encoder_id) { 1890 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1891 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1892 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; 1893 break; 1894 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1895 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1896 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) 1897 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; 1898 else 1899 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; 1900 break; 1901 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1902 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1903 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1904 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; 1905 break; 1906 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1907 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1908 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1909 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1910 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1911 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1912 else 1913 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; 1914 break; 1915 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1916 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1917 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1918 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1919 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1920 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1921 else 1922 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; 1923 break; 1924 } 1925 break; 1926 case 2: 1927 args.v2.ucCRTC = radeon_crtc->crtc_id; 1928 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { 1929 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1930 1931 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) 1932 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1933 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) 1934 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; 1935 else 1936 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1937 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1938 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1939 } else { 1940 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1941 } 1942 switch (radeon_encoder->encoder_id) { 1943 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1944 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1945 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1946 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1947 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1948 dig = radeon_encoder->enc_priv; 1949 switch (dig->dig_encoder) { 1950 case 0: 1951 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 1952 break; 1953 case 1: 1954 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1955 break; 1956 case 2: 1957 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 1958 break; 1959 case 3: 1960 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 1961 break; 1962 case 4: 1963 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 1964 break; 1965 case 5: 1966 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 1967 break; 1968 case 6: 1969 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; 1970 break; 1971 } 1972 break; 1973 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1974 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; 1975 break; 1976 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1977 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1978 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1979 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1980 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1981 else 1982 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; 1983 break; 1984 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1985 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1986 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1987 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1988 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1989 else 1990 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; 1991 break; 1992 } 1993 break; 1994 } 1995 break; 1996 default: 1997 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1998 return; 1999 } 2000 2001 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2002 2003 /* update scratch regs with new routing */ 2004 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 2005 } 2006 2007 void 2008 atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, int fe) 2009 { 2010 struct drm_device *dev = encoder->dev; 2011 struct radeon_device *rdev = dev->dev_private; 2012 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 2013 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 2014 uint8_t frev, crev; 2015 union crtc_source_param args; 2016 2017 memset(&args, 0, sizeof(args)); 2018 2019 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2020 return; 2021 2022 if (frev != 1 && crev != 2) 2023 DRM_ERROR("Unknown table for MST %d, %d\n", frev, crev); 2024 2025 args.v2.ucCRTC = radeon_crtc->crtc_id; 2026 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_DP_MST; 2027 2028 switch (fe) { 2029 case 0: 2030 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 2031 break; 2032 case 1: 2033 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 2034 break; 2035 case 2: 2036 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 2037 break; 2038 case 3: 2039 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 2040 break; 2041 case 4: 2042 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 2043 break; 2044 case 5: 2045 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 2046 break; 2047 case 6: 2048 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; 2049 break; 2050 } 2051 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2052 } 2053 2054 static void 2055 atombios_apply_encoder_quirks(struct drm_encoder *encoder, 2056 struct drm_display_mode *mode) 2057 { 2058 struct drm_device *dev = encoder->dev; 2059 struct radeon_device *rdev = dev->dev_private; 2060 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2061 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 2062 2063 /* Funky macbooks */ 2064 if ((dev->pdev->device == 0x71C5) && 2065 (dev->pdev->subsystem_vendor == 0x106b) && 2066 (dev->pdev->subsystem_device == 0x0080)) { 2067 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 2068 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); 2069 2070 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; 2071 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 2072 2073 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); 2074 } 2075 } 2076 2077 /* set scaler clears this on some chips */ 2078 if (ASIC_IS_AVIVO(rdev) && 2079 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { 2080 if (ASIC_IS_DCE8(rdev)) { 2081 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2082 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 2083 CIK_INTERLEAVE_EN); 2084 else 2085 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2086 } else if (ASIC_IS_DCE4(rdev)) { 2087 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2088 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 2089 EVERGREEN_INTERLEAVE_EN); 2090 else 2091 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2092 } else { 2093 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2094 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 2095 AVIVO_D1MODE_INTERLEAVE_EN); 2096 else 2097 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2098 } 2099 } 2100 } 2101 2102 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx) 2103 { 2104 if (enc_idx < 0) 2105 return; 2106 rdev->mode_info.active_encoders &= ~(1 << enc_idx); 2107 } 2108 2109 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx) 2110 { 2111 struct drm_device *dev = encoder->dev; 2112 struct radeon_device *rdev = dev->dev_private; 2113 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 2114 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2115 struct drm_encoder *test_encoder; 2116 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2117 uint32_t dig_enc_in_use = 0; 2118 int enc_idx = -1; 2119 2120 if (fe_idx >= 0) { 2121 enc_idx = fe_idx; 2122 goto assigned; 2123 } 2124 if (ASIC_IS_DCE6(rdev)) { 2125 /* DCE6 */ 2126 switch (radeon_encoder->encoder_id) { 2127 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2128 if (dig->linkb) 2129 enc_idx = 1; 2130 else 2131 enc_idx = 0; 2132 break; 2133 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2134 if (dig->linkb) 2135 enc_idx = 3; 2136 else 2137 enc_idx = 2; 2138 break; 2139 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2140 if (dig->linkb) 2141 enc_idx = 5; 2142 else 2143 enc_idx = 4; 2144 break; 2145 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2146 enc_idx = 6; 2147 break; 2148 } 2149 goto assigned; 2150 } else if (ASIC_IS_DCE4(rdev)) { 2151 /* DCE4/5 */ 2152 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) { 2153 /* ontario follows DCE4 */ 2154 if (rdev->family == CHIP_PALM) { 2155 if (dig->linkb) 2156 enc_idx = 1; 2157 else 2158 enc_idx = 0; 2159 } else 2160 /* llano follows DCE3.2 */ 2161 enc_idx = radeon_crtc->crtc_id; 2162 } else { 2163 switch (radeon_encoder->encoder_id) { 2164 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2165 if (dig->linkb) 2166 enc_idx = 1; 2167 else 2168 enc_idx = 0; 2169 break; 2170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2171 if (dig->linkb) 2172 enc_idx = 3; 2173 else 2174 enc_idx = 2; 2175 break; 2176 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2177 if (dig->linkb) 2178 enc_idx = 5; 2179 else 2180 enc_idx = 4; 2181 break; 2182 } 2183 } 2184 goto assigned; 2185 } 2186 2187 /* on DCE32 and encoder can driver any block so just crtc id */ 2188 if (ASIC_IS_DCE32(rdev)) { 2189 enc_idx = radeon_crtc->crtc_id; 2190 goto assigned; 2191 } 2192 2193 /* on DCE3 - LVTMA can only be driven by DIGB */ 2194 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 2195 struct radeon_encoder *radeon_test_encoder; 2196 2197 if (encoder == test_encoder) 2198 continue; 2199 2200 if (!radeon_encoder_is_digital(test_encoder)) 2201 continue; 2202 2203 radeon_test_encoder = to_radeon_encoder(test_encoder); 2204 dig = radeon_test_encoder->enc_priv; 2205 2206 if (dig->dig_encoder >= 0) 2207 dig_enc_in_use |= (1 << dig->dig_encoder); 2208 } 2209 2210 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { 2211 if (dig_enc_in_use & 0x2) 2212 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); 2213 return 1; 2214 } 2215 if (!(dig_enc_in_use & 1)) 2216 return 0; 2217 return 1; 2218 2219 assigned: 2220 if (enc_idx == -1) { 2221 DRM_ERROR("Got encoder index incorrect - returning 0\n"); 2222 return 0; 2223 } 2224 if (rdev->mode_info.active_encoders & (1 << enc_idx)) { 2225 DRM_ERROR("chosen encoder in use %d\n", enc_idx); 2226 } 2227 rdev->mode_info.active_encoders |= (1 << enc_idx); 2228 return enc_idx; 2229 } 2230 2231 /* This only needs to be called once at startup */ 2232 void 2233 radeon_atom_encoder_init(struct radeon_device *rdev) 2234 { 2235 struct drm_device *dev = rdev->ddev; 2236 struct drm_encoder *encoder; 2237 2238 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2239 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2240 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2241 2242 switch (radeon_encoder->encoder_id) { 2243 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2244 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2245 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2246 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2247 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2248 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); 2249 break; 2250 default: 2251 break; 2252 } 2253 2254 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))) 2255 atombios_external_encoder_setup(encoder, ext_encoder, 2256 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); 2257 } 2258 } 2259 2260 static void 2261 radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 2262 struct drm_display_mode *mode, 2263 struct drm_display_mode *adjusted_mode) 2264 { 2265 struct drm_device *dev = encoder->dev; 2266 struct radeon_device *rdev = dev->dev_private; 2267 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2268 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2269 int encoder_mode; 2270 2271 radeon_encoder->pixel_clock = adjusted_mode->clock; 2272 2273 /* need to call this here rather than in prepare() since we need some crtc info */ 2274 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2275 2276 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { 2277 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 2278 atombios_yuv_setup(encoder, true); 2279 else 2280 atombios_yuv_setup(encoder, false); 2281 } 2282 2283 switch (radeon_encoder->encoder_id) { 2284 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2285 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2286 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2287 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2288 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 2289 break; 2290 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2291 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2292 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2293 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2294 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2295 /* handled in dpms */ 2296 break; 2297 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2298 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2299 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2300 atombios_dvo_setup(encoder, ATOM_ENABLE); 2301 break; 2302 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2303 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2304 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2305 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2306 atombios_dac_setup(encoder, ATOM_ENABLE); 2307 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { 2308 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2309 atombios_tv_setup(encoder, ATOM_ENABLE); 2310 else 2311 atombios_tv_setup(encoder, ATOM_DISABLE); 2312 } 2313 break; 2314 } 2315 2316 atombios_apply_encoder_quirks(encoder, adjusted_mode); 2317 2318 encoder_mode = atombios_get_encoder_mode(encoder); 2319 if (connector && (radeon_audio != 0) && 2320 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) || 2321 ENCODER_MODE_IS_DP(encoder_mode))) 2322 radeon_audio_mode_set(encoder, adjusted_mode); 2323 } 2324 2325 static bool 2326 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2327 { 2328 struct drm_device *dev = encoder->dev; 2329 struct radeon_device *rdev = dev->dev_private; 2330 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2331 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2332 2333 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | 2334 ATOM_DEVICE_CV_SUPPORT | 2335 ATOM_DEVICE_CRT_SUPPORT)) { 2336 DAC_LOAD_DETECTION_PS_ALLOCATION args; 2337 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); 2338 uint8_t frev, crev; 2339 2340 memset(&args, 0, sizeof(args)); 2341 2342 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2343 return false; 2344 2345 args.sDacload.ucMisc = 0; 2346 2347 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 2348 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) 2349 args.sDacload.ucDacType = ATOM_DAC_A; 2350 else 2351 args.sDacload.ucDacType = ATOM_DAC_B; 2352 2353 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) 2354 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); 2355 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) 2356 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); 2357 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2358 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); 2359 if (crev >= 3) 2360 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2361 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2362 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); 2363 if (crev >= 3) 2364 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2365 } 2366 2367 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2368 2369 return true; 2370 } else 2371 return false; 2372 } 2373 2374 static enum drm_connector_status 2375 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2376 { 2377 struct drm_device *dev = encoder->dev; 2378 struct radeon_device *rdev = dev->dev_private; 2379 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2380 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2381 uint32_t bios_0_scratch; 2382 2383 if (!atombios_dac_load_detect(encoder, connector)) { 2384 DRM_DEBUG_KMS("detect returned false \n"); 2385 return connector_status_unknown; 2386 } 2387 2388 if (rdev->family >= CHIP_R600) 2389 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2390 else 2391 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 2392 2393 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2394 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2395 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2396 return connector_status_connected; 2397 } 2398 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2399 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2400 return connector_status_connected; 2401 } 2402 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2403 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2404 return connector_status_connected; 2405 } 2406 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2407 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2408 return connector_status_connected; /* CTV */ 2409 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2410 return connector_status_connected; /* STV */ 2411 } 2412 return connector_status_disconnected; 2413 } 2414 2415 static enum drm_connector_status 2416 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2417 { 2418 struct drm_device *dev = encoder->dev; 2419 struct radeon_device *rdev = dev->dev_private; 2420 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2421 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2422 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2423 u32 bios_0_scratch; 2424 2425 if (!ASIC_IS_DCE4(rdev)) 2426 return connector_status_unknown; 2427 2428 if (!ext_encoder) 2429 return connector_status_unknown; 2430 2431 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) 2432 return connector_status_unknown; 2433 2434 /* load detect on the dp bridge */ 2435 atombios_external_encoder_setup(encoder, ext_encoder, 2436 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); 2437 2438 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2439 2440 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2441 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2442 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2443 return connector_status_connected; 2444 } 2445 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2446 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2447 return connector_status_connected; 2448 } 2449 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2450 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2451 return connector_status_connected; 2452 } 2453 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2454 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2455 return connector_status_connected; /* CTV */ 2456 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2457 return connector_status_connected; /* STV */ 2458 } 2459 return connector_status_disconnected; 2460 } 2461 2462 void 2463 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) 2464 { 2465 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2466 2467 if (ext_encoder) 2468 /* ddc_setup on the dp bridge */ 2469 atombios_external_encoder_setup(encoder, ext_encoder, 2470 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); 2471 2472 } 2473 2474 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 2475 { 2476 struct radeon_device *rdev = encoder->dev->dev_private; 2477 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2478 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2479 2480 if ((radeon_encoder->active_device & 2481 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 2482 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 2483 ENCODER_OBJECT_ID_NONE)) { 2484 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2485 if (dig) { 2486 if (dig->dig_encoder >= 0) 2487 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder); 2488 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder, -1); 2489 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) { 2490 if (rdev->family >= CHIP_R600) 2491 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder]; 2492 else 2493 /* RS600/690/740 have only 1 afmt block */ 2494 dig->afmt = rdev->mode_info.afmt[0]; 2495 } 2496 } 2497 } 2498 2499 radeon_atom_output_lock(encoder, true); 2500 2501 if (connector) { 2502 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2503 2504 /* select the clock/data port if it uses a router */ 2505 if (radeon_connector->router.cd_valid) 2506 radeon_router_select_cd_port(radeon_connector); 2507 2508 /* turn eDP panel on for mode set */ 2509 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 2510 atombios_set_edp_panel_power(connector, 2511 ATOM_TRANSMITTER_ACTION_POWER_ON); 2512 } 2513 2514 /* this is needed for the pll/ss setup to work correctly in some cases */ 2515 atombios_set_encoder_crtc_source(encoder); 2516 /* set up the FMT blocks */ 2517 if (ASIC_IS_DCE8(rdev)) 2518 dce8_program_fmt(encoder); 2519 else if (ASIC_IS_DCE4(rdev)) 2520 dce4_program_fmt(encoder); 2521 else if (ASIC_IS_DCE3(rdev)) 2522 dce3_program_fmt(encoder); 2523 else if (ASIC_IS_AVIVO(rdev)) 2524 avivo_program_fmt(encoder); 2525 } 2526 2527 static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 2528 { 2529 /* need to call this here as we need the crtc set up */ 2530 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 2531 radeon_atom_output_lock(encoder, false); 2532 } 2533 2534 static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 2535 { 2536 struct drm_device *dev = encoder->dev; 2537 struct radeon_device *rdev = dev->dev_private; 2538 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2539 struct radeon_encoder_atom_dig *dig; 2540 2541 /* check for pre-DCE3 cards with shared encoders; 2542 * can't really use the links individually, so don't disable 2543 * the encoder if it's in use by another connector 2544 */ 2545 if (!ASIC_IS_DCE3(rdev)) { 2546 struct drm_encoder *other_encoder; 2547 struct radeon_encoder *other_radeon_encoder; 2548 2549 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { 2550 other_radeon_encoder = to_radeon_encoder(other_encoder); 2551 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && 2552 drm_helper_encoder_in_use(other_encoder)) 2553 goto disable_done; 2554 } 2555 } 2556 2557 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2558 2559 switch (radeon_encoder->encoder_id) { 2560 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2561 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2562 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2563 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2564 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); 2565 break; 2566 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2567 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2568 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2569 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2570 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2571 /* handled in dpms */ 2572 break; 2573 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2574 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2575 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2576 atombios_dvo_setup(encoder, ATOM_DISABLE); 2577 break; 2578 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2579 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2580 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2581 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2582 atombios_dac_setup(encoder, ATOM_DISABLE); 2583 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2584 atombios_tv_setup(encoder, ATOM_DISABLE); 2585 break; 2586 } 2587 2588 disable_done: 2589 if (radeon_encoder_is_digital(encoder)) { 2590 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 2591 if (rdev->asic->display.hdmi_enable) 2592 radeon_hdmi_enable(rdev, encoder, false); 2593 } 2594 if (atombios_get_encoder_mode(encoder) != ATOM_ENCODER_MODE_DP_MST) { 2595 dig = radeon_encoder->enc_priv; 2596 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder); 2597 dig->dig_encoder = -1; 2598 radeon_encoder->active_device = 0; 2599 } 2600 } else 2601 radeon_encoder->active_device = 0; 2602 } 2603 2604 /* these are handled by the primary encoders */ 2605 static void radeon_atom_ext_prepare(struct drm_encoder *encoder) 2606 { 2607 2608 } 2609 2610 static void radeon_atom_ext_commit(struct drm_encoder *encoder) 2611 { 2612 2613 } 2614 2615 static void 2616 radeon_atom_ext_mode_set(struct drm_encoder *encoder, 2617 struct drm_display_mode *mode, 2618 struct drm_display_mode *adjusted_mode) 2619 { 2620 2621 } 2622 2623 static void radeon_atom_ext_disable(struct drm_encoder *encoder) 2624 { 2625 2626 } 2627 2628 static void 2629 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) 2630 { 2631 2632 } 2633 2634 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { 2635 .dpms = radeon_atom_ext_dpms, 2636 .prepare = radeon_atom_ext_prepare, 2637 .mode_set = radeon_atom_ext_mode_set, 2638 .commit = radeon_atom_ext_commit, 2639 .disable = radeon_atom_ext_disable, 2640 /* no detect for TMDS/LVDS yet */ 2641 }; 2642 2643 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { 2644 .dpms = radeon_atom_encoder_dpms, 2645 .mode_fixup = radeon_atom_mode_fixup, 2646 .prepare = radeon_atom_encoder_prepare, 2647 .mode_set = radeon_atom_encoder_mode_set, 2648 .commit = radeon_atom_encoder_commit, 2649 .disable = radeon_atom_encoder_disable, 2650 .detect = radeon_atom_dig_detect, 2651 }; 2652 2653 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { 2654 .dpms = radeon_atom_encoder_dpms, 2655 .mode_fixup = radeon_atom_mode_fixup, 2656 .prepare = radeon_atom_encoder_prepare, 2657 .mode_set = radeon_atom_encoder_mode_set, 2658 .commit = radeon_atom_encoder_commit, 2659 .detect = radeon_atom_dac_detect, 2660 }; 2661 2662 void radeon_enc_destroy(struct drm_encoder *encoder) 2663 { 2664 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2665 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2666 radeon_atom_backlight_exit(radeon_encoder); 2667 kfree(radeon_encoder->enc_priv); 2668 drm_encoder_cleanup(encoder); 2669 kfree(radeon_encoder); 2670 } 2671 2672 static const struct drm_encoder_funcs radeon_atom_enc_funcs = { 2673 .destroy = radeon_enc_destroy, 2674 }; 2675 2676 static struct radeon_encoder_atom_dac * 2677 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) 2678 { 2679 struct drm_device *dev = radeon_encoder->base.dev; 2680 struct radeon_device *rdev = dev->dev_private; 2681 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); 2682 2683 if (!dac) 2684 return NULL; 2685 2686 dac->tv_std = radeon_atombios_get_tv_info(rdev); 2687 return dac; 2688 } 2689 2690 static struct radeon_encoder_atom_dig * 2691 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) 2692 { 2693 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 2694 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 2695 2696 if (!dig) 2697 return NULL; 2698 2699 /* coherent mode by default */ 2700 dig->coherent_mode = true; 2701 dig->dig_encoder = -1; 2702 2703 if (encoder_enum == 2) 2704 dig->linkb = true; 2705 else 2706 dig->linkb = false; 2707 2708 return dig; 2709 } 2710 2711 void 2712 radeon_add_atom_encoder(struct drm_device *dev, 2713 uint32_t encoder_enum, 2714 uint32_t supported_device, 2715 u16 caps) 2716 { 2717 struct radeon_device *rdev = dev->dev_private; 2718 struct drm_encoder *encoder; 2719 struct radeon_encoder *radeon_encoder; 2720 2721 /* see if we already added it */ 2722 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2723 radeon_encoder = to_radeon_encoder(encoder); 2724 if (radeon_encoder->encoder_enum == encoder_enum) { 2725 radeon_encoder->devices |= supported_device; 2726 return; 2727 } 2728 2729 } 2730 2731 /* add a new one */ 2732 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); 2733 if (!radeon_encoder) 2734 return; 2735 2736 encoder = &radeon_encoder->base; 2737 switch (rdev->num_crtc) { 2738 case 1: 2739 encoder->possible_crtcs = 0x1; 2740 break; 2741 case 2: 2742 default: 2743 encoder->possible_crtcs = 0x3; 2744 break; 2745 case 4: 2746 encoder->possible_crtcs = 0xf; 2747 break; 2748 case 6: 2749 encoder->possible_crtcs = 0x3f; 2750 break; 2751 } 2752 2753 radeon_encoder->enc_priv = NULL; 2754 2755 radeon_encoder->encoder_enum = encoder_enum; 2756 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 2757 radeon_encoder->devices = supported_device; 2758 radeon_encoder->rmx_type = RMX_OFF; 2759 radeon_encoder->underscan_type = UNDERSCAN_OFF; 2760 radeon_encoder->is_ext_encoder = false; 2761 radeon_encoder->caps = caps; 2762 2763 switch (radeon_encoder->encoder_id) { 2764 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2765 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2766 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2767 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2768 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2769 radeon_encoder->rmx_type = RMX_FULL; 2770 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2771 DRM_MODE_ENCODER_LVDS, NULL); 2772 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2773 } else { 2774 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2775 DRM_MODE_ENCODER_TMDS, NULL); 2776 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2777 } 2778 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2779 break; 2780 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2781 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2782 DRM_MODE_ENCODER_DAC, NULL); 2783 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2784 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2785 break; 2786 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2787 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2788 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2789 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2790 DRM_MODE_ENCODER_TVDAC, NULL); 2791 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2792 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2793 break; 2794 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2795 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2796 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2797 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2798 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2799 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2800 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2801 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2802 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2803 radeon_encoder->rmx_type = RMX_FULL; 2804 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2805 DRM_MODE_ENCODER_LVDS, NULL); 2806 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2807 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 2808 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2809 DRM_MODE_ENCODER_DAC, NULL); 2810 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2811 } else { 2812 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2813 DRM_MODE_ENCODER_TMDS, NULL); 2814 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2815 } 2816 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2817 break; 2818 case ENCODER_OBJECT_ID_SI170B: 2819 case ENCODER_OBJECT_ID_CH7303: 2820 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 2821 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 2822 case ENCODER_OBJECT_ID_TITFP513: 2823 case ENCODER_OBJECT_ID_VT1623: 2824 case ENCODER_OBJECT_ID_HDMI_SI1930: 2825 case ENCODER_OBJECT_ID_TRAVIS: 2826 case ENCODER_OBJECT_ID_NUTMEG: 2827 /* these are handled by the primary encoders */ 2828 radeon_encoder->is_ext_encoder = true; 2829 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2830 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2831 DRM_MODE_ENCODER_LVDS, NULL); 2832 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 2833 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2834 DRM_MODE_ENCODER_DAC, NULL); 2835 else 2836 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2837 DRM_MODE_ENCODER_TMDS, NULL); 2838 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); 2839 break; 2840 } 2841 } 2842