1 /* 2 * Copyright 2007-11 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <linux/backlight.h> 28 #include <linux/dmi.h> 29 #include <linux/pci.h> 30 31 #include <drm/drm_crtc_helper.h> 32 #include <drm/drm_file.h> 33 #include <drm/radeon_drm.h> 34 35 #include "atom.h" 36 #include "radeon_atombios.h" 37 #include "radeon.h" 38 #include "radeon_asic.h" 39 #include "radeon_audio.h" 40 41 extern int atom_debug; 42 43 static u8 44 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev) 45 { 46 u8 backlight_level; 47 u32 bios_2_scratch; 48 49 if (rdev->family >= CHIP_R600) 50 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 51 else 52 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 53 54 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >> 55 ATOM_S2_CURRENT_BL_LEVEL_SHIFT); 56 57 return backlight_level; 58 } 59 60 static void 61 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev, 62 u8 backlight_level) 63 { 64 u32 bios_2_scratch; 65 66 if (rdev->family >= CHIP_R600) 67 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 68 else 69 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 70 71 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; 72 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) & 73 ATOM_S2_CURRENT_BL_LEVEL_MASK); 74 75 if (rdev->family >= CHIP_R600) 76 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 77 else 78 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 79 } 80 81 u8 82 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder) 83 { 84 struct drm_device *dev = radeon_encoder->base.dev; 85 struct radeon_device *rdev = dev->dev_private; 86 87 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 88 return 0; 89 90 return radeon_atom_get_backlight_level_from_reg(rdev); 91 } 92 93 void 94 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) 95 { 96 struct drm_encoder *encoder = &radeon_encoder->base; 97 struct drm_device *dev = radeon_encoder->base.dev; 98 struct radeon_device *rdev = dev->dev_private; 99 struct radeon_encoder_atom_dig *dig; 100 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 101 int index; 102 103 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 104 return; 105 106 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 107 radeon_encoder->enc_priv) { 108 dig = radeon_encoder->enc_priv; 109 dig->backlight_level = level; 110 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level); 111 112 switch (radeon_encoder->encoder_id) { 113 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 114 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 115 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 116 if (dig->backlight_level == 0) { 117 args.ucAction = ATOM_LCD_BLOFF; 118 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 119 } else { 120 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL; 121 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 122 args.ucAction = ATOM_LCD_BLON; 123 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 124 } 125 break; 126 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 127 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 128 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 129 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 130 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 131 if (dig->backlight_level == 0) 132 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 133 else { 134 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0); 135 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 136 } 137 break; 138 default: 139 break; 140 } 141 } 142 } 143 144 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 145 146 static u8 radeon_atom_bl_level(struct backlight_device *bd) 147 { 148 u8 level; 149 150 /* Convert brightness to hardware level */ 151 if (bd->props.brightness < 0) 152 level = 0; 153 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) 154 level = RADEON_MAX_BL_LEVEL; 155 else 156 level = bd->props.brightness; 157 158 return level; 159 } 160 161 static int radeon_atom_backlight_update_status(struct backlight_device *bd) 162 { 163 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 164 struct radeon_encoder *radeon_encoder = pdata->encoder; 165 166 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd)); 167 168 return 0; 169 } 170 171 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd) 172 { 173 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 174 struct radeon_encoder *radeon_encoder = pdata->encoder; 175 struct drm_device *dev = radeon_encoder->base.dev; 176 struct radeon_device *rdev = dev->dev_private; 177 178 return radeon_atom_get_backlight_level_from_reg(rdev); 179 } 180 181 static const struct backlight_ops radeon_atom_backlight_ops = { 182 .get_brightness = radeon_atom_backlight_get_brightness, 183 .update_status = radeon_atom_backlight_update_status, 184 }; 185 186 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 187 struct drm_connector *drm_connector) 188 { 189 struct drm_device *dev = radeon_encoder->base.dev; 190 struct radeon_device *rdev = dev->dev_private; 191 struct backlight_device *bd; 192 struct backlight_properties props; 193 struct radeon_backlight_privdata *pdata; 194 struct radeon_encoder_atom_dig *dig; 195 char bl_name[16]; 196 197 /* Mac laptops with multiple GPUs use the gmux driver for backlight 198 * so don't register a backlight device 199 */ 200 if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && 201 (rdev->pdev->device == 0x6741) && 202 !dmi_match(DMI_PRODUCT_NAME, "iMac12,1")) 203 return; 204 205 if (!radeon_encoder->enc_priv) 206 return; 207 208 if (!rdev->is_atom_bios) 209 return; 210 211 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 212 return; 213 214 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL); 215 if (!pdata) { 216 DRM_ERROR("Memory allocation failed\n"); 217 goto error; 218 } 219 220 memset(&props, 0, sizeof(props)); 221 props.max_brightness = RADEON_MAX_BL_LEVEL; 222 props.type = BACKLIGHT_RAW; 223 snprintf(bl_name, sizeof(bl_name), 224 "radeon_bl%d", dev->primary->index); 225 bd = backlight_device_register(bl_name, drm_connector->kdev, 226 pdata, &radeon_atom_backlight_ops, &props); 227 if (IS_ERR(bd)) { 228 DRM_ERROR("Backlight registration failed\n"); 229 goto error; 230 } 231 232 pdata->encoder = radeon_encoder; 233 234 dig = radeon_encoder->enc_priv; 235 dig->bl_dev = bd; 236 237 bd->props.brightness = radeon_atom_backlight_get_brightness(bd); 238 /* Set a reasonable default here if the level is 0 otherwise 239 * fbdev will attempt to turn the backlight on after console 240 * unblanking and it will try and restore 0 which turns the backlight 241 * off again. 242 */ 243 if (bd->props.brightness == 0) 244 bd->props.brightness = RADEON_MAX_BL_LEVEL; 245 bd->props.power = FB_BLANK_UNBLANK; 246 backlight_update_status(bd); 247 248 DRM_INFO("radeon atom DIG backlight initialized\n"); 249 rdev->mode_info.bl_encoder = radeon_encoder; 250 251 return; 252 253 error: 254 kfree(pdata); 255 return; 256 } 257 258 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder) 259 { 260 struct drm_device *dev = radeon_encoder->base.dev; 261 struct radeon_device *rdev = dev->dev_private; 262 struct backlight_device *bd = NULL; 263 struct radeon_encoder_atom_dig *dig; 264 265 if (!radeon_encoder->enc_priv) 266 return; 267 268 if (!rdev->is_atom_bios) 269 return; 270 271 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 272 return; 273 274 dig = radeon_encoder->enc_priv; 275 bd = dig->bl_dev; 276 dig->bl_dev = NULL; 277 278 if (bd) { 279 struct radeon_legacy_backlight_privdata *pdata; 280 281 pdata = bl_get_data(bd); 282 backlight_device_unregister(bd); 283 kfree(pdata); 284 285 DRM_INFO("radeon atom LVDS backlight unloaded\n"); 286 } 287 } 288 289 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ 290 291 void radeon_atom_backlight_init(struct radeon_encoder *encoder) 292 { 293 } 294 295 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder) 296 { 297 } 298 299 #endif 300 301 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 302 const struct drm_display_mode *mode, 303 struct drm_display_mode *adjusted_mode) 304 { 305 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 306 struct drm_device *dev = encoder->dev; 307 struct radeon_device *rdev = dev->dev_private; 308 309 /* set the active encoder to connector routing */ 310 radeon_encoder_set_active_device(encoder); 311 drm_mode_set_crtcinfo(adjusted_mode, 0); 312 313 /* hw bug */ 314 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) 315 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) 316 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; 317 318 /* vertical FP must be at least 1 */ 319 if (mode->crtc_vsync_start == mode->crtc_vdisplay) 320 adjusted_mode->crtc_vsync_start++; 321 322 /* get the native mode for scaling */ 323 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { 324 radeon_panel_mode_fixup(encoder, adjusted_mode); 325 } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 326 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 327 if (tv_dac) { 328 if (tv_dac->tv_std == TV_STD_NTSC || 329 tv_dac->tv_std == TV_STD_NTSC_J || 330 tv_dac->tv_std == TV_STD_PAL_M) 331 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); 332 else 333 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); 334 } 335 } else if (radeon_encoder->rmx_type != RMX_OFF) { 336 radeon_panel_mode_fixup(encoder, adjusted_mode); 337 } 338 339 if (ASIC_IS_DCE3(rdev) && 340 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 341 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) { 342 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 343 radeon_dp_set_link_config(connector, adjusted_mode); 344 } 345 346 return true; 347 } 348 349 static void 350 atombios_dac_setup(struct drm_encoder *encoder, int action) 351 { 352 struct drm_device *dev = encoder->dev; 353 struct radeon_device *rdev = dev->dev_private; 354 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 355 DAC_ENCODER_CONTROL_PS_ALLOCATION args; 356 int index = 0; 357 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 358 359 memset(&args, 0, sizeof(args)); 360 361 switch (radeon_encoder->encoder_id) { 362 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 363 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 364 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); 365 break; 366 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 367 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 368 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); 369 break; 370 } 371 372 args.ucAction = action; 373 374 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) 375 args.ucDacStandard = ATOM_DAC1_PS2; 376 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 377 args.ucDacStandard = ATOM_DAC1_CV; 378 else { 379 switch (dac_info->tv_std) { 380 case TV_STD_PAL: 381 case TV_STD_PAL_M: 382 case TV_STD_SCART_PAL: 383 case TV_STD_SECAM: 384 case TV_STD_PAL_CN: 385 args.ucDacStandard = ATOM_DAC1_PAL; 386 break; 387 case TV_STD_NTSC: 388 case TV_STD_NTSC_J: 389 case TV_STD_PAL_60: 390 default: 391 args.ucDacStandard = ATOM_DAC1_NTSC; 392 break; 393 } 394 } 395 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 396 397 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 398 399 } 400 401 static void 402 atombios_tv_setup(struct drm_encoder *encoder, int action) 403 { 404 struct drm_device *dev = encoder->dev; 405 struct radeon_device *rdev = dev->dev_private; 406 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 407 TV_ENCODER_CONTROL_PS_ALLOCATION args; 408 int index = 0; 409 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 410 411 memset(&args, 0, sizeof(args)); 412 413 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); 414 415 args.sTVEncoder.ucAction = action; 416 417 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 418 args.sTVEncoder.ucTvStandard = ATOM_TV_CV; 419 else { 420 switch (dac_info->tv_std) { 421 case TV_STD_NTSC: 422 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 423 break; 424 case TV_STD_PAL: 425 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; 426 break; 427 case TV_STD_PAL_M: 428 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; 429 break; 430 case TV_STD_PAL_60: 431 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; 432 break; 433 case TV_STD_NTSC_J: 434 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; 435 break; 436 case TV_STD_SCART_PAL: 437 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ 438 break; 439 case TV_STD_SECAM: 440 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; 441 break; 442 case TV_STD_PAL_CN: 443 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; 444 break; 445 default: 446 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 447 break; 448 } 449 } 450 451 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 452 453 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 454 455 } 456 457 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) 458 { 459 int bpc = 8; 460 461 if (encoder->crtc) { 462 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 463 bpc = radeon_crtc->bpc; 464 } 465 466 switch (bpc) { 467 case 0: 468 return PANEL_BPC_UNDEFINE; 469 case 6: 470 return PANEL_6BIT_PER_COLOR; 471 case 8: 472 default: 473 return PANEL_8BIT_PER_COLOR; 474 case 10: 475 return PANEL_10BIT_PER_COLOR; 476 case 12: 477 return PANEL_12BIT_PER_COLOR; 478 case 16: 479 return PANEL_16BIT_PER_COLOR; 480 } 481 } 482 483 union dvo_encoder_control { 484 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; 485 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; 486 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; 487 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4; 488 }; 489 490 void 491 atombios_dvo_setup(struct drm_encoder *encoder, int action) 492 { 493 struct drm_device *dev = encoder->dev; 494 struct radeon_device *rdev = dev->dev_private; 495 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 496 union dvo_encoder_control args; 497 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 498 uint8_t frev, crev; 499 500 memset(&args, 0, sizeof(args)); 501 502 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 503 return; 504 505 /* some R4xx chips have the wrong frev */ 506 if (rdev->family <= CHIP_RV410) 507 frev = 1; 508 509 switch (frev) { 510 case 1: 511 switch (crev) { 512 case 1: 513 /* R4xx, R5xx */ 514 args.ext_tmds.sXTmdsEncoder.ucEnable = action; 515 516 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 517 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; 518 519 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; 520 break; 521 case 2: 522 /* RS600/690/740 */ 523 args.dvo.sDVOEncoder.ucAction = action; 524 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 525 /* DFP1, CRT1, TV1 depending on the type of port */ 526 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; 527 528 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 529 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; 530 break; 531 case 3: 532 /* R6xx */ 533 args.dvo_v3.ucAction = action; 534 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 535 args.dvo_v3.ucDVOConfig = 0; /* XXX */ 536 break; 537 case 4: 538 /* DCE8 */ 539 args.dvo_v4.ucAction = action; 540 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 541 args.dvo_v4.ucDVOConfig = 0; /* XXX */ 542 args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 543 break; 544 default: 545 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 546 break; 547 } 548 break; 549 default: 550 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 551 break; 552 } 553 554 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 555 } 556 557 union lvds_encoder_control { 558 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; 559 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; 560 }; 561 562 void 563 atombios_digital_setup(struct drm_encoder *encoder, int action) 564 { 565 struct drm_device *dev = encoder->dev; 566 struct radeon_device *rdev = dev->dev_private; 567 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 568 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 569 union lvds_encoder_control args; 570 int index = 0; 571 int hdmi_detected = 0; 572 uint8_t frev, crev; 573 574 if (!dig) 575 return; 576 577 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 578 hdmi_detected = 1; 579 580 memset(&args, 0, sizeof(args)); 581 582 switch (radeon_encoder->encoder_id) { 583 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 584 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 585 break; 586 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 587 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 588 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); 589 break; 590 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 591 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 592 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 593 else 594 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); 595 break; 596 } 597 598 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 599 return; 600 601 switch (frev) { 602 case 1: 603 case 2: 604 switch (crev) { 605 case 1: 606 args.v1.ucMisc = 0; 607 args.v1.ucAction = action; 608 if (hdmi_detected) 609 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 610 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 611 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 612 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 613 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 614 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 615 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 616 } else { 617 if (dig->linkb) 618 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 619 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 620 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 621 /*if (pScrn->rgbBits == 8) */ 622 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 623 } 624 break; 625 case 2: 626 case 3: 627 args.v2.ucMisc = 0; 628 args.v2.ucAction = action; 629 if (crev == 3) { 630 if (dig->coherent_mode) 631 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; 632 } 633 if (hdmi_detected) 634 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 635 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 636 args.v2.ucTruncate = 0; 637 args.v2.ucSpatial = 0; 638 args.v2.ucTemporal = 0; 639 args.v2.ucFRC = 0; 640 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 641 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 642 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 643 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { 644 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 645 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 646 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 647 } 648 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { 649 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 650 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 651 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 652 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) 653 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 654 } 655 } else { 656 if (dig->linkb) 657 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 658 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 659 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 660 } 661 break; 662 default: 663 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 664 break; 665 } 666 break; 667 default: 668 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 669 break; 670 } 671 672 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 673 } 674 675 int 676 atombios_get_encoder_mode(struct drm_encoder *encoder) 677 { 678 struct drm_device *dev = encoder->dev; 679 struct radeon_device *rdev = dev->dev_private; 680 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 681 struct drm_connector *connector; 682 struct radeon_connector *radeon_connector; 683 struct radeon_connector_atom_dig *dig_connector; 684 struct radeon_encoder_atom_dig *dig_enc; 685 686 if (radeon_encoder_is_digital(encoder)) { 687 dig_enc = radeon_encoder->enc_priv; 688 if (dig_enc->active_mst_links) 689 return ATOM_ENCODER_MODE_DP_MST; 690 } 691 if (radeon_encoder->is_mst_encoder || radeon_encoder->offset) 692 return ATOM_ENCODER_MODE_DP_MST; 693 /* dp bridges are always DP */ 694 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) 695 return ATOM_ENCODER_MODE_DP; 696 697 /* DVO is always DVO */ 698 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) || 699 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) 700 return ATOM_ENCODER_MODE_DVO; 701 702 connector = radeon_get_connector_for_encoder(encoder); 703 /* if we don't have an active device yet, just use one of 704 * the connectors tied to the encoder. 705 */ 706 if (!connector) 707 connector = radeon_get_connector_for_encoder_init(encoder); 708 radeon_connector = to_radeon_connector(connector); 709 710 switch (connector->connector_type) { 711 case DRM_MODE_CONNECTOR_DVII: 712 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 713 if (radeon_audio != 0) { 714 if (radeon_connector->use_digital && 715 (radeon_connector->audio == RADEON_AUDIO_ENABLE)) 716 return ATOM_ENCODER_MODE_HDMI; 717 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 718 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 719 return ATOM_ENCODER_MODE_HDMI; 720 else if (radeon_connector->use_digital) 721 return ATOM_ENCODER_MODE_DVI; 722 else 723 return ATOM_ENCODER_MODE_CRT; 724 } else if (radeon_connector->use_digital) { 725 return ATOM_ENCODER_MODE_DVI; 726 } else { 727 return ATOM_ENCODER_MODE_CRT; 728 } 729 break; 730 case DRM_MODE_CONNECTOR_DVID: 731 case DRM_MODE_CONNECTOR_HDMIA: 732 default: 733 if (radeon_audio != 0) { 734 if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 735 return ATOM_ENCODER_MODE_HDMI; 736 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 737 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 738 return ATOM_ENCODER_MODE_HDMI; 739 else 740 return ATOM_ENCODER_MODE_DVI; 741 } else { 742 return ATOM_ENCODER_MODE_DVI; 743 } 744 break; 745 case DRM_MODE_CONNECTOR_LVDS: 746 return ATOM_ENCODER_MODE_LVDS; 747 break; 748 case DRM_MODE_CONNECTOR_DisplayPort: 749 dig_connector = radeon_connector->con_priv; 750 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 751 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 752 if (radeon_audio != 0 && 753 drm_detect_monitor_audio(radeon_connector_edid(connector)) && 754 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev)) 755 return ATOM_ENCODER_MODE_DP_AUDIO; 756 return ATOM_ENCODER_MODE_DP; 757 } else if (radeon_audio != 0) { 758 if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 759 return ATOM_ENCODER_MODE_HDMI; 760 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 761 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 762 return ATOM_ENCODER_MODE_HDMI; 763 else 764 return ATOM_ENCODER_MODE_DVI; 765 } else { 766 return ATOM_ENCODER_MODE_DVI; 767 } 768 break; 769 case DRM_MODE_CONNECTOR_eDP: 770 if (radeon_audio != 0 && 771 drm_detect_monitor_audio(radeon_connector_edid(connector)) && 772 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev)) 773 return ATOM_ENCODER_MODE_DP_AUDIO; 774 return ATOM_ENCODER_MODE_DP; 775 case DRM_MODE_CONNECTOR_DVIA: 776 case DRM_MODE_CONNECTOR_VGA: 777 return ATOM_ENCODER_MODE_CRT; 778 break; 779 case DRM_MODE_CONNECTOR_Composite: 780 case DRM_MODE_CONNECTOR_SVIDEO: 781 case DRM_MODE_CONNECTOR_9PinDIN: 782 /* fix me */ 783 return ATOM_ENCODER_MODE_TV; 784 /*return ATOM_ENCODER_MODE_CV;*/ 785 break; 786 } 787 } 788 789 /* 790 * DIG Encoder/Transmitter Setup 791 * 792 * DCE 3.0/3.1 793 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. 794 * Supports up to 3 digital outputs 795 * - 2 DIG encoder blocks. 796 * DIG1 can drive UNIPHY link A or link B 797 * DIG2 can drive UNIPHY link B or LVTMA 798 * 799 * DCE 3.2 800 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). 801 * Supports up to 5 digital outputs 802 * - 2 DIG encoder blocks. 803 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 804 * 805 * DCE 4.0/5.0/6.0 806 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 807 * Supports up to 6 digital outputs 808 * - 6 DIG encoder blocks. 809 * - DIG to PHY mapping is hardcoded 810 * DIG1 drives UNIPHY0 link A, A+B 811 * DIG2 drives UNIPHY0 link B 812 * DIG3 drives UNIPHY1 link A, A+B 813 * DIG4 drives UNIPHY1 link B 814 * DIG5 drives UNIPHY2 link A, A+B 815 * DIG6 drives UNIPHY2 link B 816 * 817 * DCE 4.1 818 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 819 * Supports up to 6 digital outputs 820 * - 2 DIG encoder blocks. 821 * llano 822 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 823 * ontario 824 * DIG1 drives UNIPHY0/1/2 link A 825 * DIG2 drives UNIPHY0/1/2 link B 826 * 827 * Routing 828 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) 829 * Examples: 830 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI 831 * crtc1 -> dig1 -> UNIPHY0 link B -> DP 832 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS 833 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI 834 */ 835 836 union dig_encoder_control { 837 DIG_ENCODER_CONTROL_PS_ALLOCATION v1; 838 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; 839 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; 840 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; 841 }; 842 843 void 844 atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override) 845 { 846 struct drm_device *dev = encoder->dev; 847 struct radeon_device *rdev = dev->dev_private; 848 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 849 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 850 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 851 union dig_encoder_control args; 852 int index = 0; 853 uint8_t frev, crev; 854 int dp_clock = 0; 855 int dp_lane_count = 0; 856 int hpd_id = RADEON_HPD_NONE; 857 858 if (connector) { 859 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 860 struct radeon_connector_atom_dig *dig_connector = 861 radeon_connector->con_priv; 862 863 dp_clock = dig_connector->dp_clock; 864 dp_lane_count = dig_connector->dp_lane_count; 865 hpd_id = radeon_connector->hpd.hpd; 866 } 867 868 /* no dig encoder assigned */ 869 if (dig->dig_encoder == -1) 870 return; 871 872 memset(&args, 0, sizeof(args)); 873 874 if (ASIC_IS_DCE4(rdev)) 875 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); 876 else { 877 if (dig->dig_encoder) 878 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 879 else 880 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 881 } 882 883 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 884 return; 885 886 switch (frev) { 887 case 1: 888 switch (crev) { 889 case 1: 890 args.v1.ucAction = action; 891 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 892 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 893 args.v3.ucPanelMode = panel_mode; 894 else 895 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 896 897 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 898 args.v1.ucLaneNum = dp_lane_count; 899 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 900 args.v1.ucLaneNum = 8; 901 else 902 args.v1.ucLaneNum = 4; 903 904 switch (radeon_encoder->encoder_id) { 905 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 906 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; 907 break; 908 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 909 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 910 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; 911 break; 912 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 913 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; 914 break; 915 } 916 if (dig->linkb) 917 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 918 else 919 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 920 921 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) 922 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 923 924 break; 925 case 2: 926 case 3: 927 args.v3.ucAction = action; 928 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 929 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 930 args.v3.ucPanelMode = panel_mode; 931 else 932 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); 933 934 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) 935 args.v3.ucLaneNum = dp_lane_count; 936 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 937 args.v3.ucLaneNum = 8; 938 else 939 args.v3.ucLaneNum = 4; 940 941 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000)) 942 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 943 if (enc_override != -1) 944 args.v3.acConfig.ucDigSel = enc_override; 945 else 946 args.v3.acConfig.ucDigSel = dig->dig_encoder; 947 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder); 948 break; 949 case 4: 950 args.v4.ucAction = action; 951 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 952 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 953 args.v4.ucPanelMode = panel_mode; 954 else 955 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder); 956 957 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) 958 args.v4.ucLaneNum = dp_lane_count; 959 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 960 args.v4.ucLaneNum = 8; 961 else 962 args.v4.ucLaneNum = 4; 963 964 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) { 965 if (dp_clock == 540000) 966 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; 967 else if (dp_clock == 324000) 968 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ; 969 else if (dp_clock == 270000) 970 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; 971 else 972 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ; 973 } 974 975 if (enc_override != -1) 976 args.v4.acConfig.ucDigSel = enc_override; 977 else 978 args.v4.acConfig.ucDigSel = dig->dig_encoder; 979 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 980 if (hpd_id == RADEON_HPD_NONE) 981 args.v4.ucHPD_ID = 0; 982 else 983 args.v4.ucHPD_ID = hpd_id + 1; 984 break; 985 default: 986 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 987 break; 988 } 989 break; 990 default: 991 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 992 break; 993 } 994 995 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 996 997 } 998 999 void 1000 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) 1001 { 1002 atombios_dig_encoder_setup2(encoder, action, panel_mode, -1); 1003 } 1004 1005 union dig_transmitter_control { 1006 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; 1007 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; 1008 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; 1009 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; 1010 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; 1011 }; 1012 1013 void 1014 atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe) 1015 { 1016 struct drm_device *dev = encoder->dev; 1017 struct radeon_device *rdev = dev->dev_private; 1018 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1019 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1020 struct drm_connector *connector; 1021 union dig_transmitter_control args; 1022 int index = 0; 1023 uint8_t frev, crev; 1024 bool is_dp = false; 1025 int pll_id = 0; 1026 int dp_clock = 0; 1027 int dp_lane_count = 0; 1028 int connector_object_id = 0; 1029 int igp_lane_info = 0; 1030 int dig_encoder = dig->dig_encoder; 1031 int hpd_id = RADEON_HPD_NONE; 1032 1033 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1034 connector = radeon_get_connector_for_encoder_init(encoder); 1035 /* just needed to avoid bailing in the encoder check. the encoder 1036 * isn't used for init 1037 */ 1038 dig_encoder = 0; 1039 } else 1040 connector = radeon_get_connector_for_encoder(encoder); 1041 1042 if (connector) { 1043 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1044 struct radeon_connector_atom_dig *dig_connector = 1045 radeon_connector->con_priv; 1046 1047 hpd_id = radeon_connector->hpd.hpd; 1048 dp_clock = dig_connector->dp_clock; 1049 dp_lane_count = dig_connector->dp_lane_count; 1050 connector_object_id = 1051 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1052 igp_lane_info = dig_connector->igp_lane_info; 1053 } 1054 1055 if (encoder->crtc) { 1056 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1057 pll_id = radeon_crtc->pll_id; 1058 } 1059 1060 /* no dig encoder assigned */ 1061 if (dig_encoder == -1) 1062 return; 1063 1064 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))) 1065 is_dp = true; 1066 1067 memset(&args, 0, sizeof(args)); 1068 1069 switch (radeon_encoder->encoder_id) { 1070 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1071 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1072 break; 1073 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1074 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1075 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1076 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1077 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1078 break; 1079 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1080 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); 1081 break; 1082 } 1083 1084 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1085 return; 1086 1087 switch (frev) { 1088 case 1: 1089 switch (crev) { 1090 case 1: 1091 args.v1.ucAction = action; 1092 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1093 args.v1.usInitInfo = cpu_to_le16(connector_object_id); 1094 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1095 args.v1.asMode.ucLaneSel = lane_num; 1096 args.v1.asMode.ucLaneSet = lane_set; 1097 } else { 1098 if (is_dp) 1099 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10); 1100 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1101 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1102 else 1103 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1104 } 1105 1106 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 1107 1108 if (dig_encoder) 1109 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 1110 else 1111 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; 1112 1113 if ((rdev->flags & RADEON_IS_IGP) && 1114 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { 1115 if (is_dp || 1116 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) { 1117 if (igp_lane_info & 0x1) 1118 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 1119 else if (igp_lane_info & 0x2) 1120 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; 1121 else if (igp_lane_info & 0x4) 1122 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; 1123 else if (igp_lane_info & 0x8) 1124 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; 1125 } else { 1126 if (igp_lane_info & 0x3) 1127 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; 1128 else if (igp_lane_info & 0xc) 1129 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; 1130 } 1131 } 1132 1133 if (dig->linkb) 1134 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; 1135 else 1136 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; 1137 1138 if (is_dp) 1139 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1140 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1141 if (dig->coherent_mode) 1142 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1143 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1144 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; 1145 } 1146 break; 1147 case 2: 1148 args.v2.ucAction = action; 1149 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1150 args.v2.usInitInfo = cpu_to_le16(connector_object_id); 1151 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1152 args.v2.asMode.ucLaneSel = lane_num; 1153 args.v2.asMode.ucLaneSet = lane_set; 1154 } else { 1155 if (is_dp) 1156 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10); 1157 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1158 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1159 else 1160 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1161 } 1162 1163 args.v2.acConfig.ucEncoderSel = dig_encoder; 1164 if (dig->linkb) 1165 args.v2.acConfig.ucLinkSel = 1; 1166 1167 switch (radeon_encoder->encoder_id) { 1168 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1169 args.v2.acConfig.ucTransmitterSel = 0; 1170 break; 1171 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1172 args.v2.acConfig.ucTransmitterSel = 1; 1173 break; 1174 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1175 args.v2.acConfig.ucTransmitterSel = 2; 1176 break; 1177 } 1178 1179 if (is_dp) { 1180 args.v2.acConfig.fCoherentMode = 1; 1181 args.v2.acConfig.fDPConnector = 1; 1182 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1183 if (dig->coherent_mode) 1184 args.v2.acConfig.fCoherentMode = 1; 1185 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1186 args.v2.acConfig.fDualLinkConnector = 1; 1187 } 1188 break; 1189 case 3: 1190 args.v3.ucAction = action; 1191 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1192 args.v3.usInitInfo = cpu_to_le16(connector_object_id); 1193 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1194 args.v3.asMode.ucLaneSel = lane_num; 1195 args.v3.asMode.ucLaneSet = lane_set; 1196 } else { 1197 if (is_dp) 1198 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10); 1199 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1200 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1201 else 1202 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1203 } 1204 1205 if (is_dp) 1206 args.v3.ucLaneNum = dp_lane_count; 1207 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1208 args.v3.ucLaneNum = 8; 1209 else 1210 args.v3.ucLaneNum = 4; 1211 1212 if (dig->linkb) 1213 args.v3.acConfig.ucLinkSel = 1; 1214 if (dig_encoder & 1) 1215 args.v3.acConfig.ucEncoderSel = 1; 1216 1217 /* Select the PLL for the PHY 1218 * DP PHY should be clocked from external src if there is 1219 * one. 1220 */ 1221 /* On DCE4, if there is an external clock, it generates the DP ref clock */ 1222 if (is_dp && rdev->clock.dp_extclk) 1223 args.v3.acConfig.ucRefClkSource = 2; /* external src */ 1224 else 1225 args.v3.acConfig.ucRefClkSource = pll_id; 1226 1227 switch (radeon_encoder->encoder_id) { 1228 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1229 args.v3.acConfig.ucTransmitterSel = 0; 1230 break; 1231 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1232 args.v3.acConfig.ucTransmitterSel = 1; 1233 break; 1234 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1235 args.v3.acConfig.ucTransmitterSel = 2; 1236 break; 1237 } 1238 1239 if (is_dp) 1240 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1241 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1242 if (dig->coherent_mode) 1243 args.v3.acConfig.fCoherentMode = 1; 1244 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1245 args.v3.acConfig.fDualLinkConnector = 1; 1246 } 1247 break; 1248 case 4: 1249 args.v4.ucAction = action; 1250 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1251 args.v4.usInitInfo = cpu_to_le16(connector_object_id); 1252 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1253 args.v4.asMode.ucLaneSel = lane_num; 1254 args.v4.asMode.ucLaneSet = lane_set; 1255 } else { 1256 if (is_dp) 1257 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10); 1258 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1259 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1260 else 1261 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1262 } 1263 1264 if (is_dp) 1265 args.v4.ucLaneNum = dp_lane_count; 1266 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1267 args.v4.ucLaneNum = 8; 1268 else 1269 args.v4.ucLaneNum = 4; 1270 1271 if (dig->linkb) 1272 args.v4.acConfig.ucLinkSel = 1; 1273 if (dig_encoder & 1) 1274 args.v4.acConfig.ucEncoderSel = 1; 1275 1276 /* Select the PLL for the PHY 1277 * DP PHY should be clocked from external src if there is 1278 * one. 1279 */ 1280 /* On DCE5 DCPLL usually generates the DP ref clock */ 1281 if (is_dp) { 1282 if (rdev->clock.dp_extclk) 1283 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; 1284 else 1285 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; 1286 } else 1287 args.v4.acConfig.ucRefClkSource = pll_id; 1288 1289 switch (radeon_encoder->encoder_id) { 1290 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1291 args.v4.acConfig.ucTransmitterSel = 0; 1292 break; 1293 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1294 args.v4.acConfig.ucTransmitterSel = 1; 1295 break; 1296 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1297 args.v4.acConfig.ucTransmitterSel = 2; 1298 break; 1299 } 1300 1301 if (is_dp) 1302 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1303 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1304 if (dig->coherent_mode) 1305 args.v4.acConfig.fCoherentMode = 1; 1306 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1307 args.v4.acConfig.fDualLinkConnector = 1; 1308 } 1309 break; 1310 case 5: 1311 args.v5.ucAction = action; 1312 if (is_dp) 1313 args.v5.usSymClock = cpu_to_le16(dp_clock / 10); 1314 else 1315 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1316 1317 switch (radeon_encoder->encoder_id) { 1318 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1319 if (dig->linkb) 1320 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; 1321 else 1322 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; 1323 break; 1324 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1325 if (dig->linkb) 1326 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; 1327 else 1328 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; 1329 break; 1330 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1331 if (dig->linkb) 1332 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; 1333 else 1334 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; 1335 break; 1336 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1337 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG; 1338 break; 1339 } 1340 if (is_dp) 1341 args.v5.ucLaneNum = dp_lane_count; 1342 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1343 args.v5.ucLaneNum = 8; 1344 else 1345 args.v5.ucLaneNum = 4; 1346 args.v5.ucConnObjId = connector_object_id; 1347 args.v5.ucDigMode = atombios_get_encoder_mode(encoder); 1348 1349 if (is_dp && rdev->clock.dp_extclk) 1350 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK; 1351 else 1352 args.v5.asConfig.ucPhyClkSrcId = pll_id; 1353 1354 if (is_dp) 1355 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ 1356 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1357 if (dig->coherent_mode) 1358 args.v5.asConfig.ucCoherentMode = 1; 1359 } 1360 if (hpd_id == RADEON_HPD_NONE) 1361 args.v5.asConfig.ucHPDSel = 0; 1362 else 1363 args.v5.asConfig.ucHPDSel = hpd_id + 1; 1364 args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder); 1365 args.v5.ucDPLaneSet = lane_set; 1366 break; 1367 default: 1368 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1369 break; 1370 } 1371 break; 1372 default: 1373 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1374 break; 1375 } 1376 1377 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1378 } 1379 1380 void 1381 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) 1382 { 1383 atombios_dig_transmitter_setup2(encoder, action, lane_num, lane_set, -1); 1384 } 1385 1386 bool 1387 atombios_set_edp_panel_power(struct drm_connector *connector, int action) 1388 { 1389 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1390 struct drm_device *dev = radeon_connector->base.dev; 1391 struct radeon_device *rdev = dev->dev_private; 1392 union dig_transmitter_control args; 1393 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1394 uint8_t frev, crev; 1395 1396 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) 1397 goto done; 1398 1399 if (!ASIC_IS_DCE4(rdev)) 1400 goto done; 1401 1402 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && 1403 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) 1404 goto done; 1405 1406 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1407 goto done; 1408 1409 memset(&args, 0, sizeof(args)); 1410 1411 args.v1.ucAction = action; 1412 1413 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1414 1415 /* wait for the panel to power up */ 1416 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { 1417 int i; 1418 1419 for (i = 0; i < 300; i++) { 1420 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) 1421 return true; 1422 mdelay(1); 1423 } 1424 return false; 1425 } 1426 done: 1427 return true; 1428 } 1429 1430 union external_encoder_control { 1431 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; 1432 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; 1433 }; 1434 1435 static void 1436 atombios_external_encoder_setup(struct drm_encoder *encoder, 1437 struct drm_encoder *ext_encoder, 1438 int action) 1439 { 1440 struct drm_device *dev = encoder->dev; 1441 struct radeon_device *rdev = dev->dev_private; 1442 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1443 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); 1444 union external_encoder_control args; 1445 struct drm_connector *connector; 1446 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); 1447 u8 frev, crev; 1448 int dp_clock = 0; 1449 int dp_lane_count = 0; 1450 int connector_object_id = 0; 1451 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1452 1453 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1454 connector = radeon_get_connector_for_encoder_init(encoder); 1455 else 1456 connector = radeon_get_connector_for_encoder(encoder); 1457 1458 if (connector) { 1459 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1460 struct radeon_connector_atom_dig *dig_connector = 1461 radeon_connector->con_priv; 1462 1463 dp_clock = dig_connector->dp_clock; 1464 dp_lane_count = dig_connector->dp_lane_count; 1465 connector_object_id = 1466 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1467 } 1468 1469 memset(&args, 0, sizeof(args)); 1470 1471 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1472 return; 1473 1474 switch (frev) { 1475 case 1: 1476 /* no params on frev 1 */ 1477 break; 1478 case 2: 1479 switch (crev) { 1480 case 1: 1481 case 2: 1482 args.v1.sDigEncoder.ucAction = action; 1483 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1484 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1485 1486 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) { 1487 if (dp_clock == 270000) 1488 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 1489 args.v1.sDigEncoder.ucLaneNum = dp_lane_count; 1490 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1491 args.v1.sDigEncoder.ucLaneNum = 8; 1492 else 1493 args.v1.sDigEncoder.ucLaneNum = 4; 1494 break; 1495 case 3: 1496 args.v3.sExtEncoder.ucAction = action; 1497 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1498 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); 1499 else 1500 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1501 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1502 1503 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { 1504 if (dp_clock == 270000) 1505 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 1506 else if (dp_clock == 540000) 1507 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; 1508 args.v3.sExtEncoder.ucLaneNum = dp_lane_count; 1509 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1510 args.v3.sExtEncoder.ucLaneNum = 8; 1511 else 1512 args.v3.sExtEncoder.ucLaneNum = 4; 1513 switch (ext_enum) { 1514 case GRAPH_OBJECT_ENUM_ID1: 1515 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; 1516 break; 1517 case GRAPH_OBJECT_ENUM_ID2: 1518 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; 1519 break; 1520 case GRAPH_OBJECT_ENUM_ID3: 1521 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; 1522 break; 1523 } 1524 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder); 1525 break; 1526 default: 1527 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1528 return; 1529 } 1530 break; 1531 default: 1532 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1533 return; 1534 } 1535 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1536 } 1537 1538 static void 1539 atombios_yuv_setup(struct drm_encoder *encoder, bool enable) 1540 { 1541 struct drm_device *dev = encoder->dev; 1542 struct radeon_device *rdev = dev->dev_private; 1543 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1544 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1545 ENABLE_YUV_PS_ALLOCATION args; 1546 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); 1547 uint32_t temp, reg; 1548 1549 memset(&args, 0, sizeof(args)); 1550 1551 if (rdev->family >= CHIP_R600) 1552 reg = R600_BIOS_3_SCRATCH; 1553 else 1554 reg = RADEON_BIOS_3_SCRATCH; 1555 1556 /* XXX: fix up scratch reg handling */ 1557 temp = RREG32(reg); 1558 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1559 WREG32(reg, (ATOM_S3_TV1_ACTIVE | 1560 (radeon_crtc->crtc_id << 18))); 1561 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1562 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); 1563 else 1564 WREG32(reg, 0); 1565 1566 if (enable) 1567 args.ucEnable = ATOM_ENABLE; 1568 args.ucCRTC = radeon_crtc->crtc_id; 1569 1570 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1571 1572 WREG32(reg, temp); 1573 } 1574 1575 static void 1576 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode) 1577 { 1578 struct drm_device *dev = encoder->dev; 1579 struct radeon_device *rdev = dev->dev_private; 1580 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1581 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 1582 int index = 0; 1583 1584 memset(&args, 0, sizeof(args)); 1585 1586 switch (radeon_encoder->encoder_id) { 1587 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1588 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1589 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); 1590 break; 1591 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1592 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1593 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1594 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1595 break; 1596 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1597 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1598 break; 1599 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1600 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1601 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1602 else 1603 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); 1604 break; 1605 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1606 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1607 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1608 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1609 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1610 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1611 else 1612 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 1613 break; 1614 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1615 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1616 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1617 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1618 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1619 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1620 else 1621 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 1622 break; 1623 default: 1624 return; 1625 } 1626 1627 switch (mode) { 1628 case DRM_MODE_DPMS_ON: 1629 args.ucAction = ATOM_ENABLE; 1630 /* workaround for DVOOutputControl on some RS690 systems */ 1631 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { 1632 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); 1633 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); 1634 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1635 WREG32(RADEON_BIOS_3_SCRATCH, reg); 1636 } else 1637 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1638 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1639 if (rdev->mode_info.bl_encoder) { 1640 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1641 1642 atombios_set_backlight_level(radeon_encoder, dig->backlight_level); 1643 } else { 1644 args.ucAction = ATOM_LCD_BLON; 1645 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1646 } 1647 } 1648 break; 1649 case DRM_MODE_DPMS_STANDBY: 1650 case DRM_MODE_DPMS_SUSPEND: 1651 case DRM_MODE_DPMS_OFF: 1652 args.ucAction = ATOM_DISABLE; 1653 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1654 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1655 args.ucAction = ATOM_LCD_BLOFF; 1656 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1657 } 1658 break; 1659 } 1660 } 1661 1662 static void 1663 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 1664 { 1665 struct drm_device *dev = encoder->dev; 1666 struct radeon_device *rdev = dev->dev_private; 1667 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1668 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1669 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1670 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1671 struct radeon_connector *radeon_connector = NULL; 1672 struct radeon_connector_atom_dig *radeon_dig_connector = NULL; 1673 bool travis_quirk = false; 1674 1675 if (connector) { 1676 radeon_connector = to_radeon_connector(connector); 1677 radeon_dig_connector = radeon_connector->con_priv; 1678 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 1679 ENCODER_OBJECT_ID_TRAVIS) && 1680 (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 1681 !ASIC_IS_DCE5(rdev)) 1682 travis_quirk = true; 1683 } 1684 1685 switch (mode) { 1686 case DRM_MODE_DPMS_ON: 1687 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 1688 if (!connector) 1689 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 1690 else 1691 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector); 1692 1693 /* setup and enable the encoder */ 1694 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1695 atombios_dig_encoder_setup(encoder, 1696 ATOM_ENCODER_CMD_SETUP_PANEL_MODE, 1697 dig->panel_mode); 1698 if (ext_encoder) { 1699 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) 1700 atombios_external_encoder_setup(encoder, ext_encoder, 1701 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); 1702 } 1703 } else if (ASIC_IS_DCE4(rdev)) { 1704 /* setup and enable the encoder */ 1705 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1706 } else { 1707 /* setup and enable the encoder and transmitter */ 1708 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); 1709 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1710 } 1711 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1712 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1713 atombios_set_edp_panel_power(connector, 1714 ATOM_TRANSMITTER_ACTION_POWER_ON); 1715 radeon_dig_connector->edp_on = true; 1716 } 1717 } 1718 /* enable the transmitter */ 1719 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1720 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1721 /* DP_SET_POWER_D0 is set in radeon_dp_link_train */ 1722 radeon_dp_link_train(encoder, connector); 1723 if (ASIC_IS_DCE4(rdev)) 1724 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); 1725 } 1726 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1727 if (rdev->mode_info.bl_encoder) 1728 atombios_set_backlight_level(radeon_encoder, dig->backlight_level); 1729 else 1730 atombios_dig_transmitter_setup(encoder, 1731 ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 1732 } 1733 if (ext_encoder) 1734 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1735 break; 1736 case DRM_MODE_DPMS_STANDBY: 1737 case DRM_MODE_DPMS_SUSPEND: 1738 case DRM_MODE_DPMS_OFF: 1739 1740 /* don't power off encoders with active MST links */ 1741 if (dig->active_mst_links) 1742 return; 1743 1744 if (ASIC_IS_DCE4(rdev)) { 1745 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) 1746 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1747 } 1748 if (ext_encoder) 1749 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); 1750 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1751 atombios_dig_transmitter_setup(encoder, 1752 ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 1753 1754 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && 1755 connector && !travis_quirk) 1756 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); 1757 if (ASIC_IS_DCE4(rdev)) { 1758 /* disable the transmitter */ 1759 atombios_dig_transmitter_setup(encoder, 1760 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1761 } else { 1762 /* disable the encoder and transmitter */ 1763 atombios_dig_transmitter_setup(encoder, 1764 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1765 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); 1766 } 1767 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1768 if (travis_quirk) 1769 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); 1770 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1771 atombios_set_edp_panel_power(connector, 1772 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1773 radeon_dig_connector->edp_on = false; 1774 } 1775 } 1776 break; 1777 } 1778 } 1779 1780 static void 1781 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 1782 { 1783 struct drm_device *dev = encoder->dev; 1784 struct radeon_device *rdev = dev->dev_private; 1785 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1786 int encoder_mode = atombios_get_encoder_mode(encoder); 1787 1788 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", 1789 radeon_encoder->encoder_id, mode, radeon_encoder->devices, 1790 radeon_encoder->active_device); 1791 1792 if ((radeon_audio != 0) && 1793 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) || 1794 ENCODER_MODE_IS_DP(encoder_mode))) 1795 radeon_audio_dpms(encoder, mode); 1796 1797 switch (radeon_encoder->encoder_id) { 1798 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1799 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1800 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1801 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1802 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1803 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1804 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1805 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1806 radeon_atom_encoder_dpms_avivo(encoder, mode); 1807 break; 1808 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1809 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1810 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1811 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1812 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1813 radeon_atom_encoder_dpms_dig(encoder, mode); 1814 break; 1815 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1816 if (ASIC_IS_DCE5(rdev)) { 1817 switch (mode) { 1818 case DRM_MODE_DPMS_ON: 1819 atombios_dvo_setup(encoder, ATOM_ENABLE); 1820 break; 1821 case DRM_MODE_DPMS_STANDBY: 1822 case DRM_MODE_DPMS_SUSPEND: 1823 case DRM_MODE_DPMS_OFF: 1824 atombios_dvo_setup(encoder, ATOM_DISABLE); 1825 break; 1826 } 1827 } else if (ASIC_IS_DCE3(rdev)) 1828 radeon_atom_encoder_dpms_dig(encoder, mode); 1829 else 1830 radeon_atom_encoder_dpms_avivo(encoder, mode); 1831 break; 1832 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1833 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1834 if (ASIC_IS_DCE5(rdev)) { 1835 switch (mode) { 1836 case DRM_MODE_DPMS_ON: 1837 atombios_dac_setup(encoder, ATOM_ENABLE); 1838 break; 1839 case DRM_MODE_DPMS_STANDBY: 1840 case DRM_MODE_DPMS_SUSPEND: 1841 case DRM_MODE_DPMS_OFF: 1842 atombios_dac_setup(encoder, ATOM_DISABLE); 1843 break; 1844 } 1845 } else 1846 radeon_atom_encoder_dpms_avivo(encoder, mode); 1847 break; 1848 default: 1849 return; 1850 } 1851 1852 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1853 1854 } 1855 1856 union crtc_source_param { 1857 SELECT_CRTC_SOURCE_PS_ALLOCATION v1; 1858 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; 1859 }; 1860 1861 static void 1862 atombios_set_encoder_crtc_source(struct drm_encoder *encoder) 1863 { 1864 struct drm_device *dev = encoder->dev; 1865 struct radeon_device *rdev = dev->dev_private; 1866 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1867 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1868 union crtc_source_param args; 1869 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 1870 uint8_t frev, crev; 1871 struct radeon_encoder_atom_dig *dig; 1872 1873 memset(&args, 0, sizeof(args)); 1874 1875 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1876 return; 1877 1878 switch (frev) { 1879 case 1: 1880 switch (crev) { 1881 case 1: 1882 default: 1883 if (ASIC_IS_AVIVO(rdev)) 1884 args.v1.ucCRTC = radeon_crtc->crtc_id; 1885 else { 1886 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) 1887 args.v1.ucCRTC = radeon_crtc->crtc_id; 1888 else 1889 args.v1.ucCRTC = radeon_crtc->crtc_id << 2; 1890 } 1891 switch (radeon_encoder->encoder_id) { 1892 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1893 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1894 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; 1895 break; 1896 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1897 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1898 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) 1899 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; 1900 else 1901 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; 1902 break; 1903 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1904 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1905 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1906 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; 1907 break; 1908 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1909 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1910 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1911 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1912 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1913 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1914 else 1915 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; 1916 break; 1917 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1918 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1919 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1920 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1921 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1922 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1923 else 1924 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; 1925 break; 1926 } 1927 break; 1928 case 2: 1929 args.v2.ucCRTC = radeon_crtc->crtc_id; 1930 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { 1931 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1932 1933 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) 1934 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1935 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) 1936 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; 1937 else 1938 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1939 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1940 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1941 } else { 1942 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1943 } 1944 switch (radeon_encoder->encoder_id) { 1945 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1946 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1947 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1948 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1949 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1950 dig = radeon_encoder->enc_priv; 1951 switch (dig->dig_encoder) { 1952 case 0: 1953 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 1954 break; 1955 case 1: 1956 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1957 break; 1958 case 2: 1959 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 1960 break; 1961 case 3: 1962 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 1963 break; 1964 case 4: 1965 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 1966 break; 1967 case 5: 1968 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 1969 break; 1970 case 6: 1971 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; 1972 break; 1973 } 1974 break; 1975 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1976 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; 1977 break; 1978 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1979 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1980 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1981 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1982 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1983 else 1984 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; 1985 break; 1986 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1987 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1988 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1989 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1990 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1991 else 1992 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; 1993 break; 1994 } 1995 break; 1996 } 1997 break; 1998 default: 1999 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 2000 return; 2001 } 2002 2003 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2004 2005 /* update scratch regs with new routing */ 2006 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 2007 } 2008 2009 void 2010 atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, int fe) 2011 { 2012 struct drm_device *dev = encoder->dev; 2013 struct radeon_device *rdev = dev->dev_private; 2014 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 2015 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 2016 uint8_t frev, crev; 2017 union crtc_source_param args; 2018 2019 memset(&args, 0, sizeof(args)); 2020 2021 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2022 return; 2023 2024 if (frev != 1 && crev != 2) 2025 DRM_ERROR("Unknown table for MST %d, %d\n", frev, crev); 2026 2027 args.v2.ucCRTC = radeon_crtc->crtc_id; 2028 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_DP_MST; 2029 2030 switch (fe) { 2031 case 0: 2032 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 2033 break; 2034 case 1: 2035 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 2036 break; 2037 case 2: 2038 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 2039 break; 2040 case 3: 2041 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 2042 break; 2043 case 4: 2044 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 2045 break; 2046 case 5: 2047 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 2048 break; 2049 case 6: 2050 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; 2051 break; 2052 } 2053 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2054 } 2055 2056 static void 2057 atombios_apply_encoder_quirks(struct drm_encoder *encoder, 2058 struct drm_display_mode *mode) 2059 { 2060 struct drm_device *dev = encoder->dev; 2061 struct radeon_device *rdev = dev->dev_private; 2062 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2063 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 2064 2065 /* Funky macbooks */ 2066 if ((rdev->pdev->device == 0x71C5) && 2067 (rdev->pdev->subsystem_vendor == 0x106b) && 2068 (rdev->pdev->subsystem_device == 0x0080)) { 2069 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 2070 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); 2071 2072 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; 2073 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 2074 2075 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); 2076 } 2077 } 2078 2079 /* set scaler clears this on some chips */ 2080 if (ASIC_IS_AVIVO(rdev) && 2081 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { 2082 if (ASIC_IS_DCE8(rdev)) { 2083 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2084 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 2085 CIK_INTERLEAVE_EN); 2086 else 2087 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2088 } else if (ASIC_IS_DCE4(rdev)) { 2089 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2090 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 2091 EVERGREEN_INTERLEAVE_EN); 2092 else 2093 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2094 } else { 2095 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2096 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 2097 AVIVO_D1MODE_INTERLEAVE_EN); 2098 else 2099 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2100 } 2101 } 2102 } 2103 2104 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx) 2105 { 2106 if (enc_idx < 0) 2107 return; 2108 rdev->mode_info.active_encoders &= ~(1 << enc_idx); 2109 } 2110 2111 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx) 2112 { 2113 struct drm_device *dev = encoder->dev; 2114 struct radeon_device *rdev = dev->dev_private; 2115 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 2116 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2117 struct drm_encoder *test_encoder; 2118 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2119 uint32_t dig_enc_in_use = 0; 2120 int enc_idx = -1; 2121 2122 if (fe_idx >= 0) { 2123 enc_idx = fe_idx; 2124 goto assigned; 2125 } 2126 if (ASIC_IS_DCE6(rdev)) { 2127 /* DCE6 */ 2128 switch (radeon_encoder->encoder_id) { 2129 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2130 if (dig->linkb) 2131 enc_idx = 1; 2132 else 2133 enc_idx = 0; 2134 break; 2135 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2136 if (dig->linkb) 2137 enc_idx = 3; 2138 else 2139 enc_idx = 2; 2140 break; 2141 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2142 if (dig->linkb) 2143 enc_idx = 5; 2144 else 2145 enc_idx = 4; 2146 break; 2147 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2148 enc_idx = 6; 2149 break; 2150 } 2151 goto assigned; 2152 } else if (ASIC_IS_DCE4(rdev)) { 2153 /* DCE4/5 */ 2154 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) { 2155 /* ontario follows DCE4 */ 2156 if (rdev->family == CHIP_PALM) { 2157 if (dig->linkb) 2158 enc_idx = 1; 2159 else 2160 enc_idx = 0; 2161 } else 2162 /* llano follows DCE3.2 */ 2163 enc_idx = radeon_crtc->crtc_id; 2164 } else { 2165 switch (radeon_encoder->encoder_id) { 2166 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2167 if (dig->linkb) 2168 enc_idx = 1; 2169 else 2170 enc_idx = 0; 2171 break; 2172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2173 if (dig->linkb) 2174 enc_idx = 3; 2175 else 2176 enc_idx = 2; 2177 break; 2178 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2179 if (dig->linkb) 2180 enc_idx = 5; 2181 else 2182 enc_idx = 4; 2183 break; 2184 } 2185 } 2186 goto assigned; 2187 } 2188 2189 /* 2190 * On DCE32 any encoder can drive any block so usually just use crtc id, 2191 * but Apple thinks different at least on iMac10,1, so there use linkb, 2192 * otherwise the internal eDP panel will stay dark. 2193 */ 2194 if (ASIC_IS_DCE32(rdev)) { 2195 if (dmi_match(DMI_PRODUCT_NAME, "iMac10,1")) 2196 enc_idx = (dig->linkb) ? 1 : 0; 2197 else 2198 enc_idx = radeon_crtc->crtc_id; 2199 2200 goto assigned; 2201 } 2202 2203 /* on DCE3 - LVTMA can only be driven by DIGB */ 2204 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 2205 struct radeon_encoder *radeon_test_encoder; 2206 2207 if (encoder == test_encoder) 2208 continue; 2209 2210 if (!radeon_encoder_is_digital(test_encoder)) 2211 continue; 2212 2213 radeon_test_encoder = to_radeon_encoder(test_encoder); 2214 dig = radeon_test_encoder->enc_priv; 2215 2216 if (dig->dig_encoder >= 0) 2217 dig_enc_in_use |= (1 << dig->dig_encoder); 2218 } 2219 2220 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { 2221 if (dig_enc_in_use & 0x2) 2222 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); 2223 return 1; 2224 } 2225 if (!(dig_enc_in_use & 1)) 2226 return 0; 2227 return 1; 2228 2229 assigned: 2230 if (enc_idx == -1) { 2231 DRM_ERROR("Got encoder index incorrect - returning 0\n"); 2232 return 0; 2233 } 2234 if (rdev->mode_info.active_encoders & (1 << enc_idx)) 2235 DRM_ERROR("chosen encoder in use %d\n", enc_idx); 2236 2237 rdev->mode_info.active_encoders |= (1 << enc_idx); 2238 return enc_idx; 2239 } 2240 2241 /* This only needs to be called once at startup */ 2242 void 2243 radeon_atom_encoder_init(struct radeon_device *rdev) 2244 { 2245 struct drm_device *dev = rdev->ddev; 2246 struct drm_encoder *encoder; 2247 2248 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2249 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2250 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2251 2252 switch (radeon_encoder->encoder_id) { 2253 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2254 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2255 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2256 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2257 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2258 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); 2259 break; 2260 default: 2261 break; 2262 } 2263 2264 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))) 2265 atombios_external_encoder_setup(encoder, ext_encoder, 2266 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); 2267 } 2268 } 2269 2270 static void 2271 radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 2272 struct drm_display_mode *mode, 2273 struct drm_display_mode *adjusted_mode) 2274 { 2275 struct drm_device *dev = encoder->dev; 2276 struct radeon_device *rdev = dev->dev_private; 2277 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2278 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2279 int encoder_mode; 2280 2281 radeon_encoder->pixel_clock = adjusted_mode->clock; 2282 2283 /* need to call this here rather than in prepare() since we need some crtc info */ 2284 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2285 2286 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { 2287 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 2288 atombios_yuv_setup(encoder, true); 2289 else 2290 atombios_yuv_setup(encoder, false); 2291 } 2292 2293 switch (radeon_encoder->encoder_id) { 2294 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2295 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2296 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2297 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2298 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 2299 break; 2300 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2301 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2302 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2303 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2304 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2305 /* handled in dpms */ 2306 break; 2307 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2308 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2309 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2310 atombios_dvo_setup(encoder, ATOM_ENABLE); 2311 break; 2312 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2313 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2314 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2315 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2316 atombios_dac_setup(encoder, ATOM_ENABLE); 2317 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { 2318 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2319 atombios_tv_setup(encoder, ATOM_ENABLE); 2320 else 2321 atombios_tv_setup(encoder, ATOM_DISABLE); 2322 } 2323 break; 2324 } 2325 2326 atombios_apply_encoder_quirks(encoder, adjusted_mode); 2327 2328 encoder_mode = atombios_get_encoder_mode(encoder); 2329 if (connector && (radeon_audio != 0) && 2330 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) || 2331 ENCODER_MODE_IS_DP(encoder_mode))) 2332 radeon_audio_mode_set(encoder, adjusted_mode); 2333 } 2334 2335 static bool 2336 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2337 { 2338 struct drm_device *dev = encoder->dev; 2339 struct radeon_device *rdev = dev->dev_private; 2340 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2341 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2342 2343 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | 2344 ATOM_DEVICE_CV_SUPPORT | 2345 ATOM_DEVICE_CRT_SUPPORT)) { 2346 DAC_LOAD_DETECTION_PS_ALLOCATION args; 2347 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); 2348 uint8_t frev, crev; 2349 2350 memset(&args, 0, sizeof(args)); 2351 2352 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2353 return false; 2354 2355 args.sDacload.ucMisc = 0; 2356 2357 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 2358 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) 2359 args.sDacload.ucDacType = ATOM_DAC_A; 2360 else 2361 args.sDacload.ucDacType = ATOM_DAC_B; 2362 2363 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) 2364 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); 2365 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) 2366 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); 2367 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2368 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); 2369 if (crev >= 3) 2370 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2371 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2372 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); 2373 if (crev >= 3) 2374 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2375 } 2376 2377 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2378 2379 return true; 2380 } else 2381 return false; 2382 } 2383 2384 static enum drm_connector_status 2385 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2386 { 2387 struct drm_device *dev = encoder->dev; 2388 struct radeon_device *rdev = dev->dev_private; 2389 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2390 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2391 uint32_t bios_0_scratch; 2392 2393 if (!atombios_dac_load_detect(encoder, connector)) { 2394 DRM_DEBUG_KMS("detect returned false \n"); 2395 return connector_status_unknown; 2396 } 2397 2398 if (rdev->family >= CHIP_R600) 2399 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2400 else 2401 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 2402 2403 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2404 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2405 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2406 return connector_status_connected; 2407 } 2408 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2409 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2410 return connector_status_connected; 2411 } 2412 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2413 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2414 return connector_status_connected; 2415 } 2416 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2417 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2418 return connector_status_connected; /* CTV */ 2419 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2420 return connector_status_connected; /* STV */ 2421 } 2422 return connector_status_disconnected; 2423 } 2424 2425 static enum drm_connector_status 2426 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2427 { 2428 struct drm_device *dev = encoder->dev; 2429 struct radeon_device *rdev = dev->dev_private; 2430 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2431 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2432 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2433 u32 bios_0_scratch; 2434 2435 if (!ASIC_IS_DCE4(rdev)) 2436 return connector_status_unknown; 2437 2438 if (!ext_encoder) 2439 return connector_status_unknown; 2440 2441 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) 2442 return connector_status_unknown; 2443 2444 /* load detect on the dp bridge */ 2445 atombios_external_encoder_setup(encoder, ext_encoder, 2446 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); 2447 2448 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2449 2450 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2451 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2452 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2453 return connector_status_connected; 2454 } 2455 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2456 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2457 return connector_status_connected; 2458 } 2459 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2460 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2461 return connector_status_connected; 2462 } 2463 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2464 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2465 return connector_status_connected; /* CTV */ 2466 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2467 return connector_status_connected; /* STV */ 2468 } 2469 return connector_status_disconnected; 2470 } 2471 2472 void 2473 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) 2474 { 2475 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2476 2477 if (ext_encoder) 2478 /* ddc_setup on the dp bridge */ 2479 atombios_external_encoder_setup(encoder, ext_encoder, 2480 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); 2481 2482 } 2483 2484 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 2485 { 2486 struct radeon_device *rdev = encoder->dev->dev_private; 2487 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2488 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2489 2490 if ((radeon_encoder->active_device & 2491 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 2492 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 2493 ENCODER_OBJECT_ID_NONE)) { 2494 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2495 if (dig) { 2496 if (dig->dig_encoder >= 0) 2497 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder); 2498 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder, -1); 2499 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) { 2500 if (rdev->family >= CHIP_R600) 2501 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder]; 2502 else 2503 /* RS600/690/740 have only 1 afmt block */ 2504 dig->afmt = rdev->mode_info.afmt[0]; 2505 } 2506 } 2507 } 2508 2509 radeon_atom_output_lock(encoder, true); 2510 2511 if (connector) { 2512 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2513 2514 /* select the clock/data port if it uses a router */ 2515 if (radeon_connector->router.cd_valid) 2516 radeon_router_select_cd_port(radeon_connector); 2517 2518 /* turn eDP panel on for mode set */ 2519 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 2520 atombios_set_edp_panel_power(connector, 2521 ATOM_TRANSMITTER_ACTION_POWER_ON); 2522 } 2523 2524 /* this is needed for the pll/ss setup to work correctly in some cases */ 2525 atombios_set_encoder_crtc_source(encoder); 2526 /* set up the FMT blocks */ 2527 if (ASIC_IS_DCE8(rdev)) 2528 dce8_program_fmt(encoder); 2529 else if (ASIC_IS_DCE4(rdev)) 2530 dce4_program_fmt(encoder); 2531 else if (ASIC_IS_DCE3(rdev)) 2532 dce3_program_fmt(encoder); 2533 else if (ASIC_IS_AVIVO(rdev)) 2534 avivo_program_fmt(encoder); 2535 } 2536 2537 static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 2538 { 2539 /* need to call this here as we need the crtc set up */ 2540 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 2541 radeon_atom_output_lock(encoder, false); 2542 } 2543 2544 static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 2545 { 2546 struct drm_device *dev = encoder->dev; 2547 struct radeon_device *rdev = dev->dev_private; 2548 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2549 struct radeon_encoder_atom_dig *dig; 2550 2551 /* check for pre-DCE3 cards with shared encoders; 2552 * can't really use the links individually, so don't disable 2553 * the encoder if it's in use by another connector 2554 */ 2555 if (!ASIC_IS_DCE3(rdev)) { 2556 struct drm_encoder *other_encoder; 2557 struct radeon_encoder *other_radeon_encoder; 2558 2559 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { 2560 other_radeon_encoder = to_radeon_encoder(other_encoder); 2561 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && 2562 drm_helper_encoder_in_use(other_encoder)) 2563 goto disable_done; 2564 } 2565 } 2566 2567 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2568 2569 switch (radeon_encoder->encoder_id) { 2570 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2571 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2572 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2573 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2574 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); 2575 break; 2576 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2577 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2578 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2579 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2580 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2581 /* handled in dpms */ 2582 break; 2583 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2584 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2585 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2586 atombios_dvo_setup(encoder, ATOM_DISABLE); 2587 break; 2588 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2589 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2590 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2591 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2592 atombios_dac_setup(encoder, ATOM_DISABLE); 2593 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2594 atombios_tv_setup(encoder, ATOM_DISABLE); 2595 break; 2596 } 2597 2598 disable_done: 2599 if (radeon_encoder_is_digital(encoder)) { 2600 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 2601 if (rdev->asic->display.hdmi_enable) 2602 radeon_hdmi_enable(rdev, encoder, false); 2603 } 2604 if (atombios_get_encoder_mode(encoder) != ATOM_ENCODER_MODE_DP_MST) { 2605 dig = radeon_encoder->enc_priv; 2606 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder); 2607 dig->dig_encoder = -1; 2608 radeon_encoder->active_device = 0; 2609 } 2610 } else 2611 radeon_encoder->active_device = 0; 2612 } 2613 2614 /* these are handled by the primary encoders */ 2615 static void radeon_atom_ext_prepare(struct drm_encoder *encoder) 2616 { 2617 2618 } 2619 2620 static void radeon_atom_ext_commit(struct drm_encoder *encoder) 2621 { 2622 2623 } 2624 2625 static void 2626 radeon_atom_ext_mode_set(struct drm_encoder *encoder, 2627 struct drm_display_mode *mode, 2628 struct drm_display_mode *adjusted_mode) 2629 { 2630 2631 } 2632 2633 static void radeon_atom_ext_disable(struct drm_encoder *encoder) 2634 { 2635 2636 } 2637 2638 static void 2639 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) 2640 { 2641 2642 } 2643 2644 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { 2645 .dpms = radeon_atom_ext_dpms, 2646 .prepare = radeon_atom_ext_prepare, 2647 .mode_set = radeon_atom_ext_mode_set, 2648 .commit = radeon_atom_ext_commit, 2649 .disable = radeon_atom_ext_disable, 2650 /* no detect for TMDS/LVDS yet */ 2651 }; 2652 2653 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { 2654 .dpms = radeon_atom_encoder_dpms, 2655 .mode_fixup = radeon_atom_mode_fixup, 2656 .prepare = radeon_atom_encoder_prepare, 2657 .mode_set = radeon_atom_encoder_mode_set, 2658 .commit = radeon_atom_encoder_commit, 2659 .disable = radeon_atom_encoder_disable, 2660 .detect = radeon_atom_dig_detect, 2661 }; 2662 2663 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { 2664 .dpms = radeon_atom_encoder_dpms, 2665 .mode_fixup = radeon_atom_mode_fixup, 2666 .prepare = radeon_atom_encoder_prepare, 2667 .mode_set = radeon_atom_encoder_mode_set, 2668 .commit = radeon_atom_encoder_commit, 2669 .detect = radeon_atom_dac_detect, 2670 }; 2671 2672 void radeon_enc_destroy(struct drm_encoder *encoder) 2673 { 2674 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2675 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2676 radeon_atom_backlight_exit(radeon_encoder); 2677 kfree(radeon_encoder->enc_priv); 2678 drm_encoder_cleanup(encoder); 2679 kfree(radeon_encoder); 2680 } 2681 2682 static const struct drm_encoder_funcs radeon_atom_enc_funcs = { 2683 .destroy = radeon_enc_destroy, 2684 }; 2685 2686 static struct radeon_encoder_atom_dac * 2687 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) 2688 { 2689 struct drm_device *dev = radeon_encoder->base.dev; 2690 struct radeon_device *rdev = dev->dev_private; 2691 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); 2692 2693 if (!dac) 2694 return NULL; 2695 2696 dac->tv_std = radeon_atombios_get_tv_info(rdev); 2697 return dac; 2698 } 2699 2700 static struct radeon_encoder_atom_dig * 2701 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) 2702 { 2703 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 2704 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 2705 2706 if (!dig) 2707 return NULL; 2708 2709 /* coherent mode by default */ 2710 dig->coherent_mode = true; 2711 dig->dig_encoder = -1; 2712 2713 if (encoder_enum == 2) 2714 dig->linkb = true; 2715 else 2716 dig->linkb = false; 2717 2718 return dig; 2719 } 2720 2721 void 2722 radeon_add_atom_encoder(struct drm_device *dev, 2723 uint32_t encoder_enum, 2724 uint32_t supported_device, 2725 u16 caps) 2726 { 2727 struct radeon_device *rdev = dev->dev_private; 2728 struct drm_encoder *encoder; 2729 struct radeon_encoder *radeon_encoder; 2730 2731 /* see if we already added it */ 2732 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2733 radeon_encoder = to_radeon_encoder(encoder); 2734 if (radeon_encoder->encoder_enum == encoder_enum) { 2735 radeon_encoder->devices |= supported_device; 2736 return; 2737 } 2738 2739 } 2740 2741 /* add a new one */ 2742 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); 2743 if (!radeon_encoder) 2744 return; 2745 2746 encoder = &radeon_encoder->base; 2747 switch (rdev->num_crtc) { 2748 case 1: 2749 encoder->possible_crtcs = 0x1; 2750 break; 2751 case 2: 2752 default: 2753 encoder->possible_crtcs = 0x3; 2754 break; 2755 case 4: 2756 encoder->possible_crtcs = 0xf; 2757 break; 2758 case 6: 2759 encoder->possible_crtcs = 0x3f; 2760 break; 2761 } 2762 2763 radeon_encoder->enc_priv = NULL; 2764 2765 radeon_encoder->encoder_enum = encoder_enum; 2766 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 2767 radeon_encoder->devices = supported_device; 2768 radeon_encoder->rmx_type = RMX_OFF; 2769 radeon_encoder->underscan_type = UNDERSCAN_OFF; 2770 radeon_encoder->is_ext_encoder = false; 2771 radeon_encoder->caps = caps; 2772 2773 switch (radeon_encoder->encoder_id) { 2774 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2775 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2776 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2777 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2778 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2779 radeon_encoder->rmx_type = RMX_FULL; 2780 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2781 DRM_MODE_ENCODER_LVDS, NULL); 2782 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2783 } else { 2784 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2785 DRM_MODE_ENCODER_TMDS, NULL); 2786 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2787 } 2788 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2789 break; 2790 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2791 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2792 DRM_MODE_ENCODER_DAC, NULL); 2793 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2794 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2795 break; 2796 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2797 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2798 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2799 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2800 DRM_MODE_ENCODER_TVDAC, NULL); 2801 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2802 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2803 break; 2804 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2805 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2806 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2807 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2808 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2809 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2810 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2811 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2812 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2813 radeon_encoder->rmx_type = RMX_FULL; 2814 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2815 DRM_MODE_ENCODER_LVDS, NULL); 2816 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2817 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 2818 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2819 DRM_MODE_ENCODER_DAC, NULL); 2820 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2821 } else { 2822 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2823 DRM_MODE_ENCODER_TMDS, NULL); 2824 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2825 } 2826 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2827 break; 2828 case ENCODER_OBJECT_ID_SI170B: 2829 case ENCODER_OBJECT_ID_CH7303: 2830 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 2831 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 2832 case ENCODER_OBJECT_ID_TITFP513: 2833 case ENCODER_OBJECT_ID_VT1623: 2834 case ENCODER_OBJECT_ID_HDMI_SI1930: 2835 case ENCODER_OBJECT_ID_TRAVIS: 2836 case ENCODER_OBJECT_ID_NUTMEG: 2837 /* these are handled by the primary encoders */ 2838 radeon_encoder->is_ext_encoder = true; 2839 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2840 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2841 DRM_MODE_ENCODER_LVDS, NULL); 2842 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 2843 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2844 DRM_MODE_ENCODER_DAC, NULL); 2845 else 2846 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2847 DRM_MODE_ENCODER_TMDS, NULL); 2848 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); 2849 break; 2850 } 2851 } 2852