1 /* 2 * Copyright 2007-11 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_crtc_helper.h> 28 #include <drm/radeon_drm.h> 29 #include "radeon.h" 30 #include "atom.h" 31 #include <linux/backlight.h> 32 33 extern int atom_debug; 34 35 static u8 36 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev) 37 { 38 u8 backlight_level; 39 u32 bios_2_scratch; 40 41 if (rdev->family >= CHIP_R600) 42 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 43 else 44 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 45 46 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >> 47 ATOM_S2_CURRENT_BL_LEVEL_SHIFT); 48 49 return backlight_level; 50 } 51 52 static void 53 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev, 54 u8 backlight_level) 55 { 56 u32 bios_2_scratch; 57 58 if (rdev->family >= CHIP_R600) 59 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 60 else 61 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 62 63 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; 64 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) & 65 ATOM_S2_CURRENT_BL_LEVEL_MASK); 66 67 if (rdev->family >= CHIP_R600) 68 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 69 else 70 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 71 } 72 73 u8 74 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder) 75 { 76 struct drm_device *dev = radeon_encoder->base.dev; 77 struct radeon_device *rdev = dev->dev_private; 78 79 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 80 return 0; 81 82 return radeon_atom_get_backlight_level_from_reg(rdev); 83 } 84 85 void 86 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) 87 { 88 struct drm_encoder *encoder = &radeon_encoder->base; 89 struct drm_device *dev = radeon_encoder->base.dev; 90 struct radeon_device *rdev = dev->dev_private; 91 struct radeon_encoder_atom_dig *dig; 92 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 93 int index; 94 95 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 96 return; 97 98 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 99 radeon_encoder->enc_priv) { 100 dig = radeon_encoder->enc_priv; 101 dig->backlight_level = level; 102 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level); 103 104 switch (radeon_encoder->encoder_id) { 105 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 106 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 107 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 108 if (dig->backlight_level == 0) { 109 args.ucAction = ATOM_LCD_BLOFF; 110 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 111 } else { 112 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL; 113 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 114 args.ucAction = ATOM_LCD_BLON; 115 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 116 } 117 break; 118 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 119 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 120 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 122 if (dig->backlight_level == 0) 123 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 124 else { 125 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0); 126 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 127 } 128 break; 129 default: 130 break; 131 } 132 } 133 } 134 135 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 136 137 static u8 radeon_atom_bl_level(struct backlight_device *bd) 138 { 139 u8 level; 140 141 /* Convert brightness to hardware level */ 142 if (bd->props.brightness < 0) 143 level = 0; 144 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) 145 level = RADEON_MAX_BL_LEVEL; 146 else 147 level = bd->props.brightness; 148 149 return level; 150 } 151 152 static int radeon_atom_backlight_update_status(struct backlight_device *bd) 153 { 154 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 155 struct radeon_encoder *radeon_encoder = pdata->encoder; 156 157 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd)); 158 159 return 0; 160 } 161 162 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd) 163 { 164 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 165 struct radeon_encoder *radeon_encoder = pdata->encoder; 166 struct drm_device *dev = radeon_encoder->base.dev; 167 struct radeon_device *rdev = dev->dev_private; 168 169 return radeon_atom_get_backlight_level_from_reg(rdev); 170 } 171 172 static const struct backlight_ops radeon_atom_backlight_ops = { 173 .get_brightness = radeon_atom_backlight_get_brightness, 174 .update_status = radeon_atom_backlight_update_status, 175 }; 176 177 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 178 struct drm_connector *drm_connector) 179 { 180 struct drm_device *dev = radeon_encoder->base.dev; 181 struct radeon_device *rdev = dev->dev_private; 182 struct backlight_device *bd; 183 struct backlight_properties props; 184 struct radeon_backlight_privdata *pdata; 185 struct radeon_encoder_atom_dig *dig; 186 u8 backlight_level; 187 char bl_name[16]; 188 189 /* Mac laptops with multiple GPUs use the gmux driver for backlight 190 * so don't register a backlight device 191 */ 192 if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && 193 (rdev->pdev->device == 0x6741)) 194 return; 195 196 if (!radeon_encoder->enc_priv) 197 return; 198 199 if (!rdev->is_atom_bios) 200 return; 201 202 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 203 return; 204 205 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL); 206 if (!pdata) { 207 DRM_ERROR("Memory allocation failed\n"); 208 goto error; 209 } 210 211 memset(&props, 0, sizeof(props)); 212 props.max_brightness = RADEON_MAX_BL_LEVEL; 213 props.type = BACKLIGHT_RAW; 214 snprintf(bl_name, sizeof(bl_name), 215 "radeon_bl%d", dev->primary->index); 216 bd = backlight_device_register(bl_name, drm_connector->kdev, 217 pdata, &radeon_atom_backlight_ops, &props); 218 if (IS_ERR(bd)) { 219 DRM_ERROR("Backlight registration failed\n"); 220 goto error; 221 } 222 223 pdata->encoder = radeon_encoder; 224 225 backlight_level = radeon_atom_get_backlight_level_from_reg(rdev); 226 227 dig = radeon_encoder->enc_priv; 228 dig->bl_dev = bd; 229 230 bd->props.brightness = radeon_atom_backlight_get_brightness(bd); 231 bd->props.power = FB_BLANK_UNBLANK; 232 backlight_update_status(bd); 233 234 DRM_INFO("radeon atom DIG backlight initialized\n"); 235 236 return; 237 238 error: 239 kfree(pdata); 240 return; 241 } 242 243 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder) 244 { 245 struct drm_device *dev = radeon_encoder->base.dev; 246 struct radeon_device *rdev = dev->dev_private; 247 struct backlight_device *bd = NULL; 248 struct radeon_encoder_atom_dig *dig; 249 250 if (!radeon_encoder->enc_priv) 251 return; 252 253 if (!rdev->is_atom_bios) 254 return; 255 256 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 257 return; 258 259 dig = radeon_encoder->enc_priv; 260 bd = dig->bl_dev; 261 dig->bl_dev = NULL; 262 263 if (bd) { 264 struct radeon_legacy_backlight_privdata *pdata; 265 266 pdata = bl_get_data(bd); 267 backlight_device_unregister(bd); 268 kfree(pdata); 269 270 DRM_INFO("radeon atom LVDS backlight unloaded\n"); 271 } 272 } 273 274 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ 275 276 void radeon_atom_backlight_init(struct radeon_encoder *encoder) 277 { 278 } 279 280 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder) 281 { 282 } 283 284 #endif 285 286 /* evil but including atombios.h is much worse */ 287 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 288 struct drm_display_mode *mode); 289 290 291 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder) 292 { 293 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 294 switch (radeon_encoder->encoder_id) { 295 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 296 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 297 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 298 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 299 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 300 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 301 case ENCODER_OBJECT_ID_INTERNAL_DDI: 302 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 303 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 304 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 305 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 306 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 307 return true; 308 default: 309 return false; 310 } 311 } 312 313 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 314 const struct drm_display_mode *mode, 315 struct drm_display_mode *adjusted_mode) 316 { 317 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 318 struct drm_device *dev = encoder->dev; 319 struct radeon_device *rdev = dev->dev_private; 320 321 /* set the active encoder to connector routing */ 322 radeon_encoder_set_active_device(encoder); 323 drm_mode_set_crtcinfo(adjusted_mode, 0); 324 325 /* hw bug */ 326 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) 327 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) 328 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; 329 330 /* get the native mode for LVDS */ 331 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) 332 radeon_panel_mode_fixup(encoder, adjusted_mode); 333 334 /* get the native mode for TV */ 335 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 336 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 337 if (tv_dac) { 338 if (tv_dac->tv_std == TV_STD_NTSC || 339 tv_dac->tv_std == TV_STD_NTSC_J || 340 tv_dac->tv_std == TV_STD_PAL_M) 341 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); 342 else 343 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); 344 } 345 } 346 347 if (ASIC_IS_DCE3(rdev) && 348 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 349 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) { 350 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 351 radeon_dp_set_link_config(connector, adjusted_mode); 352 } 353 354 return true; 355 } 356 357 static void 358 atombios_dac_setup(struct drm_encoder *encoder, int action) 359 { 360 struct drm_device *dev = encoder->dev; 361 struct radeon_device *rdev = dev->dev_private; 362 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 363 DAC_ENCODER_CONTROL_PS_ALLOCATION args; 364 int index = 0; 365 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 366 367 memset(&args, 0, sizeof(args)); 368 369 switch (radeon_encoder->encoder_id) { 370 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 371 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 372 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); 373 break; 374 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 375 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 376 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); 377 break; 378 } 379 380 args.ucAction = action; 381 382 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) 383 args.ucDacStandard = ATOM_DAC1_PS2; 384 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 385 args.ucDacStandard = ATOM_DAC1_CV; 386 else { 387 switch (dac_info->tv_std) { 388 case TV_STD_PAL: 389 case TV_STD_PAL_M: 390 case TV_STD_SCART_PAL: 391 case TV_STD_SECAM: 392 case TV_STD_PAL_CN: 393 args.ucDacStandard = ATOM_DAC1_PAL; 394 break; 395 case TV_STD_NTSC: 396 case TV_STD_NTSC_J: 397 case TV_STD_PAL_60: 398 default: 399 args.ucDacStandard = ATOM_DAC1_NTSC; 400 break; 401 } 402 } 403 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 404 405 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 406 407 } 408 409 static void 410 atombios_tv_setup(struct drm_encoder *encoder, int action) 411 { 412 struct drm_device *dev = encoder->dev; 413 struct radeon_device *rdev = dev->dev_private; 414 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 415 TV_ENCODER_CONTROL_PS_ALLOCATION args; 416 int index = 0; 417 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 418 419 memset(&args, 0, sizeof(args)); 420 421 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); 422 423 args.sTVEncoder.ucAction = action; 424 425 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 426 args.sTVEncoder.ucTvStandard = ATOM_TV_CV; 427 else { 428 switch (dac_info->tv_std) { 429 case TV_STD_NTSC: 430 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 431 break; 432 case TV_STD_PAL: 433 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; 434 break; 435 case TV_STD_PAL_M: 436 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; 437 break; 438 case TV_STD_PAL_60: 439 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; 440 break; 441 case TV_STD_NTSC_J: 442 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; 443 break; 444 case TV_STD_SCART_PAL: 445 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ 446 break; 447 case TV_STD_SECAM: 448 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; 449 break; 450 case TV_STD_PAL_CN: 451 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; 452 break; 453 default: 454 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 455 break; 456 } 457 } 458 459 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 460 461 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 462 463 } 464 465 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) 466 { 467 int bpc = 8; 468 469 if (encoder->crtc) { 470 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 471 bpc = radeon_crtc->bpc; 472 } 473 474 switch (bpc) { 475 case 0: 476 return PANEL_BPC_UNDEFINE; 477 case 6: 478 return PANEL_6BIT_PER_COLOR; 479 case 8: 480 default: 481 return PANEL_8BIT_PER_COLOR; 482 case 10: 483 return PANEL_10BIT_PER_COLOR; 484 case 12: 485 return PANEL_12BIT_PER_COLOR; 486 case 16: 487 return PANEL_16BIT_PER_COLOR; 488 } 489 } 490 491 union dvo_encoder_control { 492 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; 493 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; 494 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; 495 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4; 496 }; 497 498 void 499 atombios_dvo_setup(struct drm_encoder *encoder, int action) 500 { 501 struct drm_device *dev = encoder->dev; 502 struct radeon_device *rdev = dev->dev_private; 503 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 504 union dvo_encoder_control args; 505 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 506 uint8_t frev, crev; 507 508 memset(&args, 0, sizeof(args)); 509 510 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 511 return; 512 513 /* some R4xx chips have the wrong frev */ 514 if (rdev->family <= CHIP_RV410) 515 frev = 1; 516 517 switch (frev) { 518 case 1: 519 switch (crev) { 520 case 1: 521 /* R4xx, R5xx */ 522 args.ext_tmds.sXTmdsEncoder.ucEnable = action; 523 524 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 525 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; 526 527 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; 528 break; 529 case 2: 530 /* RS600/690/740 */ 531 args.dvo.sDVOEncoder.ucAction = action; 532 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 533 /* DFP1, CRT1, TV1 depending on the type of port */ 534 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; 535 536 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 537 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; 538 break; 539 case 3: 540 /* R6xx */ 541 args.dvo_v3.ucAction = action; 542 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 543 args.dvo_v3.ucDVOConfig = 0; /* XXX */ 544 break; 545 case 4: 546 /* DCE8 */ 547 args.dvo_v4.ucAction = action; 548 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 549 args.dvo_v4.ucDVOConfig = 0; /* XXX */ 550 args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 551 break; 552 default: 553 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 554 break; 555 } 556 break; 557 default: 558 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 559 break; 560 } 561 562 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 563 } 564 565 union lvds_encoder_control { 566 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; 567 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; 568 }; 569 570 void 571 atombios_digital_setup(struct drm_encoder *encoder, int action) 572 { 573 struct drm_device *dev = encoder->dev; 574 struct radeon_device *rdev = dev->dev_private; 575 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 576 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 577 union lvds_encoder_control args; 578 int index = 0; 579 int hdmi_detected = 0; 580 uint8_t frev, crev; 581 582 if (!dig) 583 return; 584 585 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 586 hdmi_detected = 1; 587 588 memset(&args, 0, sizeof(args)); 589 590 switch (radeon_encoder->encoder_id) { 591 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 592 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 593 break; 594 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 595 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 596 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); 597 break; 598 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 599 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 600 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 601 else 602 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); 603 break; 604 } 605 606 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 607 return; 608 609 switch (frev) { 610 case 1: 611 case 2: 612 switch (crev) { 613 case 1: 614 args.v1.ucMisc = 0; 615 args.v1.ucAction = action; 616 if (hdmi_detected) 617 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 618 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 619 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 620 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 621 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 622 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 623 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 624 } else { 625 if (dig->linkb) 626 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 627 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 628 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 629 /*if (pScrn->rgbBits == 8) */ 630 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 631 } 632 break; 633 case 2: 634 case 3: 635 args.v2.ucMisc = 0; 636 args.v2.ucAction = action; 637 if (crev == 3) { 638 if (dig->coherent_mode) 639 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; 640 } 641 if (hdmi_detected) 642 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 643 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 644 args.v2.ucTruncate = 0; 645 args.v2.ucSpatial = 0; 646 args.v2.ucTemporal = 0; 647 args.v2.ucFRC = 0; 648 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 649 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 650 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 651 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { 652 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 653 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 654 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 655 } 656 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { 657 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 658 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 659 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 660 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) 661 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 662 } 663 } else { 664 if (dig->linkb) 665 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 666 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 667 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 668 } 669 break; 670 default: 671 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 672 break; 673 } 674 break; 675 default: 676 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 677 break; 678 } 679 680 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 681 } 682 683 int 684 atombios_get_encoder_mode(struct drm_encoder *encoder) 685 { 686 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 687 struct drm_connector *connector; 688 struct radeon_connector *radeon_connector; 689 struct radeon_connector_atom_dig *dig_connector; 690 691 /* dp bridges are always DP */ 692 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) 693 return ATOM_ENCODER_MODE_DP; 694 695 /* DVO is always DVO */ 696 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) || 697 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) 698 return ATOM_ENCODER_MODE_DVO; 699 700 connector = radeon_get_connector_for_encoder(encoder); 701 /* if we don't have an active device yet, just use one of 702 * the connectors tied to the encoder. 703 */ 704 if (!connector) 705 connector = radeon_get_connector_for_encoder_init(encoder); 706 radeon_connector = to_radeon_connector(connector); 707 708 switch (connector->connector_type) { 709 case DRM_MODE_CONNECTOR_DVII: 710 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 711 if (radeon_audio != 0) { 712 if (radeon_connector->use_digital && 713 (radeon_connector->audio == RADEON_AUDIO_ENABLE)) 714 return ATOM_ENCODER_MODE_HDMI; 715 else if (drm_detect_hdmi_monitor(radeon_connector->edid) && 716 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 717 return ATOM_ENCODER_MODE_HDMI; 718 else if (radeon_connector->use_digital) 719 return ATOM_ENCODER_MODE_DVI; 720 else 721 return ATOM_ENCODER_MODE_CRT; 722 } else if (radeon_connector->use_digital) { 723 return ATOM_ENCODER_MODE_DVI; 724 } else { 725 return ATOM_ENCODER_MODE_CRT; 726 } 727 break; 728 case DRM_MODE_CONNECTOR_DVID: 729 case DRM_MODE_CONNECTOR_HDMIA: 730 default: 731 if (radeon_audio != 0) { 732 if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 733 return ATOM_ENCODER_MODE_HDMI; 734 else if (drm_detect_hdmi_monitor(radeon_connector->edid) && 735 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 736 return ATOM_ENCODER_MODE_HDMI; 737 else 738 return ATOM_ENCODER_MODE_DVI; 739 } else { 740 return ATOM_ENCODER_MODE_DVI; 741 } 742 break; 743 case DRM_MODE_CONNECTOR_LVDS: 744 return ATOM_ENCODER_MODE_LVDS; 745 break; 746 case DRM_MODE_CONNECTOR_DisplayPort: 747 dig_connector = radeon_connector->con_priv; 748 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 749 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 750 return ATOM_ENCODER_MODE_DP; 751 } else if (radeon_audio != 0) { 752 if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 753 return ATOM_ENCODER_MODE_HDMI; 754 else if (drm_detect_hdmi_monitor(radeon_connector->edid) && 755 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 756 return ATOM_ENCODER_MODE_HDMI; 757 else 758 return ATOM_ENCODER_MODE_DVI; 759 } else { 760 return ATOM_ENCODER_MODE_DVI; 761 } 762 break; 763 case DRM_MODE_CONNECTOR_eDP: 764 return ATOM_ENCODER_MODE_DP; 765 case DRM_MODE_CONNECTOR_DVIA: 766 case DRM_MODE_CONNECTOR_VGA: 767 return ATOM_ENCODER_MODE_CRT; 768 break; 769 case DRM_MODE_CONNECTOR_Composite: 770 case DRM_MODE_CONNECTOR_SVIDEO: 771 case DRM_MODE_CONNECTOR_9PinDIN: 772 /* fix me */ 773 return ATOM_ENCODER_MODE_TV; 774 /*return ATOM_ENCODER_MODE_CV;*/ 775 break; 776 } 777 } 778 779 /* 780 * DIG Encoder/Transmitter Setup 781 * 782 * DCE 3.0/3.1 783 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. 784 * Supports up to 3 digital outputs 785 * - 2 DIG encoder blocks. 786 * DIG1 can drive UNIPHY link A or link B 787 * DIG2 can drive UNIPHY link B or LVTMA 788 * 789 * DCE 3.2 790 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). 791 * Supports up to 5 digital outputs 792 * - 2 DIG encoder blocks. 793 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 794 * 795 * DCE 4.0/5.0/6.0 796 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 797 * Supports up to 6 digital outputs 798 * - 6 DIG encoder blocks. 799 * - DIG to PHY mapping is hardcoded 800 * DIG1 drives UNIPHY0 link A, A+B 801 * DIG2 drives UNIPHY0 link B 802 * DIG3 drives UNIPHY1 link A, A+B 803 * DIG4 drives UNIPHY1 link B 804 * DIG5 drives UNIPHY2 link A, A+B 805 * DIG6 drives UNIPHY2 link B 806 * 807 * DCE 4.1 808 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 809 * Supports up to 6 digital outputs 810 * - 2 DIG encoder blocks. 811 * llano 812 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 813 * ontario 814 * DIG1 drives UNIPHY0/1/2 link A 815 * DIG2 drives UNIPHY0/1/2 link B 816 * 817 * Routing 818 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) 819 * Examples: 820 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI 821 * crtc1 -> dig1 -> UNIPHY0 link B -> DP 822 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS 823 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI 824 */ 825 826 union dig_encoder_control { 827 DIG_ENCODER_CONTROL_PS_ALLOCATION v1; 828 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; 829 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; 830 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; 831 }; 832 833 void 834 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) 835 { 836 struct drm_device *dev = encoder->dev; 837 struct radeon_device *rdev = dev->dev_private; 838 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 839 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 840 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 841 union dig_encoder_control args; 842 int index = 0; 843 uint8_t frev, crev; 844 int dp_clock = 0; 845 int dp_lane_count = 0; 846 int hpd_id = RADEON_HPD_NONE; 847 848 if (connector) { 849 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 850 struct radeon_connector_atom_dig *dig_connector = 851 radeon_connector->con_priv; 852 853 dp_clock = dig_connector->dp_clock; 854 dp_lane_count = dig_connector->dp_lane_count; 855 hpd_id = radeon_connector->hpd.hpd; 856 } 857 858 /* no dig encoder assigned */ 859 if (dig->dig_encoder == -1) 860 return; 861 862 memset(&args, 0, sizeof(args)); 863 864 if (ASIC_IS_DCE4(rdev)) 865 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); 866 else { 867 if (dig->dig_encoder) 868 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 869 else 870 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 871 } 872 873 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 874 return; 875 876 switch (frev) { 877 case 1: 878 switch (crev) { 879 case 1: 880 args.v1.ucAction = action; 881 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 882 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 883 args.v3.ucPanelMode = panel_mode; 884 else 885 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 886 887 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 888 args.v1.ucLaneNum = dp_lane_count; 889 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 890 args.v1.ucLaneNum = 8; 891 else 892 args.v1.ucLaneNum = 4; 893 894 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) 895 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 896 switch (radeon_encoder->encoder_id) { 897 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 898 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; 899 break; 900 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 901 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 902 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; 903 break; 904 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 905 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; 906 break; 907 } 908 if (dig->linkb) 909 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 910 else 911 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 912 break; 913 case 2: 914 case 3: 915 args.v3.ucAction = action; 916 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 917 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 918 args.v3.ucPanelMode = panel_mode; 919 else 920 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); 921 922 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) 923 args.v3.ucLaneNum = dp_lane_count; 924 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 925 args.v3.ucLaneNum = 8; 926 else 927 args.v3.ucLaneNum = 4; 928 929 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000)) 930 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 931 args.v3.acConfig.ucDigSel = dig->dig_encoder; 932 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder); 933 break; 934 case 4: 935 args.v4.ucAction = action; 936 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 937 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 938 args.v4.ucPanelMode = panel_mode; 939 else 940 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder); 941 942 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) 943 args.v4.ucLaneNum = dp_lane_count; 944 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 945 args.v4.ucLaneNum = 8; 946 else 947 args.v4.ucLaneNum = 4; 948 949 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) { 950 if (dp_clock == 540000) 951 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; 952 else if (dp_clock == 324000) 953 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ; 954 else if (dp_clock == 270000) 955 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; 956 else 957 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ; 958 } 959 args.v4.acConfig.ucDigSel = dig->dig_encoder; 960 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 961 if (hpd_id == RADEON_HPD_NONE) 962 args.v4.ucHPD_ID = 0; 963 else 964 args.v4.ucHPD_ID = hpd_id + 1; 965 break; 966 default: 967 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 968 break; 969 } 970 break; 971 default: 972 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 973 break; 974 } 975 976 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 977 978 } 979 980 union dig_transmitter_control { 981 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; 982 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; 983 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; 984 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; 985 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; 986 }; 987 988 void 989 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) 990 { 991 struct drm_device *dev = encoder->dev; 992 struct radeon_device *rdev = dev->dev_private; 993 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 994 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 995 struct drm_connector *connector; 996 union dig_transmitter_control args; 997 int index = 0; 998 uint8_t frev, crev; 999 bool is_dp = false; 1000 int pll_id = 0; 1001 int dp_clock = 0; 1002 int dp_lane_count = 0; 1003 int connector_object_id = 0; 1004 int igp_lane_info = 0; 1005 int dig_encoder = dig->dig_encoder; 1006 int hpd_id = RADEON_HPD_NONE; 1007 1008 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1009 connector = radeon_get_connector_for_encoder_init(encoder); 1010 /* just needed to avoid bailing in the encoder check. the encoder 1011 * isn't used for init 1012 */ 1013 dig_encoder = 0; 1014 } else 1015 connector = radeon_get_connector_for_encoder(encoder); 1016 1017 if (connector) { 1018 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1019 struct radeon_connector_atom_dig *dig_connector = 1020 radeon_connector->con_priv; 1021 1022 hpd_id = radeon_connector->hpd.hpd; 1023 dp_clock = dig_connector->dp_clock; 1024 dp_lane_count = dig_connector->dp_lane_count; 1025 connector_object_id = 1026 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1027 igp_lane_info = dig_connector->igp_lane_info; 1028 } 1029 1030 if (encoder->crtc) { 1031 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1032 pll_id = radeon_crtc->pll_id; 1033 } 1034 1035 /* no dig encoder assigned */ 1036 if (dig_encoder == -1) 1037 return; 1038 1039 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))) 1040 is_dp = true; 1041 1042 memset(&args, 0, sizeof(args)); 1043 1044 switch (radeon_encoder->encoder_id) { 1045 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1046 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1047 break; 1048 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1049 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1050 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1051 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1052 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1053 break; 1054 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1055 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); 1056 break; 1057 } 1058 1059 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1060 return; 1061 1062 switch (frev) { 1063 case 1: 1064 switch (crev) { 1065 case 1: 1066 args.v1.ucAction = action; 1067 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1068 args.v1.usInitInfo = cpu_to_le16(connector_object_id); 1069 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1070 args.v1.asMode.ucLaneSel = lane_num; 1071 args.v1.asMode.ucLaneSet = lane_set; 1072 } else { 1073 if (is_dp) 1074 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10); 1075 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1076 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1077 else 1078 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1079 } 1080 1081 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 1082 1083 if (dig_encoder) 1084 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 1085 else 1086 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; 1087 1088 if ((rdev->flags & RADEON_IS_IGP) && 1089 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { 1090 if (is_dp || 1091 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) { 1092 if (igp_lane_info & 0x1) 1093 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 1094 else if (igp_lane_info & 0x2) 1095 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; 1096 else if (igp_lane_info & 0x4) 1097 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; 1098 else if (igp_lane_info & 0x8) 1099 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; 1100 } else { 1101 if (igp_lane_info & 0x3) 1102 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; 1103 else if (igp_lane_info & 0xc) 1104 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; 1105 } 1106 } 1107 1108 if (dig->linkb) 1109 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; 1110 else 1111 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; 1112 1113 if (is_dp) 1114 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1115 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1116 if (dig->coherent_mode) 1117 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1118 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1119 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; 1120 } 1121 break; 1122 case 2: 1123 args.v2.ucAction = action; 1124 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1125 args.v2.usInitInfo = cpu_to_le16(connector_object_id); 1126 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1127 args.v2.asMode.ucLaneSel = lane_num; 1128 args.v2.asMode.ucLaneSet = lane_set; 1129 } else { 1130 if (is_dp) 1131 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10); 1132 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1133 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1134 else 1135 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1136 } 1137 1138 args.v2.acConfig.ucEncoderSel = dig_encoder; 1139 if (dig->linkb) 1140 args.v2.acConfig.ucLinkSel = 1; 1141 1142 switch (radeon_encoder->encoder_id) { 1143 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1144 args.v2.acConfig.ucTransmitterSel = 0; 1145 break; 1146 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1147 args.v2.acConfig.ucTransmitterSel = 1; 1148 break; 1149 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1150 args.v2.acConfig.ucTransmitterSel = 2; 1151 break; 1152 } 1153 1154 if (is_dp) { 1155 args.v2.acConfig.fCoherentMode = 1; 1156 args.v2.acConfig.fDPConnector = 1; 1157 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1158 if (dig->coherent_mode) 1159 args.v2.acConfig.fCoherentMode = 1; 1160 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1161 args.v2.acConfig.fDualLinkConnector = 1; 1162 } 1163 break; 1164 case 3: 1165 args.v3.ucAction = action; 1166 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1167 args.v3.usInitInfo = cpu_to_le16(connector_object_id); 1168 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1169 args.v3.asMode.ucLaneSel = lane_num; 1170 args.v3.asMode.ucLaneSet = lane_set; 1171 } else { 1172 if (is_dp) 1173 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10); 1174 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1175 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1176 else 1177 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1178 } 1179 1180 if (is_dp) 1181 args.v3.ucLaneNum = dp_lane_count; 1182 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1183 args.v3.ucLaneNum = 8; 1184 else 1185 args.v3.ucLaneNum = 4; 1186 1187 if (dig->linkb) 1188 args.v3.acConfig.ucLinkSel = 1; 1189 if (dig_encoder & 1) 1190 args.v3.acConfig.ucEncoderSel = 1; 1191 1192 /* Select the PLL for the PHY 1193 * DP PHY should be clocked from external src if there is 1194 * one. 1195 */ 1196 /* On DCE4, if there is an external clock, it generates the DP ref clock */ 1197 if (is_dp && rdev->clock.dp_extclk) 1198 args.v3.acConfig.ucRefClkSource = 2; /* external src */ 1199 else 1200 args.v3.acConfig.ucRefClkSource = pll_id; 1201 1202 switch (radeon_encoder->encoder_id) { 1203 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1204 args.v3.acConfig.ucTransmitterSel = 0; 1205 break; 1206 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1207 args.v3.acConfig.ucTransmitterSel = 1; 1208 break; 1209 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1210 args.v3.acConfig.ucTransmitterSel = 2; 1211 break; 1212 } 1213 1214 if (is_dp) 1215 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1216 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1217 if (dig->coherent_mode) 1218 args.v3.acConfig.fCoherentMode = 1; 1219 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1220 args.v3.acConfig.fDualLinkConnector = 1; 1221 } 1222 break; 1223 case 4: 1224 args.v4.ucAction = action; 1225 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1226 args.v4.usInitInfo = cpu_to_le16(connector_object_id); 1227 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1228 args.v4.asMode.ucLaneSel = lane_num; 1229 args.v4.asMode.ucLaneSet = lane_set; 1230 } else { 1231 if (is_dp) 1232 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10); 1233 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1234 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1235 else 1236 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1237 } 1238 1239 if (is_dp) 1240 args.v4.ucLaneNum = dp_lane_count; 1241 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1242 args.v4.ucLaneNum = 8; 1243 else 1244 args.v4.ucLaneNum = 4; 1245 1246 if (dig->linkb) 1247 args.v4.acConfig.ucLinkSel = 1; 1248 if (dig_encoder & 1) 1249 args.v4.acConfig.ucEncoderSel = 1; 1250 1251 /* Select the PLL for the PHY 1252 * DP PHY should be clocked from external src if there is 1253 * one. 1254 */ 1255 /* On DCE5 DCPLL usually generates the DP ref clock */ 1256 if (is_dp) { 1257 if (rdev->clock.dp_extclk) 1258 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; 1259 else 1260 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; 1261 } else 1262 args.v4.acConfig.ucRefClkSource = pll_id; 1263 1264 switch (radeon_encoder->encoder_id) { 1265 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1266 args.v4.acConfig.ucTransmitterSel = 0; 1267 break; 1268 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1269 args.v4.acConfig.ucTransmitterSel = 1; 1270 break; 1271 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1272 args.v4.acConfig.ucTransmitterSel = 2; 1273 break; 1274 } 1275 1276 if (is_dp) 1277 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1278 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1279 if (dig->coherent_mode) 1280 args.v4.acConfig.fCoherentMode = 1; 1281 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1282 args.v4.acConfig.fDualLinkConnector = 1; 1283 } 1284 break; 1285 case 5: 1286 args.v5.ucAction = action; 1287 if (is_dp) 1288 args.v5.usSymClock = cpu_to_le16(dp_clock / 10); 1289 else 1290 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1291 1292 switch (radeon_encoder->encoder_id) { 1293 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1294 if (dig->linkb) 1295 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; 1296 else 1297 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; 1298 break; 1299 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1300 if (dig->linkb) 1301 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; 1302 else 1303 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; 1304 break; 1305 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1306 if (dig->linkb) 1307 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; 1308 else 1309 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; 1310 break; 1311 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1312 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG; 1313 break; 1314 } 1315 if (is_dp) 1316 args.v5.ucLaneNum = dp_lane_count; 1317 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1318 args.v5.ucLaneNum = 8; 1319 else 1320 args.v5.ucLaneNum = 4; 1321 args.v5.ucConnObjId = connector_object_id; 1322 args.v5.ucDigMode = atombios_get_encoder_mode(encoder); 1323 1324 if (is_dp && rdev->clock.dp_extclk) 1325 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK; 1326 else 1327 args.v5.asConfig.ucPhyClkSrcId = pll_id; 1328 1329 if (is_dp) 1330 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ 1331 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1332 if (dig->coherent_mode) 1333 args.v5.asConfig.ucCoherentMode = 1; 1334 } 1335 if (hpd_id == RADEON_HPD_NONE) 1336 args.v5.asConfig.ucHPDSel = 0; 1337 else 1338 args.v5.asConfig.ucHPDSel = hpd_id + 1; 1339 args.v5.ucDigEncoderSel = 1 << dig_encoder; 1340 args.v5.ucDPLaneSet = lane_set; 1341 break; 1342 default: 1343 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1344 break; 1345 } 1346 break; 1347 default: 1348 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1349 break; 1350 } 1351 1352 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1353 } 1354 1355 bool 1356 atombios_set_edp_panel_power(struct drm_connector *connector, int action) 1357 { 1358 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1359 struct drm_device *dev = radeon_connector->base.dev; 1360 struct radeon_device *rdev = dev->dev_private; 1361 union dig_transmitter_control args; 1362 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1363 uint8_t frev, crev; 1364 1365 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) 1366 goto done; 1367 1368 if (!ASIC_IS_DCE4(rdev)) 1369 goto done; 1370 1371 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && 1372 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) 1373 goto done; 1374 1375 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1376 goto done; 1377 1378 memset(&args, 0, sizeof(args)); 1379 1380 args.v1.ucAction = action; 1381 1382 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1383 1384 /* wait for the panel to power up */ 1385 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { 1386 int i; 1387 1388 for (i = 0; i < 300; i++) { 1389 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) 1390 return true; 1391 mdelay(1); 1392 } 1393 return false; 1394 } 1395 done: 1396 return true; 1397 } 1398 1399 union external_encoder_control { 1400 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; 1401 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; 1402 }; 1403 1404 static void 1405 atombios_external_encoder_setup(struct drm_encoder *encoder, 1406 struct drm_encoder *ext_encoder, 1407 int action) 1408 { 1409 struct drm_device *dev = encoder->dev; 1410 struct radeon_device *rdev = dev->dev_private; 1411 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1412 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); 1413 union external_encoder_control args; 1414 struct drm_connector *connector; 1415 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); 1416 u8 frev, crev; 1417 int dp_clock = 0; 1418 int dp_lane_count = 0; 1419 int connector_object_id = 0; 1420 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1421 1422 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1423 connector = radeon_get_connector_for_encoder_init(encoder); 1424 else 1425 connector = radeon_get_connector_for_encoder(encoder); 1426 1427 if (connector) { 1428 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1429 struct radeon_connector_atom_dig *dig_connector = 1430 radeon_connector->con_priv; 1431 1432 dp_clock = dig_connector->dp_clock; 1433 dp_lane_count = dig_connector->dp_lane_count; 1434 connector_object_id = 1435 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1436 } 1437 1438 memset(&args, 0, sizeof(args)); 1439 1440 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1441 return; 1442 1443 switch (frev) { 1444 case 1: 1445 /* no params on frev 1 */ 1446 break; 1447 case 2: 1448 switch (crev) { 1449 case 1: 1450 case 2: 1451 args.v1.sDigEncoder.ucAction = action; 1452 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1453 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1454 1455 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) { 1456 if (dp_clock == 270000) 1457 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 1458 args.v1.sDigEncoder.ucLaneNum = dp_lane_count; 1459 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1460 args.v1.sDigEncoder.ucLaneNum = 8; 1461 else 1462 args.v1.sDigEncoder.ucLaneNum = 4; 1463 break; 1464 case 3: 1465 args.v3.sExtEncoder.ucAction = action; 1466 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1467 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); 1468 else 1469 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1470 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1471 1472 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { 1473 if (dp_clock == 270000) 1474 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 1475 else if (dp_clock == 540000) 1476 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; 1477 args.v3.sExtEncoder.ucLaneNum = dp_lane_count; 1478 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1479 args.v3.sExtEncoder.ucLaneNum = 8; 1480 else 1481 args.v3.sExtEncoder.ucLaneNum = 4; 1482 switch (ext_enum) { 1483 case GRAPH_OBJECT_ENUM_ID1: 1484 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; 1485 break; 1486 case GRAPH_OBJECT_ENUM_ID2: 1487 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; 1488 break; 1489 case GRAPH_OBJECT_ENUM_ID3: 1490 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; 1491 break; 1492 } 1493 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder); 1494 break; 1495 default: 1496 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1497 return; 1498 } 1499 break; 1500 default: 1501 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1502 return; 1503 } 1504 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1505 } 1506 1507 static void 1508 atombios_yuv_setup(struct drm_encoder *encoder, bool enable) 1509 { 1510 struct drm_device *dev = encoder->dev; 1511 struct radeon_device *rdev = dev->dev_private; 1512 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1513 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1514 ENABLE_YUV_PS_ALLOCATION args; 1515 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); 1516 uint32_t temp, reg; 1517 1518 memset(&args, 0, sizeof(args)); 1519 1520 if (rdev->family >= CHIP_R600) 1521 reg = R600_BIOS_3_SCRATCH; 1522 else 1523 reg = RADEON_BIOS_3_SCRATCH; 1524 1525 /* XXX: fix up scratch reg handling */ 1526 temp = RREG32(reg); 1527 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1528 WREG32(reg, (ATOM_S3_TV1_ACTIVE | 1529 (radeon_crtc->crtc_id << 18))); 1530 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1531 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); 1532 else 1533 WREG32(reg, 0); 1534 1535 if (enable) 1536 args.ucEnable = ATOM_ENABLE; 1537 args.ucCRTC = radeon_crtc->crtc_id; 1538 1539 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1540 1541 WREG32(reg, temp); 1542 } 1543 1544 static void 1545 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode) 1546 { 1547 struct drm_device *dev = encoder->dev; 1548 struct radeon_device *rdev = dev->dev_private; 1549 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1550 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 1551 int index = 0; 1552 1553 memset(&args, 0, sizeof(args)); 1554 1555 switch (radeon_encoder->encoder_id) { 1556 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1557 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1558 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); 1559 break; 1560 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1561 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1562 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1563 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1564 break; 1565 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1566 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1567 break; 1568 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1569 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1570 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1571 else 1572 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); 1573 break; 1574 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1575 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1576 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1577 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1578 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1579 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1580 else 1581 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 1582 break; 1583 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1584 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1585 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1586 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1587 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1588 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1589 else 1590 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 1591 break; 1592 default: 1593 return; 1594 } 1595 1596 switch (mode) { 1597 case DRM_MODE_DPMS_ON: 1598 args.ucAction = ATOM_ENABLE; 1599 /* workaround for DVOOutputControl on some RS690 systems */ 1600 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { 1601 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); 1602 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); 1603 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1604 WREG32(RADEON_BIOS_3_SCRATCH, reg); 1605 } else 1606 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1607 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1608 args.ucAction = ATOM_LCD_BLON; 1609 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1610 } 1611 break; 1612 case DRM_MODE_DPMS_STANDBY: 1613 case DRM_MODE_DPMS_SUSPEND: 1614 case DRM_MODE_DPMS_OFF: 1615 args.ucAction = ATOM_DISABLE; 1616 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1617 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1618 args.ucAction = ATOM_LCD_BLOFF; 1619 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1620 } 1621 break; 1622 } 1623 } 1624 1625 static void 1626 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 1627 { 1628 struct drm_device *dev = encoder->dev; 1629 struct radeon_device *rdev = dev->dev_private; 1630 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1631 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1632 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1633 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1634 struct radeon_connector *radeon_connector = NULL; 1635 struct radeon_connector_atom_dig *radeon_dig_connector = NULL; 1636 1637 if (connector) { 1638 radeon_connector = to_radeon_connector(connector); 1639 radeon_dig_connector = radeon_connector->con_priv; 1640 } 1641 1642 switch (mode) { 1643 case DRM_MODE_DPMS_ON: 1644 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 1645 if (!connector) 1646 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 1647 else 1648 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector); 1649 1650 /* setup and enable the encoder */ 1651 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1652 atombios_dig_encoder_setup(encoder, 1653 ATOM_ENCODER_CMD_SETUP_PANEL_MODE, 1654 dig->panel_mode); 1655 if (ext_encoder) { 1656 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) 1657 atombios_external_encoder_setup(encoder, ext_encoder, 1658 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); 1659 } 1660 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1661 } else if (ASIC_IS_DCE4(rdev)) { 1662 /* setup and enable the encoder */ 1663 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1664 /* enable the transmitter */ 1665 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1666 } else { 1667 /* setup and enable the encoder and transmitter */ 1668 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); 1669 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1670 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1671 } 1672 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1673 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1674 atombios_set_edp_panel_power(connector, 1675 ATOM_TRANSMITTER_ACTION_POWER_ON); 1676 radeon_dig_connector->edp_on = true; 1677 } 1678 radeon_dp_link_train(encoder, connector); 1679 if (ASIC_IS_DCE4(rdev)) 1680 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); 1681 } 1682 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1683 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 1684 break; 1685 case DRM_MODE_DPMS_STANDBY: 1686 case DRM_MODE_DPMS_SUSPEND: 1687 case DRM_MODE_DPMS_OFF: 1688 if (ASIC_IS_DCE4(rdev)) { 1689 /* disable the transmitter */ 1690 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1691 } else { 1692 /* disable the encoder and transmitter */ 1693 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1694 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); 1695 } 1696 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1697 if (ASIC_IS_DCE4(rdev)) 1698 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1699 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1700 atombios_set_edp_panel_power(connector, 1701 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1702 radeon_dig_connector->edp_on = false; 1703 } 1704 } 1705 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1706 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 1707 break; 1708 } 1709 } 1710 1711 static void 1712 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder, 1713 struct drm_encoder *ext_encoder, 1714 int mode) 1715 { 1716 struct drm_device *dev = encoder->dev; 1717 struct radeon_device *rdev = dev->dev_private; 1718 1719 switch (mode) { 1720 case DRM_MODE_DPMS_ON: 1721 default: 1722 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) { 1723 atombios_external_encoder_setup(encoder, ext_encoder, 1724 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT); 1725 atombios_external_encoder_setup(encoder, ext_encoder, 1726 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF); 1727 } else 1728 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1729 break; 1730 case DRM_MODE_DPMS_STANDBY: 1731 case DRM_MODE_DPMS_SUSPEND: 1732 case DRM_MODE_DPMS_OFF: 1733 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) { 1734 atombios_external_encoder_setup(encoder, ext_encoder, 1735 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING); 1736 atombios_external_encoder_setup(encoder, ext_encoder, 1737 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT); 1738 } else 1739 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); 1740 break; 1741 } 1742 } 1743 1744 static void 1745 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 1746 { 1747 struct drm_device *dev = encoder->dev; 1748 struct radeon_device *rdev = dev->dev_private; 1749 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1750 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1751 1752 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", 1753 radeon_encoder->encoder_id, mode, radeon_encoder->devices, 1754 radeon_encoder->active_device); 1755 switch (radeon_encoder->encoder_id) { 1756 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1757 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1758 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1759 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1760 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1761 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1762 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1763 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1764 radeon_atom_encoder_dpms_avivo(encoder, mode); 1765 break; 1766 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1767 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1768 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1769 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1770 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1771 radeon_atom_encoder_dpms_dig(encoder, mode); 1772 break; 1773 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1774 if (ASIC_IS_DCE5(rdev)) { 1775 switch (mode) { 1776 case DRM_MODE_DPMS_ON: 1777 atombios_dvo_setup(encoder, ATOM_ENABLE); 1778 break; 1779 case DRM_MODE_DPMS_STANDBY: 1780 case DRM_MODE_DPMS_SUSPEND: 1781 case DRM_MODE_DPMS_OFF: 1782 atombios_dvo_setup(encoder, ATOM_DISABLE); 1783 break; 1784 } 1785 } else if (ASIC_IS_DCE3(rdev)) 1786 radeon_atom_encoder_dpms_dig(encoder, mode); 1787 else 1788 radeon_atom_encoder_dpms_avivo(encoder, mode); 1789 break; 1790 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1791 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1792 if (ASIC_IS_DCE5(rdev)) { 1793 switch (mode) { 1794 case DRM_MODE_DPMS_ON: 1795 atombios_dac_setup(encoder, ATOM_ENABLE); 1796 break; 1797 case DRM_MODE_DPMS_STANDBY: 1798 case DRM_MODE_DPMS_SUSPEND: 1799 case DRM_MODE_DPMS_OFF: 1800 atombios_dac_setup(encoder, ATOM_DISABLE); 1801 break; 1802 } 1803 } else 1804 radeon_atom_encoder_dpms_avivo(encoder, mode); 1805 break; 1806 default: 1807 return; 1808 } 1809 1810 if (ext_encoder) 1811 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode); 1812 1813 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1814 1815 } 1816 1817 union crtc_source_param { 1818 SELECT_CRTC_SOURCE_PS_ALLOCATION v1; 1819 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; 1820 }; 1821 1822 static void 1823 atombios_set_encoder_crtc_source(struct drm_encoder *encoder) 1824 { 1825 struct drm_device *dev = encoder->dev; 1826 struct radeon_device *rdev = dev->dev_private; 1827 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1828 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1829 union crtc_source_param args; 1830 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 1831 uint8_t frev, crev; 1832 struct radeon_encoder_atom_dig *dig; 1833 1834 memset(&args, 0, sizeof(args)); 1835 1836 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1837 return; 1838 1839 switch (frev) { 1840 case 1: 1841 switch (crev) { 1842 case 1: 1843 default: 1844 if (ASIC_IS_AVIVO(rdev)) 1845 args.v1.ucCRTC = radeon_crtc->crtc_id; 1846 else { 1847 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { 1848 args.v1.ucCRTC = radeon_crtc->crtc_id; 1849 } else { 1850 args.v1.ucCRTC = radeon_crtc->crtc_id << 2; 1851 } 1852 } 1853 switch (radeon_encoder->encoder_id) { 1854 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1855 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1856 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; 1857 break; 1858 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1859 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1860 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) 1861 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; 1862 else 1863 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; 1864 break; 1865 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1866 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1867 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1868 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; 1869 break; 1870 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1871 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1872 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1873 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1874 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1875 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1876 else 1877 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; 1878 break; 1879 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1880 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1881 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1882 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1883 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1884 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1885 else 1886 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; 1887 break; 1888 } 1889 break; 1890 case 2: 1891 args.v2.ucCRTC = radeon_crtc->crtc_id; 1892 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { 1893 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1894 1895 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) 1896 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1897 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) 1898 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; 1899 else 1900 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1901 } else 1902 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1903 switch (radeon_encoder->encoder_id) { 1904 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1905 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1906 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1907 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1908 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1909 dig = radeon_encoder->enc_priv; 1910 switch (dig->dig_encoder) { 1911 case 0: 1912 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 1913 break; 1914 case 1: 1915 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1916 break; 1917 case 2: 1918 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 1919 break; 1920 case 3: 1921 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 1922 break; 1923 case 4: 1924 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 1925 break; 1926 case 5: 1927 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 1928 break; 1929 case 6: 1930 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; 1931 break; 1932 } 1933 break; 1934 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1935 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; 1936 break; 1937 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1938 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1939 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1940 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1941 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1942 else 1943 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; 1944 break; 1945 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1946 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1947 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1948 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1949 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1950 else 1951 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; 1952 break; 1953 } 1954 break; 1955 } 1956 break; 1957 default: 1958 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1959 return; 1960 } 1961 1962 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1963 1964 /* update scratch regs with new routing */ 1965 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1966 } 1967 1968 static void 1969 atombios_apply_encoder_quirks(struct drm_encoder *encoder, 1970 struct drm_display_mode *mode) 1971 { 1972 struct drm_device *dev = encoder->dev; 1973 struct radeon_device *rdev = dev->dev_private; 1974 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1975 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1976 1977 /* Funky macbooks */ 1978 if ((dev->pdev->device == 0x71C5) && 1979 (dev->pdev->subsystem_vendor == 0x106b) && 1980 (dev->pdev->subsystem_device == 0x0080)) { 1981 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 1982 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); 1983 1984 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; 1985 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 1986 1987 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); 1988 } 1989 } 1990 1991 /* set scaler clears this on some chips */ 1992 if (ASIC_IS_AVIVO(rdev) && 1993 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { 1994 if (ASIC_IS_DCE8(rdev)) { 1995 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1996 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 1997 CIK_INTERLEAVE_EN); 1998 else 1999 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2000 } else if (ASIC_IS_DCE4(rdev)) { 2001 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2002 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 2003 EVERGREEN_INTERLEAVE_EN); 2004 else 2005 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2006 } else { 2007 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2008 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 2009 AVIVO_D1MODE_INTERLEAVE_EN); 2010 else 2011 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2012 } 2013 } 2014 } 2015 2016 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) 2017 { 2018 struct drm_device *dev = encoder->dev; 2019 struct radeon_device *rdev = dev->dev_private; 2020 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 2021 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2022 struct drm_encoder *test_encoder; 2023 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2024 uint32_t dig_enc_in_use = 0; 2025 2026 if (ASIC_IS_DCE6(rdev)) { 2027 /* DCE6 */ 2028 switch (radeon_encoder->encoder_id) { 2029 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2030 if (dig->linkb) 2031 return 1; 2032 else 2033 return 0; 2034 break; 2035 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2036 if (dig->linkb) 2037 return 3; 2038 else 2039 return 2; 2040 break; 2041 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2042 if (dig->linkb) 2043 return 5; 2044 else 2045 return 4; 2046 break; 2047 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2048 return 6; 2049 break; 2050 } 2051 } else if (ASIC_IS_DCE4(rdev)) { 2052 /* DCE4/5 */ 2053 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) { 2054 /* ontario follows DCE4 */ 2055 if (rdev->family == CHIP_PALM) { 2056 if (dig->linkb) 2057 return 1; 2058 else 2059 return 0; 2060 } else 2061 /* llano follows DCE3.2 */ 2062 return radeon_crtc->crtc_id; 2063 } else { 2064 switch (radeon_encoder->encoder_id) { 2065 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2066 if (dig->linkb) 2067 return 1; 2068 else 2069 return 0; 2070 break; 2071 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2072 if (dig->linkb) 2073 return 3; 2074 else 2075 return 2; 2076 break; 2077 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2078 if (dig->linkb) 2079 return 5; 2080 else 2081 return 4; 2082 break; 2083 } 2084 } 2085 } 2086 2087 /* on DCE32 and encoder can driver any block so just crtc id */ 2088 if (ASIC_IS_DCE32(rdev)) { 2089 return radeon_crtc->crtc_id; 2090 } 2091 2092 /* on DCE3 - LVTMA can only be driven by DIGB */ 2093 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 2094 struct radeon_encoder *radeon_test_encoder; 2095 2096 if (encoder == test_encoder) 2097 continue; 2098 2099 if (!radeon_encoder_is_digital(test_encoder)) 2100 continue; 2101 2102 radeon_test_encoder = to_radeon_encoder(test_encoder); 2103 dig = radeon_test_encoder->enc_priv; 2104 2105 if (dig->dig_encoder >= 0) 2106 dig_enc_in_use |= (1 << dig->dig_encoder); 2107 } 2108 2109 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { 2110 if (dig_enc_in_use & 0x2) 2111 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); 2112 return 1; 2113 } 2114 if (!(dig_enc_in_use & 1)) 2115 return 0; 2116 return 1; 2117 } 2118 2119 /* This only needs to be called once at startup */ 2120 void 2121 radeon_atom_encoder_init(struct radeon_device *rdev) 2122 { 2123 struct drm_device *dev = rdev->ddev; 2124 struct drm_encoder *encoder; 2125 2126 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2127 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2128 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2129 2130 switch (radeon_encoder->encoder_id) { 2131 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2132 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2133 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2134 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2135 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2136 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); 2137 break; 2138 default: 2139 break; 2140 } 2141 2142 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))) 2143 atombios_external_encoder_setup(encoder, ext_encoder, 2144 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); 2145 } 2146 } 2147 2148 static void 2149 radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 2150 struct drm_display_mode *mode, 2151 struct drm_display_mode *adjusted_mode) 2152 { 2153 struct drm_device *dev = encoder->dev; 2154 struct radeon_device *rdev = dev->dev_private; 2155 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2156 2157 radeon_encoder->pixel_clock = adjusted_mode->clock; 2158 2159 /* need to call this here rather than in prepare() since we need some crtc info */ 2160 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2161 2162 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { 2163 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 2164 atombios_yuv_setup(encoder, true); 2165 else 2166 atombios_yuv_setup(encoder, false); 2167 } 2168 2169 switch (radeon_encoder->encoder_id) { 2170 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2172 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2173 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2174 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 2175 break; 2176 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2177 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2178 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2179 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2180 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2181 /* handled in dpms */ 2182 break; 2183 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2184 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2185 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2186 atombios_dvo_setup(encoder, ATOM_ENABLE); 2187 break; 2188 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2189 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2190 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2191 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2192 atombios_dac_setup(encoder, ATOM_ENABLE); 2193 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { 2194 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2195 atombios_tv_setup(encoder, ATOM_ENABLE); 2196 else 2197 atombios_tv_setup(encoder, ATOM_DISABLE); 2198 } 2199 break; 2200 } 2201 2202 atombios_apply_encoder_quirks(encoder, adjusted_mode); 2203 2204 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 2205 if (rdev->asic->display.hdmi_enable) 2206 radeon_hdmi_enable(rdev, encoder, true); 2207 if (rdev->asic->display.hdmi_setmode) 2208 radeon_hdmi_setmode(rdev, encoder, adjusted_mode); 2209 } 2210 } 2211 2212 static bool 2213 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2214 { 2215 struct drm_device *dev = encoder->dev; 2216 struct radeon_device *rdev = dev->dev_private; 2217 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2218 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2219 2220 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | 2221 ATOM_DEVICE_CV_SUPPORT | 2222 ATOM_DEVICE_CRT_SUPPORT)) { 2223 DAC_LOAD_DETECTION_PS_ALLOCATION args; 2224 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); 2225 uint8_t frev, crev; 2226 2227 memset(&args, 0, sizeof(args)); 2228 2229 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2230 return false; 2231 2232 args.sDacload.ucMisc = 0; 2233 2234 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 2235 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) 2236 args.sDacload.ucDacType = ATOM_DAC_A; 2237 else 2238 args.sDacload.ucDacType = ATOM_DAC_B; 2239 2240 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) 2241 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); 2242 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) 2243 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); 2244 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2245 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); 2246 if (crev >= 3) 2247 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2248 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2249 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); 2250 if (crev >= 3) 2251 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2252 } 2253 2254 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2255 2256 return true; 2257 } else 2258 return false; 2259 } 2260 2261 static enum drm_connector_status 2262 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2263 { 2264 struct drm_device *dev = encoder->dev; 2265 struct radeon_device *rdev = dev->dev_private; 2266 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2267 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2268 uint32_t bios_0_scratch; 2269 2270 if (!atombios_dac_load_detect(encoder, connector)) { 2271 DRM_DEBUG_KMS("detect returned false \n"); 2272 return connector_status_unknown; 2273 } 2274 2275 if (rdev->family >= CHIP_R600) 2276 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2277 else 2278 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 2279 2280 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2281 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2282 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2283 return connector_status_connected; 2284 } 2285 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2286 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2287 return connector_status_connected; 2288 } 2289 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2290 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2291 return connector_status_connected; 2292 } 2293 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2294 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2295 return connector_status_connected; /* CTV */ 2296 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2297 return connector_status_connected; /* STV */ 2298 } 2299 return connector_status_disconnected; 2300 } 2301 2302 static enum drm_connector_status 2303 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2304 { 2305 struct drm_device *dev = encoder->dev; 2306 struct radeon_device *rdev = dev->dev_private; 2307 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2308 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2309 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2310 u32 bios_0_scratch; 2311 2312 if (!ASIC_IS_DCE4(rdev)) 2313 return connector_status_unknown; 2314 2315 if (!ext_encoder) 2316 return connector_status_unknown; 2317 2318 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) 2319 return connector_status_unknown; 2320 2321 /* load detect on the dp bridge */ 2322 atombios_external_encoder_setup(encoder, ext_encoder, 2323 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); 2324 2325 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2326 2327 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2328 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2329 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2330 return connector_status_connected; 2331 } 2332 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2333 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2334 return connector_status_connected; 2335 } 2336 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2337 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2338 return connector_status_connected; 2339 } 2340 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2341 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2342 return connector_status_connected; /* CTV */ 2343 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2344 return connector_status_connected; /* STV */ 2345 } 2346 return connector_status_disconnected; 2347 } 2348 2349 void 2350 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) 2351 { 2352 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2353 2354 if (ext_encoder) 2355 /* ddc_setup on the dp bridge */ 2356 atombios_external_encoder_setup(encoder, ext_encoder, 2357 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); 2358 2359 } 2360 2361 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 2362 { 2363 struct radeon_device *rdev = encoder->dev->dev_private; 2364 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2365 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2366 2367 if ((radeon_encoder->active_device & 2368 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 2369 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 2370 ENCODER_OBJECT_ID_NONE)) { 2371 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2372 if (dig) { 2373 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); 2374 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) { 2375 if (rdev->family >= CHIP_R600) 2376 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder]; 2377 else 2378 /* RS600/690/740 have only 1 afmt block */ 2379 dig->afmt = rdev->mode_info.afmt[0]; 2380 } 2381 } 2382 } 2383 2384 radeon_atom_output_lock(encoder, true); 2385 2386 if (connector) { 2387 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2388 2389 /* select the clock/data port if it uses a router */ 2390 if (radeon_connector->router.cd_valid) 2391 radeon_router_select_cd_port(radeon_connector); 2392 2393 /* turn eDP panel on for mode set */ 2394 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 2395 atombios_set_edp_panel_power(connector, 2396 ATOM_TRANSMITTER_ACTION_POWER_ON); 2397 } 2398 2399 /* this is needed for the pll/ss setup to work correctly in some cases */ 2400 atombios_set_encoder_crtc_source(encoder); 2401 /* set up the FMT blocks */ 2402 if (ASIC_IS_DCE8(rdev)) 2403 dce8_program_fmt(encoder); 2404 else if (ASIC_IS_DCE4(rdev)) 2405 dce4_program_fmt(encoder); 2406 else if (ASIC_IS_DCE3(rdev)) 2407 dce3_program_fmt(encoder); 2408 else if (ASIC_IS_AVIVO(rdev)) 2409 avivo_program_fmt(encoder); 2410 } 2411 2412 static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 2413 { 2414 /* need to call this here as we need the crtc set up */ 2415 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 2416 radeon_atom_output_lock(encoder, false); 2417 } 2418 2419 static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 2420 { 2421 struct drm_device *dev = encoder->dev; 2422 struct radeon_device *rdev = dev->dev_private; 2423 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2424 struct radeon_encoder_atom_dig *dig; 2425 2426 /* check for pre-DCE3 cards with shared encoders; 2427 * can't really use the links individually, so don't disable 2428 * the encoder if it's in use by another connector 2429 */ 2430 if (!ASIC_IS_DCE3(rdev)) { 2431 struct drm_encoder *other_encoder; 2432 struct radeon_encoder *other_radeon_encoder; 2433 2434 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { 2435 other_radeon_encoder = to_radeon_encoder(other_encoder); 2436 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && 2437 drm_helper_encoder_in_use(other_encoder)) 2438 goto disable_done; 2439 } 2440 } 2441 2442 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2443 2444 switch (radeon_encoder->encoder_id) { 2445 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2446 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2447 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2448 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2449 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); 2450 break; 2451 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2452 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2453 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2454 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2455 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2456 /* handled in dpms */ 2457 break; 2458 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2459 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2460 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2461 atombios_dvo_setup(encoder, ATOM_DISABLE); 2462 break; 2463 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2464 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2465 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2466 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2467 atombios_dac_setup(encoder, ATOM_DISABLE); 2468 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2469 atombios_tv_setup(encoder, ATOM_DISABLE); 2470 break; 2471 } 2472 2473 disable_done: 2474 if (radeon_encoder_is_digital(encoder)) { 2475 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 2476 if (rdev->asic->display.hdmi_enable) 2477 radeon_hdmi_enable(rdev, encoder, false); 2478 } 2479 dig = radeon_encoder->enc_priv; 2480 dig->dig_encoder = -1; 2481 } 2482 radeon_encoder->active_device = 0; 2483 } 2484 2485 /* these are handled by the primary encoders */ 2486 static void radeon_atom_ext_prepare(struct drm_encoder *encoder) 2487 { 2488 2489 } 2490 2491 static void radeon_atom_ext_commit(struct drm_encoder *encoder) 2492 { 2493 2494 } 2495 2496 static void 2497 radeon_atom_ext_mode_set(struct drm_encoder *encoder, 2498 struct drm_display_mode *mode, 2499 struct drm_display_mode *adjusted_mode) 2500 { 2501 2502 } 2503 2504 static void radeon_atom_ext_disable(struct drm_encoder *encoder) 2505 { 2506 2507 } 2508 2509 static void 2510 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) 2511 { 2512 2513 } 2514 2515 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder, 2516 const struct drm_display_mode *mode, 2517 struct drm_display_mode *adjusted_mode) 2518 { 2519 return true; 2520 } 2521 2522 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { 2523 .dpms = radeon_atom_ext_dpms, 2524 .mode_fixup = radeon_atom_ext_mode_fixup, 2525 .prepare = radeon_atom_ext_prepare, 2526 .mode_set = radeon_atom_ext_mode_set, 2527 .commit = radeon_atom_ext_commit, 2528 .disable = radeon_atom_ext_disable, 2529 /* no detect for TMDS/LVDS yet */ 2530 }; 2531 2532 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { 2533 .dpms = radeon_atom_encoder_dpms, 2534 .mode_fixup = radeon_atom_mode_fixup, 2535 .prepare = radeon_atom_encoder_prepare, 2536 .mode_set = radeon_atom_encoder_mode_set, 2537 .commit = radeon_atom_encoder_commit, 2538 .disable = radeon_atom_encoder_disable, 2539 .detect = radeon_atom_dig_detect, 2540 }; 2541 2542 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { 2543 .dpms = radeon_atom_encoder_dpms, 2544 .mode_fixup = radeon_atom_mode_fixup, 2545 .prepare = radeon_atom_encoder_prepare, 2546 .mode_set = radeon_atom_encoder_mode_set, 2547 .commit = radeon_atom_encoder_commit, 2548 .detect = radeon_atom_dac_detect, 2549 }; 2550 2551 void radeon_enc_destroy(struct drm_encoder *encoder) 2552 { 2553 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2554 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2555 radeon_atom_backlight_exit(radeon_encoder); 2556 kfree(radeon_encoder->enc_priv); 2557 drm_encoder_cleanup(encoder); 2558 kfree(radeon_encoder); 2559 } 2560 2561 static const struct drm_encoder_funcs radeon_atom_enc_funcs = { 2562 .destroy = radeon_enc_destroy, 2563 }; 2564 2565 static struct radeon_encoder_atom_dac * 2566 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) 2567 { 2568 struct drm_device *dev = radeon_encoder->base.dev; 2569 struct radeon_device *rdev = dev->dev_private; 2570 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); 2571 2572 if (!dac) 2573 return NULL; 2574 2575 dac->tv_std = radeon_atombios_get_tv_info(rdev); 2576 return dac; 2577 } 2578 2579 static struct radeon_encoder_atom_dig * 2580 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) 2581 { 2582 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 2583 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 2584 2585 if (!dig) 2586 return NULL; 2587 2588 /* coherent mode by default */ 2589 dig->coherent_mode = true; 2590 dig->dig_encoder = -1; 2591 2592 if (encoder_enum == 2) 2593 dig->linkb = true; 2594 else 2595 dig->linkb = false; 2596 2597 return dig; 2598 } 2599 2600 void 2601 radeon_add_atom_encoder(struct drm_device *dev, 2602 uint32_t encoder_enum, 2603 uint32_t supported_device, 2604 u16 caps) 2605 { 2606 struct radeon_device *rdev = dev->dev_private; 2607 struct drm_encoder *encoder; 2608 struct radeon_encoder *radeon_encoder; 2609 2610 /* see if we already added it */ 2611 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2612 radeon_encoder = to_radeon_encoder(encoder); 2613 if (radeon_encoder->encoder_enum == encoder_enum) { 2614 radeon_encoder->devices |= supported_device; 2615 return; 2616 } 2617 2618 } 2619 2620 /* add a new one */ 2621 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); 2622 if (!radeon_encoder) 2623 return; 2624 2625 encoder = &radeon_encoder->base; 2626 switch (rdev->num_crtc) { 2627 case 1: 2628 encoder->possible_crtcs = 0x1; 2629 break; 2630 case 2: 2631 default: 2632 encoder->possible_crtcs = 0x3; 2633 break; 2634 case 4: 2635 encoder->possible_crtcs = 0xf; 2636 break; 2637 case 6: 2638 encoder->possible_crtcs = 0x3f; 2639 break; 2640 } 2641 2642 radeon_encoder->enc_priv = NULL; 2643 2644 radeon_encoder->encoder_enum = encoder_enum; 2645 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 2646 radeon_encoder->devices = supported_device; 2647 radeon_encoder->rmx_type = RMX_OFF; 2648 radeon_encoder->underscan_type = UNDERSCAN_OFF; 2649 radeon_encoder->is_ext_encoder = false; 2650 radeon_encoder->caps = caps; 2651 2652 switch (radeon_encoder->encoder_id) { 2653 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2654 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2655 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2656 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2657 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2658 radeon_encoder->rmx_type = RMX_FULL; 2659 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2660 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2661 } else { 2662 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2663 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2664 } 2665 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2666 break; 2667 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2668 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2669 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2670 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2671 break; 2672 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2673 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2674 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2675 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); 2676 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2677 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2678 break; 2679 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2680 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2681 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2682 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2683 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2684 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2685 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2686 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2687 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2688 radeon_encoder->rmx_type = RMX_FULL; 2689 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2690 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2691 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 2692 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2693 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2694 } else { 2695 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2696 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2697 } 2698 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2699 break; 2700 case ENCODER_OBJECT_ID_SI170B: 2701 case ENCODER_OBJECT_ID_CH7303: 2702 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 2703 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 2704 case ENCODER_OBJECT_ID_TITFP513: 2705 case ENCODER_OBJECT_ID_VT1623: 2706 case ENCODER_OBJECT_ID_HDMI_SI1930: 2707 case ENCODER_OBJECT_ID_TRAVIS: 2708 case ENCODER_OBJECT_ID_NUTMEG: 2709 /* these are handled by the primary encoders */ 2710 radeon_encoder->is_ext_encoder = true; 2711 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2712 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2713 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 2714 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2715 else 2716 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2717 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); 2718 break; 2719 } 2720 } 2721