1 /*
2  * Copyright 2007-11 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: Dave Airlie
24  *          Alex Deucher
25  */
26 
27 #include <linux/backlight.h>
28 #include <linux/dmi.h>
29 #include <linux/pci.h>
30 
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/drm_file.h>
33 #include <drm/radeon_drm.h>
34 
35 #include "atom.h"
36 #include "radeon_atombios.h"
37 #include "radeon.h"
38 #include "radeon_asic.h"
39 #include "radeon_audio.h"
40 
41 extern int atom_debug;
42 
43 static u8
44 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
45 {
46 	u8 backlight_level;
47 	u32 bios_2_scratch;
48 
49 	if (rdev->family >= CHIP_R600)
50 		bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
51 	else
52 		bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
53 
54 	backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
55 			   ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
56 
57 	return backlight_level;
58 }
59 
60 static void
61 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
62 				       u8 backlight_level)
63 {
64 	u32 bios_2_scratch;
65 
66 	if (rdev->family >= CHIP_R600)
67 		bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
68 	else
69 		bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
70 
71 	bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
72 	bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
73 			   ATOM_S2_CURRENT_BL_LEVEL_MASK);
74 
75 	if (rdev->family >= CHIP_R600)
76 		WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
77 	else
78 		WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
79 }
80 
81 u8
82 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
83 {
84 	struct drm_device *dev = radeon_encoder->base.dev;
85 	struct radeon_device *rdev = dev->dev_private;
86 
87 	if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
88 		return 0;
89 
90 	return radeon_atom_get_backlight_level_from_reg(rdev);
91 }
92 
93 void
94 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
95 {
96 	struct drm_encoder *encoder = &radeon_encoder->base;
97 	struct drm_device *dev = radeon_encoder->base.dev;
98 	struct radeon_device *rdev = dev->dev_private;
99 	struct radeon_encoder_atom_dig *dig;
100 	DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
101 	int index;
102 
103 	if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
104 		return;
105 
106 	if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
107 	    radeon_encoder->enc_priv) {
108 		dig = radeon_encoder->enc_priv;
109 		dig->backlight_level = level;
110 		radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
111 
112 		switch (radeon_encoder->encoder_id) {
113 		case ENCODER_OBJECT_ID_INTERNAL_LVDS:
114 		case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
115 			index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
116 			if (dig->backlight_level == 0) {
117 				args.ucAction = ATOM_LCD_BLOFF;
118 				atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
119 			} else {
120 				args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
121 				atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
122 				args.ucAction = ATOM_LCD_BLON;
123 				atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
124 			}
125 			break;
126 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
127 		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
128 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
129 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
130 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
131 			if (dig->backlight_level == 0)
132 				atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
133 			else {
134 				atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
135 				atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
136 			}
137 			break;
138 		default:
139 			break;
140 		}
141 	}
142 }
143 
144 static u8 radeon_atom_bl_level(struct backlight_device *bd)
145 {
146 	u8 level;
147 
148 	/* Convert brightness to hardware level */
149 	if (bd->props.brightness < 0)
150 		level = 0;
151 	else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
152 		level = RADEON_MAX_BL_LEVEL;
153 	else
154 		level = bd->props.brightness;
155 
156 	return level;
157 }
158 
159 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
160 {
161 	struct radeon_backlight_privdata *pdata = bl_get_data(bd);
162 	struct radeon_encoder *radeon_encoder = pdata->encoder;
163 
164 	atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
165 
166 	return 0;
167 }
168 
169 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
170 {
171 	struct radeon_backlight_privdata *pdata = bl_get_data(bd);
172 	struct radeon_encoder *radeon_encoder = pdata->encoder;
173 	struct drm_device *dev = radeon_encoder->base.dev;
174 	struct radeon_device *rdev = dev->dev_private;
175 
176 	return radeon_atom_get_backlight_level_from_reg(rdev);
177 }
178 
179 static const struct backlight_ops radeon_atom_backlight_ops = {
180 	.get_brightness = radeon_atom_backlight_get_brightness,
181 	.update_status	= radeon_atom_backlight_update_status,
182 };
183 
184 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
185 				struct drm_connector *drm_connector)
186 {
187 	struct drm_device *dev = radeon_encoder->base.dev;
188 	struct radeon_device *rdev = dev->dev_private;
189 	struct backlight_device *bd;
190 	struct backlight_properties props;
191 	struct radeon_backlight_privdata *pdata;
192 	struct radeon_encoder_atom_dig *dig;
193 	char bl_name[16];
194 
195 	/* Mac laptops with multiple GPUs use the gmux driver for backlight
196 	 * so don't register a backlight device
197 	 */
198 	if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
199 	    (rdev->pdev->device == 0x6741) &&
200 	    !dmi_match(DMI_PRODUCT_NAME, "iMac12,1"))
201 		return;
202 
203 	if (!radeon_encoder->enc_priv)
204 		return;
205 
206 	if (!rdev->is_atom_bios)
207 		return;
208 
209 	if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
210 		return;
211 
212 	pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
213 	if (!pdata) {
214 		DRM_ERROR("Memory allocation failed\n");
215 		goto error;
216 	}
217 
218 	memset(&props, 0, sizeof(props));
219 	props.max_brightness = RADEON_MAX_BL_LEVEL;
220 	props.type = BACKLIGHT_RAW;
221 	snprintf(bl_name, sizeof(bl_name),
222 		 "radeon_bl%d", dev->primary->index);
223 	bd = backlight_device_register(bl_name, drm_connector->kdev,
224 				       pdata, &radeon_atom_backlight_ops, &props);
225 	if (IS_ERR(bd)) {
226 		DRM_ERROR("Backlight registration failed\n");
227 		goto error;
228 	}
229 
230 	pdata->encoder = radeon_encoder;
231 
232 	dig = radeon_encoder->enc_priv;
233 	dig->bl_dev = bd;
234 
235 	bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
236 	/* Set a reasonable default here if the level is 0 otherwise
237 	 * fbdev will attempt to turn the backlight on after console
238 	 * unblanking and it will try and restore 0 which turns the backlight
239 	 * off again.
240 	 */
241 	if (bd->props.brightness == 0)
242 		bd->props.brightness = RADEON_MAX_BL_LEVEL;
243 	bd->props.power = FB_BLANK_UNBLANK;
244 	backlight_update_status(bd);
245 
246 	DRM_INFO("radeon atom DIG backlight initialized\n");
247 	rdev->mode_info.bl_encoder = radeon_encoder;
248 
249 	return;
250 
251 error:
252 	kfree(pdata);
253 	return;
254 }
255 
256 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
257 {
258 	struct drm_device *dev = radeon_encoder->base.dev;
259 	struct radeon_device *rdev = dev->dev_private;
260 	struct backlight_device *bd = NULL;
261 	struct radeon_encoder_atom_dig *dig;
262 
263 	if (!radeon_encoder->enc_priv)
264 		return;
265 
266 	if (!rdev->is_atom_bios)
267 		return;
268 
269 	if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
270 		return;
271 
272 	dig = radeon_encoder->enc_priv;
273 	bd = dig->bl_dev;
274 	dig->bl_dev = NULL;
275 
276 	if (bd) {
277 		struct radeon_legacy_backlight_privdata *pdata;
278 
279 		pdata = bl_get_data(bd);
280 		backlight_device_unregister(bd);
281 		kfree(pdata);
282 
283 		DRM_INFO("radeon atom LVDS backlight unloaded\n");
284 	}
285 }
286 
287 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
288 				   const struct drm_display_mode *mode,
289 				   struct drm_display_mode *adjusted_mode)
290 {
291 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
292 	struct drm_device *dev = encoder->dev;
293 	struct radeon_device *rdev = dev->dev_private;
294 
295 	/* set the active encoder to connector routing */
296 	radeon_encoder_set_active_device(encoder);
297 	drm_mode_set_crtcinfo(adjusted_mode, 0);
298 
299 	/* hw bug */
300 	if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
301 	    && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
302 		adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
303 
304 	/* vertical FP must be at least 1 */
305 	if (mode->crtc_vsync_start == mode->crtc_vdisplay)
306 		adjusted_mode->crtc_vsync_start++;
307 
308 	/* get the native mode for scaling */
309 	if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
310 		radeon_panel_mode_fixup(encoder, adjusted_mode);
311 	} else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
312 		struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
313 		if (tv_dac) {
314 			if (tv_dac->tv_std == TV_STD_NTSC ||
315 			    tv_dac->tv_std == TV_STD_NTSC_J ||
316 			    tv_dac->tv_std == TV_STD_PAL_M)
317 				radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
318 			else
319 				radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
320 		}
321 	} else if (radeon_encoder->rmx_type != RMX_OFF) {
322 		radeon_panel_mode_fixup(encoder, adjusted_mode);
323 	}
324 
325 	if (ASIC_IS_DCE3(rdev) &&
326 	    ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
327 	     (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
328 		struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
329 		radeon_dp_set_link_config(connector, adjusted_mode);
330 	}
331 
332 	return true;
333 }
334 
335 static void
336 atombios_dac_setup(struct drm_encoder *encoder, int action)
337 {
338 	struct drm_device *dev = encoder->dev;
339 	struct radeon_device *rdev = dev->dev_private;
340 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
341 	DAC_ENCODER_CONTROL_PS_ALLOCATION args;
342 	int index = 0;
343 	struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
344 
345 	memset(&args, 0, sizeof(args));
346 
347 	switch (radeon_encoder->encoder_id) {
348 	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
349 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
350 		index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
351 		break;
352 	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
353 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
354 		index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
355 		break;
356 	}
357 
358 	args.ucAction = action;
359 
360 	if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
361 		args.ucDacStandard = ATOM_DAC1_PS2;
362 	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
363 		args.ucDacStandard = ATOM_DAC1_CV;
364 	else {
365 		switch (dac_info->tv_std) {
366 		case TV_STD_PAL:
367 		case TV_STD_PAL_M:
368 		case TV_STD_SCART_PAL:
369 		case TV_STD_SECAM:
370 		case TV_STD_PAL_CN:
371 			args.ucDacStandard = ATOM_DAC1_PAL;
372 			break;
373 		case TV_STD_NTSC:
374 		case TV_STD_NTSC_J:
375 		case TV_STD_PAL_60:
376 		default:
377 			args.ucDacStandard = ATOM_DAC1_NTSC;
378 			break;
379 		}
380 	}
381 	args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
382 
383 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
384 
385 }
386 
387 static void
388 atombios_tv_setup(struct drm_encoder *encoder, int action)
389 {
390 	struct drm_device *dev = encoder->dev;
391 	struct radeon_device *rdev = dev->dev_private;
392 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
393 	TV_ENCODER_CONTROL_PS_ALLOCATION args;
394 	int index = 0;
395 	struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
396 
397 	memset(&args, 0, sizeof(args));
398 
399 	index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
400 
401 	args.sTVEncoder.ucAction = action;
402 
403 	if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
404 		args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
405 	else {
406 		switch (dac_info->tv_std) {
407 		case TV_STD_NTSC:
408 			args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
409 			break;
410 		case TV_STD_PAL:
411 			args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
412 			break;
413 		case TV_STD_PAL_M:
414 			args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
415 			break;
416 		case TV_STD_PAL_60:
417 			args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
418 			break;
419 		case TV_STD_NTSC_J:
420 			args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
421 			break;
422 		case TV_STD_SCART_PAL:
423 			args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
424 			break;
425 		case TV_STD_SECAM:
426 			args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
427 			break;
428 		case TV_STD_PAL_CN:
429 			args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
430 			break;
431 		default:
432 			args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
433 			break;
434 		}
435 	}
436 
437 	args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
438 
439 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
440 
441 }
442 
443 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
444 {
445 	int bpc = 8;
446 
447 	if (encoder->crtc) {
448 		struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
449 		bpc = radeon_crtc->bpc;
450 	}
451 
452 	switch (bpc) {
453 	case 0:
454 		return PANEL_BPC_UNDEFINE;
455 	case 6:
456 		return PANEL_6BIT_PER_COLOR;
457 	case 8:
458 	default:
459 		return PANEL_8BIT_PER_COLOR;
460 	case 10:
461 		return PANEL_10BIT_PER_COLOR;
462 	case 12:
463 		return PANEL_12BIT_PER_COLOR;
464 	case 16:
465 		return PANEL_16BIT_PER_COLOR;
466 	}
467 }
468 
469 union dvo_encoder_control {
470 	ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
471 	DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
472 	DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
473 	DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
474 };
475 
476 void
477 atombios_dvo_setup(struct drm_encoder *encoder, int action)
478 {
479 	struct drm_device *dev = encoder->dev;
480 	struct radeon_device *rdev = dev->dev_private;
481 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
482 	union dvo_encoder_control args;
483 	int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
484 	uint8_t frev, crev;
485 
486 	memset(&args, 0, sizeof(args));
487 
488 	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
489 		return;
490 
491 	/* some R4xx chips have the wrong frev */
492 	if (rdev->family <= CHIP_RV410)
493 		frev = 1;
494 
495 	switch (frev) {
496 	case 1:
497 		switch (crev) {
498 		case 1:
499 			/* R4xx, R5xx */
500 			args.ext_tmds.sXTmdsEncoder.ucEnable = action;
501 
502 			if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
503 				args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
504 
505 			args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
506 			break;
507 		case 2:
508 			/* RS600/690/740 */
509 			args.dvo.sDVOEncoder.ucAction = action;
510 			args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
511 			/* DFP1, CRT1, TV1 depending on the type of port */
512 			args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
513 
514 			if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
515 				args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
516 			break;
517 		case 3:
518 			/* R6xx */
519 			args.dvo_v3.ucAction = action;
520 			args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
521 			args.dvo_v3.ucDVOConfig = 0; /* XXX */
522 			break;
523 		case 4:
524 			/* DCE8 */
525 			args.dvo_v4.ucAction = action;
526 			args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
527 			args.dvo_v4.ucDVOConfig = 0; /* XXX */
528 			args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
529 			break;
530 		default:
531 			DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
532 			break;
533 		}
534 		break;
535 	default:
536 		DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
537 		break;
538 	}
539 
540 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
541 }
542 
543 union lvds_encoder_control {
544 	LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
545 	LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
546 };
547 
548 void
549 atombios_digital_setup(struct drm_encoder *encoder, int action)
550 {
551 	struct drm_device *dev = encoder->dev;
552 	struct radeon_device *rdev = dev->dev_private;
553 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
554 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
555 	union lvds_encoder_control args;
556 	int index = 0;
557 	int hdmi_detected = 0;
558 	uint8_t frev, crev;
559 
560 	if (!dig)
561 		return;
562 
563 	if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
564 		hdmi_detected = 1;
565 
566 	memset(&args, 0, sizeof(args));
567 
568 	switch (radeon_encoder->encoder_id) {
569 	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
570 		index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
571 		break;
572 	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
573 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
574 		index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
575 		break;
576 	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
577 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
578 			index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
579 		else
580 			index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
581 		break;
582 	}
583 
584 	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
585 		return;
586 
587 	switch (frev) {
588 	case 1:
589 	case 2:
590 		switch (crev) {
591 		case 1:
592 			args.v1.ucMisc = 0;
593 			args.v1.ucAction = action;
594 			if (hdmi_detected)
595 				args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
596 			args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
597 			if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
598 				if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
599 					args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
600 				if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
601 					args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
602 			} else {
603 				if (dig->linkb)
604 					args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
605 				if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
606 					args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
607 				/*if (pScrn->rgbBits == 8) */
608 				args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
609 			}
610 			break;
611 		case 2:
612 		case 3:
613 			args.v2.ucMisc = 0;
614 			args.v2.ucAction = action;
615 			if (crev == 3) {
616 				if (dig->coherent_mode)
617 					args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
618 			}
619 			if (hdmi_detected)
620 				args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
621 			args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
622 			args.v2.ucTruncate = 0;
623 			args.v2.ucSpatial = 0;
624 			args.v2.ucTemporal = 0;
625 			args.v2.ucFRC = 0;
626 			if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
627 				if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
628 					args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
629 				if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
630 					args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
631 					if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
632 						args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
633 				}
634 				if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
635 					args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
636 					if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
637 						args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
638 					if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
639 						args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
640 				}
641 			} else {
642 				if (dig->linkb)
643 					args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
644 				if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
645 					args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
646 			}
647 			break;
648 		default:
649 			DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
650 			break;
651 		}
652 		break;
653 	default:
654 		DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
655 		break;
656 	}
657 
658 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
659 }
660 
661 int
662 atombios_get_encoder_mode(struct drm_encoder *encoder)
663 {
664 	struct drm_device *dev = encoder->dev;
665 	struct radeon_device *rdev = dev->dev_private;
666 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
667 	struct drm_connector *connector;
668 	struct radeon_connector *radeon_connector;
669 	struct radeon_connector_atom_dig *dig_connector;
670 
671 	/* dp bridges are always DP */
672 	if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
673 		return ATOM_ENCODER_MODE_DP;
674 
675 	/* DVO is always DVO */
676 	if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
677 	    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
678 		return ATOM_ENCODER_MODE_DVO;
679 
680 	connector = radeon_get_connector_for_encoder(encoder);
681 	/* if we don't have an active device yet, just use one of
682 	 * the connectors tied to the encoder.
683 	 */
684 	if (!connector)
685 		connector = radeon_get_connector_for_encoder_init(encoder);
686 	radeon_connector = to_radeon_connector(connector);
687 
688 	switch (connector->connector_type) {
689 	case DRM_MODE_CONNECTOR_DVII:
690 	case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
691 		if (radeon_audio != 0) {
692 			if (radeon_connector->use_digital &&
693 			    (radeon_connector->audio == RADEON_AUDIO_ENABLE))
694 				return ATOM_ENCODER_MODE_HDMI;
695 			else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
696 				 (radeon_connector->audio == RADEON_AUDIO_AUTO))
697 				return ATOM_ENCODER_MODE_HDMI;
698 			else if (radeon_connector->use_digital)
699 				return ATOM_ENCODER_MODE_DVI;
700 			else
701 				return ATOM_ENCODER_MODE_CRT;
702 		} else if (radeon_connector->use_digital) {
703 			return ATOM_ENCODER_MODE_DVI;
704 		} else {
705 			return ATOM_ENCODER_MODE_CRT;
706 		}
707 		break;
708 	case DRM_MODE_CONNECTOR_DVID:
709 	case DRM_MODE_CONNECTOR_HDMIA:
710 	default:
711 		if (radeon_audio != 0) {
712 			if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
713 				return ATOM_ENCODER_MODE_HDMI;
714 			else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
715 				 (radeon_connector->audio == RADEON_AUDIO_AUTO))
716 				return ATOM_ENCODER_MODE_HDMI;
717 			else
718 				return ATOM_ENCODER_MODE_DVI;
719 		} else {
720 			return ATOM_ENCODER_MODE_DVI;
721 		}
722 		break;
723 	case DRM_MODE_CONNECTOR_LVDS:
724 		return ATOM_ENCODER_MODE_LVDS;
725 		break;
726 	case DRM_MODE_CONNECTOR_DisplayPort:
727 		dig_connector = radeon_connector->con_priv;
728 		if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
729 		    (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
730 			if (radeon_audio != 0 &&
731 			    drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
732 			    ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
733 				return ATOM_ENCODER_MODE_DP_AUDIO;
734 			return ATOM_ENCODER_MODE_DP;
735 		} else if (radeon_audio != 0) {
736 			if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
737 				return ATOM_ENCODER_MODE_HDMI;
738 			else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
739 				 (radeon_connector->audio == RADEON_AUDIO_AUTO))
740 				return ATOM_ENCODER_MODE_HDMI;
741 			else
742 				return ATOM_ENCODER_MODE_DVI;
743 		} else {
744 			return ATOM_ENCODER_MODE_DVI;
745 		}
746 		break;
747 	case DRM_MODE_CONNECTOR_eDP:
748 		if (radeon_audio != 0 &&
749 		    drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
750 		    ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
751 			return ATOM_ENCODER_MODE_DP_AUDIO;
752 		return ATOM_ENCODER_MODE_DP;
753 	case DRM_MODE_CONNECTOR_DVIA:
754 	case DRM_MODE_CONNECTOR_VGA:
755 		return ATOM_ENCODER_MODE_CRT;
756 		break;
757 	case DRM_MODE_CONNECTOR_Composite:
758 	case DRM_MODE_CONNECTOR_SVIDEO:
759 	case DRM_MODE_CONNECTOR_9PinDIN:
760 		/* fix me */
761 		return ATOM_ENCODER_MODE_TV;
762 		/*return ATOM_ENCODER_MODE_CV;*/
763 		break;
764 	}
765 }
766 
767 /*
768  * DIG Encoder/Transmitter Setup
769  *
770  * DCE 3.0/3.1
771  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
772  * Supports up to 3 digital outputs
773  * - 2 DIG encoder blocks.
774  * DIG1 can drive UNIPHY link A or link B
775  * DIG2 can drive UNIPHY link B or LVTMA
776  *
777  * DCE 3.2
778  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
779  * Supports up to 5 digital outputs
780  * - 2 DIG encoder blocks.
781  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
782  *
783  * DCE 4.0/5.0/6.0
784  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
785  * Supports up to 6 digital outputs
786  * - 6 DIG encoder blocks.
787  * - DIG to PHY mapping is hardcoded
788  * DIG1 drives UNIPHY0 link A, A+B
789  * DIG2 drives UNIPHY0 link B
790  * DIG3 drives UNIPHY1 link A, A+B
791  * DIG4 drives UNIPHY1 link B
792  * DIG5 drives UNIPHY2 link A, A+B
793  * DIG6 drives UNIPHY2 link B
794  *
795  * DCE 4.1
796  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
797  * Supports up to 6 digital outputs
798  * - 2 DIG encoder blocks.
799  * llano
800  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
801  * ontario
802  * DIG1 drives UNIPHY0/1/2 link A
803  * DIG2 drives UNIPHY0/1/2 link B
804  *
805  * Routing
806  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
807  * Examples:
808  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
809  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
810  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
811  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
812  */
813 
814 union dig_encoder_control {
815 	DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
816 	DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
817 	DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
818 	DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
819 };
820 
821 void
822 atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override)
823 {
824 	struct drm_device *dev = encoder->dev;
825 	struct radeon_device *rdev = dev->dev_private;
826 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
827 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
828 	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
829 	union dig_encoder_control args;
830 	int index = 0;
831 	uint8_t frev, crev;
832 	int dp_clock = 0;
833 	int dp_lane_count = 0;
834 	int hpd_id = RADEON_HPD_NONE;
835 
836 	if (connector) {
837 		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
838 		struct radeon_connector_atom_dig *dig_connector =
839 			radeon_connector->con_priv;
840 
841 		dp_clock = dig_connector->dp_clock;
842 		dp_lane_count = dig_connector->dp_lane_count;
843 		hpd_id = radeon_connector->hpd.hpd;
844 	}
845 
846 	/* no dig encoder assigned */
847 	if (dig->dig_encoder == -1)
848 		return;
849 
850 	memset(&args, 0, sizeof(args));
851 
852 	if (ASIC_IS_DCE4(rdev))
853 		index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
854 	else {
855 		if (dig->dig_encoder)
856 			index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
857 		else
858 			index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
859 	}
860 
861 	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
862 		return;
863 
864 	switch (frev) {
865 	case 1:
866 		switch (crev) {
867 		case 1:
868 			args.v1.ucAction = action;
869 			args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
870 			if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
871 				args.v3.ucPanelMode = panel_mode;
872 			else
873 				args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
874 
875 			if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
876 				args.v1.ucLaneNum = dp_lane_count;
877 			else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
878 				args.v1.ucLaneNum = 8;
879 			else
880 				args.v1.ucLaneNum = 4;
881 
882 			switch (radeon_encoder->encoder_id) {
883 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
884 				args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
885 				break;
886 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
887 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
888 				args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
889 				break;
890 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
891 				args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
892 				break;
893 			}
894 			if (dig->linkb)
895 				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
896 			else
897 				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
898 
899 			if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
900 				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
901 
902 			break;
903 		case 2:
904 		case 3:
905 			args.v3.ucAction = action;
906 			args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
907 			if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
908 				args.v3.ucPanelMode = panel_mode;
909 			else
910 				args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
911 
912 			if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
913 				args.v3.ucLaneNum = dp_lane_count;
914 			else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
915 				args.v3.ucLaneNum = 8;
916 			else
917 				args.v3.ucLaneNum = 4;
918 
919 			if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
920 				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
921 			if (enc_override != -1)
922 				args.v3.acConfig.ucDigSel = enc_override;
923 			else
924 				args.v3.acConfig.ucDigSel = dig->dig_encoder;
925 			args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
926 			break;
927 		case 4:
928 			args.v4.ucAction = action;
929 			args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
930 			if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
931 				args.v4.ucPanelMode = panel_mode;
932 			else
933 				args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
934 
935 			if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
936 				args.v4.ucLaneNum = dp_lane_count;
937 			else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
938 				args.v4.ucLaneNum = 8;
939 			else
940 				args.v4.ucLaneNum = 4;
941 
942 			if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
943 				if (dp_clock == 540000)
944 					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
945 				else if (dp_clock == 324000)
946 					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
947 				else if (dp_clock == 270000)
948 					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
949 				else
950 					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
951 			}
952 
953 			if (enc_override != -1)
954 				args.v4.acConfig.ucDigSel = enc_override;
955 			else
956 				args.v4.acConfig.ucDigSel = dig->dig_encoder;
957 			args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
958 			if (hpd_id == RADEON_HPD_NONE)
959 				args.v4.ucHPD_ID = 0;
960 			else
961 				args.v4.ucHPD_ID = hpd_id + 1;
962 			break;
963 		default:
964 			DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
965 			break;
966 		}
967 		break;
968 	default:
969 		DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
970 		break;
971 	}
972 
973 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
974 
975 }
976 
977 void
978 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
979 {
980 	atombios_dig_encoder_setup2(encoder, action, panel_mode, -1);
981 }
982 
983 union dig_transmitter_control {
984 	DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
985 	DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
986 	DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
987 	DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
988 	DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
989 };
990 
991 void
992 atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe)
993 {
994 	struct drm_device *dev = encoder->dev;
995 	struct radeon_device *rdev = dev->dev_private;
996 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
997 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
998 	struct drm_connector *connector;
999 	union dig_transmitter_control args;
1000 	int index = 0;
1001 	uint8_t frev, crev;
1002 	bool is_dp = false;
1003 	int pll_id = 0;
1004 	int dp_clock = 0;
1005 	int dp_lane_count = 0;
1006 	int connector_object_id = 0;
1007 	int igp_lane_info = 0;
1008 	int dig_encoder = dig->dig_encoder;
1009 	int hpd_id = RADEON_HPD_NONE;
1010 
1011 	if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1012 		connector = radeon_get_connector_for_encoder_init(encoder);
1013 		/* just needed to avoid bailing in the encoder check.  the encoder
1014 		 * isn't used for init
1015 		 */
1016 		dig_encoder = 0;
1017 	} else
1018 		connector = radeon_get_connector_for_encoder(encoder);
1019 
1020 	if (connector) {
1021 		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1022 		struct radeon_connector_atom_dig *dig_connector =
1023 			radeon_connector->con_priv;
1024 
1025 		hpd_id = radeon_connector->hpd.hpd;
1026 		dp_clock = dig_connector->dp_clock;
1027 		dp_lane_count = dig_connector->dp_lane_count;
1028 		connector_object_id =
1029 			(radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1030 		igp_lane_info = dig_connector->igp_lane_info;
1031 	}
1032 
1033 	if (encoder->crtc) {
1034 		struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1035 		pll_id = radeon_crtc->pll_id;
1036 	}
1037 
1038 	/* no dig encoder assigned */
1039 	if (dig_encoder == -1)
1040 		return;
1041 
1042 	if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1043 		is_dp = true;
1044 
1045 	memset(&args, 0, sizeof(args));
1046 
1047 	switch (radeon_encoder->encoder_id) {
1048 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1049 		index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1050 		break;
1051 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1052 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1053 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1054 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1055 		index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1056 		break;
1057 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1058 		index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1059 		break;
1060 	}
1061 
1062 	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1063 		return;
1064 
1065 	switch (frev) {
1066 	case 1:
1067 		switch (crev) {
1068 		case 1:
1069 			args.v1.ucAction = action;
1070 			if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1071 				args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1072 			} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1073 				args.v1.asMode.ucLaneSel = lane_num;
1074 				args.v1.asMode.ucLaneSet = lane_set;
1075 			} else {
1076 				if (is_dp)
1077 					args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1078 				else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1079 					args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1080 				else
1081 					args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1082 			}
1083 
1084 			args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1085 
1086 			if (dig_encoder)
1087 				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1088 			else
1089 				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1090 
1091 			if ((rdev->flags & RADEON_IS_IGP) &&
1092 			    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1093 				if (is_dp ||
1094 				    !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1095 					if (igp_lane_info & 0x1)
1096 						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1097 					else if (igp_lane_info & 0x2)
1098 						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1099 					else if (igp_lane_info & 0x4)
1100 						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1101 					else if (igp_lane_info & 0x8)
1102 						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1103 				} else {
1104 					if (igp_lane_info & 0x3)
1105 						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1106 					else if (igp_lane_info & 0xc)
1107 						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1108 				}
1109 			}
1110 
1111 			if (dig->linkb)
1112 				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1113 			else
1114 				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1115 
1116 			if (is_dp)
1117 				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1118 			else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1119 				if (dig->coherent_mode)
1120 					args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1121 				if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1122 					args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1123 			}
1124 			break;
1125 		case 2:
1126 			args.v2.ucAction = action;
1127 			if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1128 				args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1129 			} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1130 				args.v2.asMode.ucLaneSel = lane_num;
1131 				args.v2.asMode.ucLaneSet = lane_set;
1132 			} else {
1133 				if (is_dp)
1134 					args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1135 				else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1136 					args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1137 				else
1138 					args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1139 			}
1140 
1141 			args.v2.acConfig.ucEncoderSel = dig_encoder;
1142 			if (dig->linkb)
1143 				args.v2.acConfig.ucLinkSel = 1;
1144 
1145 			switch (radeon_encoder->encoder_id) {
1146 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1147 				args.v2.acConfig.ucTransmitterSel = 0;
1148 				break;
1149 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1150 				args.v2.acConfig.ucTransmitterSel = 1;
1151 				break;
1152 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1153 				args.v2.acConfig.ucTransmitterSel = 2;
1154 				break;
1155 			}
1156 
1157 			if (is_dp) {
1158 				args.v2.acConfig.fCoherentMode = 1;
1159 				args.v2.acConfig.fDPConnector = 1;
1160 			} else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1161 				if (dig->coherent_mode)
1162 					args.v2.acConfig.fCoherentMode = 1;
1163 				if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1164 					args.v2.acConfig.fDualLinkConnector = 1;
1165 			}
1166 			break;
1167 		case 3:
1168 			args.v3.ucAction = action;
1169 			if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1170 				args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1171 			} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1172 				args.v3.asMode.ucLaneSel = lane_num;
1173 				args.v3.asMode.ucLaneSet = lane_set;
1174 			} else {
1175 				if (is_dp)
1176 					args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1177 				else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1178 					args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1179 				else
1180 					args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1181 			}
1182 
1183 			if (is_dp)
1184 				args.v3.ucLaneNum = dp_lane_count;
1185 			else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1186 				args.v3.ucLaneNum = 8;
1187 			else
1188 				args.v3.ucLaneNum = 4;
1189 
1190 			if (dig->linkb)
1191 				args.v3.acConfig.ucLinkSel = 1;
1192 			if (dig_encoder & 1)
1193 				args.v3.acConfig.ucEncoderSel = 1;
1194 
1195 			/* Select the PLL for the PHY
1196 			 * DP PHY should be clocked from external src if there is
1197 			 * one.
1198 			 */
1199 			/* On DCE4, if there is an external clock, it generates the DP ref clock */
1200 			if (is_dp && rdev->clock.dp_extclk)
1201 				args.v3.acConfig.ucRefClkSource = 2; /* external src */
1202 			else
1203 				args.v3.acConfig.ucRefClkSource = pll_id;
1204 
1205 			switch (radeon_encoder->encoder_id) {
1206 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1207 				args.v3.acConfig.ucTransmitterSel = 0;
1208 				break;
1209 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1210 				args.v3.acConfig.ucTransmitterSel = 1;
1211 				break;
1212 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1213 				args.v3.acConfig.ucTransmitterSel = 2;
1214 				break;
1215 			}
1216 
1217 			if (is_dp)
1218 				args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1219 			else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1220 				if (dig->coherent_mode)
1221 					args.v3.acConfig.fCoherentMode = 1;
1222 				if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1223 					args.v3.acConfig.fDualLinkConnector = 1;
1224 			}
1225 			break;
1226 		case 4:
1227 			args.v4.ucAction = action;
1228 			if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1229 				args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1230 			} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1231 				args.v4.asMode.ucLaneSel = lane_num;
1232 				args.v4.asMode.ucLaneSet = lane_set;
1233 			} else {
1234 				if (is_dp)
1235 					args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1236 				else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1237 					args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1238 				else
1239 					args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1240 			}
1241 
1242 			if (is_dp)
1243 				args.v4.ucLaneNum = dp_lane_count;
1244 			else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1245 				args.v4.ucLaneNum = 8;
1246 			else
1247 				args.v4.ucLaneNum = 4;
1248 
1249 			if (dig->linkb)
1250 				args.v4.acConfig.ucLinkSel = 1;
1251 			if (dig_encoder & 1)
1252 				args.v4.acConfig.ucEncoderSel = 1;
1253 
1254 			/* Select the PLL for the PHY
1255 			 * DP PHY should be clocked from external src if there is
1256 			 * one.
1257 			 */
1258 			/* On DCE5 DCPLL usually generates the DP ref clock */
1259 			if (is_dp) {
1260 				if (rdev->clock.dp_extclk)
1261 					args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1262 				else
1263 					args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1264 			} else
1265 				args.v4.acConfig.ucRefClkSource = pll_id;
1266 
1267 			switch (radeon_encoder->encoder_id) {
1268 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1269 				args.v4.acConfig.ucTransmitterSel = 0;
1270 				break;
1271 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1272 				args.v4.acConfig.ucTransmitterSel = 1;
1273 				break;
1274 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1275 				args.v4.acConfig.ucTransmitterSel = 2;
1276 				break;
1277 			}
1278 
1279 			if (is_dp)
1280 				args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1281 			else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1282 				if (dig->coherent_mode)
1283 					args.v4.acConfig.fCoherentMode = 1;
1284 				if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1285 					args.v4.acConfig.fDualLinkConnector = 1;
1286 			}
1287 			break;
1288 		case 5:
1289 			args.v5.ucAction = action;
1290 			if (is_dp)
1291 				args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1292 			else
1293 				args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1294 
1295 			switch (radeon_encoder->encoder_id) {
1296 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1297 				if (dig->linkb)
1298 					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1299 				else
1300 					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1301 				break;
1302 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1303 				if (dig->linkb)
1304 					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1305 				else
1306 					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1307 				break;
1308 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1309 				if (dig->linkb)
1310 					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1311 				else
1312 					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1313 				break;
1314 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1315 				args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1316 				break;
1317 			}
1318 			if (is_dp)
1319 				args.v5.ucLaneNum = dp_lane_count;
1320 			else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1321 				args.v5.ucLaneNum = 8;
1322 			else
1323 				args.v5.ucLaneNum = 4;
1324 			args.v5.ucConnObjId = connector_object_id;
1325 			args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1326 
1327 			if (is_dp && rdev->clock.dp_extclk)
1328 				args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1329 			else
1330 				args.v5.asConfig.ucPhyClkSrcId = pll_id;
1331 
1332 			if (is_dp)
1333 				args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1334 			else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1335 				if (dig->coherent_mode)
1336 					args.v5.asConfig.ucCoherentMode = 1;
1337 			}
1338 			if (hpd_id == RADEON_HPD_NONE)
1339 				args.v5.asConfig.ucHPDSel = 0;
1340 			else
1341 				args.v5.asConfig.ucHPDSel = hpd_id + 1;
1342 			args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder);
1343 			args.v5.ucDPLaneSet = lane_set;
1344 			break;
1345 		default:
1346 			DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1347 			break;
1348 		}
1349 		break;
1350 	default:
1351 		DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1352 		break;
1353 	}
1354 
1355 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1356 }
1357 
1358 void
1359 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
1360 {
1361 	atombios_dig_transmitter_setup2(encoder, action, lane_num, lane_set, -1);
1362 }
1363 
1364 bool
1365 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1366 {
1367 	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1368 	struct drm_device *dev = radeon_connector->base.dev;
1369 	struct radeon_device *rdev = dev->dev_private;
1370 	union dig_transmitter_control args;
1371 	int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1372 	uint8_t frev, crev;
1373 
1374 	if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1375 		goto done;
1376 
1377 	if (!ASIC_IS_DCE4(rdev))
1378 		goto done;
1379 
1380 	if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1381 	    (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1382 		goto done;
1383 
1384 	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1385 		goto done;
1386 
1387 	memset(&args, 0, sizeof(args));
1388 
1389 	args.v1.ucAction = action;
1390 
1391 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1392 
1393 	/* wait for the panel to power up */
1394 	if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1395 		int i;
1396 
1397 		for (i = 0; i < 300; i++) {
1398 			if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1399 				return true;
1400 			mdelay(1);
1401 		}
1402 		return false;
1403 	}
1404 done:
1405 	return true;
1406 }
1407 
1408 union external_encoder_control {
1409 	EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1410 	EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1411 };
1412 
1413 static void
1414 atombios_external_encoder_setup(struct drm_encoder *encoder,
1415 				struct drm_encoder *ext_encoder,
1416 				int action)
1417 {
1418 	struct drm_device *dev = encoder->dev;
1419 	struct radeon_device *rdev = dev->dev_private;
1420 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1421 	struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1422 	union external_encoder_control args;
1423 	struct drm_connector *connector;
1424 	int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1425 	u8 frev, crev;
1426 	int dp_clock = 0;
1427 	int dp_lane_count = 0;
1428 	int connector_object_id = 0;
1429 	u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1430 
1431 	if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1432 		connector = radeon_get_connector_for_encoder_init(encoder);
1433 	else
1434 		connector = radeon_get_connector_for_encoder(encoder);
1435 
1436 	if (connector) {
1437 		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1438 		struct radeon_connector_atom_dig *dig_connector =
1439 			radeon_connector->con_priv;
1440 
1441 		dp_clock = dig_connector->dp_clock;
1442 		dp_lane_count = dig_connector->dp_lane_count;
1443 		connector_object_id =
1444 			(radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1445 	}
1446 
1447 	memset(&args, 0, sizeof(args));
1448 
1449 	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1450 		return;
1451 
1452 	switch (frev) {
1453 	case 1:
1454 		/* no params on frev 1 */
1455 		break;
1456 	case 2:
1457 		switch (crev) {
1458 		case 1:
1459 		case 2:
1460 			args.v1.sDigEncoder.ucAction = action;
1461 			args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1462 			args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1463 
1464 			if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1465 				if (dp_clock == 270000)
1466 					args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1467 				args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1468 			} else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1469 				args.v1.sDigEncoder.ucLaneNum = 8;
1470 			else
1471 				args.v1.sDigEncoder.ucLaneNum = 4;
1472 			break;
1473 		case 3:
1474 			args.v3.sExtEncoder.ucAction = action;
1475 			if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1476 				args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1477 			else
1478 				args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1479 			args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1480 
1481 			if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1482 				if (dp_clock == 270000)
1483 					args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1484 				else if (dp_clock == 540000)
1485 					args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1486 				args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1487 			} else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1488 				args.v3.sExtEncoder.ucLaneNum = 8;
1489 			else
1490 				args.v3.sExtEncoder.ucLaneNum = 4;
1491 			switch (ext_enum) {
1492 			case GRAPH_OBJECT_ENUM_ID1:
1493 				args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1494 				break;
1495 			case GRAPH_OBJECT_ENUM_ID2:
1496 				args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1497 				break;
1498 			case GRAPH_OBJECT_ENUM_ID3:
1499 				args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1500 				break;
1501 			}
1502 			args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1503 			break;
1504 		default:
1505 			DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1506 			return;
1507 		}
1508 		break;
1509 	default:
1510 		DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1511 		return;
1512 	}
1513 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1514 }
1515 
1516 static void
1517 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1518 {
1519 	struct drm_device *dev = encoder->dev;
1520 	struct radeon_device *rdev = dev->dev_private;
1521 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1522 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1523 	ENABLE_YUV_PS_ALLOCATION args;
1524 	int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1525 	uint32_t temp, reg;
1526 
1527 	memset(&args, 0, sizeof(args));
1528 
1529 	if (rdev->family >= CHIP_R600)
1530 		reg = R600_BIOS_3_SCRATCH;
1531 	else
1532 		reg = RADEON_BIOS_3_SCRATCH;
1533 
1534 	/* XXX: fix up scratch reg handling */
1535 	temp = RREG32(reg);
1536 	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1537 		WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1538 			     (radeon_crtc->crtc_id << 18)));
1539 	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1540 		WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1541 	else
1542 		WREG32(reg, 0);
1543 
1544 	if (enable)
1545 		args.ucEnable = ATOM_ENABLE;
1546 	args.ucCRTC = radeon_crtc->crtc_id;
1547 
1548 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1549 
1550 	WREG32(reg, temp);
1551 }
1552 
1553 static void
1554 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1555 {
1556 	struct drm_device *dev = encoder->dev;
1557 	struct radeon_device *rdev = dev->dev_private;
1558 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1559 	DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1560 	int index = 0;
1561 
1562 	memset(&args, 0, sizeof(args));
1563 
1564 	switch (radeon_encoder->encoder_id) {
1565 	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1566 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1567 		index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1568 		break;
1569 	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1570 	case ENCODER_OBJECT_ID_INTERNAL_DDI:
1571 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1572 		index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1573 		break;
1574 	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1575 		index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1576 		break;
1577 	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1578 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1579 			index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1580 		else
1581 			index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1582 		break;
1583 	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1584 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1585 		if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1586 			index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1587 		else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1588 			index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1589 		else
1590 			index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1591 		break;
1592 	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1593 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1594 		if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1595 			index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1596 		else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1597 			index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1598 		else
1599 			index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1600 		break;
1601 	default:
1602 		return;
1603 	}
1604 
1605 	switch (mode) {
1606 	case DRM_MODE_DPMS_ON:
1607 		args.ucAction = ATOM_ENABLE;
1608 		/* workaround for DVOOutputControl on some RS690 systems */
1609 		if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1610 			u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1611 			WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1612 			atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1613 			WREG32(RADEON_BIOS_3_SCRATCH, reg);
1614 		} else
1615 			atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1616 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1617 			if (rdev->mode_info.bl_encoder) {
1618 				struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1619 
1620 				atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1621 			} else {
1622 				args.ucAction = ATOM_LCD_BLON;
1623 				atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1624 			}
1625 		}
1626 		break;
1627 	case DRM_MODE_DPMS_STANDBY:
1628 	case DRM_MODE_DPMS_SUSPEND:
1629 	case DRM_MODE_DPMS_OFF:
1630 		args.ucAction = ATOM_DISABLE;
1631 		atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1632 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1633 			args.ucAction = ATOM_LCD_BLOFF;
1634 			atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1635 		}
1636 		break;
1637 	}
1638 }
1639 
1640 static void
1641 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1642 {
1643 	struct drm_device *dev = encoder->dev;
1644 	struct radeon_device *rdev = dev->dev_private;
1645 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1646 	struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1647 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1648 	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1649 	struct radeon_connector *radeon_connector = NULL;
1650 	struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1651 	bool travis_quirk = false;
1652 
1653 	if (connector) {
1654 		radeon_connector = to_radeon_connector(connector);
1655 		radeon_dig_connector = radeon_connector->con_priv;
1656 		if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
1657 		     ENCODER_OBJECT_ID_TRAVIS) &&
1658 		    (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
1659 		    !ASIC_IS_DCE5(rdev))
1660 			travis_quirk = true;
1661 	}
1662 
1663 	switch (mode) {
1664 	case DRM_MODE_DPMS_ON:
1665 		if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1666 			if (!connector)
1667 				dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1668 			else
1669 				dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1670 
1671 			/* setup and enable the encoder */
1672 			atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1673 			atombios_dig_encoder_setup(encoder,
1674 						   ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1675 						   dig->panel_mode);
1676 			if (ext_encoder) {
1677 				if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1678 					atombios_external_encoder_setup(encoder, ext_encoder,
1679 									EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1680 			}
1681 		} else if (ASIC_IS_DCE4(rdev)) {
1682 			/* setup and enable the encoder */
1683 			atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1684 		} else {
1685 			/* setup and enable the encoder and transmitter */
1686 			atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1687 			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1688 		}
1689 		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1690 			if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1691 				atombios_set_edp_panel_power(connector,
1692 							     ATOM_TRANSMITTER_ACTION_POWER_ON);
1693 				radeon_dig_connector->edp_on = true;
1694 			}
1695 		}
1696 		/* enable the transmitter */
1697 		atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1698 		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1699 			/* DP_SET_POWER_D0 is set in radeon_dp_link_train */
1700 			radeon_dp_link_train(encoder, connector);
1701 			if (ASIC_IS_DCE4(rdev))
1702 				atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1703 		}
1704 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1705 			if (rdev->mode_info.bl_encoder)
1706 				atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1707 			else
1708 				atombios_dig_transmitter_setup(encoder,
1709 							       ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1710 		}
1711 		if (ext_encoder)
1712 			atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1713 		break;
1714 	case DRM_MODE_DPMS_STANDBY:
1715 	case DRM_MODE_DPMS_SUSPEND:
1716 	case DRM_MODE_DPMS_OFF:
1717 
1718 		if (ASIC_IS_DCE4(rdev)) {
1719 			if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector)
1720 				atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1721 		}
1722 		if (ext_encoder)
1723 			atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1724 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1725 			atombios_dig_transmitter_setup(encoder,
1726 						       ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1727 
1728 		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) &&
1729 		    connector && !travis_quirk)
1730 			radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1731 		if (ASIC_IS_DCE4(rdev)) {
1732 			/* disable the transmitter */
1733 			atombios_dig_transmitter_setup(encoder,
1734 						       ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1735 		} else {
1736 			/* disable the encoder and transmitter */
1737 			atombios_dig_transmitter_setup(encoder,
1738 						       ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1739 			atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1740 		}
1741 		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1742 			if (travis_quirk)
1743 				radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1744 			if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1745 				atombios_set_edp_panel_power(connector,
1746 							     ATOM_TRANSMITTER_ACTION_POWER_OFF);
1747 				radeon_dig_connector->edp_on = false;
1748 			}
1749 		}
1750 		break;
1751 	}
1752 }
1753 
1754 static void
1755 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1756 {
1757 	struct drm_device *dev = encoder->dev;
1758 	struct radeon_device *rdev = dev->dev_private;
1759 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1760 	int encoder_mode = atombios_get_encoder_mode(encoder);
1761 
1762 	DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1763 		  radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1764 		  radeon_encoder->active_device);
1765 
1766 	if ((radeon_audio != 0) &&
1767 	    ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
1768 	     ENCODER_MODE_IS_DP(encoder_mode)))
1769 		radeon_audio_dpms(encoder, mode);
1770 
1771 	switch (radeon_encoder->encoder_id) {
1772 	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1773 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1774 	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1775 	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1776 	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1777 	case ENCODER_OBJECT_ID_INTERNAL_DDI:
1778 	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1779 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1780 		radeon_atom_encoder_dpms_avivo(encoder, mode);
1781 		break;
1782 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1783 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1784 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1785 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1786 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1787 		radeon_atom_encoder_dpms_dig(encoder, mode);
1788 		break;
1789 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1790 		if (ASIC_IS_DCE5(rdev)) {
1791 			switch (mode) {
1792 			case DRM_MODE_DPMS_ON:
1793 				atombios_dvo_setup(encoder, ATOM_ENABLE);
1794 				break;
1795 			case DRM_MODE_DPMS_STANDBY:
1796 			case DRM_MODE_DPMS_SUSPEND:
1797 			case DRM_MODE_DPMS_OFF:
1798 				atombios_dvo_setup(encoder, ATOM_DISABLE);
1799 				break;
1800 			}
1801 		} else if (ASIC_IS_DCE3(rdev))
1802 			radeon_atom_encoder_dpms_dig(encoder, mode);
1803 		else
1804 			radeon_atom_encoder_dpms_avivo(encoder, mode);
1805 		break;
1806 	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1807 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1808 		if (ASIC_IS_DCE5(rdev)) {
1809 			switch (mode) {
1810 			case DRM_MODE_DPMS_ON:
1811 				atombios_dac_setup(encoder, ATOM_ENABLE);
1812 				break;
1813 			case DRM_MODE_DPMS_STANDBY:
1814 			case DRM_MODE_DPMS_SUSPEND:
1815 			case DRM_MODE_DPMS_OFF:
1816 				atombios_dac_setup(encoder, ATOM_DISABLE);
1817 				break;
1818 			}
1819 		} else
1820 			radeon_atom_encoder_dpms_avivo(encoder, mode);
1821 		break;
1822 	default:
1823 		return;
1824 	}
1825 
1826 	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1827 
1828 }
1829 
1830 union crtc_source_param {
1831 	SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1832 	SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1833 };
1834 
1835 static void
1836 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1837 {
1838 	struct drm_device *dev = encoder->dev;
1839 	struct radeon_device *rdev = dev->dev_private;
1840 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1841 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1842 	union crtc_source_param args;
1843 	int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1844 	uint8_t frev, crev;
1845 	struct radeon_encoder_atom_dig *dig;
1846 
1847 	memset(&args, 0, sizeof(args));
1848 
1849 	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1850 		return;
1851 
1852 	switch (frev) {
1853 	case 1:
1854 		switch (crev) {
1855 		case 1:
1856 		default:
1857 			if (ASIC_IS_AVIVO(rdev))
1858 				args.v1.ucCRTC = radeon_crtc->crtc_id;
1859 			else {
1860 				if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1)
1861 					args.v1.ucCRTC = radeon_crtc->crtc_id;
1862 				else
1863 					args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1864 			}
1865 			switch (radeon_encoder->encoder_id) {
1866 			case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1867 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1868 				args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1869 				break;
1870 			case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1871 			case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1872 				if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1873 					args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1874 				else
1875 					args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1876 				break;
1877 			case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1878 			case ENCODER_OBJECT_ID_INTERNAL_DDI:
1879 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1880 				args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1881 				break;
1882 			case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1883 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1884 				if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1885 					args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1886 				else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1887 					args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1888 				else
1889 					args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1890 				break;
1891 			case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1892 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1893 				if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1894 					args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1895 				else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1896 					args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1897 				else
1898 					args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1899 				break;
1900 			}
1901 			break;
1902 		case 2:
1903 			args.v2.ucCRTC = radeon_crtc->crtc_id;
1904 			if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1905 				struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1906 
1907 				if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1908 					args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1909 				else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1910 					args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1911 				else
1912 					args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1913 			} else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1914 				args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1915 			} else {
1916 				args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1917 			}
1918 			switch (radeon_encoder->encoder_id) {
1919 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1920 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1921 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1922 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1923 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1924 				dig = radeon_encoder->enc_priv;
1925 				switch (dig->dig_encoder) {
1926 				case 0:
1927 					args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1928 					break;
1929 				case 1:
1930 					args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1931 					break;
1932 				case 2:
1933 					args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1934 					break;
1935 				case 3:
1936 					args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1937 					break;
1938 				case 4:
1939 					args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1940 					break;
1941 				case 5:
1942 					args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1943 					break;
1944 				case 6:
1945 					args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1946 					break;
1947 				}
1948 				break;
1949 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1950 				args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1951 				break;
1952 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1953 				if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1954 					args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1955 				else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1956 					args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1957 				else
1958 					args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1959 				break;
1960 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1961 				if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1962 					args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1963 				else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1964 					args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1965 				else
1966 					args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1967 				break;
1968 			}
1969 			break;
1970 		}
1971 		break;
1972 	default:
1973 		DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1974 		return;
1975 	}
1976 
1977 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1978 
1979 	/* update scratch regs with new routing */
1980 	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1981 }
1982 
1983 static void
1984 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1985 			      struct drm_display_mode *mode)
1986 {
1987 	struct drm_device *dev = encoder->dev;
1988 	struct radeon_device *rdev = dev->dev_private;
1989 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1990 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1991 
1992 	/* Funky macbooks */
1993 	if ((rdev->pdev->device == 0x71C5) &&
1994 	    (rdev->pdev->subsystem_vendor == 0x106b) &&
1995 	    (rdev->pdev->subsystem_device == 0x0080)) {
1996 		if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1997 			uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1998 
1999 			lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
2000 			lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
2001 
2002 			WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
2003 		}
2004 	}
2005 
2006 	/* set scaler clears this on some chips */
2007 	if (ASIC_IS_AVIVO(rdev) &&
2008 	    (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
2009 		if (ASIC_IS_DCE8(rdev)) {
2010 			if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2011 				WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
2012 				       CIK_INTERLEAVE_EN);
2013 			else
2014 				WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2015 		} else if (ASIC_IS_DCE4(rdev)) {
2016 			if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2017 				WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
2018 				       EVERGREEN_INTERLEAVE_EN);
2019 			else
2020 				WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2021 		} else {
2022 			if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2023 				WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
2024 				       AVIVO_D1MODE_INTERLEAVE_EN);
2025 			else
2026 				WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2027 		}
2028 	}
2029 }
2030 
2031 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx)
2032 {
2033 	if (enc_idx < 0)
2034 		return;
2035 	rdev->mode_info.active_encoders &= ~(1 << enc_idx);
2036 }
2037 
2038 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx)
2039 {
2040 	struct drm_device *dev = encoder->dev;
2041 	struct radeon_device *rdev = dev->dev_private;
2042 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2043 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2044 	struct drm_encoder *test_encoder;
2045 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2046 	uint32_t dig_enc_in_use = 0;
2047 	int enc_idx = -1;
2048 
2049 	if (fe_idx >= 0) {
2050 		enc_idx = fe_idx;
2051 		goto assigned;
2052 	}
2053 	if (ASIC_IS_DCE6(rdev)) {
2054 		/* DCE6 */
2055 		switch (radeon_encoder->encoder_id) {
2056 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2057 			if (dig->linkb)
2058 				enc_idx = 1;
2059 			else
2060 				enc_idx = 0;
2061 			break;
2062 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2063 			if (dig->linkb)
2064 				enc_idx = 3;
2065 			else
2066 				enc_idx = 2;
2067 			break;
2068 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2069 			if (dig->linkb)
2070 				enc_idx = 5;
2071 			else
2072 				enc_idx = 4;
2073 			break;
2074 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2075 			enc_idx = 6;
2076 			break;
2077 		}
2078 		goto assigned;
2079 	} else if (ASIC_IS_DCE4(rdev)) {
2080 		/* DCE4/5 */
2081 		if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2082 			/* ontario follows DCE4 */
2083 			if (rdev->family == CHIP_PALM) {
2084 				if (dig->linkb)
2085 					enc_idx = 1;
2086 				else
2087 					enc_idx = 0;
2088 			} else
2089 				/* llano follows DCE3.2 */
2090 				enc_idx = radeon_crtc->crtc_id;
2091 		} else {
2092 			switch (radeon_encoder->encoder_id) {
2093 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2094 				if (dig->linkb)
2095 					enc_idx = 1;
2096 				else
2097 					enc_idx = 0;
2098 				break;
2099 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2100 				if (dig->linkb)
2101 					enc_idx = 3;
2102 				else
2103 					enc_idx = 2;
2104 				break;
2105 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2106 				if (dig->linkb)
2107 					enc_idx = 5;
2108 				else
2109 					enc_idx = 4;
2110 				break;
2111 			}
2112 		}
2113 		goto assigned;
2114 	}
2115 
2116 	/*
2117 	 * On DCE32 any encoder can drive any block so usually just use crtc id,
2118 	 * but Apple thinks different at least on iMac10,1, so there use linkb,
2119 	 * otherwise the internal eDP panel will stay dark.
2120 	 */
2121 	if (ASIC_IS_DCE32(rdev)) {
2122 		if (dmi_match(DMI_PRODUCT_NAME, "iMac10,1"))
2123 			enc_idx = (dig->linkb) ? 1 : 0;
2124 		else
2125 			enc_idx = radeon_crtc->crtc_id;
2126 
2127 		goto assigned;
2128 	}
2129 
2130 	/* on DCE3 - LVTMA can only be driven by DIGB */
2131 	list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2132 		struct radeon_encoder *radeon_test_encoder;
2133 
2134 		if (encoder == test_encoder)
2135 			continue;
2136 
2137 		if (!radeon_encoder_is_digital(test_encoder))
2138 			continue;
2139 
2140 		radeon_test_encoder = to_radeon_encoder(test_encoder);
2141 		dig = radeon_test_encoder->enc_priv;
2142 
2143 		if (dig->dig_encoder >= 0)
2144 			dig_enc_in_use |= (1 << dig->dig_encoder);
2145 	}
2146 
2147 	if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2148 		if (dig_enc_in_use & 0x2)
2149 			DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2150 		return 1;
2151 	}
2152 	if (!(dig_enc_in_use & 1))
2153 		return 0;
2154 	return 1;
2155 
2156 assigned:
2157 	if (enc_idx == -1) {
2158 		DRM_ERROR("Got encoder index incorrect - returning 0\n");
2159 		return 0;
2160 	}
2161 	if (rdev->mode_info.active_encoders & (1 << enc_idx))
2162 		DRM_ERROR("chosen encoder in use %d\n", enc_idx);
2163 
2164 	rdev->mode_info.active_encoders |= (1 << enc_idx);
2165 	return enc_idx;
2166 }
2167 
2168 /* This only needs to be called once at startup */
2169 void
2170 radeon_atom_encoder_init(struct radeon_device *rdev)
2171 {
2172 	struct drm_device *dev = rdev->ddev;
2173 	struct drm_encoder *encoder;
2174 
2175 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2176 		struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2177 		struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2178 
2179 		switch (radeon_encoder->encoder_id) {
2180 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2181 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2182 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2183 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2184 		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2185 			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2186 			break;
2187 		default:
2188 			break;
2189 		}
2190 
2191 		if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2192 			atombios_external_encoder_setup(encoder, ext_encoder,
2193 							EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2194 	}
2195 }
2196 
2197 static void
2198 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2199 			     struct drm_display_mode *mode,
2200 			     struct drm_display_mode *adjusted_mode)
2201 {
2202 	struct drm_device *dev = encoder->dev;
2203 	struct radeon_device *rdev = dev->dev_private;
2204 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2205 	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2206 	int encoder_mode;
2207 
2208 	radeon_encoder->pixel_clock = adjusted_mode->clock;
2209 
2210 	/* need to call this here rather than in prepare() since we need some crtc info */
2211 	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2212 
2213 	if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2214 		if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2215 			atombios_yuv_setup(encoder, true);
2216 		else
2217 			atombios_yuv_setup(encoder, false);
2218 	}
2219 
2220 	switch (radeon_encoder->encoder_id) {
2221 	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2222 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2223 	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2224 	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2225 		atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2226 		break;
2227 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2228 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2229 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2230 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2231 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2232 		/* handled in dpms */
2233 		break;
2234 	case ENCODER_OBJECT_ID_INTERNAL_DDI:
2235 	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2236 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2237 		atombios_dvo_setup(encoder, ATOM_ENABLE);
2238 		break;
2239 	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2240 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2241 	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2242 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2243 		atombios_dac_setup(encoder, ATOM_ENABLE);
2244 		if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2245 			if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2246 				atombios_tv_setup(encoder, ATOM_ENABLE);
2247 			else
2248 				atombios_tv_setup(encoder, ATOM_DISABLE);
2249 		}
2250 		break;
2251 	}
2252 
2253 	atombios_apply_encoder_quirks(encoder, adjusted_mode);
2254 
2255 	encoder_mode = atombios_get_encoder_mode(encoder);
2256 	if (connector && (radeon_audio != 0) &&
2257 	    ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
2258 	     ENCODER_MODE_IS_DP(encoder_mode)))
2259 		radeon_audio_mode_set(encoder, adjusted_mode);
2260 }
2261 
2262 static bool
2263 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2264 {
2265 	struct drm_device *dev = encoder->dev;
2266 	struct radeon_device *rdev = dev->dev_private;
2267 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2268 	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2269 
2270 	if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2271 				       ATOM_DEVICE_CV_SUPPORT |
2272 				       ATOM_DEVICE_CRT_SUPPORT)) {
2273 		DAC_LOAD_DETECTION_PS_ALLOCATION args;
2274 		int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2275 		uint8_t frev, crev;
2276 
2277 		memset(&args, 0, sizeof(args));
2278 
2279 		if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2280 			return false;
2281 
2282 		args.sDacload.ucMisc = 0;
2283 
2284 		if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2285 		    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2286 			args.sDacload.ucDacType = ATOM_DAC_A;
2287 		else
2288 			args.sDacload.ucDacType = ATOM_DAC_B;
2289 
2290 		if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2291 			args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2292 		else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2293 			args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2294 		else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2295 			args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2296 			if (crev >= 3)
2297 				args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2298 		} else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2299 			args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2300 			if (crev >= 3)
2301 				args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2302 		}
2303 
2304 		atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2305 
2306 		return true;
2307 	} else
2308 		return false;
2309 }
2310 
2311 static enum drm_connector_status
2312 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2313 {
2314 	struct drm_device *dev = encoder->dev;
2315 	struct radeon_device *rdev = dev->dev_private;
2316 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2317 	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2318 	uint32_t bios_0_scratch;
2319 
2320 	if (!atombios_dac_load_detect(encoder, connector)) {
2321 		DRM_DEBUG_KMS("detect returned false \n");
2322 		return connector_status_unknown;
2323 	}
2324 
2325 	if (rdev->family >= CHIP_R600)
2326 		bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2327 	else
2328 		bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2329 
2330 	DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2331 	if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2332 		if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2333 			return connector_status_connected;
2334 	}
2335 	if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2336 		if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2337 			return connector_status_connected;
2338 	}
2339 	if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2340 		if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2341 			return connector_status_connected;
2342 	}
2343 	if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2344 		if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2345 			return connector_status_connected; /* CTV */
2346 		else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2347 			return connector_status_connected; /* STV */
2348 	}
2349 	return connector_status_disconnected;
2350 }
2351 
2352 static enum drm_connector_status
2353 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2354 {
2355 	struct drm_device *dev = encoder->dev;
2356 	struct radeon_device *rdev = dev->dev_private;
2357 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2358 	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2359 	struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2360 	u32 bios_0_scratch;
2361 
2362 	if (!ASIC_IS_DCE4(rdev))
2363 		return connector_status_unknown;
2364 
2365 	if (!ext_encoder)
2366 		return connector_status_unknown;
2367 
2368 	if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2369 		return connector_status_unknown;
2370 
2371 	/* load detect on the dp bridge */
2372 	atombios_external_encoder_setup(encoder, ext_encoder,
2373 					EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2374 
2375 	bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2376 
2377 	DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2378 	if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2379 		if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2380 			return connector_status_connected;
2381 	}
2382 	if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2383 		if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2384 			return connector_status_connected;
2385 	}
2386 	if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2387 		if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2388 			return connector_status_connected;
2389 	}
2390 	if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2391 		if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2392 			return connector_status_connected; /* CTV */
2393 		else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2394 			return connector_status_connected; /* STV */
2395 	}
2396 	return connector_status_disconnected;
2397 }
2398 
2399 void
2400 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2401 {
2402 	struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2403 
2404 	if (ext_encoder)
2405 		/* ddc_setup on the dp bridge */
2406 		atombios_external_encoder_setup(encoder, ext_encoder,
2407 						EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2408 
2409 }
2410 
2411 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2412 {
2413 	struct radeon_device *rdev = encoder->dev->dev_private;
2414 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2415 	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2416 
2417 	if ((radeon_encoder->active_device &
2418 	     (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2419 	    (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2420 	     ENCODER_OBJECT_ID_NONE)) {
2421 		struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2422 		if (dig) {
2423 			if (dig->dig_encoder >= 0)
2424 				radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2425 			dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder, -1);
2426 			if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2427 				if (rdev->family >= CHIP_R600)
2428 					dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2429 				else
2430 					/* RS600/690/740 have only 1 afmt block */
2431 					dig->afmt = rdev->mode_info.afmt[0];
2432 			}
2433 		}
2434 	}
2435 
2436 	radeon_atom_output_lock(encoder, true);
2437 
2438 	if (connector) {
2439 		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2440 
2441 		/* select the clock/data port if it uses a router */
2442 		if (radeon_connector->router.cd_valid)
2443 			radeon_router_select_cd_port(radeon_connector);
2444 
2445 		/* turn eDP panel on for mode set */
2446 		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2447 			atombios_set_edp_panel_power(connector,
2448 						     ATOM_TRANSMITTER_ACTION_POWER_ON);
2449 	}
2450 
2451 	/* this is needed for the pll/ss setup to work correctly in some cases */
2452 	atombios_set_encoder_crtc_source(encoder);
2453 	/* set up the FMT blocks */
2454 	if (ASIC_IS_DCE8(rdev))
2455 		dce8_program_fmt(encoder);
2456 	else if (ASIC_IS_DCE4(rdev))
2457 		dce4_program_fmt(encoder);
2458 	else if (ASIC_IS_DCE3(rdev))
2459 		dce3_program_fmt(encoder);
2460 	else if (ASIC_IS_AVIVO(rdev))
2461 		avivo_program_fmt(encoder);
2462 }
2463 
2464 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2465 {
2466 	/* need to call this here as we need the crtc set up */
2467 	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2468 	radeon_atom_output_lock(encoder, false);
2469 }
2470 
2471 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2472 {
2473 	struct drm_device *dev = encoder->dev;
2474 	struct radeon_device *rdev = dev->dev_private;
2475 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2476 	struct radeon_encoder_atom_dig *dig;
2477 
2478 	/* check for pre-DCE3 cards with shared encoders;
2479 	 * can't really use the links individually, so don't disable
2480 	 * the encoder if it's in use by another connector
2481 	 */
2482 	if (!ASIC_IS_DCE3(rdev)) {
2483 		struct drm_encoder *other_encoder;
2484 		struct radeon_encoder *other_radeon_encoder;
2485 
2486 		list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2487 			other_radeon_encoder = to_radeon_encoder(other_encoder);
2488 			if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2489 			    drm_helper_encoder_in_use(other_encoder))
2490 				goto disable_done;
2491 		}
2492 	}
2493 
2494 	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2495 
2496 	switch (radeon_encoder->encoder_id) {
2497 	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2498 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2499 	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2500 	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2501 		atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2502 		break;
2503 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2504 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2505 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2506 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2507 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2508 		/* handled in dpms */
2509 		break;
2510 	case ENCODER_OBJECT_ID_INTERNAL_DDI:
2511 	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2512 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2513 		atombios_dvo_setup(encoder, ATOM_DISABLE);
2514 		break;
2515 	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2516 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2517 	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2518 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2519 		atombios_dac_setup(encoder, ATOM_DISABLE);
2520 		if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2521 			atombios_tv_setup(encoder, ATOM_DISABLE);
2522 		break;
2523 	}
2524 
2525 disable_done:
2526 	if (radeon_encoder_is_digital(encoder)) {
2527 		if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2528 			if (rdev->asic->display.hdmi_enable)
2529 				radeon_hdmi_enable(rdev, encoder, false);
2530 		}
2531 		if (atombios_get_encoder_mode(encoder) != ATOM_ENCODER_MODE_DP_MST) {
2532 			dig = radeon_encoder->enc_priv;
2533 			radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2534 			dig->dig_encoder = -1;
2535 			radeon_encoder->active_device = 0;
2536 		}
2537 	} else
2538 		radeon_encoder->active_device = 0;
2539 }
2540 
2541 /* these are handled by the primary encoders */
2542 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2543 {
2544 
2545 }
2546 
2547 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2548 {
2549 
2550 }
2551 
2552 static void
2553 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2554 			 struct drm_display_mode *mode,
2555 			 struct drm_display_mode *adjusted_mode)
2556 {
2557 
2558 }
2559 
2560 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2561 {
2562 
2563 }
2564 
2565 static void
2566 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2567 {
2568 
2569 }
2570 
2571 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2572 	.dpms = radeon_atom_ext_dpms,
2573 	.prepare = radeon_atom_ext_prepare,
2574 	.mode_set = radeon_atom_ext_mode_set,
2575 	.commit = radeon_atom_ext_commit,
2576 	.disable = radeon_atom_ext_disable,
2577 	/* no detect for TMDS/LVDS yet */
2578 };
2579 
2580 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2581 	.dpms = radeon_atom_encoder_dpms,
2582 	.mode_fixup = radeon_atom_mode_fixup,
2583 	.prepare = radeon_atom_encoder_prepare,
2584 	.mode_set = radeon_atom_encoder_mode_set,
2585 	.commit = radeon_atom_encoder_commit,
2586 	.disable = radeon_atom_encoder_disable,
2587 	.detect = radeon_atom_dig_detect,
2588 };
2589 
2590 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2591 	.dpms = radeon_atom_encoder_dpms,
2592 	.mode_fixup = radeon_atom_mode_fixup,
2593 	.prepare = radeon_atom_encoder_prepare,
2594 	.mode_set = radeon_atom_encoder_mode_set,
2595 	.commit = radeon_atom_encoder_commit,
2596 	.detect = radeon_atom_dac_detect,
2597 };
2598 
2599 void radeon_enc_destroy(struct drm_encoder *encoder)
2600 {
2601 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2602 	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2603 		radeon_atom_backlight_exit(radeon_encoder);
2604 	kfree(radeon_encoder->enc_priv);
2605 	drm_encoder_cleanup(encoder);
2606 	kfree(radeon_encoder);
2607 }
2608 
2609 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2610 	.destroy = radeon_enc_destroy,
2611 };
2612 
2613 static struct radeon_encoder_atom_dac *
2614 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2615 {
2616 	struct drm_device *dev = radeon_encoder->base.dev;
2617 	struct radeon_device *rdev = dev->dev_private;
2618 	struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2619 
2620 	if (!dac)
2621 		return NULL;
2622 
2623 	dac->tv_std = radeon_atombios_get_tv_info(rdev);
2624 	return dac;
2625 }
2626 
2627 static struct radeon_encoder_atom_dig *
2628 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2629 {
2630 	int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2631 	struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2632 
2633 	if (!dig)
2634 		return NULL;
2635 
2636 	/* coherent mode by default */
2637 	dig->coherent_mode = true;
2638 	dig->dig_encoder = -1;
2639 
2640 	if (encoder_enum == 2)
2641 		dig->linkb = true;
2642 	else
2643 		dig->linkb = false;
2644 
2645 	return dig;
2646 }
2647 
2648 void
2649 radeon_add_atom_encoder(struct drm_device *dev,
2650 			uint32_t encoder_enum,
2651 			uint32_t supported_device,
2652 			u16 caps)
2653 {
2654 	struct radeon_device *rdev = dev->dev_private;
2655 	struct drm_encoder *encoder;
2656 	struct radeon_encoder *radeon_encoder;
2657 
2658 	/* see if we already added it */
2659 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2660 		radeon_encoder = to_radeon_encoder(encoder);
2661 		if (radeon_encoder->encoder_enum == encoder_enum) {
2662 			radeon_encoder->devices |= supported_device;
2663 			return;
2664 		}
2665 
2666 	}
2667 
2668 	/* add a new one */
2669 	radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2670 	if (!radeon_encoder)
2671 		return;
2672 
2673 	encoder = &radeon_encoder->base;
2674 	switch (rdev->num_crtc) {
2675 	case 1:
2676 		encoder->possible_crtcs = 0x1;
2677 		break;
2678 	case 2:
2679 	default:
2680 		encoder->possible_crtcs = 0x3;
2681 		break;
2682 	case 4:
2683 		encoder->possible_crtcs = 0xf;
2684 		break;
2685 	case 6:
2686 		encoder->possible_crtcs = 0x3f;
2687 		break;
2688 	}
2689 
2690 	radeon_encoder->enc_priv = NULL;
2691 
2692 	radeon_encoder->encoder_enum = encoder_enum;
2693 	radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2694 	radeon_encoder->devices = supported_device;
2695 	radeon_encoder->rmx_type = RMX_OFF;
2696 	radeon_encoder->underscan_type = UNDERSCAN_OFF;
2697 	radeon_encoder->is_ext_encoder = false;
2698 	radeon_encoder->caps = caps;
2699 
2700 	switch (radeon_encoder->encoder_id) {
2701 	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2702 	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2703 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2704 	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2705 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2706 			radeon_encoder->rmx_type = RMX_FULL;
2707 			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2708 					 DRM_MODE_ENCODER_LVDS, NULL);
2709 			radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2710 		} else {
2711 			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2712 					 DRM_MODE_ENCODER_TMDS, NULL);
2713 			radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2714 		}
2715 		drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2716 		break;
2717 	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2718 		drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2719 				 DRM_MODE_ENCODER_DAC, NULL);
2720 		radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2721 		drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2722 		break;
2723 	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2724 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2725 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2726 		drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2727 				 DRM_MODE_ENCODER_TVDAC, NULL);
2728 		radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2729 		drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2730 		break;
2731 	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2732 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2733 	case ENCODER_OBJECT_ID_INTERNAL_DDI:
2734 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2735 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2736 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2737 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2738 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2739 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2740 			radeon_encoder->rmx_type = RMX_FULL;
2741 			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2742 					 DRM_MODE_ENCODER_LVDS, NULL);
2743 			radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2744 		} else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2745 			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2746 					 DRM_MODE_ENCODER_DAC, NULL);
2747 			radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2748 		} else {
2749 			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2750 					 DRM_MODE_ENCODER_TMDS, NULL);
2751 			radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2752 		}
2753 		drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2754 		break;
2755 	case ENCODER_OBJECT_ID_SI170B:
2756 	case ENCODER_OBJECT_ID_CH7303:
2757 	case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2758 	case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2759 	case ENCODER_OBJECT_ID_TITFP513:
2760 	case ENCODER_OBJECT_ID_VT1623:
2761 	case ENCODER_OBJECT_ID_HDMI_SI1930:
2762 	case ENCODER_OBJECT_ID_TRAVIS:
2763 	case ENCODER_OBJECT_ID_NUTMEG:
2764 		/* these are handled by the primary encoders */
2765 		radeon_encoder->is_ext_encoder = true;
2766 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2767 			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2768 					 DRM_MODE_ENCODER_LVDS, NULL);
2769 		else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2770 			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2771 					 DRM_MODE_ENCODER_DAC, NULL);
2772 		else
2773 			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2774 					 DRM_MODE_ENCODER_TMDS, NULL);
2775 		drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2776 		break;
2777 	}
2778 }
2779