1 /* 2 * Copyright 2007-11 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include "drmP.h" 27 #include "drm_crtc_helper.h" 28 #include "radeon_drm.h" 29 #include "radeon.h" 30 #include "atom.h" 31 32 extern int atom_debug; 33 34 /* evil but including atombios.h is much worse */ 35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 36 struct drm_display_mode *mode); 37 38 39 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder) 40 { 41 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 42 switch (radeon_encoder->encoder_id) { 43 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 44 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 45 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 46 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 47 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 48 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 49 case ENCODER_OBJECT_ID_INTERNAL_DDI: 50 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 51 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 52 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 53 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 54 return true; 55 default: 56 return false; 57 } 58 } 59 60 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 61 struct drm_display_mode *mode, 62 struct drm_display_mode *adjusted_mode) 63 { 64 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 65 struct drm_device *dev = encoder->dev; 66 struct radeon_device *rdev = dev->dev_private; 67 68 /* set the active encoder to connector routing */ 69 radeon_encoder_set_active_device(encoder); 70 drm_mode_set_crtcinfo(adjusted_mode, 0); 71 72 /* hw bug */ 73 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) 74 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) 75 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; 76 77 /* get the native mode for LVDS */ 78 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) 79 radeon_panel_mode_fixup(encoder, adjusted_mode); 80 81 /* get the native mode for TV */ 82 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 83 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 84 if (tv_dac) { 85 if (tv_dac->tv_std == TV_STD_NTSC || 86 tv_dac->tv_std == TV_STD_NTSC_J || 87 tv_dac->tv_std == TV_STD_PAL_M) 88 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); 89 else 90 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); 91 } 92 } 93 94 if (ASIC_IS_DCE3(rdev) && 95 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 96 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) { 97 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 98 radeon_dp_set_link_config(connector, mode); 99 } 100 101 return true; 102 } 103 104 static void 105 atombios_dac_setup(struct drm_encoder *encoder, int action) 106 { 107 struct drm_device *dev = encoder->dev; 108 struct radeon_device *rdev = dev->dev_private; 109 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 110 DAC_ENCODER_CONTROL_PS_ALLOCATION args; 111 int index = 0; 112 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 113 114 memset(&args, 0, sizeof(args)); 115 116 switch (radeon_encoder->encoder_id) { 117 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 118 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 119 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); 120 break; 121 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 122 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 123 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); 124 break; 125 } 126 127 args.ucAction = action; 128 129 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) 130 args.ucDacStandard = ATOM_DAC1_PS2; 131 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 132 args.ucDacStandard = ATOM_DAC1_CV; 133 else { 134 switch (dac_info->tv_std) { 135 case TV_STD_PAL: 136 case TV_STD_PAL_M: 137 case TV_STD_SCART_PAL: 138 case TV_STD_SECAM: 139 case TV_STD_PAL_CN: 140 args.ucDacStandard = ATOM_DAC1_PAL; 141 break; 142 case TV_STD_NTSC: 143 case TV_STD_NTSC_J: 144 case TV_STD_PAL_60: 145 default: 146 args.ucDacStandard = ATOM_DAC1_NTSC; 147 break; 148 } 149 } 150 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 151 152 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 153 154 } 155 156 static void 157 atombios_tv_setup(struct drm_encoder *encoder, int action) 158 { 159 struct drm_device *dev = encoder->dev; 160 struct radeon_device *rdev = dev->dev_private; 161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 162 TV_ENCODER_CONTROL_PS_ALLOCATION args; 163 int index = 0; 164 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 165 166 memset(&args, 0, sizeof(args)); 167 168 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); 169 170 args.sTVEncoder.ucAction = action; 171 172 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 173 args.sTVEncoder.ucTvStandard = ATOM_TV_CV; 174 else { 175 switch (dac_info->tv_std) { 176 case TV_STD_NTSC: 177 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 178 break; 179 case TV_STD_PAL: 180 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; 181 break; 182 case TV_STD_PAL_M: 183 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; 184 break; 185 case TV_STD_PAL_60: 186 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; 187 break; 188 case TV_STD_NTSC_J: 189 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; 190 break; 191 case TV_STD_SCART_PAL: 192 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ 193 break; 194 case TV_STD_SECAM: 195 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; 196 break; 197 case TV_STD_PAL_CN: 198 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; 199 break; 200 default: 201 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 202 break; 203 } 204 } 205 206 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 207 208 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 209 210 } 211 212 union dvo_encoder_control { 213 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; 214 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; 215 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; 216 }; 217 218 void 219 atombios_dvo_setup(struct drm_encoder *encoder, int action) 220 { 221 struct drm_device *dev = encoder->dev; 222 struct radeon_device *rdev = dev->dev_private; 223 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 224 union dvo_encoder_control args; 225 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 226 uint8_t frev, crev; 227 228 memset(&args, 0, sizeof(args)); 229 230 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 231 return; 232 233 /* some R4xx chips have the wrong frev */ 234 if (rdev->family <= CHIP_RV410) 235 frev = 1; 236 237 switch (frev) { 238 case 1: 239 switch (crev) { 240 case 1: 241 /* R4xx, R5xx */ 242 args.ext_tmds.sXTmdsEncoder.ucEnable = action; 243 244 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 245 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; 246 247 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; 248 break; 249 case 2: 250 /* RS600/690/740 */ 251 args.dvo.sDVOEncoder.ucAction = action; 252 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 253 /* DFP1, CRT1, TV1 depending on the type of port */ 254 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; 255 256 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 257 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; 258 break; 259 case 3: 260 /* R6xx */ 261 args.dvo_v3.ucAction = action; 262 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 263 args.dvo_v3.ucDVOConfig = 0; /* XXX */ 264 break; 265 default: 266 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 267 break; 268 } 269 break; 270 default: 271 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 272 break; 273 } 274 275 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 276 } 277 278 union lvds_encoder_control { 279 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; 280 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; 281 }; 282 283 void 284 atombios_digital_setup(struct drm_encoder *encoder, int action) 285 { 286 struct drm_device *dev = encoder->dev; 287 struct radeon_device *rdev = dev->dev_private; 288 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 289 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 290 union lvds_encoder_control args; 291 int index = 0; 292 int hdmi_detected = 0; 293 uint8_t frev, crev; 294 295 if (!dig) 296 return; 297 298 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 299 hdmi_detected = 1; 300 301 memset(&args, 0, sizeof(args)); 302 303 switch (radeon_encoder->encoder_id) { 304 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 305 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 306 break; 307 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 308 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 309 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); 310 break; 311 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 312 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 313 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 314 else 315 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); 316 break; 317 } 318 319 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 320 return; 321 322 switch (frev) { 323 case 1: 324 case 2: 325 switch (crev) { 326 case 1: 327 args.v1.ucMisc = 0; 328 args.v1.ucAction = action; 329 if (hdmi_detected) 330 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 331 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 332 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 333 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 334 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 335 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 336 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 337 } else { 338 if (dig->linkb) 339 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 340 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 341 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 342 /*if (pScrn->rgbBits == 8) */ 343 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 344 } 345 break; 346 case 2: 347 case 3: 348 args.v2.ucMisc = 0; 349 args.v2.ucAction = action; 350 if (crev == 3) { 351 if (dig->coherent_mode) 352 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; 353 } 354 if (hdmi_detected) 355 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 356 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 357 args.v2.ucTruncate = 0; 358 args.v2.ucSpatial = 0; 359 args.v2.ucTemporal = 0; 360 args.v2.ucFRC = 0; 361 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 362 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 363 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 364 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { 365 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 366 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 367 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 368 } 369 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { 370 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 371 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 372 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 373 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) 374 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 375 } 376 } else { 377 if (dig->linkb) 378 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 379 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 380 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 381 } 382 break; 383 default: 384 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 385 break; 386 } 387 break; 388 default: 389 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 390 break; 391 } 392 393 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 394 } 395 396 int 397 atombios_get_encoder_mode(struct drm_encoder *encoder) 398 { 399 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 400 struct drm_connector *connector; 401 struct radeon_connector *radeon_connector; 402 struct radeon_connector_atom_dig *dig_connector; 403 404 /* dp bridges are always DP */ 405 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) 406 return ATOM_ENCODER_MODE_DP; 407 408 /* DVO is always DVO */ 409 if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO) 410 return ATOM_ENCODER_MODE_DVO; 411 412 connector = radeon_get_connector_for_encoder(encoder); 413 /* if we don't have an active device yet, just use one of 414 * the connectors tied to the encoder. 415 */ 416 if (!connector) 417 connector = radeon_get_connector_for_encoder_init(encoder); 418 radeon_connector = to_radeon_connector(connector); 419 420 switch (connector->connector_type) { 421 case DRM_MODE_CONNECTOR_DVII: 422 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 423 if (drm_detect_hdmi_monitor(radeon_connector->edid) && 424 radeon_audio) 425 return ATOM_ENCODER_MODE_HDMI; 426 else if (radeon_connector->use_digital) 427 return ATOM_ENCODER_MODE_DVI; 428 else 429 return ATOM_ENCODER_MODE_CRT; 430 break; 431 case DRM_MODE_CONNECTOR_DVID: 432 case DRM_MODE_CONNECTOR_HDMIA: 433 default: 434 if (drm_detect_hdmi_monitor(radeon_connector->edid) && 435 radeon_audio) 436 return ATOM_ENCODER_MODE_HDMI; 437 else 438 return ATOM_ENCODER_MODE_DVI; 439 break; 440 case DRM_MODE_CONNECTOR_LVDS: 441 return ATOM_ENCODER_MODE_LVDS; 442 break; 443 case DRM_MODE_CONNECTOR_DisplayPort: 444 dig_connector = radeon_connector->con_priv; 445 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 446 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) 447 return ATOM_ENCODER_MODE_DP; 448 else if (drm_detect_hdmi_monitor(radeon_connector->edid) && 449 radeon_audio) 450 return ATOM_ENCODER_MODE_HDMI; 451 else 452 return ATOM_ENCODER_MODE_DVI; 453 break; 454 case DRM_MODE_CONNECTOR_eDP: 455 return ATOM_ENCODER_MODE_DP; 456 case DRM_MODE_CONNECTOR_DVIA: 457 case DRM_MODE_CONNECTOR_VGA: 458 return ATOM_ENCODER_MODE_CRT; 459 break; 460 case DRM_MODE_CONNECTOR_Composite: 461 case DRM_MODE_CONNECTOR_SVIDEO: 462 case DRM_MODE_CONNECTOR_9PinDIN: 463 /* fix me */ 464 return ATOM_ENCODER_MODE_TV; 465 /*return ATOM_ENCODER_MODE_CV;*/ 466 break; 467 } 468 } 469 470 /* 471 * DIG Encoder/Transmitter Setup 472 * 473 * DCE 3.0/3.1 474 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. 475 * Supports up to 3 digital outputs 476 * - 2 DIG encoder blocks. 477 * DIG1 can drive UNIPHY link A or link B 478 * DIG2 can drive UNIPHY link B or LVTMA 479 * 480 * DCE 3.2 481 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). 482 * Supports up to 5 digital outputs 483 * - 2 DIG encoder blocks. 484 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 485 * 486 * DCE 4.0/5.0/6.0 487 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 488 * Supports up to 6 digital outputs 489 * - 6 DIG encoder blocks. 490 * - DIG to PHY mapping is hardcoded 491 * DIG1 drives UNIPHY0 link A, A+B 492 * DIG2 drives UNIPHY0 link B 493 * DIG3 drives UNIPHY1 link A, A+B 494 * DIG4 drives UNIPHY1 link B 495 * DIG5 drives UNIPHY2 link A, A+B 496 * DIG6 drives UNIPHY2 link B 497 * 498 * DCE 4.1 499 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 500 * Supports up to 6 digital outputs 501 * - 2 DIG encoder blocks. 502 * llano 503 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 504 * ontario 505 * DIG1 drives UNIPHY0/1/2 link A 506 * DIG2 drives UNIPHY0/1/2 link B 507 * 508 * Routing 509 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) 510 * Examples: 511 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI 512 * crtc1 -> dig1 -> UNIPHY0 link B -> DP 513 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS 514 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI 515 */ 516 517 union dig_encoder_control { 518 DIG_ENCODER_CONTROL_PS_ALLOCATION v1; 519 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; 520 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; 521 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; 522 }; 523 524 void 525 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) 526 { 527 struct drm_device *dev = encoder->dev; 528 struct radeon_device *rdev = dev->dev_private; 529 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 530 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 531 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 532 union dig_encoder_control args; 533 int index = 0; 534 uint8_t frev, crev; 535 int dp_clock = 0; 536 int dp_lane_count = 0; 537 int hpd_id = RADEON_HPD_NONE; 538 int bpc = 8; 539 540 if (connector) { 541 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 542 struct radeon_connector_atom_dig *dig_connector = 543 radeon_connector->con_priv; 544 545 dp_clock = dig_connector->dp_clock; 546 dp_lane_count = dig_connector->dp_lane_count; 547 hpd_id = radeon_connector->hpd.hpd; 548 /* bpc = connector->display_info.bpc; */ 549 } 550 551 /* no dig encoder assigned */ 552 if (dig->dig_encoder == -1) 553 return; 554 555 memset(&args, 0, sizeof(args)); 556 557 if (ASIC_IS_DCE4(rdev)) 558 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); 559 else { 560 if (dig->dig_encoder) 561 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 562 else 563 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 564 } 565 566 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 567 return; 568 569 switch (frev) { 570 case 1: 571 switch (crev) { 572 case 1: 573 args.v1.ucAction = action; 574 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 575 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 576 args.v3.ucPanelMode = panel_mode; 577 else 578 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 579 580 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 581 args.v1.ucLaneNum = dp_lane_count; 582 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 583 args.v1.ucLaneNum = 8; 584 else 585 args.v1.ucLaneNum = 4; 586 587 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) 588 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 589 switch (radeon_encoder->encoder_id) { 590 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 591 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; 592 break; 593 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 594 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 595 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; 596 break; 597 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 598 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; 599 break; 600 } 601 if (dig->linkb) 602 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 603 else 604 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 605 break; 606 case 2: 607 case 3: 608 args.v3.ucAction = action; 609 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 610 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 611 args.v3.ucPanelMode = panel_mode; 612 else 613 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); 614 615 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 616 args.v3.ucLaneNum = dp_lane_count; 617 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 618 args.v3.ucLaneNum = 8; 619 else 620 args.v3.ucLaneNum = 4; 621 622 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) 623 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 624 args.v3.acConfig.ucDigSel = dig->dig_encoder; 625 switch (bpc) { 626 case 0: 627 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE; 628 break; 629 case 6: 630 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR; 631 break; 632 case 8: 633 default: 634 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR; 635 break; 636 case 10: 637 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR; 638 break; 639 case 12: 640 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR; 641 break; 642 case 16: 643 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR; 644 break; 645 } 646 break; 647 case 4: 648 args.v4.ucAction = action; 649 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 650 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 651 args.v4.ucPanelMode = panel_mode; 652 else 653 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder); 654 655 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 656 args.v4.ucLaneNum = dp_lane_count; 657 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 658 args.v4.ucLaneNum = 8; 659 else 660 args.v4.ucLaneNum = 4; 661 662 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) { 663 if (dp_clock == 270000) 664 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; 665 else if (dp_clock == 540000) 666 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; 667 } 668 args.v4.acConfig.ucDigSel = dig->dig_encoder; 669 switch (bpc) { 670 case 0: 671 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE; 672 break; 673 case 6: 674 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR; 675 break; 676 case 8: 677 default: 678 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR; 679 break; 680 case 10: 681 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR; 682 break; 683 case 12: 684 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR; 685 break; 686 case 16: 687 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR; 688 break; 689 } 690 if (hpd_id == RADEON_HPD_NONE) 691 args.v4.ucHPD_ID = 0; 692 else 693 args.v4.ucHPD_ID = hpd_id + 1; 694 break; 695 default: 696 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 697 break; 698 } 699 break; 700 default: 701 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 702 break; 703 } 704 705 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 706 707 } 708 709 union dig_transmitter_control { 710 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; 711 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; 712 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; 713 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; 714 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; 715 }; 716 717 void 718 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) 719 { 720 struct drm_device *dev = encoder->dev; 721 struct radeon_device *rdev = dev->dev_private; 722 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 723 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 724 struct drm_connector *connector; 725 union dig_transmitter_control args; 726 int index = 0; 727 uint8_t frev, crev; 728 bool is_dp = false; 729 int pll_id = 0; 730 int dp_clock = 0; 731 int dp_lane_count = 0; 732 int connector_object_id = 0; 733 int igp_lane_info = 0; 734 int dig_encoder = dig->dig_encoder; 735 int hpd_id = RADEON_HPD_NONE; 736 737 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 738 connector = radeon_get_connector_for_encoder_init(encoder); 739 /* just needed to avoid bailing in the encoder check. the encoder 740 * isn't used for init 741 */ 742 dig_encoder = 0; 743 } else 744 connector = radeon_get_connector_for_encoder(encoder); 745 746 if (connector) { 747 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 748 struct radeon_connector_atom_dig *dig_connector = 749 radeon_connector->con_priv; 750 751 hpd_id = radeon_connector->hpd.hpd; 752 dp_clock = dig_connector->dp_clock; 753 dp_lane_count = dig_connector->dp_lane_count; 754 connector_object_id = 755 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 756 igp_lane_info = dig_connector->igp_lane_info; 757 } 758 759 if (encoder->crtc) { 760 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 761 pll_id = radeon_crtc->pll_id; 762 } 763 764 /* no dig encoder assigned */ 765 if (dig_encoder == -1) 766 return; 767 768 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))) 769 is_dp = true; 770 771 memset(&args, 0, sizeof(args)); 772 773 switch (radeon_encoder->encoder_id) { 774 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 775 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 776 break; 777 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 778 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 779 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 780 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 781 break; 782 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 783 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); 784 break; 785 } 786 787 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 788 return; 789 790 switch (frev) { 791 case 1: 792 switch (crev) { 793 case 1: 794 args.v1.ucAction = action; 795 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 796 args.v1.usInitInfo = cpu_to_le16(connector_object_id); 797 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 798 args.v1.asMode.ucLaneSel = lane_num; 799 args.v1.asMode.ucLaneSet = lane_set; 800 } else { 801 if (is_dp) 802 args.v1.usPixelClock = 803 cpu_to_le16(dp_clock / 10); 804 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 805 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 806 else 807 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 808 } 809 810 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 811 812 if (dig_encoder) 813 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 814 else 815 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; 816 817 if ((rdev->flags & RADEON_IS_IGP) && 818 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { 819 if (is_dp || 820 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) { 821 if (igp_lane_info & 0x1) 822 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 823 else if (igp_lane_info & 0x2) 824 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; 825 else if (igp_lane_info & 0x4) 826 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; 827 else if (igp_lane_info & 0x8) 828 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; 829 } else { 830 if (igp_lane_info & 0x3) 831 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; 832 else if (igp_lane_info & 0xc) 833 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; 834 } 835 } 836 837 if (dig->linkb) 838 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; 839 else 840 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; 841 842 if (is_dp) 843 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 844 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 845 if (dig->coherent_mode) 846 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 847 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 848 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; 849 } 850 break; 851 case 2: 852 args.v2.ucAction = action; 853 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 854 args.v2.usInitInfo = cpu_to_le16(connector_object_id); 855 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 856 args.v2.asMode.ucLaneSel = lane_num; 857 args.v2.asMode.ucLaneSet = lane_set; 858 } else { 859 if (is_dp) 860 args.v2.usPixelClock = 861 cpu_to_le16(dp_clock / 10); 862 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 863 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 864 else 865 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 866 } 867 868 args.v2.acConfig.ucEncoderSel = dig_encoder; 869 if (dig->linkb) 870 args.v2.acConfig.ucLinkSel = 1; 871 872 switch (radeon_encoder->encoder_id) { 873 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 874 args.v2.acConfig.ucTransmitterSel = 0; 875 break; 876 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 877 args.v2.acConfig.ucTransmitterSel = 1; 878 break; 879 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 880 args.v2.acConfig.ucTransmitterSel = 2; 881 break; 882 } 883 884 if (is_dp) { 885 args.v2.acConfig.fCoherentMode = 1; 886 args.v2.acConfig.fDPConnector = 1; 887 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 888 if (dig->coherent_mode) 889 args.v2.acConfig.fCoherentMode = 1; 890 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 891 args.v2.acConfig.fDualLinkConnector = 1; 892 } 893 break; 894 case 3: 895 args.v3.ucAction = action; 896 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 897 args.v3.usInitInfo = cpu_to_le16(connector_object_id); 898 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 899 args.v3.asMode.ucLaneSel = lane_num; 900 args.v3.asMode.ucLaneSet = lane_set; 901 } else { 902 if (is_dp) 903 args.v3.usPixelClock = 904 cpu_to_le16(dp_clock / 10); 905 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 906 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 907 else 908 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 909 } 910 911 if (is_dp) 912 args.v3.ucLaneNum = dp_lane_count; 913 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 914 args.v3.ucLaneNum = 8; 915 else 916 args.v3.ucLaneNum = 4; 917 918 if (dig->linkb) 919 args.v3.acConfig.ucLinkSel = 1; 920 if (dig_encoder & 1) 921 args.v3.acConfig.ucEncoderSel = 1; 922 923 /* Select the PLL for the PHY 924 * DP PHY should be clocked from external src if there is 925 * one. 926 */ 927 /* On DCE4, if there is an external clock, it generates the DP ref clock */ 928 if (is_dp && rdev->clock.dp_extclk) 929 args.v3.acConfig.ucRefClkSource = 2; /* external src */ 930 else 931 args.v3.acConfig.ucRefClkSource = pll_id; 932 933 switch (radeon_encoder->encoder_id) { 934 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 935 args.v3.acConfig.ucTransmitterSel = 0; 936 break; 937 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 938 args.v3.acConfig.ucTransmitterSel = 1; 939 break; 940 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 941 args.v3.acConfig.ucTransmitterSel = 2; 942 break; 943 } 944 945 if (is_dp) 946 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ 947 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 948 if (dig->coherent_mode) 949 args.v3.acConfig.fCoherentMode = 1; 950 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 951 args.v3.acConfig.fDualLinkConnector = 1; 952 } 953 break; 954 case 4: 955 args.v4.ucAction = action; 956 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 957 args.v4.usInitInfo = cpu_to_le16(connector_object_id); 958 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 959 args.v4.asMode.ucLaneSel = lane_num; 960 args.v4.asMode.ucLaneSet = lane_set; 961 } else { 962 if (is_dp) 963 args.v4.usPixelClock = 964 cpu_to_le16(dp_clock / 10); 965 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 966 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 967 else 968 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 969 } 970 971 if (is_dp) 972 args.v4.ucLaneNum = dp_lane_count; 973 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 974 args.v4.ucLaneNum = 8; 975 else 976 args.v4.ucLaneNum = 4; 977 978 if (dig->linkb) 979 args.v4.acConfig.ucLinkSel = 1; 980 if (dig_encoder & 1) 981 args.v4.acConfig.ucEncoderSel = 1; 982 983 /* Select the PLL for the PHY 984 * DP PHY should be clocked from external src if there is 985 * one. 986 */ 987 /* On DCE5 DCPLL usually generates the DP ref clock */ 988 if (is_dp) { 989 if (rdev->clock.dp_extclk) 990 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; 991 else 992 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; 993 } else 994 args.v4.acConfig.ucRefClkSource = pll_id; 995 996 switch (radeon_encoder->encoder_id) { 997 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 998 args.v4.acConfig.ucTransmitterSel = 0; 999 break; 1000 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1001 args.v4.acConfig.ucTransmitterSel = 1; 1002 break; 1003 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1004 args.v4.acConfig.ucTransmitterSel = 2; 1005 break; 1006 } 1007 1008 if (is_dp) 1009 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1010 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1011 if (dig->coherent_mode) 1012 args.v4.acConfig.fCoherentMode = 1; 1013 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1014 args.v4.acConfig.fDualLinkConnector = 1; 1015 } 1016 break; 1017 case 5: 1018 args.v5.ucAction = action; 1019 if (is_dp) 1020 args.v5.usSymClock = cpu_to_le16(dp_clock / 10); 1021 else 1022 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1023 1024 switch (radeon_encoder->encoder_id) { 1025 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1026 if (dig->linkb) 1027 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; 1028 else 1029 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; 1030 break; 1031 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1032 if (dig->linkb) 1033 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; 1034 else 1035 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; 1036 break; 1037 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1038 if (dig->linkb) 1039 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; 1040 else 1041 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; 1042 break; 1043 } 1044 if (is_dp) 1045 args.v5.ucLaneNum = dp_lane_count; 1046 else if (radeon_encoder->pixel_clock > 165000) 1047 args.v5.ucLaneNum = 8; 1048 else 1049 args.v5.ucLaneNum = 4; 1050 args.v5.ucConnObjId = connector_object_id; 1051 args.v5.ucDigMode = atombios_get_encoder_mode(encoder); 1052 1053 if (is_dp && rdev->clock.dp_extclk) 1054 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK; 1055 else 1056 args.v5.asConfig.ucPhyClkSrcId = pll_id; 1057 1058 if (is_dp) 1059 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ 1060 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1061 if (dig->coherent_mode) 1062 args.v5.asConfig.ucCoherentMode = 1; 1063 } 1064 if (hpd_id == RADEON_HPD_NONE) 1065 args.v5.asConfig.ucHPDSel = 0; 1066 else 1067 args.v5.asConfig.ucHPDSel = hpd_id + 1; 1068 args.v5.ucDigEncoderSel = 1 << dig_encoder; 1069 args.v5.ucDPLaneSet = lane_set; 1070 break; 1071 default: 1072 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1073 break; 1074 } 1075 break; 1076 default: 1077 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1078 break; 1079 } 1080 1081 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1082 } 1083 1084 bool 1085 atombios_set_edp_panel_power(struct drm_connector *connector, int action) 1086 { 1087 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1088 struct drm_device *dev = radeon_connector->base.dev; 1089 struct radeon_device *rdev = dev->dev_private; 1090 union dig_transmitter_control args; 1091 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1092 uint8_t frev, crev; 1093 1094 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) 1095 goto done; 1096 1097 if (!ASIC_IS_DCE4(rdev)) 1098 goto done; 1099 1100 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && 1101 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) 1102 goto done; 1103 1104 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1105 goto done; 1106 1107 memset(&args, 0, sizeof(args)); 1108 1109 args.v1.ucAction = action; 1110 1111 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1112 1113 /* wait for the panel to power up */ 1114 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { 1115 int i; 1116 1117 for (i = 0; i < 300; i++) { 1118 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) 1119 return true; 1120 mdelay(1); 1121 } 1122 return false; 1123 } 1124 done: 1125 return true; 1126 } 1127 1128 union external_encoder_control { 1129 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; 1130 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; 1131 }; 1132 1133 static void 1134 atombios_external_encoder_setup(struct drm_encoder *encoder, 1135 struct drm_encoder *ext_encoder, 1136 int action) 1137 { 1138 struct drm_device *dev = encoder->dev; 1139 struct radeon_device *rdev = dev->dev_private; 1140 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1141 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); 1142 union external_encoder_control args; 1143 struct drm_connector *connector; 1144 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); 1145 u8 frev, crev; 1146 int dp_clock = 0; 1147 int dp_lane_count = 0; 1148 int connector_object_id = 0; 1149 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1150 int bpc = 8; 1151 1152 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1153 connector = radeon_get_connector_for_encoder_init(encoder); 1154 else 1155 connector = radeon_get_connector_for_encoder(encoder); 1156 1157 if (connector) { 1158 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1159 struct radeon_connector_atom_dig *dig_connector = 1160 radeon_connector->con_priv; 1161 1162 dp_clock = dig_connector->dp_clock; 1163 dp_lane_count = dig_connector->dp_lane_count; 1164 connector_object_id = 1165 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1166 /* bpc = connector->display_info.bpc; */ 1167 } 1168 1169 memset(&args, 0, sizeof(args)); 1170 1171 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1172 return; 1173 1174 switch (frev) { 1175 case 1: 1176 /* no params on frev 1 */ 1177 break; 1178 case 2: 1179 switch (crev) { 1180 case 1: 1181 case 2: 1182 args.v1.sDigEncoder.ucAction = action; 1183 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1184 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1185 1186 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) { 1187 if (dp_clock == 270000) 1188 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 1189 args.v1.sDigEncoder.ucLaneNum = dp_lane_count; 1190 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1191 args.v1.sDigEncoder.ucLaneNum = 8; 1192 else 1193 args.v1.sDigEncoder.ucLaneNum = 4; 1194 break; 1195 case 3: 1196 args.v3.sExtEncoder.ucAction = action; 1197 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1198 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); 1199 else 1200 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1201 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1202 1203 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { 1204 if (dp_clock == 270000) 1205 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 1206 else if (dp_clock == 540000) 1207 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; 1208 args.v3.sExtEncoder.ucLaneNum = dp_lane_count; 1209 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1210 args.v3.sExtEncoder.ucLaneNum = 8; 1211 else 1212 args.v3.sExtEncoder.ucLaneNum = 4; 1213 switch (ext_enum) { 1214 case GRAPH_OBJECT_ENUM_ID1: 1215 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; 1216 break; 1217 case GRAPH_OBJECT_ENUM_ID2: 1218 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; 1219 break; 1220 case GRAPH_OBJECT_ENUM_ID3: 1221 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; 1222 break; 1223 } 1224 switch (bpc) { 1225 case 0: 1226 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE; 1227 break; 1228 case 6: 1229 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR; 1230 break; 1231 case 8: 1232 default: 1233 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR; 1234 break; 1235 case 10: 1236 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR; 1237 break; 1238 case 12: 1239 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR; 1240 break; 1241 case 16: 1242 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR; 1243 break; 1244 } 1245 break; 1246 default: 1247 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1248 return; 1249 } 1250 break; 1251 default: 1252 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1253 return; 1254 } 1255 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1256 } 1257 1258 static void 1259 atombios_yuv_setup(struct drm_encoder *encoder, bool enable) 1260 { 1261 struct drm_device *dev = encoder->dev; 1262 struct radeon_device *rdev = dev->dev_private; 1263 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1264 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1265 ENABLE_YUV_PS_ALLOCATION args; 1266 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); 1267 uint32_t temp, reg; 1268 1269 memset(&args, 0, sizeof(args)); 1270 1271 if (rdev->family >= CHIP_R600) 1272 reg = R600_BIOS_3_SCRATCH; 1273 else 1274 reg = RADEON_BIOS_3_SCRATCH; 1275 1276 /* XXX: fix up scratch reg handling */ 1277 temp = RREG32(reg); 1278 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1279 WREG32(reg, (ATOM_S3_TV1_ACTIVE | 1280 (radeon_crtc->crtc_id << 18))); 1281 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1282 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); 1283 else 1284 WREG32(reg, 0); 1285 1286 if (enable) 1287 args.ucEnable = ATOM_ENABLE; 1288 args.ucCRTC = radeon_crtc->crtc_id; 1289 1290 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1291 1292 WREG32(reg, temp); 1293 } 1294 1295 static void 1296 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode) 1297 { 1298 struct drm_device *dev = encoder->dev; 1299 struct radeon_device *rdev = dev->dev_private; 1300 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1301 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 1302 int index = 0; 1303 1304 memset(&args, 0, sizeof(args)); 1305 1306 switch (radeon_encoder->encoder_id) { 1307 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1308 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1309 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); 1310 break; 1311 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1312 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1313 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1314 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1315 break; 1316 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1317 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1318 break; 1319 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1320 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1321 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1322 else 1323 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); 1324 break; 1325 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1326 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1327 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1328 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1329 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1330 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1331 else 1332 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 1333 break; 1334 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1335 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1336 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1337 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1338 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1339 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1340 else 1341 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 1342 break; 1343 default: 1344 return; 1345 } 1346 1347 switch (mode) { 1348 case DRM_MODE_DPMS_ON: 1349 args.ucAction = ATOM_ENABLE; 1350 /* workaround for DVOOutputControl on some RS690 systems */ 1351 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { 1352 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); 1353 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); 1354 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1355 WREG32(RADEON_BIOS_3_SCRATCH, reg); 1356 } else 1357 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1358 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1359 args.ucAction = ATOM_LCD_BLON; 1360 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1361 } 1362 break; 1363 case DRM_MODE_DPMS_STANDBY: 1364 case DRM_MODE_DPMS_SUSPEND: 1365 case DRM_MODE_DPMS_OFF: 1366 args.ucAction = ATOM_DISABLE; 1367 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1368 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1369 args.ucAction = ATOM_LCD_BLOFF; 1370 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1371 } 1372 break; 1373 } 1374 } 1375 1376 static void 1377 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 1378 { 1379 struct drm_device *dev = encoder->dev; 1380 struct radeon_device *rdev = dev->dev_private; 1381 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1382 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1383 struct radeon_connector *radeon_connector = NULL; 1384 struct radeon_connector_atom_dig *radeon_dig_connector = NULL; 1385 1386 if (connector) { 1387 radeon_connector = to_radeon_connector(connector); 1388 radeon_dig_connector = radeon_connector->con_priv; 1389 } 1390 1391 switch (mode) { 1392 case DRM_MODE_DPMS_ON: 1393 /* some early dce3.2 boards have a bug in their transmitter control table */ 1394 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730) || 1395 ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) 1396 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1397 else 1398 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1399 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1400 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1401 atombios_set_edp_panel_power(connector, 1402 ATOM_TRANSMITTER_ACTION_POWER_ON); 1403 radeon_dig_connector->edp_on = true; 1404 } 1405 radeon_dp_link_train(encoder, connector); 1406 if (ASIC_IS_DCE4(rdev)) 1407 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); 1408 } 1409 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1410 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 1411 break; 1412 case DRM_MODE_DPMS_STANDBY: 1413 case DRM_MODE_DPMS_SUSPEND: 1414 case DRM_MODE_DPMS_OFF: 1415 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) 1416 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1417 else 1418 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); 1419 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1420 if (ASIC_IS_DCE4(rdev)) 1421 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1422 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1423 atombios_set_edp_panel_power(connector, 1424 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1425 radeon_dig_connector->edp_on = false; 1426 } 1427 } 1428 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1429 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 1430 break; 1431 } 1432 } 1433 1434 static void 1435 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder, 1436 struct drm_encoder *ext_encoder, 1437 int mode) 1438 { 1439 struct drm_device *dev = encoder->dev; 1440 struct radeon_device *rdev = dev->dev_private; 1441 1442 switch (mode) { 1443 case DRM_MODE_DPMS_ON: 1444 default: 1445 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) { 1446 atombios_external_encoder_setup(encoder, ext_encoder, 1447 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT); 1448 atombios_external_encoder_setup(encoder, ext_encoder, 1449 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF); 1450 } else 1451 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1452 break; 1453 case DRM_MODE_DPMS_STANDBY: 1454 case DRM_MODE_DPMS_SUSPEND: 1455 case DRM_MODE_DPMS_OFF: 1456 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) { 1457 atombios_external_encoder_setup(encoder, ext_encoder, 1458 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING); 1459 atombios_external_encoder_setup(encoder, ext_encoder, 1460 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT); 1461 } else 1462 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); 1463 break; 1464 } 1465 } 1466 1467 static void 1468 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 1469 { 1470 struct drm_device *dev = encoder->dev; 1471 struct radeon_device *rdev = dev->dev_private; 1472 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1473 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1474 1475 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", 1476 radeon_encoder->encoder_id, mode, radeon_encoder->devices, 1477 radeon_encoder->active_device); 1478 switch (radeon_encoder->encoder_id) { 1479 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1480 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1481 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1482 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1483 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1484 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1485 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1486 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1487 radeon_atom_encoder_dpms_avivo(encoder, mode); 1488 break; 1489 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1490 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1491 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1492 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1493 radeon_atom_encoder_dpms_dig(encoder, mode); 1494 break; 1495 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1496 if (ASIC_IS_DCE5(rdev)) { 1497 switch (mode) { 1498 case DRM_MODE_DPMS_ON: 1499 atombios_dvo_setup(encoder, ATOM_ENABLE); 1500 break; 1501 case DRM_MODE_DPMS_STANDBY: 1502 case DRM_MODE_DPMS_SUSPEND: 1503 case DRM_MODE_DPMS_OFF: 1504 atombios_dvo_setup(encoder, ATOM_DISABLE); 1505 break; 1506 } 1507 } else if (ASIC_IS_DCE3(rdev)) 1508 radeon_atom_encoder_dpms_dig(encoder, mode); 1509 else 1510 radeon_atom_encoder_dpms_avivo(encoder, mode); 1511 break; 1512 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1513 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1514 if (ASIC_IS_DCE5(rdev)) { 1515 switch (mode) { 1516 case DRM_MODE_DPMS_ON: 1517 atombios_dac_setup(encoder, ATOM_ENABLE); 1518 break; 1519 case DRM_MODE_DPMS_STANDBY: 1520 case DRM_MODE_DPMS_SUSPEND: 1521 case DRM_MODE_DPMS_OFF: 1522 atombios_dac_setup(encoder, ATOM_DISABLE); 1523 break; 1524 } 1525 } else 1526 radeon_atom_encoder_dpms_avivo(encoder, mode); 1527 break; 1528 default: 1529 return; 1530 } 1531 1532 if (ext_encoder) 1533 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode); 1534 1535 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1536 1537 } 1538 1539 union crtc_source_param { 1540 SELECT_CRTC_SOURCE_PS_ALLOCATION v1; 1541 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; 1542 }; 1543 1544 static void 1545 atombios_set_encoder_crtc_source(struct drm_encoder *encoder) 1546 { 1547 struct drm_device *dev = encoder->dev; 1548 struct radeon_device *rdev = dev->dev_private; 1549 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1550 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1551 union crtc_source_param args; 1552 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 1553 uint8_t frev, crev; 1554 struct radeon_encoder_atom_dig *dig; 1555 1556 memset(&args, 0, sizeof(args)); 1557 1558 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1559 return; 1560 1561 switch (frev) { 1562 case 1: 1563 switch (crev) { 1564 case 1: 1565 default: 1566 if (ASIC_IS_AVIVO(rdev)) 1567 args.v1.ucCRTC = radeon_crtc->crtc_id; 1568 else { 1569 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { 1570 args.v1.ucCRTC = radeon_crtc->crtc_id; 1571 } else { 1572 args.v1.ucCRTC = radeon_crtc->crtc_id << 2; 1573 } 1574 } 1575 switch (radeon_encoder->encoder_id) { 1576 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1577 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1578 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; 1579 break; 1580 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1581 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1582 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) 1583 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; 1584 else 1585 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; 1586 break; 1587 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1588 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1589 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1590 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; 1591 break; 1592 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1593 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1594 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1595 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1596 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1597 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1598 else 1599 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; 1600 break; 1601 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1602 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1603 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1604 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1605 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1606 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1607 else 1608 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; 1609 break; 1610 } 1611 break; 1612 case 2: 1613 args.v2.ucCRTC = radeon_crtc->crtc_id; 1614 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { 1615 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1616 1617 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) 1618 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1619 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) 1620 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; 1621 else 1622 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1623 } else 1624 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1625 switch (radeon_encoder->encoder_id) { 1626 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1627 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1628 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1629 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1630 dig = radeon_encoder->enc_priv; 1631 switch (dig->dig_encoder) { 1632 case 0: 1633 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 1634 break; 1635 case 1: 1636 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1637 break; 1638 case 2: 1639 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 1640 break; 1641 case 3: 1642 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 1643 break; 1644 case 4: 1645 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 1646 break; 1647 case 5: 1648 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 1649 break; 1650 } 1651 break; 1652 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1653 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; 1654 break; 1655 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1656 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1657 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1658 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1659 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1660 else 1661 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; 1662 break; 1663 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1664 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1665 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1666 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1667 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1668 else 1669 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; 1670 break; 1671 } 1672 break; 1673 } 1674 break; 1675 default: 1676 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1677 return; 1678 } 1679 1680 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1681 1682 /* update scratch regs with new routing */ 1683 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1684 } 1685 1686 static void 1687 atombios_apply_encoder_quirks(struct drm_encoder *encoder, 1688 struct drm_display_mode *mode) 1689 { 1690 struct drm_device *dev = encoder->dev; 1691 struct radeon_device *rdev = dev->dev_private; 1692 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1693 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1694 1695 /* Funky macbooks */ 1696 if ((dev->pdev->device == 0x71C5) && 1697 (dev->pdev->subsystem_vendor == 0x106b) && 1698 (dev->pdev->subsystem_device == 0x0080)) { 1699 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 1700 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); 1701 1702 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; 1703 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 1704 1705 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); 1706 } 1707 } 1708 1709 /* set scaler clears this on some chips */ 1710 if (ASIC_IS_AVIVO(rdev) && 1711 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { 1712 if (ASIC_IS_DCE4(rdev)) { 1713 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1714 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 1715 EVERGREEN_INTERLEAVE_EN); 1716 else 1717 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 1718 } else { 1719 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1720 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 1721 AVIVO_D1MODE_INTERLEAVE_EN); 1722 else 1723 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 1724 } 1725 } 1726 } 1727 1728 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) 1729 { 1730 struct drm_device *dev = encoder->dev; 1731 struct radeon_device *rdev = dev->dev_private; 1732 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1733 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1734 struct drm_encoder *test_encoder; 1735 struct radeon_encoder_atom_dig *dig; 1736 uint32_t dig_enc_in_use = 0; 1737 1738 /* DCE4/5 */ 1739 if (ASIC_IS_DCE4(rdev)) { 1740 dig = radeon_encoder->enc_priv; 1741 if (ASIC_IS_DCE41(rdev)) { 1742 /* ontario follows DCE4 */ 1743 if (rdev->family == CHIP_PALM) { 1744 if (dig->linkb) 1745 return 1; 1746 else 1747 return 0; 1748 } else 1749 /* llano follows DCE3.2 */ 1750 return radeon_crtc->crtc_id; 1751 } else { 1752 switch (radeon_encoder->encoder_id) { 1753 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1754 if (dig->linkb) 1755 return 1; 1756 else 1757 return 0; 1758 break; 1759 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1760 if (dig->linkb) 1761 return 3; 1762 else 1763 return 2; 1764 break; 1765 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1766 if (dig->linkb) 1767 return 5; 1768 else 1769 return 4; 1770 break; 1771 } 1772 } 1773 } 1774 1775 /* on DCE32 and encoder can driver any block so just crtc id */ 1776 if (ASIC_IS_DCE32(rdev)) { 1777 return radeon_crtc->crtc_id; 1778 } 1779 1780 /* on DCE3 - LVTMA can only be driven by DIGB */ 1781 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 1782 struct radeon_encoder *radeon_test_encoder; 1783 1784 if (encoder == test_encoder) 1785 continue; 1786 1787 if (!radeon_encoder_is_digital(test_encoder)) 1788 continue; 1789 1790 radeon_test_encoder = to_radeon_encoder(test_encoder); 1791 dig = radeon_test_encoder->enc_priv; 1792 1793 if (dig->dig_encoder >= 0) 1794 dig_enc_in_use |= (1 << dig->dig_encoder); 1795 } 1796 1797 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { 1798 if (dig_enc_in_use & 0x2) 1799 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); 1800 return 1; 1801 } 1802 if (!(dig_enc_in_use & 1)) 1803 return 0; 1804 return 1; 1805 } 1806 1807 /* This only needs to be called once at startup */ 1808 void 1809 radeon_atom_encoder_init(struct radeon_device *rdev) 1810 { 1811 struct drm_device *dev = rdev->ddev; 1812 struct drm_encoder *encoder; 1813 1814 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1815 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1816 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1817 1818 switch (radeon_encoder->encoder_id) { 1819 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1820 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1821 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1822 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1823 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); 1824 break; 1825 default: 1826 break; 1827 } 1828 1829 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))) 1830 atombios_external_encoder_setup(encoder, ext_encoder, 1831 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); 1832 } 1833 } 1834 1835 static void 1836 radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 1837 struct drm_display_mode *mode, 1838 struct drm_display_mode *adjusted_mode) 1839 { 1840 struct drm_device *dev = encoder->dev; 1841 struct radeon_device *rdev = dev->dev_private; 1842 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1843 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1844 1845 radeon_encoder->pixel_clock = adjusted_mode->clock; 1846 1847 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { 1848 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 1849 atombios_yuv_setup(encoder, true); 1850 else 1851 atombios_yuv_setup(encoder, false); 1852 } 1853 1854 switch (radeon_encoder->encoder_id) { 1855 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1856 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1857 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1858 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1859 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 1860 break; 1861 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1862 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1863 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1864 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1865 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 1866 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1867 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1868 1869 if (!connector) 1870 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 1871 else 1872 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector); 1873 1874 /* setup and enable the encoder */ 1875 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1876 atombios_dig_encoder_setup(encoder, 1877 ATOM_ENCODER_CMD_SETUP_PANEL_MODE, 1878 dig->panel_mode); 1879 } else if (ASIC_IS_DCE4(rdev)) { 1880 /* disable the transmitter */ 1881 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1882 /* setup and enable the encoder */ 1883 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1884 1885 /* enable the transmitter */ 1886 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1887 } else { 1888 /* disable the encoder and transmitter */ 1889 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1890 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); 1891 1892 /* setup and enable the encoder and transmitter */ 1893 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); 1894 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1895 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1896 } 1897 break; 1898 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1899 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1900 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1901 atombios_dvo_setup(encoder, ATOM_ENABLE); 1902 break; 1903 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1904 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1905 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1906 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1907 atombios_dac_setup(encoder, ATOM_ENABLE); 1908 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { 1909 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 1910 atombios_tv_setup(encoder, ATOM_ENABLE); 1911 else 1912 atombios_tv_setup(encoder, ATOM_DISABLE); 1913 } 1914 break; 1915 } 1916 1917 if (ext_encoder) { 1918 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) 1919 atombios_external_encoder_setup(encoder, ext_encoder, 1920 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); 1921 else 1922 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1923 } 1924 1925 atombios_apply_encoder_quirks(encoder, adjusted_mode); 1926 1927 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 1928 r600_hdmi_enable(encoder); 1929 r600_hdmi_setmode(encoder, adjusted_mode); 1930 } 1931 } 1932 1933 static bool 1934 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) 1935 { 1936 struct drm_device *dev = encoder->dev; 1937 struct radeon_device *rdev = dev->dev_private; 1938 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1939 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1940 1941 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | 1942 ATOM_DEVICE_CV_SUPPORT | 1943 ATOM_DEVICE_CRT_SUPPORT)) { 1944 DAC_LOAD_DETECTION_PS_ALLOCATION args; 1945 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); 1946 uint8_t frev, crev; 1947 1948 memset(&args, 0, sizeof(args)); 1949 1950 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1951 return false; 1952 1953 args.sDacload.ucMisc = 0; 1954 1955 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 1956 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) 1957 args.sDacload.ucDacType = ATOM_DAC_A; 1958 else 1959 args.sDacload.ucDacType = ATOM_DAC_B; 1960 1961 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) 1962 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); 1963 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) 1964 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); 1965 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 1966 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); 1967 if (crev >= 3) 1968 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 1969 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 1970 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); 1971 if (crev >= 3) 1972 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 1973 } 1974 1975 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1976 1977 return true; 1978 } else 1979 return false; 1980 } 1981 1982 static enum drm_connector_status 1983 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 1984 { 1985 struct drm_device *dev = encoder->dev; 1986 struct radeon_device *rdev = dev->dev_private; 1987 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1988 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1989 uint32_t bios_0_scratch; 1990 1991 if (!atombios_dac_load_detect(encoder, connector)) { 1992 DRM_DEBUG_KMS("detect returned false \n"); 1993 return connector_status_unknown; 1994 } 1995 1996 if (rdev->family >= CHIP_R600) 1997 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 1998 else 1999 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 2000 2001 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2002 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2003 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2004 return connector_status_connected; 2005 } 2006 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2007 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2008 return connector_status_connected; 2009 } 2010 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2011 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2012 return connector_status_connected; 2013 } 2014 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2015 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2016 return connector_status_connected; /* CTV */ 2017 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2018 return connector_status_connected; /* STV */ 2019 } 2020 return connector_status_disconnected; 2021 } 2022 2023 static enum drm_connector_status 2024 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2025 { 2026 struct drm_device *dev = encoder->dev; 2027 struct radeon_device *rdev = dev->dev_private; 2028 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2029 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2030 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2031 u32 bios_0_scratch; 2032 2033 if (!ASIC_IS_DCE4(rdev)) 2034 return connector_status_unknown; 2035 2036 if (!ext_encoder) 2037 return connector_status_unknown; 2038 2039 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) 2040 return connector_status_unknown; 2041 2042 /* load detect on the dp bridge */ 2043 atombios_external_encoder_setup(encoder, ext_encoder, 2044 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); 2045 2046 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2047 2048 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2049 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2050 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2051 return connector_status_connected; 2052 } 2053 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2054 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2055 return connector_status_connected; 2056 } 2057 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2058 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2059 return connector_status_connected; 2060 } 2061 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2062 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2063 return connector_status_connected; /* CTV */ 2064 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2065 return connector_status_connected; /* STV */ 2066 } 2067 return connector_status_disconnected; 2068 } 2069 2070 void 2071 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) 2072 { 2073 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2074 2075 if (ext_encoder) 2076 /* ddc_setup on the dp bridge */ 2077 atombios_external_encoder_setup(encoder, ext_encoder, 2078 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); 2079 2080 } 2081 2082 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 2083 { 2084 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2085 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2086 2087 if ((radeon_encoder->active_device & 2088 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 2089 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 2090 ENCODER_OBJECT_ID_NONE)) { 2091 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2092 if (dig) 2093 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); 2094 } 2095 2096 radeon_atom_output_lock(encoder, true); 2097 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2098 2099 if (connector) { 2100 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2101 2102 /* select the clock/data port if it uses a router */ 2103 if (radeon_connector->router.cd_valid) 2104 radeon_router_select_cd_port(radeon_connector); 2105 2106 /* turn eDP panel on for mode set */ 2107 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 2108 atombios_set_edp_panel_power(connector, 2109 ATOM_TRANSMITTER_ACTION_POWER_ON); 2110 } 2111 2112 /* this is needed for the pll/ss setup to work correctly in some cases */ 2113 atombios_set_encoder_crtc_source(encoder); 2114 } 2115 2116 static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 2117 { 2118 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 2119 radeon_atom_output_lock(encoder, false); 2120 } 2121 2122 static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 2123 { 2124 struct drm_device *dev = encoder->dev; 2125 struct radeon_device *rdev = dev->dev_private; 2126 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2127 struct radeon_encoder_atom_dig *dig; 2128 2129 /* check for pre-DCE3 cards with shared encoders; 2130 * can't really use the links individually, so don't disable 2131 * the encoder if it's in use by another connector 2132 */ 2133 if (!ASIC_IS_DCE3(rdev)) { 2134 struct drm_encoder *other_encoder; 2135 struct radeon_encoder *other_radeon_encoder; 2136 2137 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { 2138 other_radeon_encoder = to_radeon_encoder(other_encoder); 2139 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && 2140 drm_helper_encoder_in_use(other_encoder)) 2141 goto disable_done; 2142 } 2143 } 2144 2145 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2146 2147 switch (radeon_encoder->encoder_id) { 2148 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2149 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2150 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2151 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2152 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); 2153 break; 2154 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2155 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2156 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2157 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2158 if (ASIC_IS_DCE4(rdev)) 2159 /* disable the transmitter */ 2160 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 2161 else { 2162 /* disable the encoder and transmitter */ 2163 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 2164 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); 2165 } 2166 break; 2167 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2168 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2169 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2170 atombios_dvo_setup(encoder, ATOM_DISABLE); 2171 break; 2172 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2173 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2174 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2175 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2176 atombios_dac_setup(encoder, ATOM_DISABLE); 2177 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2178 atombios_tv_setup(encoder, ATOM_DISABLE); 2179 break; 2180 } 2181 2182 disable_done: 2183 if (radeon_encoder_is_digital(encoder)) { 2184 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 2185 r600_hdmi_disable(encoder); 2186 dig = radeon_encoder->enc_priv; 2187 dig->dig_encoder = -1; 2188 } 2189 radeon_encoder->active_device = 0; 2190 } 2191 2192 /* these are handled by the primary encoders */ 2193 static void radeon_atom_ext_prepare(struct drm_encoder *encoder) 2194 { 2195 2196 } 2197 2198 static void radeon_atom_ext_commit(struct drm_encoder *encoder) 2199 { 2200 2201 } 2202 2203 static void 2204 radeon_atom_ext_mode_set(struct drm_encoder *encoder, 2205 struct drm_display_mode *mode, 2206 struct drm_display_mode *adjusted_mode) 2207 { 2208 2209 } 2210 2211 static void radeon_atom_ext_disable(struct drm_encoder *encoder) 2212 { 2213 2214 } 2215 2216 static void 2217 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) 2218 { 2219 2220 } 2221 2222 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder, 2223 struct drm_display_mode *mode, 2224 struct drm_display_mode *adjusted_mode) 2225 { 2226 return true; 2227 } 2228 2229 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { 2230 .dpms = radeon_atom_ext_dpms, 2231 .mode_fixup = radeon_atom_ext_mode_fixup, 2232 .prepare = radeon_atom_ext_prepare, 2233 .mode_set = radeon_atom_ext_mode_set, 2234 .commit = radeon_atom_ext_commit, 2235 .disable = radeon_atom_ext_disable, 2236 /* no detect for TMDS/LVDS yet */ 2237 }; 2238 2239 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { 2240 .dpms = radeon_atom_encoder_dpms, 2241 .mode_fixup = radeon_atom_mode_fixup, 2242 .prepare = radeon_atom_encoder_prepare, 2243 .mode_set = radeon_atom_encoder_mode_set, 2244 .commit = radeon_atom_encoder_commit, 2245 .disable = radeon_atom_encoder_disable, 2246 .detect = radeon_atom_dig_detect, 2247 }; 2248 2249 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { 2250 .dpms = radeon_atom_encoder_dpms, 2251 .mode_fixup = radeon_atom_mode_fixup, 2252 .prepare = radeon_atom_encoder_prepare, 2253 .mode_set = radeon_atom_encoder_mode_set, 2254 .commit = radeon_atom_encoder_commit, 2255 .detect = radeon_atom_dac_detect, 2256 }; 2257 2258 void radeon_enc_destroy(struct drm_encoder *encoder) 2259 { 2260 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2261 kfree(radeon_encoder->enc_priv); 2262 drm_encoder_cleanup(encoder); 2263 kfree(radeon_encoder); 2264 } 2265 2266 static const struct drm_encoder_funcs radeon_atom_enc_funcs = { 2267 .destroy = radeon_enc_destroy, 2268 }; 2269 2270 struct radeon_encoder_atom_dac * 2271 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) 2272 { 2273 struct drm_device *dev = radeon_encoder->base.dev; 2274 struct radeon_device *rdev = dev->dev_private; 2275 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); 2276 2277 if (!dac) 2278 return NULL; 2279 2280 dac->tv_std = radeon_atombios_get_tv_info(rdev); 2281 return dac; 2282 } 2283 2284 struct radeon_encoder_atom_dig * 2285 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) 2286 { 2287 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 2288 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 2289 2290 if (!dig) 2291 return NULL; 2292 2293 /* coherent mode by default */ 2294 dig->coherent_mode = true; 2295 dig->dig_encoder = -1; 2296 2297 if (encoder_enum == 2) 2298 dig->linkb = true; 2299 else 2300 dig->linkb = false; 2301 2302 return dig; 2303 } 2304 2305 void 2306 radeon_add_atom_encoder(struct drm_device *dev, 2307 uint32_t encoder_enum, 2308 uint32_t supported_device, 2309 u16 caps) 2310 { 2311 struct radeon_device *rdev = dev->dev_private; 2312 struct drm_encoder *encoder; 2313 struct radeon_encoder *radeon_encoder; 2314 2315 /* see if we already added it */ 2316 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2317 radeon_encoder = to_radeon_encoder(encoder); 2318 if (radeon_encoder->encoder_enum == encoder_enum) { 2319 radeon_encoder->devices |= supported_device; 2320 return; 2321 } 2322 2323 } 2324 2325 /* add a new one */ 2326 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); 2327 if (!radeon_encoder) 2328 return; 2329 2330 encoder = &radeon_encoder->base; 2331 switch (rdev->num_crtc) { 2332 case 1: 2333 encoder->possible_crtcs = 0x1; 2334 break; 2335 case 2: 2336 default: 2337 encoder->possible_crtcs = 0x3; 2338 break; 2339 case 4: 2340 encoder->possible_crtcs = 0xf; 2341 break; 2342 case 6: 2343 encoder->possible_crtcs = 0x3f; 2344 break; 2345 } 2346 2347 radeon_encoder->enc_priv = NULL; 2348 2349 radeon_encoder->encoder_enum = encoder_enum; 2350 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 2351 radeon_encoder->devices = supported_device; 2352 radeon_encoder->rmx_type = RMX_OFF; 2353 radeon_encoder->underscan_type = UNDERSCAN_OFF; 2354 radeon_encoder->is_ext_encoder = false; 2355 radeon_encoder->caps = caps; 2356 2357 switch (radeon_encoder->encoder_id) { 2358 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2359 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2360 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2361 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2362 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2363 radeon_encoder->rmx_type = RMX_FULL; 2364 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2365 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2366 } else { 2367 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2368 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2369 } 2370 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2371 break; 2372 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2373 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2374 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2375 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2376 break; 2377 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2378 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2379 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2380 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); 2381 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2382 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2383 break; 2384 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2385 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2386 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2387 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2388 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2389 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2390 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2391 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2392 radeon_encoder->rmx_type = RMX_FULL; 2393 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2394 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2395 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 2396 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2397 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2398 } else { 2399 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2400 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2401 } 2402 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2403 break; 2404 case ENCODER_OBJECT_ID_SI170B: 2405 case ENCODER_OBJECT_ID_CH7303: 2406 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 2407 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 2408 case ENCODER_OBJECT_ID_TITFP513: 2409 case ENCODER_OBJECT_ID_VT1623: 2410 case ENCODER_OBJECT_ID_HDMI_SI1930: 2411 case ENCODER_OBJECT_ID_TRAVIS: 2412 case ENCODER_OBJECT_ID_NUTMEG: 2413 /* these are handled by the primary encoders */ 2414 radeon_encoder->is_ext_encoder = true; 2415 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2416 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2417 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 2418 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2419 else 2420 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2421 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); 2422 break; 2423 } 2424 } 2425