1 /* 2 * Copyright 2007-11 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_crtc_helper.h> 28 #include <drm/radeon_drm.h> 29 #include "radeon.h" 30 #include "atom.h" 31 #include <linux/backlight.h> 32 33 extern int atom_debug; 34 35 static u8 36 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev) 37 { 38 u8 backlight_level; 39 u32 bios_2_scratch; 40 41 if (rdev->family >= CHIP_R600) 42 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 43 else 44 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 45 46 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >> 47 ATOM_S2_CURRENT_BL_LEVEL_SHIFT); 48 49 return backlight_level; 50 } 51 52 static void 53 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev, 54 u8 backlight_level) 55 { 56 u32 bios_2_scratch; 57 58 if (rdev->family >= CHIP_R600) 59 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 60 else 61 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 62 63 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; 64 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) & 65 ATOM_S2_CURRENT_BL_LEVEL_MASK); 66 67 if (rdev->family >= CHIP_R600) 68 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 69 else 70 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 71 } 72 73 u8 74 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder) 75 { 76 struct drm_device *dev = radeon_encoder->base.dev; 77 struct radeon_device *rdev = dev->dev_private; 78 79 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 80 return 0; 81 82 return radeon_atom_get_backlight_level_from_reg(rdev); 83 } 84 85 void 86 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) 87 { 88 struct drm_encoder *encoder = &radeon_encoder->base; 89 struct drm_device *dev = radeon_encoder->base.dev; 90 struct radeon_device *rdev = dev->dev_private; 91 struct radeon_encoder_atom_dig *dig; 92 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 93 int index; 94 95 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 96 return; 97 98 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 99 radeon_encoder->enc_priv) { 100 dig = radeon_encoder->enc_priv; 101 dig->backlight_level = level; 102 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level); 103 104 switch (radeon_encoder->encoder_id) { 105 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 106 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 107 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 108 if (dig->backlight_level == 0) { 109 args.ucAction = ATOM_LCD_BLOFF; 110 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 111 } else { 112 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL; 113 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 114 args.ucAction = ATOM_LCD_BLON; 115 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 116 } 117 break; 118 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 119 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 120 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 122 if (dig->backlight_level == 0) 123 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 124 else { 125 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0); 126 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 127 } 128 break; 129 default: 130 break; 131 } 132 } 133 } 134 135 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 136 137 static u8 radeon_atom_bl_level(struct backlight_device *bd) 138 { 139 u8 level; 140 141 /* Convert brightness to hardware level */ 142 if (bd->props.brightness < 0) 143 level = 0; 144 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) 145 level = RADEON_MAX_BL_LEVEL; 146 else 147 level = bd->props.brightness; 148 149 return level; 150 } 151 152 static int radeon_atom_backlight_update_status(struct backlight_device *bd) 153 { 154 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 155 struct radeon_encoder *radeon_encoder = pdata->encoder; 156 157 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd)); 158 159 return 0; 160 } 161 162 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd) 163 { 164 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 165 struct radeon_encoder *radeon_encoder = pdata->encoder; 166 struct drm_device *dev = radeon_encoder->base.dev; 167 struct radeon_device *rdev = dev->dev_private; 168 169 return radeon_atom_get_backlight_level_from_reg(rdev); 170 } 171 172 static const struct backlight_ops radeon_atom_backlight_ops = { 173 .get_brightness = radeon_atom_backlight_get_brightness, 174 .update_status = radeon_atom_backlight_update_status, 175 }; 176 177 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 178 struct drm_connector *drm_connector) 179 { 180 struct drm_device *dev = radeon_encoder->base.dev; 181 struct radeon_device *rdev = dev->dev_private; 182 struct backlight_device *bd; 183 struct backlight_properties props; 184 struct radeon_backlight_privdata *pdata; 185 struct radeon_encoder_atom_dig *dig; 186 u8 backlight_level; 187 char bl_name[16]; 188 189 /* Mac laptops with multiple GPUs use the gmux driver for backlight 190 * so don't register a backlight device 191 */ 192 if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && 193 (rdev->pdev->device == 0x6741)) 194 return; 195 196 if (!radeon_encoder->enc_priv) 197 return; 198 199 if (!rdev->is_atom_bios) 200 return; 201 202 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 203 return; 204 205 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL); 206 if (!pdata) { 207 DRM_ERROR("Memory allocation failed\n"); 208 goto error; 209 } 210 211 memset(&props, 0, sizeof(props)); 212 props.max_brightness = RADEON_MAX_BL_LEVEL; 213 props.type = BACKLIGHT_RAW; 214 snprintf(bl_name, sizeof(bl_name), 215 "radeon_bl%d", dev->primary->index); 216 bd = backlight_device_register(bl_name, &drm_connector->kdev, 217 pdata, &radeon_atom_backlight_ops, &props); 218 if (IS_ERR(bd)) { 219 DRM_ERROR("Backlight registration failed\n"); 220 goto error; 221 } 222 223 pdata->encoder = radeon_encoder; 224 225 backlight_level = radeon_atom_get_backlight_level_from_reg(rdev); 226 227 dig = radeon_encoder->enc_priv; 228 dig->bl_dev = bd; 229 230 bd->props.brightness = radeon_atom_backlight_get_brightness(bd); 231 bd->props.power = FB_BLANK_UNBLANK; 232 backlight_update_status(bd); 233 234 DRM_INFO("radeon atom DIG backlight initialized\n"); 235 236 return; 237 238 error: 239 kfree(pdata); 240 return; 241 } 242 243 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder) 244 { 245 struct drm_device *dev = radeon_encoder->base.dev; 246 struct radeon_device *rdev = dev->dev_private; 247 struct backlight_device *bd = NULL; 248 struct radeon_encoder_atom_dig *dig; 249 250 if (!radeon_encoder->enc_priv) 251 return; 252 253 if (!rdev->is_atom_bios) 254 return; 255 256 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 257 return; 258 259 dig = radeon_encoder->enc_priv; 260 bd = dig->bl_dev; 261 dig->bl_dev = NULL; 262 263 if (bd) { 264 struct radeon_legacy_backlight_privdata *pdata; 265 266 pdata = bl_get_data(bd); 267 backlight_device_unregister(bd); 268 kfree(pdata); 269 270 DRM_INFO("radeon atom LVDS backlight unloaded\n"); 271 } 272 } 273 274 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ 275 276 void radeon_atom_backlight_init(struct radeon_encoder *encoder) 277 { 278 } 279 280 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder) 281 { 282 } 283 284 #endif 285 286 /* evil but including atombios.h is much worse */ 287 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 288 struct drm_display_mode *mode); 289 290 291 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder) 292 { 293 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 294 switch (radeon_encoder->encoder_id) { 295 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 296 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 297 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 298 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 299 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 300 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 301 case ENCODER_OBJECT_ID_INTERNAL_DDI: 302 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 303 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 304 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 305 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 306 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 307 return true; 308 default: 309 return false; 310 } 311 } 312 313 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 314 const struct drm_display_mode *mode, 315 struct drm_display_mode *adjusted_mode) 316 { 317 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 318 struct drm_device *dev = encoder->dev; 319 struct radeon_device *rdev = dev->dev_private; 320 321 /* set the active encoder to connector routing */ 322 radeon_encoder_set_active_device(encoder); 323 drm_mode_set_crtcinfo(adjusted_mode, 0); 324 325 /* hw bug */ 326 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) 327 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) 328 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; 329 330 /* get the native mode for LVDS */ 331 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) 332 radeon_panel_mode_fixup(encoder, adjusted_mode); 333 334 /* get the native mode for TV */ 335 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 336 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 337 if (tv_dac) { 338 if (tv_dac->tv_std == TV_STD_NTSC || 339 tv_dac->tv_std == TV_STD_NTSC_J || 340 tv_dac->tv_std == TV_STD_PAL_M) 341 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); 342 else 343 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); 344 } 345 } 346 347 if (ASIC_IS_DCE3(rdev) && 348 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 349 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) { 350 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 351 radeon_dp_set_link_config(connector, adjusted_mode); 352 } 353 354 return true; 355 } 356 357 static void 358 atombios_dac_setup(struct drm_encoder *encoder, int action) 359 { 360 struct drm_device *dev = encoder->dev; 361 struct radeon_device *rdev = dev->dev_private; 362 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 363 DAC_ENCODER_CONTROL_PS_ALLOCATION args; 364 int index = 0; 365 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 366 367 memset(&args, 0, sizeof(args)); 368 369 switch (radeon_encoder->encoder_id) { 370 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 371 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 372 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); 373 break; 374 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 375 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 376 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); 377 break; 378 } 379 380 args.ucAction = action; 381 382 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) 383 args.ucDacStandard = ATOM_DAC1_PS2; 384 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 385 args.ucDacStandard = ATOM_DAC1_CV; 386 else { 387 switch (dac_info->tv_std) { 388 case TV_STD_PAL: 389 case TV_STD_PAL_M: 390 case TV_STD_SCART_PAL: 391 case TV_STD_SECAM: 392 case TV_STD_PAL_CN: 393 args.ucDacStandard = ATOM_DAC1_PAL; 394 break; 395 case TV_STD_NTSC: 396 case TV_STD_NTSC_J: 397 case TV_STD_PAL_60: 398 default: 399 args.ucDacStandard = ATOM_DAC1_NTSC; 400 break; 401 } 402 } 403 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 404 405 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 406 407 } 408 409 static void 410 atombios_tv_setup(struct drm_encoder *encoder, int action) 411 { 412 struct drm_device *dev = encoder->dev; 413 struct radeon_device *rdev = dev->dev_private; 414 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 415 TV_ENCODER_CONTROL_PS_ALLOCATION args; 416 int index = 0; 417 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 418 419 memset(&args, 0, sizeof(args)); 420 421 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); 422 423 args.sTVEncoder.ucAction = action; 424 425 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 426 args.sTVEncoder.ucTvStandard = ATOM_TV_CV; 427 else { 428 switch (dac_info->tv_std) { 429 case TV_STD_NTSC: 430 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 431 break; 432 case TV_STD_PAL: 433 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; 434 break; 435 case TV_STD_PAL_M: 436 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; 437 break; 438 case TV_STD_PAL_60: 439 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; 440 break; 441 case TV_STD_NTSC_J: 442 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; 443 break; 444 case TV_STD_SCART_PAL: 445 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ 446 break; 447 case TV_STD_SECAM: 448 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; 449 break; 450 case TV_STD_PAL_CN: 451 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; 452 break; 453 default: 454 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 455 break; 456 } 457 } 458 459 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 460 461 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 462 463 } 464 465 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) 466 { 467 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 468 int bpc = 8; 469 470 if (connector) 471 bpc = radeon_get_monitor_bpc(connector); 472 473 switch (bpc) { 474 case 0: 475 return PANEL_BPC_UNDEFINE; 476 case 6: 477 return PANEL_6BIT_PER_COLOR; 478 case 8: 479 default: 480 return PANEL_8BIT_PER_COLOR; 481 case 10: 482 return PANEL_10BIT_PER_COLOR; 483 case 12: 484 return PANEL_12BIT_PER_COLOR; 485 case 16: 486 return PANEL_16BIT_PER_COLOR; 487 } 488 } 489 490 union dvo_encoder_control { 491 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; 492 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; 493 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; 494 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4; 495 }; 496 497 void 498 atombios_dvo_setup(struct drm_encoder *encoder, int action) 499 { 500 struct drm_device *dev = encoder->dev; 501 struct radeon_device *rdev = dev->dev_private; 502 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 503 union dvo_encoder_control args; 504 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 505 uint8_t frev, crev; 506 507 memset(&args, 0, sizeof(args)); 508 509 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 510 return; 511 512 /* some R4xx chips have the wrong frev */ 513 if (rdev->family <= CHIP_RV410) 514 frev = 1; 515 516 switch (frev) { 517 case 1: 518 switch (crev) { 519 case 1: 520 /* R4xx, R5xx */ 521 args.ext_tmds.sXTmdsEncoder.ucEnable = action; 522 523 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 524 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; 525 526 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; 527 break; 528 case 2: 529 /* RS600/690/740 */ 530 args.dvo.sDVOEncoder.ucAction = action; 531 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 532 /* DFP1, CRT1, TV1 depending on the type of port */ 533 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; 534 535 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 536 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; 537 break; 538 case 3: 539 /* R6xx */ 540 args.dvo_v3.ucAction = action; 541 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 542 args.dvo_v3.ucDVOConfig = 0; /* XXX */ 543 break; 544 case 4: 545 /* DCE8 */ 546 args.dvo_v4.ucAction = action; 547 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 548 args.dvo_v4.ucDVOConfig = 0; /* XXX */ 549 args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 550 break; 551 default: 552 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 553 break; 554 } 555 break; 556 default: 557 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 558 break; 559 } 560 561 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 562 } 563 564 union lvds_encoder_control { 565 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; 566 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; 567 }; 568 569 void 570 atombios_digital_setup(struct drm_encoder *encoder, int action) 571 { 572 struct drm_device *dev = encoder->dev; 573 struct radeon_device *rdev = dev->dev_private; 574 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 575 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 576 union lvds_encoder_control args; 577 int index = 0; 578 int hdmi_detected = 0; 579 uint8_t frev, crev; 580 581 if (!dig) 582 return; 583 584 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 585 hdmi_detected = 1; 586 587 memset(&args, 0, sizeof(args)); 588 589 switch (radeon_encoder->encoder_id) { 590 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 591 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 592 break; 593 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 594 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 595 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); 596 break; 597 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 598 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 599 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 600 else 601 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); 602 break; 603 } 604 605 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 606 return; 607 608 switch (frev) { 609 case 1: 610 case 2: 611 switch (crev) { 612 case 1: 613 args.v1.ucMisc = 0; 614 args.v1.ucAction = action; 615 if (hdmi_detected) 616 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 617 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 618 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 619 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 620 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 621 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 622 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 623 } else { 624 if (dig->linkb) 625 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 626 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 627 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 628 /*if (pScrn->rgbBits == 8) */ 629 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 630 } 631 break; 632 case 2: 633 case 3: 634 args.v2.ucMisc = 0; 635 args.v2.ucAction = action; 636 if (crev == 3) { 637 if (dig->coherent_mode) 638 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; 639 } 640 if (hdmi_detected) 641 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 642 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 643 args.v2.ucTruncate = 0; 644 args.v2.ucSpatial = 0; 645 args.v2.ucTemporal = 0; 646 args.v2.ucFRC = 0; 647 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 648 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 649 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 650 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { 651 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 652 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 653 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 654 } 655 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { 656 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 657 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 658 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 659 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) 660 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 661 } 662 } else { 663 if (dig->linkb) 664 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 665 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 666 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 667 } 668 break; 669 default: 670 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 671 break; 672 } 673 break; 674 default: 675 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 676 break; 677 } 678 679 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 680 } 681 682 int 683 atombios_get_encoder_mode(struct drm_encoder *encoder) 684 { 685 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 686 struct drm_connector *connector; 687 struct radeon_connector *radeon_connector; 688 struct radeon_connector_atom_dig *dig_connector; 689 690 /* dp bridges are always DP */ 691 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) 692 return ATOM_ENCODER_MODE_DP; 693 694 /* DVO is always DVO */ 695 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) || 696 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) 697 return ATOM_ENCODER_MODE_DVO; 698 699 connector = radeon_get_connector_for_encoder(encoder); 700 /* if we don't have an active device yet, just use one of 701 * the connectors tied to the encoder. 702 */ 703 if (!connector) 704 connector = radeon_get_connector_for_encoder_init(encoder); 705 radeon_connector = to_radeon_connector(connector); 706 707 switch (connector->connector_type) { 708 case DRM_MODE_CONNECTOR_DVII: 709 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 710 if (radeon_audio != 0) { 711 if (radeon_connector->use_digital && 712 (radeon_connector->audio == RADEON_AUDIO_ENABLE)) 713 return ATOM_ENCODER_MODE_HDMI; 714 else if (drm_detect_hdmi_monitor(radeon_connector->edid) && 715 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 716 return ATOM_ENCODER_MODE_HDMI; 717 else if (radeon_connector->use_digital) 718 return ATOM_ENCODER_MODE_DVI; 719 else 720 return ATOM_ENCODER_MODE_CRT; 721 } else if (radeon_connector->use_digital) { 722 return ATOM_ENCODER_MODE_DVI; 723 } else { 724 return ATOM_ENCODER_MODE_CRT; 725 } 726 break; 727 case DRM_MODE_CONNECTOR_DVID: 728 case DRM_MODE_CONNECTOR_HDMIA: 729 default: 730 if (radeon_audio != 0) { 731 if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 732 return ATOM_ENCODER_MODE_HDMI; 733 else if (drm_detect_hdmi_monitor(radeon_connector->edid) && 734 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 735 return ATOM_ENCODER_MODE_HDMI; 736 else 737 return ATOM_ENCODER_MODE_DVI; 738 } else { 739 return ATOM_ENCODER_MODE_DVI; 740 } 741 break; 742 case DRM_MODE_CONNECTOR_LVDS: 743 return ATOM_ENCODER_MODE_LVDS; 744 break; 745 case DRM_MODE_CONNECTOR_DisplayPort: 746 dig_connector = radeon_connector->con_priv; 747 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 748 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 749 return ATOM_ENCODER_MODE_DP; 750 } else if (radeon_audio != 0) { 751 if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 752 return ATOM_ENCODER_MODE_HDMI; 753 else if (drm_detect_hdmi_monitor(radeon_connector->edid) && 754 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 755 return ATOM_ENCODER_MODE_HDMI; 756 else 757 return ATOM_ENCODER_MODE_DVI; 758 } else { 759 return ATOM_ENCODER_MODE_DVI; 760 } 761 break; 762 case DRM_MODE_CONNECTOR_eDP: 763 return ATOM_ENCODER_MODE_DP; 764 case DRM_MODE_CONNECTOR_DVIA: 765 case DRM_MODE_CONNECTOR_VGA: 766 return ATOM_ENCODER_MODE_CRT; 767 break; 768 case DRM_MODE_CONNECTOR_Composite: 769 case DRM_MODE_CONNECTOR_SVIDEO: 770 case DRM_MODE_CONNECTOR_9PinDIN: 771 /* fix me */ 772 return ATOM_ENCODER_MODE_TV; 773 /*return ATOM_ENCODER_MODE_CV;*/ 774 break; 775 } 776 } 777 778 /* 779 * DIG Encoder/Transmitter Setup 780 * 781 * DCE 3.0/3.1 782 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. 783 * Supports up to 3 digital outputs 784 * - 2 DIG encoder blocks. 785 * DIG1 can drive UNIPHY link A or link B 786 * DIG2 can drive UNIPHY link B or LVTMA 787 * 788 * DCE 3.2 789 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). 790 * Supports up to 5 digital outputs 791 * - 2 DIG encoder blocks. 792 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 793 * 794 * DCE 4.0/5.0/6.0 795 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 796 * Supports up to 6 digital outputs 797 * - 6 DIG encoder blocks. 798 * - DIG to PHY mapping is hardcoded 799 * DIG1 drives UNIPHY0 link A, A+B 800 * DIG2 drives UNIPHY0 link B 801 * DIG3 drives UNIPHY1 link A, A+B 802 * DIG4 drives UNIPHY1 link B 803 * DIG5 drives UNIPHY2 link A, A+B 804 * DIG6 drives UNIPHY2 link B 805 * 806 * DCE 4.1 807 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 808 * Supports up to 6 digital outputs 809 * - 2 DIG encoder blocks. 810 * llano 811 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 812 * ontario 813 * DIG1 drives UNIPHY0/1/2 link A 814 * DIG2 drives UNIPHY0/1/2 link B 815 * 816 * Routing 817 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) 818 * Examples: 819 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI 820 * crtc1 -> dig1 -> UNIPHY0 link B -> DP 821 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS 822 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI 823 */ 824 825 union dig_encoder_control { 826 DIG_ENCODER_CONTROL_PS_ALLOCATION v1; 827 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; 828 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; 829 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; 830 }; 831 832 void 833 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) 834 { 835 struct drm_device *dev = encoder->dev; 836 struct radeon_device *rdev = dev->dev_private; 837 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 838 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 839 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 840 union dig_encoder_control args; 841 int index = 0; 842 uint8_t frev, crev; 843 int dp_clock = 0; 844 int dp_lane_count = 0; 845 int hpd_id = RADEON_HPD_NONE; 846 847 if (connector) { 848 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 849 struct radeon_connector_atom_dig *dig_connector = 850 radeon_connector->con_priv; 851 852 dp_clock = dig_connector->dp_clock; 853 dp_lane_count = dig_connector->dp_lane_count; 854 hpd_id = radeon_connector->hpd.hpd; 855 } 856 857 /* no dig encoder assigned */ 858 if (dig->dig_encoder == -1) 859 return; 860 861 memset(&args, 0, sizeof(args)); 862 863 if (ASIC_IS_DCE4(rdev)) 864 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); 865 else { 866 if (dig->dig_encoder) 867 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 868 else 869 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 870 } 871 872 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 873 return; 874 875 switch (frev) { 876 case 1: 877 switch (crev) { 878 case 1: 879 args.v1.ucAction = action; 880 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 881 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 882 args.v3.ucPanelMode = panel_mode; 883 else 884 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 885 886 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 887 args.v1.ucLaneNum = dp_lane_count; 888 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 889 args.v1.ucLaneNum = 8; 890 else 891 args.v1.ucLaneNum = 4; 892 893 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) 894 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 895 switch (radeon_encoder->encoder_id) { 896 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 897 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; 898 break; 899 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 900 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 901 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; 902 break; 903 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 904 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; 905 break; 906 } 907 if (dig->linkb) 908 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 909 else 910 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 911 break; 912 case 2: 913 case 3: 914 args.v3.ucAction = action; 915 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 916 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 917 args.v3.ucPanelMode = panel_mode; 918 else 919 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); 920 921 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) 922 args.v3.ucLaneNum = dp_lane_count; 923 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 924 args.v3.ucLaneNum = 8; 925 else 926 args.v3.ucLaneNum = 4; 927 928 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000)) 929 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 930 args.v3.acConfig.ucDigSel = dig->dig_encoder; 931 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder); 932 break; 933 case 4: 934 args.v4.ucAction = action; 935 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 936 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 937 args.v4.ucPanelMode = panel_mode; 938 else 939 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder); 940 941 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) 942 args.v4.ucLaneNum = dp_lane_count; 943 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 944 args.v4.ucLaneNum = 8; 945 else 946 args.v4.ucLaneNum = 4; 947 948 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) { 949 if (dp_clock == 540000) 950 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; 951 else if (dp_clock == 324000) 952 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ; 953 else if (dp_clock == 270000) 954 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; 955 else 956 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ; 957 } 958 args.v4.acConfig.ucDigSel = dig->dig_encoder; 959 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 960 if (hpd_id == RADEON_HPD_NONE) 961 args.v4.ucHPD_ID = 0; 962 else 963 args.v4.ucHPD_ID = hpd_id + 1; 964 break; 965 default: 966 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 967 break; 968 } 969 break; 970 default: 971 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 972 break; 973 } 974 975 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 976 977 } 978 979 union dig_transmitter_control { 980 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; 981 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; 982 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; 983 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; 984 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; 985 }; 986 987 void 988 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) 989 { 990 struct drm_device *dev = encoder->dev; 991 struct radeon_device *rdev = dev->dev_private; 992 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 993 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 994 struct drm_connector *connector; 995 union dig_transmitter_control args; 996 int index = 0; 997 uint8_t frev, crev; 998 bool is_dp = false; 999 int pll_id = 0; 1000 int dp_clock = 0; 1001 int dp_lane_count = 0; 1002 int connector_object_id = 0; 1003 int igp_lane_info = 0; 1004 int dig_encoder = dig->dig_encoder; 1005 int hpd_id = RADEON_HPD_NONE; 1006 1007 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1008 connector = radeon_get_connector_for_encoder_init(encoder); 1009 /* just needed to avoid bailing in the encoder check. the encoder 1010 * isn't used for init 1011 */ 1012 dig_encoder = 0; 1013 } else 1014 connector = radeon_get_connector_for_encoder(encoder); 1015 1016 if (connector) { 1017 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1018 struct radeon_connector_atom_dig *dig_connector = 1019 radeon_connector->con_priv; 1020 1021 hpd_id = radeon_connector->hpd.hpd; 1022 dp_clock = dig_connector->dp_clock; 1023 dp_lane_count = dig_connector->dp_lane_count; 1024 connector_object_id = 1025 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1026 igp_lane_info = dig_connector->igp_lane_info; 1027 } 1028 1029 if (encoder->crtc) { 1030 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1031 pll_id = radeon_crtc->pll_id; 1032 } 1033 1034 /* no dig encoder assigned */ 1035 if (dig_encoder == -1) 1036 return; 1037 1038 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))) 1039 is_dp = true; 1040 1041 memset(&args, 0, sizeof(args)); 1042 1043 switch (radeon_encoder->encoder_id) { 1044 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1045 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1046 break; 1047 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1048 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1049 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1050 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1051 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1052 break; 1053 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1054 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); 1055 break; 1056 } 1057 1058 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1059 return; 1060 1061 switch (frev) { 1062 case 1: 1063 switch (crev) { 1064 case 1: 1065 args.v1.ucAction = action; 1066 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1067 args.v1.usInitInfo = cpu_to_le16(connector_object_id); 1068 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1069 args.v1.asMode.ucLaneSel = lane_num; 1070 args.v1.asMode.ucLaneSet = lane_set; 1071 } else { 1072 if (is_dp) 1073 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10); 1074 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1075 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1076 else 1077 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1078 } 1079 1080 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 1081 1082 if (dig_encoder) 1083 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 1084 else 1085 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; 1086 1087 if ((rdev->flags & RADEON_IS_IGP) && 1088 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { 1089 if (is_dp || 1090 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) { 1091 if (igp_lane_info & 0x1) 1092 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 1093 else if (igp_lane_info & 0x2) 1094 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; 1095 else if (igp_lane_info & 0x4) 1096 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; 1097 else if (igp_lane_info & 0x8) 1098 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; 1099 } else { 1100 if (igp_lane_info & 0x3) 1101 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; 1102 else if (igp_lane_info & 0xc) 1103 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; 1104 } 1105 } 1106 1107 if (dig->linkb) 1108 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; 1109 else 1110 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; 1111 1112 if (is_dp) 1113 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1114 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1115 if (dig->coherent_mode) 1116 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1117 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1118 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; 1119 } 1120 break; 1121 case 2: 1122 args.v2.ucAction = action; 1123 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1124 args.v2.usInitInfo = cpu_to_le16(connector_object_id); 1125 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1126 args.v2.asMode.ucLaneSel = lane_num; 1127 args.v2.asMode.ucLaneSet = lane_set; 1128 } else { 1129 if (is_dp) 1130 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10); 1131 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1132 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1133 else 1134 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1135 } 1136 1137 args.v2.acConfig.ucEncoderSel = dig_encoder; 1138 if (dig->linkb) 1139 args.v2.acConfig.ucLinkSel = 1; 1140 1141 switch (radeon_encoder->encoder_id) { 1142 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1143 args.v2.acConfig.ucTransmitterSel = 0; 1144 break; 1145 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1146 args.v2.acConfig.ucTransmitterSel = 1; 1147 break; 1148 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1149 args.v2.acConfig.ucTransmitterSel = 2; 1150 break; 1151 } 1152 1153 if (is_dp) { 1154 args.v2.acConfig.fCoherentMode = 1; 1155 args.v2.acConfig.fDPConnector = 1; 1156 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1157 if (dig->coherent_mode) 1158 args.v2.acConfig.fCoherentMode = 1; 1159 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1160 args.v2.acConfig.fDualLinkConnector = 1; 1161 } 1162 break; 1163 case 3: 1164 args.v3.ucAction = action; 1165 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1166 args.v3.usInitInfo = cpu_to_le16(connector_object_id); 1167 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1168 args.v3.asMode.ucLaneSel = lane_num; 1169 args.v3.asMode.ucLaneSet = lane_set; 1170 } else { 1171 if (is_dp) 1172 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10); 1173 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1174 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1175 else 1176 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1177 } 1178 1179 if (is_dp) 1180 args.v3.ucLaneNum = dp_lane_count; 1181 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1182 args.v3.ucLaneNum = 8; 1183 else 1184 args.v3.ucLaneNum = 4; 1185 1186 if (dig->linkb) 1187 args.v3.acConfig.ucLinkSel = 1; 1188 if (dig_encoder & 1) 1189 args.v3.acConfig.ucEncoderSel = 1; 1190 1191 /* Select the PLL for the PHY 1192 * DP PHY should be clocked from external src if there is 1193 * one. 1194 */ 1195 /* On DCE4, if there is an external clock, it generates the DP ref clock */ 1196 if (is_dp && rdev->clock.dp_extclk) 1197 args.v3.acConfig.ucRefClkSource = 2; /* external src */ 1198 else 1199 args.v3.acConfig.ucRefClkSource = pll_id; 1200 1201 switch (radeon_encoder->encoder_id) { 1202 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1203 args.v3.acConfig.ucTransmitterSel = 0; 1204 break; 1205 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1206 args.v3.acConfig.ucTransmitterSel = 1; 1207 break; 1208 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1209 args.v3.acConfig.ucTransmitterSel = 2; 1210 break; 1211 } 1212 1213 if (is_dp) 1214 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1215 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1216 if (dig->coherent_mode) 1217 args.v3.acConfig.fCoherentMode = 1; 1218 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1219 args.v3.acConfig.fDualLinkConnector = 1; 1220 } 1221 break; 1222 case 4: 1223 args.v4.ucAction = action; 1224 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1225 args.v4.usInitInfo = cpu_to_le16(connector_object_id); 1226 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1227 args.v4.asMode.ucLaneSel = lane_num; 1228 args.v4.asMode.ucLaneSet = lane_set; 1229 } else { 1230 if (is_dp) 1231 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10); 1232 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1233 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1234 else 1235 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1236 } 1237 1238 if (is_dp) 1239 args.v4.ucLaneNum = dp_lane_count; 1240 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1241 args.v4.ucLaneNum = 8; 1242 else 1243 args.v4.ucLaneNum = 4; 1244 1245 if (dig->linkb) 1246 args.v4.acConfig.ucLinkSel = 1; 1247 if (dig_encoder & 1) 1248 args.v4.acConfig.ucEncoderSel = 1; 1249 1250 /* Select the PLL for the PHY 1251 * DP PHY should be clocked from external src if there is 1252 * one. 1253 */ 1254 /* On DCE5 DCPLL usually generates the DP ref clock */ 1255 if (is_dp) { 1256 if (rdev->clock.dp_extclk) 1257 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; 1258 else 1259 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; 1260 } else 1261 args.v4.acConfig.ucRefClkSource = pll_id; 1262 1263 switch (radeon_encoder->encoder_id) { 1264 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1265 args.v4.acConfig.ucTransmitterSel = 0; 1266 break; 1267 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1268 args.v4.acConfig.ucTransmitterSel = 1; 1269 break; 1270 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1271 args.v4.acConfig.ucTransmitterSel = 2; 1272 break; 1273 } 1274 1275 if (is_dp) 1276 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1277 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1278 if (dig->coherent_mode) 1279 args.v4.acConfig.fCoherentMode = 1; 1280 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1281 args.v4.acConfig.fDualLinkConnector = 1; 1282 } 1283 break; 1284 case 5: 1285 args.v5.ucAction = action; 1286 if (is_dp) 1287 args.v5.usSymClock = cpu_to_le16(dp_clock / 10); 1288 else 1289 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1290 1291 switch (radeon_encoder->encoder_id) { 1292 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1293 if (dig->linkb) 1294 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; 1295 else 1296 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; 1297 break; 1298 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1299 if (dig->linkb) 1300 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; 1301 else 1302 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; 1303 break; 1304 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1305 if (dig->linkb) 1306 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; 1307 else 1308 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; 1309 break; 1310 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1311 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG; 1312 break; 1313 } 1314 if (is_dp) 1315 args.v5.ucLaneNum = dp_lane_count; 1316 else if (radeon_encoder->pixel_clock > 165000) 1317 args.v5.ucLaneNum = 8; 1318 else 1319 args.v5.ucLaneNum = 4; 1320 args.v5.ucConnObjId = connector_object_id; 1321 args.v5.ucDigMode = atombios_get_encoder_mode(encoder); 1322 1323 if (is_dp && rdev->clock.dp_extclk) 1324 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK; 1325 else 1326 args.v5.asConfig.ucPhyClkSrcId = pll_id; 1327 1328 if (is_dp) 1329 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ 1330 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1331 if (dig->coherent_mode) 1332 args.v5.asConfig.ucCoherentMode = 1; 1333 } 1334 if (hpd_id == RADEON_HPD_NONE) 1335 args.v5.asConfig.ucHPDSel = 0; 1336 else 1337 args.v5.asConfig.ucHPDSel = hpd_id + 1; 1338 args.v5.ucDigEncoderSel = 1 << dig_encoder; 1339 args.v5.ucDPLaneSet = lane_set; 1340 break; 1341 default: 1342 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1343 break; 1344 } 1345 break; 1346 default: 1347 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1348 break; 1349 } 1350 1351 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1352 } 1353 1354 bool 1355 atombios_set_edp_panel_power(struct drm_connector *connector, int action) 1356 { 1357 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1358 struct drm_device *dev = radeon_connector->base.dev; 1359 struct radeon_device *rdev = dev->dev_private; 1360 union dig_transmitter_control args; 1361 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1362 uint8_t frev, crev; 1363 1364 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) 1365 goto done; 1366 1367 if (!ASIC_IS_DCE4(rdev)) 1368 goto done; 1369 1370 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && 1371 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) 1372 goto done; 1373 1374 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1375 goto done; 1376 1377 memset(&args, 0, sizeof(args)); 1378 1379 args.v1.ucAction = action; 1380 1381 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1382 1383 /* wait for the panel to power up */ 1384 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { 1385 int i; 1386 1387 for (i = 0; i < 300; i++) { 1388 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) 1389 return true; 1390 mdelay(1); 1391 } 1392 return false; 1393 } 1394 done: 1395 return true; 1396 } 1397 1398 union external_encoder_control { 1399 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; 1400 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; 1401 }; 1402 1403 static void 1404 atombios_external_encoder_setup(struct drm_encoder *encoder, 1405 struct drm_encoder *ext_encoder, 1406 int action) 1407 { 1408 struct drm_device *dev = encoder->dev; 1409 struct radeon_device *rdev = dev->dev_private; 1410 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1411 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); 1412 union external_encoder_control args; 1413 struct drm_connector *connector; 1414 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); 1415 u8 frev, crev; 1416 int dp_clock = 0; 1417 int dp_lane_count = 0; 1418 int connector_object_id = 0; 1419 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1420 1421 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1422 connector = radeon_get_connector_for_encoder_init(encoder); 1423 else 1424 connector = radeon_get_connector_for_encoder(encoder); 1425 1426 if (connector) { 1427 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1428 struct radeon_connector_atom_dig *dig_connector = 1429 radeon_connector->con_priv; 1430 1431 dp_clock = dig_connector->dp_clock; 1432 dp_lane_count = dig_connector->dp_lane_count; 1433 connector_object_id = 1434 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1435 } 1436 1437 memset(&args, 0, sizeof(args)); 1438 1439 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1440 return; 1441 1442 switch (frev) { 1443 case 1: 1444 /* no params on frev 1 */ 1445 break; 1446 case 2: 1447 switch (crev) { 1448 case 1: 1449 case 2: 1450 args.v1.sDigEncoder.ucAction = action; 1451 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1452 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1453 1454 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) { 1455 if (dp_clock == 270000) 1456 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 1457 args.v1.sDigEncoder.ucLaneNum = dp_lane_count; 1458 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1459 args.v1.sDigEncoder.ucLaneNum = 8; 1460 else 1461 args.v1.sDigEncoder.ucLaneNum = 4; 1462 break; 1463 case 3: 1464 args.v3.sExtEncoder.ucAction = action; 1465 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1466 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); 1467 else 1468 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1469 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1470 1471 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { 1472 if (dp_clock == 270000) 1473 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 1474 else if (dp_clock == 540000) 1475 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; 1476 args.v3.sExtEncoder.ucLaneNum = dp_lane_count; 1477 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1478 args.v3.sExtEncoder.ucLaneNum = 8; 1479 else 1480 args.v3.sExtEncoder.ucLaneNum = 4; 1481 switch (ext_enum) { 1482 case GRAPH_OBJECT_ENUM_ID1: 1483 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; 1484 break; 1485 case GRAPH_OBJECT_ENUM_ID2: 1486 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; 1487 break; 1488 case GRAPH_OBJECT_ENUM_ID3: 1489 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; 1490 break; 1491 } 1492 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder); 1493 break; 1494 default: 1495 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1496 return; 1497 } 1498 break; 1499 default: 1500 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1501 return; 1502 } 1503 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1504 } 1505 1506 static void 1507 atombios_yuv_setup(struct drm_encoder *encoder, bool enable) 1508 { 1509 struct drm_device *dev = encoder->dev; 1510 struct radeon_device *rdev = dev->dev_private; 1511 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1512 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1513 ENABLE_YUV_PS_ALLOCATION args; 1514 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); 1515 uint32_t temp, reg; 1516 1517 memset(&args, 0, sizeof(args)); 1518 1519 if (rdev->family >= CHIP_R600) 1520 reg = R600_BIOS_3_SCRATCH; 1521 else 1522 reg = RADEON_BIOS_3_SCRATCH; 1523 1524 /* XXX: fix up scratch reg handling */ 1525 temp = RREG32(reg); 1526 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1527 WREG32(reg, (ATOM_S3_TV1_ACTIVE | 1528 (radeon_crtc->crtc_id << 18))); 1529 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1530 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); 1531 else 1532 WREG32(reg, 0); 1533 1534 if (enable) 1535 args.ucEnable = ATOM_ENABLE; 1536 args.ucCRTC = radeon_crtc->crtc_id; 1537 1538 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1539 1540 WREG32(reg, temp); 1541 } 1542 1543 static void 1544 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode) 1545 { 1546 struct drm_device *dev = encoder->dev; 1547 struct radeon_device *rdev = dev->dev_private; 1548 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1549 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 1550 int index = 0; 1551 1552 memset(&args, 0, sizeof(args)); 1553 1554 switch (radeon_encoder->encoder_id) { 1555 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1556 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1557 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); 1558 break; 1559 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1560 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1561 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1562 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1563 break; 1564 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1565 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1566 break; 1567 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1568 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1569 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1570 else 1571 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); 1572 break; 1573 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1574 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1575 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1576 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1577 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1578 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1579 else 1580 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 1581 break; 1582 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1583 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1584 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1585 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1586 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1587 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1588 else 1589 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 1590 break; 1591 default: 1592 return; 1593 } 1594 1595 switch (mode) { 1596 case DRM_MODE_DPMS_ON: 1597 args.ucAction = ATOM_ENABLE; 1598 /* workaround for DVOOutputControl on some RS690 systems */ 1599 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { 1600 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); 1601 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); 1602 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1603 WREG32(RADEON_BIOS_3_SCRATCH, reg); 1604 } else 1605 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1606 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1607 args.ucAction = ATOM_LCD_BLON; 1608 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1609 } 1610 break; 1611 case DRM_MODE_DPMS_STANDBY: 1612 case DRM_MODE_DPMS_SUSPEND: 1613 case DRM_MODE_DPMS_OFF: 1614 args.ucAction = ATOM_DISABLE; 1615 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1616 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1617 args.ucAction = ATOM_LCD_BLOFF; 1618 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1619 } 1620 break; 1621 } 1622 } 1623 1624 static void 1625 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 1626 { 1627 struct drm_device *dev = encoder->dev; 1628 struct radeon_device *rdev = dev->dev_private; 1629 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1630 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1631 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1632 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1633 struct radeon_connector *radeon_connector = NULL; 1634 struct radeon_connector_atom_dig *radeon_dig_connector = NULL; 1635 1636 if (connector) { 1637 radeon_connector = to_radeon_connector(connector); 1638 radeon_dig_connector = radeon_connector->con_priv; 1639 } 1640 1641 switch (mode) { 1642 case DRM_MODE_DPMS_ON: 1643 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 1644 if (!connector) 1645 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 1646 else 1647 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector); 1648 1649 /* setup and enable the encoder */ 1650 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1651 atombios_dig_encoder_setup(encoder, 1652 ATOM_ENCODER_CMD_SETUP_PANEL_MODE, 1653 dig->panel_mode); 1654 if (ext_encoder) { 1655 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) 1656 atombios_external_encoder_setup(encoder, ext_encoder, 1657 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); 1658 } 1659 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1660 } else if (ASIC_IS_DCE4(rdev)) { 1661 /* setup and enable the encoder */ 1662 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1663 /* enable the transmitter */ 1664 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1665 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1666 } else { 1667 /* setup and enable the encoder and transmitter */ 1668 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); 1669 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1670 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1671 /* some dce3.x boards have a bug in their transmitter control table. 1672 * ACTION_ENABLE_OUTPUT can probably be dropped since ACTION_ENABLE 1673 * does the same thing and more. 1674 */ 1675 if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730) && 1676 (rdev->family != CHIP_RS780) && (rdev->family != CHIP_RS880)) 1677 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1678 } 1679 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1680 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1681 atombios_set_edp_panel_power(connector, 1682 ATOM_TRANSMITTER_ACTION_POWER_ON); 1683 radeon_dig_connector->edp_on = true; 1684 } 1685 radeon_dp_link_train(encoder, connector); 1686 if (ASIC_IS_DCE4(rdev)) 1687 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); 1688 } 1689 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1690 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 1691 break; 1692 case DRM_MODE_DPMS_STANDBY: 1693 case DRM_MODE_DPMS_SUSPEND: 1694 case DRM_MODE_DPMS_OFF: 1695 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 1696 /* disable the transmitter */ 1697 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1698 } else if (ASIC_IS_DCE4(rdev)) { 1699 /* disable the transmitter */ 1700 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); 1701 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1702 } else { 1703 /* disable the encoder and transmitter */ 1704 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); 1705 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1706 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); 1707 } 1708 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1709 if (ASIC_IS_DCE4(rdev)) 1710 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1711 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1712 atombios_set_edp_panel_power(connector, 1713 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1714 radeon_dig_connector->edp_on = false; 1715 } 1716 } 1717 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1718 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 1719 break; 1720 } 1721 } 1722 1723 static void 1724 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder, 1725 struct drm_encoder *ext_encoder, 1726 int mode) 1727 { 1728 struct drm_device *dev = encoder->dev; 1729 struct radeon_device *rdev = dev->dev_private; 1730 1731 switch (mode) { 1732 case DRM_MODE_DPMS_ON: 1733 default: 1734 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) { 1735 atombios_external_encoder_setup(encoder, ext_encoder, 1736 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT); 1737 atombios_external_encoder_setup(encoder, ext_encoder, 1738 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF); 1739 } else 1740 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1741 break; 1742 case DRM_MODE_DPMS_STANDBY: 1743 case DRM_MODE_DPMS_SUSPEND: 1744 case DRM_MODE_DPMS_OFF: 1745 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) { 1746 atombios_external_encoder_setup(encoder, ext_encoder, 1747 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING); 1748 atombios_external_encoder_setup(encoder, ext_encoder, 1749 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT); 1750 } else 1751 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); 1752 break; 1753 } 1754 } 1755 1756 static void 1757 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 1758 { 1759 struct drm_device *dev = encoder->dev; 1760 struct radeon_device *rdev = dev->dev_private; 1761 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1762 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1763 1764 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", 1765 radeon_encoder->encoder_id, mode, radeon_encoder->devices, 1766 radeon_encoder->active_device); 1767 switch (radeon_encoder->encoder_id) { 1768 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1769 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1770 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1771 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1772 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1773 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1774 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1775 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1776 radeon_atom_encoder_dpms_avivo(encoder, mode); 1777 break; 1778 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1779 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1780 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1781 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1782 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1783 radeon_atom_encoder_dpms_dig(encoder, mode); 1784 break; 1785 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1786 if (ASIC_IS_DCE5(rdev)) { 1787 switch (mode) { 1788 case DRM_MODE_DPMS_ON: 1789 atombios_dvo_setup(encoder, ATOM_ENABLE); 1790 break; 1791 case DRM_MODE_DPMS_STANDBY: 1792 case DRM_MODE_DPMS_SUSPEND: 1793 case DRM_MODE_DPMS_OFF: 1794 atombios_dvo_setup(encoder, ATOM_DISABLE); 1795 break; 1796 } 1797 } else if (ASIC_IS_DCE3(rdev)) 1798 radeon_atom_encoder_dpms_dig(encoder, mode); 1799 else 1800 radeon_atom_encoder_dpms_avivo(encoder, mode); 1801 break; 1802 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1803 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1804 if (ASIC_IS_DCE5(rdev)) { 1805 switch (mode) { 1806 case DRM_MODE_DPMS_ON: 1807 atombios_dac_setup(encoder, ATOM_ENABLE); 1808 break; 1809 case DRM_MODE_DPMS_STANDBY: 1810 case DRM_MODE_DPMS_SUSPEND: 1811 case DRM_MODE_DPMS_OFF: 1812 atombios_dac_setup(encoder, ATOM_DISABLE); 1813 break; 1814 } 1815 } else 1816 radeon_atom_encoder_dpms_avivo(encoder, mode); 1817 break; 1818 default: 1819 return; 1820 } 1821 1822 if (ext_encoder) 1823 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode); 1824 1825 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1826 1827 } 1828 1829 union crtc_source_param { 1830 SELECT_CRTC_SOURCE_PS_ALLOCATION v1; 1831 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; 1832 }; 1833 1834 static void 1835 atombios_set_encoder_crtc_source(struct drm_encoder *encoder) 1836 { 1837 struct drm_device *dev = encoder->dev; 1838 struct radeon_device *rdev = dev->dev_private; 1839 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1840 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1841 union crtc_source_param args; 1842 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 1843 uint8_t frev, crev; 1844 struct radeon_encoder_atom_dig *dig; 1845 1846 memset(&args, 0, sizeof(args)); 1847 1848 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1849 return; 1850 1851 switch (frev) { 1852 case 1: 1853 switch (crev) { 1854 case 1: 1855 default: 1856 if (ASIC_IS_AVIVO(rdev)) 1857 args.v1.ucCRTC = radeon_crtc->crtc_id; 1858 else { 1859 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { 1860 args.v1.ucCRTC = radeon_crtc->crtc_id; 1861 } else { 1862 args.v1.ucCRTC = radeon_crtc->crtc_id << 2; 1863 } 1864 } 1865 switch (radeon_encoder->encoder_id) { 1866 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1867 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1868 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; 1869 break; 1870 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1871 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1872 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) 1873 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; 1874 else 1875 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; 1876 break; 1877 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1878 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1879 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1880 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; 1881 break; 1882 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1883 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1884 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1885 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1886 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1887 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1888 else 1889 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; 1890 break; 1891 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1892 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1893 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1894 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1895 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1896 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1897 else 1898 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; 1899 break; 1900 } 1901 break; 1902 case 2: 1903 args.v2.ucCRTC = radeon_crtc->crtc_id; 1904 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { 1905 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1906 1907 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) 1908 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1909 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) 1910 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; 1911 else 1912 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1913 } else 1914 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1915 switch (radeon_encoder->encoder_id) { 1916 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1917 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1918 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1919 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1920 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1921 dig = radeon_encoder->enc_priv; 1922 switch (dig->dig_encoder) { 1923 case 0: 1924 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 1925 break; 1926 case 1: 1927 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1928 break; 1929 case 2: 1930 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 1931 break; 1932 case 3: 1933 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 1934 break; 1935 case 4: 1936 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 1937 break; 1938 case 5: 1939 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 1940 break; 1941 case 6: 1942 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; 1943 break; 1944 } 1945 break; 1946 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1947 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; 1948 break; 1949 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1950 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1951 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1952 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1953 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1954 else 1955 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; 1956 break; 1957 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1958 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1959 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1960 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1961 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1962 else 1963 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; 1964 break; 1965 } 1966 break; 1967 } 1968 break; 1969 default: 1970 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1971 return; 1972 } 1973 1974 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1975 1976 /* update scratch regs with new routing */ 1977 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1978 } 1979 1980 static void 1981 atombios_apply_encoder_quirks(struct drm_encoder *encoder, 1982 struct drm_display_mode *mode) 1983 { 1984 struct drm_device *dev = encoder->dev; 1985 struct radeon_device *rdev = dev->dev_private; 1986 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1987 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1988 1989 /* Funky macbooks */ 1990 if ((dev->pdev->device == 0x71C5) && 1991 (dev->pdev->subsystem_vendor == 0x106b) && 1992 (dev->pdev->subsystem_device == 0x0080)) { 1993 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 1994 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); 1995 1996 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; 1997 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 1998 1999 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); 2000 } 2001 } 2002 2003 /* set scaler clears this on some chips */ 2004 if (ASIC_IS_AVIVO(rdev) && 2005 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { 2006 if (ASIC_IS_DCE8(rdev)) { 2007 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2008 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 2009 CIK_INTERLEAVE_EN); 2010 else 2011 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2012 } else if (ASIC_IS_DCE4(rdev)) { 2013 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2014 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 2015 EVERGREEN_INTERLEAVE_EN); 2016 else 2017 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2018 } else { 2019 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2020 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 2021 AVIVO_D1MODE_INTERLEAVE_EN); 2022 else 2023 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2024 } 2025 } 2026 } 2027 2028 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) 2029 { 2030 struct drm_device *dev = encoder->dev; 2031 struct radeon_device *rdev = dev->dev_private; 2032 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 2033 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2034 struct drm_encoder *test_encoder; 2035 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2036 uint32_t dig_enc_in_use = 0; 2037 2038 if (ASIC_IS_DCE6(rdev)) { 2039 /* DCE6 */ 2040 switch (radeon_encoder->encoder_id) { 2041 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2042 if (dig->linkb) 2043 return 1; 2044 else 2045 return 0; 2046 break; 2047 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2048 if (dig->linkb) 2049 return 3; 2050 else 2051 return 2; 2052 break; 2053 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2054 if (dig->linkb) 2055 return 5; 2056 else 2057 return 4; 2058 break; 2059 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2060 return 6; 2061 break; 2062 } 2063 } else if (ASIC_IS_DCE4(rdev)) { 2064 /* DCE4/5 */ 2065 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) { 2066 /* ontario follows DCE4 */ 2067 if (rdev->family == CHIP_PALM) { 2068 if (dig->linkb) 2069 return 1; 2070 else 2071 return 0; 2072 } else 2073 /* llano follows DCE3.2 */ 2074 return radeon_crtc->crtc_id; 2075 } else { 2076 switch (radeon_encoder->encoder_id) { 2077 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2078 if (dig->linkb) 2079 return 1; 2080 else 2081 return 0; 2082 break; 2083 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2084 if (dig->linkb) 2085 return 3; 2086 else 2087 return 2; 2088 break; 2089 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2090 if (dig->linkb) 2091 return 5; 2092 else 2093 return 4; 2094 break; 2095 } 2096 } 2097 } 2098 2099 /* on DCE32 and encoder can driver any block so just crtc id */ 2100 if (ASIC_IS_DCE32(rdev)) { 2101 return radeon_crtc->crtc_id; 2102 } 2103 2104 /* on DCE3 - LVTMA can only be driven by DIGB */ 2105 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 2106 struct radeon_encoder *radeon_test_encoder; 2107 2108 if (encoder == test_encoder) 2109 continue; 2110 2111 if (!radeon_encoder_is_digital(test_encoder)) 2112 continue; 2113 2114 radeon_test_encoder = to_radeon_encoder(test_encoder); 2115 dig = radeon_test_encoder->enc_priv; 2116 2117 if (dig->dig_encoder >= 0) 2118 dig_enc_in_use |= (1 << dig->dig_encoder); 2119 } 2120 2121 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { 2122 if (dig_enc_in_use & 0x2) 2123 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); 2124 return 1; 2125 } 2126 if (!(dig_enc_in_use & 1)) 2127 return 0; 2128 return 1; 2129 } 2130 2131 /* This only needs to be called once at startup */ 2132 void 2133 radeon_atom_encoder_init(struct radeon_device *rdev) 2134 { 2135 struct drm_device *dev = rdev->ddev; 2136 struct drm_encoder *encoder; 2137 2138 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2139 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2140 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2141 2142 switch (radeon_encoder->encoder_id) { 2143 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2144 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2145 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2146 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2147 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2148 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); 2149 break; 2150 default: 2151 break; 2152 } 2153 2154 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))) 2155 atombios_external_encoder_setup(encoder, ext_encoder, 2156 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); 2157 } 2158 } 2159 2160 static void 2161 radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 2162 struct drm_display_mode *mode, 2163 struct drm_display_mode *adjusted_mode) 2164 { 2165 struct drm_device *dev = encoder->dev; 2166 struct radeon_device *rdev = dev->dev_private; 2167 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2168 2169 radeon_encoder->pixel_clock = adjusted_mode->clock; 2170 2171 /* need to call this here rather than in prepare() since we need some crtc info */ 2172 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2173 2174 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { 2175 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 2176 atombios_yuv_setup(encoder, true); 2177 else 2178 atombios_yuv_setup(encoder, false); 2179 } 2180 2181 switch (radeon_encoder->encoder_id) { 2182 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2183 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2184 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2185 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2186 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 2187 break; 2188 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2189 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2190 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2191 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2192 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2193 /* handled in dpms */ 2194 break; 2195 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2196 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2197 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2198 atombios_dvo_setup(encoder, ATOM_ENABLE); 2199 break; 2200 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2201 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2202 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2203 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2204 atombios_dac_setup(encoder, ATOM_ENABLE); 2205 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { 2206 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2207 atombios_tv_setup(encoder, ATOM_ENABLE); 2208 else 2209 atombios_tv_setup(encoder, ATOM_DISABLE); 2210 } 2211 break; 2212 } 2213 2214 atombios_apply_encoder_quirks(encoder, adjusted_mode); 2215 2216 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 2217 if (rdev->asic->display.hdmi_enable) 2218 radeon_hdmi_enable(rdev, encoder, true); 2219 if (rdev->asic->display.hdmi_setmode) 2220 radeon_hdmi_setmode(rdev, encoder, adjusted_mode); 2221 } 2222 } 2223 2224 static bool 2225 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2226 { 2227 struct drm_device *dev = encoder->dev; 2228 struct radeon_device *rdev = dev->dev_private; 2229 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2230 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2231 2232 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | 2233 ATOM_DEVICE_CV_SUPPORT | 2234 ATOM_DEVICE_CRT_SUPPORT)) { 2235 DAC_LOAD_DETECTION_PS_ALLOCATION args; 2236 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); 2237 uint8_t frev, crev; 2238 2239 memset(&args, 0, sizeof(args)); 2240 2241 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2242 return false; 2243 2244 args.sDacload.ucMisc = 0; 2245 2246 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 2247 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) 2248 args.sDacload.ucDacType = ATOM_DAC_A; 2249 else 2250 args.sDacload.ucDacType = ATOM_DAC_B; 2251 2252 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) 2253 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); 2254 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) 2255 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); 2256 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2257 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); 2258 if (crev >= 3) 2259 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2260 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2261 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); 2262 if (crev >= 3) 2263 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2264 } 2265 2266 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2267 2268 return true; 2269 } else 2270 return false; 2271 } 2272 2273 static enum drm_connector_status 2274 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2275 { 2276 struct drm_device *dev = encoder->dev; 2277 struct radeon_device *rdev = dev->dev_private; 2278 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2279 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2280 uint32_t bios_0_scratch; 2281 2282 if (!atombios_dac_load_detect(encoder, connector)) { 2283 DRM_DEBUG_KMS("detect returned false \n"); 2284 return connector_status_unknown; 2285 } 2286 2287 if (rdev->family >= CHIP_R600) 2288 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2289 else 2290 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 2291 2292 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2293 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2294 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2295 return connector_status_connected; 2296 } 2297 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2298 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2299 return connector_status_connected; 2300 } 2301 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2302 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2303 return connector_status_connected; 2304 } 2305 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2306 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2307 return connector_status_connected; /* CTV */ 2308 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2309 return connector_status_connected; /* STV */ 2310 } 2311 return connector_status_disconnected; 2312 } 2313 2314 static enum drm_connector_status 2315 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2316 { 2317 struct drm_device *dev = encoder->dev; 2318 struct radeon_device *rdev = dev->dev_private; 2319 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2320 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2321 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2322 u32 bios_0_scratch; 2323 2324 if (!ASIC_IS_DCE4(rdev)) 2325 return connector_status_unknown; 2326 2327 if (!ext_encoder) 2328 return connector_status_unknown; 2329 2330 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) 2331 return connector_status_unknown; 2332 2333 /* load detect on the dp bridge */ 2334 atombios_external_encoder_setup(encoder, ext_encoder, 2335 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); 2336 2337 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2338 2339 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2340 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2341 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2342 return connector_status_connected; 2343 } 2344 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2345 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2346 return connector_status_connected; 2347 } 2348 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2349 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2350 return connector_status_connected; 2351 } 2352 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2353 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2354 return connector_status_connected; /* CTV */ 2355 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2356 return connector_status_connected; /* STV */ 2357 } 2358 return connector_status_disconnected; 2359 } 2360 2361 void 2362 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) 2363 { 2364 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2365 2366 if (ext_encoder) 2367 /* ddc_setup on the dp bridge */ 2368 atombios_external_encoder_setup(encoder, ext_encoder, 2369 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); 2370 2371 } 2372 2373 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 2374 { 2375 struct radeon_device *rdev = encoder->dev->dev_private; 2376 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2377 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2378 2379 if ((radeon_encoder->active_device & 2380 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 2381 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 2382 ENCODER_OBJECT_ID_NONE)) { 2383 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2384 if (dig) { 2385 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); 2386 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) { 2387 if (rdev->family >= CHIP_R600) 2388 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder]; 2389 else 2390 /* RS600/690/740 have only 1 afmt block */ 2391 dig->afmt = rdev->mode_info.afmt[0]; 2392 } 2393 } 2394 } 2395 2396 radeon_atom_output_lock(encoder, true); 2397 2398 if (connector) { 2399 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2400 2401 /* select the clock/data port if it uses a router */ 2402 if (radeon_connector->router.cd_valid) 2403 radeon_router_select_cd_port(radeon_connector); 2404 2405 /* turn eDP panel on for mode set */ 2406 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 2407 atombios_set_edp_panel_power(connector, 2408 ATOM_TRANSMITTER_ACTION_POWER_ON); 2409 } 2410 2411 /* this is needed for the pll/ss setup to work correctly in some cases */ 2412 atombios_set_encoder_crtc_source(encoder); 2413 } 2414 2415 static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 2416 { 2417 /* need to call this here as we need the crtc set up */ 2418 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 2419 radeon_atom_output_lock(encoder, false); 2420 } 2421 2422 static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 2423 { 2424 struct drm_device *dev = encoder->dev; 2425 struct radeon_device *rdev = dev->dev_private; 2426 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2427 struct radeon_encoder_atom_dig *dig; 2428 2429 /* check for pre-DCE3 cards with shared encoders; 2430 * can't really use the links individually, so don't disable 2431 * the encoder if it's in use by another connector 2432 */ 2433 if (!ASIC_IS_DCE3(rdev)) { 2434 struct drm_encoder *other_encoder; 2435 struct radeon_encoder *other_radeon_encoder; 2436 2437 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { 2438 other_radeon_encoder = to_radeon_encoder(other_encoder); 2439 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && 2440 drm_helper_encoder_in_use(other_encoder)) 2441 goto disable_done; 2442 } 2443 } 2444 2445 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2446 2447 switch (radeon_encoder->encoder_id) { 2448 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2449 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2450 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2451 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2452 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); 2453 break; 2454 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2455 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2456 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2457 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2458 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2459 /* handled in dpms */ 2460 break; 2461 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2462 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2463 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2464 atombios_dvo_setup(encoder, ATOM_DISABLE); 2465 break; 2466 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2467 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2468 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2469 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2470 atombios_dac_setup(encoder, ATOM_DISABLE); 2471 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2472 atombios_tv_setup(encoder, ATOM_DISABLE); 2473 break; 2474 } 2475 2476 disable_done: 2477 if (radeon_encoder_is_digital(encoder)) { 2478 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 2479 if (rdev->asic->display.hdmi_enable) 2480 radeon_hdmi_enable(rdev, encoder, false); 2481 } 2482 dig = radeon_encoder->enc_priv; 2483 dig->dig_encoder = -1; 2484 } 2485 radeon_encoder->active_device = 0; 2486 } 2487 2488 /* these are handled by the primary encoders */ 2489 static void radeon_atom_ext_prepare(struct drm_encoder *encoder) 2490 { 2491 2492 } 2493 2494 static void radeon_atom_ext_commit(struct drm_encoder *encoder) 2495 { 2496 2497 } 2498 2499 static void 2500 radeon_atom_ext_mode_set(struct drm_encoder *encoder, 2501 struct drm_display_mode *mode, 2502 struct drm_display_mode *adjusted_mode) 2503 { 2504 2505 } 2506 2507 static void radeon_atom_ext_disable(struct drm_encoder *encoder) 2508 { 2509 2510 } 2511 2512 static void 2513 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) 2514 { 2515 2516 } 2517 2518 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder, 2519 const struct drm_display_mode *mode, 2520 struct drm_display_mode *adjusted_mode) 2521 { 2522 return true; 2523 } 2524 2525 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { 2526 .dpms = radeon_atom_ext_dpms, 2527 .mode_fixup = radeon_atom_ext_mode_fixup, 2528 .prepare = radeon_atom_ext_prepare, 2529 .mode_set = radeon_atom_ext_mode_set, 2530 .commit = radeon_atom_ext_commit, 2531 .disable = radeon_atom_ext_disable, 2532 /* no detect for TMDS/LVDS yet */ 2533 }; 2534 2535 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { 2536 .dpms = radeon_atom_encoder_dpms, 2537 .mode_fixup = radeon_atom_mode_fixup, 2538 .prepare = radeon_atom_encoder_prepare, 2539 .mode_set = radeon_atom_encoder_mode_set, 2540 .commit = radeon_atom_encoder_commit, 2541 .disable = radeon_atom_encoder_disable, 2542 .detect = radeon_atom_dig_detect, 2543 }; 2544 2545 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { 2546 .dpms = radeon_atom_encoder_dpms, 2547 .mode_fixup = radeon_atom_mode_fixup, 2548 .prepare = radeon_atom_encoder_prepare, 2549 .mode_set = radeon_atom_encoder_mode_set, 2550 .commit = radeon_atom_encoder_commit, 2551 .detect = radeon_atom_dac_detect, 2552 }; 2553 2554 void radeon_enc_destroy(struct drm_encoder *encoder) 2555 { 2556 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2557 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2558 radeon_atom_backlight_exit(radeon_encoder); 2559 kfree(radeon_encoder->enc_priv); 2560 drm_encoder_cleanup(encoder); 2561 kfree(radeon_encoder); 2562 } 2563 2564 static const struct drm_encoder_funcs radeon_atom_enc_funcs = { 2565 .destroy = radeon_enc_destroy, 2566 }; 2567 2568 static struct radeon_encoder_atom_dac * 2569 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) 2570 { 2571 struct drm_device *dev = radeon_encoder->base.dev; 2572 struct radeon_device *rdev = dev->dev_private; 2573 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); 2574 2575 if (!dac) 2576 return NULL; 2577 2578 dac->tv_std = radeon_atombios_get_tv_info(rdev); 2579 return dac; 2580 } 2581 2582 static struct radeon_encoder_atom_dig * 2583 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) 2584 { 2585 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 2586 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 2587 2588 if (!dig) 2589 return NULL; 2590 2591 /* coherent mode by default */ 2592 dig->coherent_mode = true; 2593 dig->dig_encoder = -1; 2594 2595 if (encoder_enum == 2) 2596 dig->linkb = true; 2597 else 2598 dig->linkb = false; 2599 2600 return dig; 2601 } 2602 2603 void 2604 radeon_add_atom_encoder(struct drm_device *dev, 2605 uint32_t encoder_enum, 2606 uint32_t supported_device, 2607 u16 caps) 2608 { 2609 struct radeon_device *rdev = dev->dev_private; 2610 struct drm_encoder *encoder; 2611 struct radeon_encoder *radeon_encoder; 2612 2613 /* see if we already added it */ 2614 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2615 radeon_encoder = to_radeon_encoder(encoder); 2616 if (radeon_encoder->encoder_enum == encoder_enum) { 2617 radeon_encoder->devices |= supported_device; 2618 return; 2619 } 2620 2621 } 2622 2623 /* add a new one */ 2624 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); 2625 if (!radeon_encoder) 2626 return; 2627 2628 encoder = &radeon_encoder->base; 2629 switch (rdev->num_crtc) { 2630 case 1: 2631 encoder->possible_crtcs = 0x1; 2632 break; 2633 case 2: 2634 default: 2635 encoder->possible_crtcs = 0x3; 2636 break; 2637 case 4: 2638 encoder->possible_crtcs = 0xf; 2639 break; 2640 case 6: 2641 encoder->possible_crtcs = 0x3f; 2642 break; 2643 } 2644 2645 radeon_encoder->enc_priv = NULL; 2646 2647 radeon_encoder->encoder_enum = encoder_enum; 2648 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 2649 radeon_encoder->devices = supported_device; 2650 radeon_encoder->rmx_type = RMX_OFF; 2651 radeon_encoder->underscan_type = UNDERSCAN_OFF; 2652 radeon_encoder->is_ext_encoder = false; 2653 radeon_encoder->caps = caps; 2654 2655 switch (radeon_encoder->encoder_id) { 2656 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2657 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2658 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2659 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2660 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2661 radeon_encoder->rmx_type = RMX_FULL; 2662 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2663 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2664 } else { 2665 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2666 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2667 } 2668 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2669 break; 2670 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2671 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2672 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2673 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2674 break; 2675 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2676 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2677 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2678 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); 2679 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2680 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2681 break; 2682 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2683 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2684 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2685 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2686 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2687 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2688 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2689 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2690 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2691 radeon_encoder->rmx_type = RMX_FULL; 2692 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2693 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2694 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 2695 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2696 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2697 } else { 2698 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2699 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2700 } 2701 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2702 break; 2703 case ENCODER_OBJECT_ID_SI170B: 2704 case ENCODER_OBJECT_ID_CH7303: 2705 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 2706 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 2707 case ENCODER_OBJECT_ID_TITFP513: 2708 case ENCODER_OBJECT_ID_VT1623: 2709 case ENCODER_OBJECT_ID_HDMI_SI1930: 2710 case ENCODER_OBJECT_ID_TRAVIS: 2711 case ENCODER_OBJECT_ID_NUTMEG: 2712 /* these are handled by the primary encoders */ 2713 radeon_encoder->is_ext_encoder = true; 2714 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2715 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2716 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 2717 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2718 else 2719 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2720 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); 2721 break; 2722 } 2723 } 2724