1 /*
2  * Copyright 2007-11 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: Dave Airlie
24  *          Alex Deucher
25  */
26 #include <drm/drmP.h>
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include "radeon.h"
30 #include "atom.h"
31 #include <linux/backlight.h>
32 
33 extern int atom_debug;
34 
35 static u8
36 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
37 {
38 	u8 backlight_level;
39 	u32 bios_2_scratch;
40 
41 	if (rdev->family >= CHIP_R600)
42 		bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
43 	else
44 		bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
45 
46 	backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
47 			   ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
48 
49 	return backlight_level;
50 }
51 
52 static void
53 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
54 				       u8 backlight_level)
55 {
56 	u32 bios_2_scratch;
57 
58 	if (rdev->family >= CHIP_R600)
59 		bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
60 	else
61 		bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
62 
63 	bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
64 	bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
65 			   ATOM_S2_CURRENT_BL_LEVEL_MASK);
66 
67 	if (rdev->family >= CHIP_R600)
68 		WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
69 	else
70 		WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
71 }
72 
73 u8
74 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
75 {
76 	struct drm_device *dev = radeon_encoder->base.dev;
77 	struct radeon_device *rdev = dev->dev_private;
78 
79 	if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
80 		return 0;
81 
82 	return radeon_atom_get_backlight_level_from_reg(rdev);
83 }
84 
85 void
86 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
87 {
88 	struct drm_encoder *encoder = &radeon_encoder->base;
89 	struct drm_device *dev = radeon_encoder->base.dev;
90 	struct radeon_device *rdev = dev->dev_private;
91 	struct radeon_encoder_atom_dig *dig;
92 	DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
93 	int index;
94 
95 	if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
96 		return;
97 
98 	if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
99 	    radeon_encoder->enc_priv) {
100 		dig = radeon_encoder->enc_priv;
101 		dig->backlight_level = level;
102 		radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
103 
104 		switch (radeon_encoder->encoder_id) {
105 		case ENCODER_OBJECT_ID_INTERNAL_LVDS:
106 		case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
107 			index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
108 			if (dig->backlight_level == 0) {
109 				args.ucAction = ATOM_LCD_BLOFF;
110 				atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
111 			} else {
112 				args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
113 				atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
114 				args.ucAction = ATOM_LCD_BLON;
115 				atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
116 			}
117 			break;
118 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
119 		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
120 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
121 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
122 			if (dig->backlight_level == 0)
123 				atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
124 			else {
125 				atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
126 				atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
127 			}
128 			break;
129 		default:
130 			break;
131 		}
132 	}
133 }
134 
135 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
136 
137 static u8 radeon_atom_bl_level(struct backlight_device *bd)
138 {
139 	u8 level;
140 
141 	/* Convert brightness to hardware level */
142 	if (bd->props.brightness < 0)
143 		level = 0;
144 	else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
145 		level = RADEON_MAX_BL_LEVEL;
146 	else
147 		level = bd->props.brightness;
148 
149 	return level;
150 }
151 
152 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
153 {
154 	struct radeon_backlight_privdata *pdata = bl_get_data(bd);
155 	struct radeon_encoder *radeon_encoder = pdata->encoder;
156 
157 	atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
158 
159 	return 0;
160 }
161 
162 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
163 {
164 	struct radeon_backlight_privdata *pdata = bl_get_data(bd);
165 	struct radeon_encoder *radeon_encoder = pdata->encoder;
166 	struct drm_device *dev = radeon_encoder->base.dev;
167 	struct radeon_device *rdev = dev->dev_private;
168 
169 	return radeon_atom_get_backlight_level_from_reg(rdev);
170 }
171 
172 static const struct backlight_ops radeon_atom_backlight_ops = {
173 	.get_brightness = radeon_atom_backlight_get_brightness,
174 	.update_status	= radeon_atom_backlight_update_status,
175 };
176 
177 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
178 				struct drm_connector *drm_connector)
179 {
180 	struct drm_device *dev = radeon_encoder->base.dev;
181 	struct radeon_device *rdev = dev->dev_private;
182 	struct backlight_device *bd;
183 	struct backlight_properties props;
184 	struct radeon_backlight_privdata *pdata;
185 	struct radeon_encoder_atom_dig *dig;
186 	u8 backlight_level;
187 	char bl_name[16];
188 
189 	/* Mac laptops with multiple GPUs use the gmux driver for backlight
190 	 * so don't register a backlight device
191 	 */
192 	if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
193 	    (rdev->pdev->device == 0x6741))
194 		return;
195 
196 	if (!radeon_encoder->enc_priv)
197 		return;
198 
199 	if (!rdev->is_atom_bios)
200 		return;
201 
202 	if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
203 		return;
204 
205 	pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
206 	if (!pdata) {
207 		DRM_ERROR("Memory allocation failed\n");
208 		goto error;
209 	}
210 
211 	memset(&props, 0, sizeof(props));
212 	props.max_brightness = RADEON_MAX_BL_LEVEL;
213 	props.type = BACKLIGHT_RAW;
214 	snprintf(bl_name, sizeof(bl_name),
215 		 "radeon_bl%d", dev->primary->index);
216 	bd = backlight_device_register(bl_name, &drm_connector->kdev,
217 				       pdata, &radeon_atom_backlight_ops, &props);
218 	if (IS_ERR(bd)) {
219 		DRM_ERROR("Backlight registration failed\n");
220 		goto error;
221 	}
222 
223 	pdata->encoder = radeon_encoder;
224 
225 	backlight_level = radeon_atom_get_backlight_level_from_reg(rdev);
226 
227 	dig = radeon_encoder->enc_priv;
228 	dig->bl_dev = bd;
229 
230 	bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
231 	bd->props.power = FB_BLANK_UNBLANK;
232 	backlight_update_status(bd);
233 
234 	DRM_INFO("radeon atom DIG backlight initialized\n");
235 
236 	return;
237 
238 error:
239 	kfree(pdata);
240 	return;
241 }
242 
243 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
244 {
245 	struct drm_device *dev = radeon_encoder->base.dev;
246 	struct radeon_device *rdev = dev->dev_private;
247 	struct backlight_device *bd = NULL;
248 	struct radeon_encoder_atom_dig *dig;
249 
250 	if (!radeon_encoder->enc_priv)
251 		return;
252 
253 	if (!rdev->is_atom_bios)
254 		return;
255 
256 	if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
257 		return;
258 
259 	dig = radeon_encoder->enc_priv;
260 	bd = dig->bl_dev;
261 	dig->bl_dev = NULL;
262 
263 	if (bd) {
264 		struct radeon_legacy_backlight_privdata *pdata;
265 
266 		pdata = bl_get_data(bd);
267 		backlight_device_unregister(bd);
268 		kfree(pdata);
269 
270 		DRM_INFO("radeon atom LVDS backlight unloaded\n");
271 	}
272 }
273 
274 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
275 
276 void radeon_atom_backlight_init(struct radeon_encoder *encoder)
277 {
278 }
279 
280 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
281 {
282 }
283 
284 #endif
285 
286 /* evil but including atombios.h is much worse */
287 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
288 				struct drm_display_mode *mode);
289 
290 
291 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
292 {
293 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
294 	switch (radeon_encoder->encoder_id) {
295 	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
296 	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
297 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
298 	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
299 	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
300 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
301 	case ENCODER_OBJECT_ID_INTERNAL_DDI:
302 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
303 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
304 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
305 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
306 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
307 		return true;
308 	default:
309 		return false;
310 	}
311 }
312 
313 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
314 				   const struct drm_display_mode *mode,
315 				   struct drm_display_mode *adjusted_mode)
316 {
317 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
318 	struct drm_device *dev = encoder->dev;
319 	struct radeon_device *rdev = dev->dev_private;
320 
321 	/* set the active encoder to connector routing */
322 	radeon_encoder_set_active_device(encoder);
323 	drm_mode_set_crtcinfo(adjusted_mode, 0);
324 
325 	/* hw bug */
326 	if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
327 	    && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
328 		adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
329 
330 	/* get the native mode for LVDS */
331 	if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
332 		radeon_panel_mode_fixup(encoder, adjusted_mode);
333 
334 	/* get the native mode for TV */
335 	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
336 		struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
337 		if (tv_dac) {
338 			if (tv_dac->tv_std == TV_STD_NTSC ||
339 			    tv_dac->tv_std == TV_STD_NTSC_J ||
340 			    tv_dac->tv_std == TV_STD_PAL_M)
341 				radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
342 			else
343 				radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
344 		}
345 	}
346 
347 	if (ASIC_IS_DCE3(rdev) &&
348 	    ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
349 	     (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
350 		struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
351 		radeon_dp_set_link_config(connector, adjusted_mode);
352 	}
353 
354 	return true;
355 }
356 
357 static void
358 atombios_dac_setup(struct drm_encoder *encoder, int action)
359 {
360 	struct drm_device *dev = encoder->dev;
361 	struct radeon_device *rdev = dev->dev_private;
362 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
363 	DAC_ENCODER_CONTROL_PS_ALLOCATION args;
364 	int index = 0;
365 	struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
366 
367 	memset(&args, 0, sizeof(args));
368 
369 	switch (radeon_encoder->encoder_id) {
370 	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
371 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
372 		index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
373 		break;
374 	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
375 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
376 		index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
377 		break;
378 	}
379 
380 	args.ucAction = action;
381 
382 	if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
383 		args.ucDacStandard = ATOM_DAC1_PS2;
384 	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
385 		args.ucDacStandard = ATOM_DAC1_CV;
386 	else {
387 		switch (dac_info->tv_std) {
388 		case TV_STD_PAL:
389 		case TV_STD_PAL_M:
390 		case TV_STD_SCART_PAL:
391 		case TV_STD_SECAM:
392 		case TV_STD_PAL_CN:
393 			args.ucDacStandard = ATOM_DAC1_PAL;
394 			break;
395 		case TV_STD_NTSC:
396 		case TV_STD_NTSC_J:
397 		case TV_STD_PAL_60:
398 		default:
399 			args.ucDacStandard = ATOM_DAC1_NTSC;
400 			break;
401 		}
402 	}
403 	args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
404 
405 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
406 
407 }
408 
409 static void
410 atombios_tv_setup(struct drm_encoder *encoder, int action)
411 {
412 	struct drm_device *dev = encoder->dev;
413 	struct radeon_device *rdev = dev->dev_private;
414 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
415 	TV_ENCODER_CONTROL_PS_ALLOCATION args;
416 	int index = 0;
417 	struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
418 
419 	memset(&args, 0, sizeof(args));
420 
421 	index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
422 
423 	args.sTVEncoder.ucAction = action;
424 
425 	if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
426 		args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
427 	else {
428 		switch (dac_info->tv_std) {
429 		case TV_STD_NTSC:
430 			args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
431 			break;
432 		case TV_STD_PAL:
433 			args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
434 			break;
435 		case TV_STD_PAL_M:
436 			args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
437 			break;
438 		case TV_STD_PAL_60:
439 			args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
440 			break;
441 		case TV_STD_NTSC_J:
442 			args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
443 			break;
444 		case TV_STD_SCART_PAL:
445 			args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
446 			break;
447 		case TV_STD_SECAM:
448 			args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
449 			break;
450 		case TV_STD_PAL_CN:
451 			args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
452 			break;
453 		default:
454 			args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
455 			break;
456 		}
457 	}
458 
459 	args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
460 
461 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
462 
463 }
464 
465 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
466 {
467 	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
468 	int bpc = 8;
469 
470 	if (connector)
471 		bpc = radeon_get_monitor_bpc(connector);
472 
473 	switch (bpc) {
474 	case 0:
475 		return PANEL_BPC_UNDEFINE;
476 	case 6:
477 		return PANEL_6BIT_PER_COLOR;
478 	case 8:
479 	default:
480 		return PANEL_8BIT_PER_COLOR;
481 	case 10:
482 		return PANEL_10BIT_PER_COLOR;
483 	case 12:
484 		return PANEL_12BIT_PER_COLOR;
485 	case 16:
486 		return PANEL_16BIT_PER_COLOR;
487 	}
488 }
489 
490 union dvo_encoder_control {
491 	ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
492 	DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
493 	DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
494 	DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
495 };
496 
497 void
498 atombios_dvo_setup(struct drm_encoder *encoder, int action)
499 {
500 	struct drm_device *dev = encoder->dev;
501 	struct radeon_device *rdev = dev->dev_private;
502 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
503 	union dvo_encoder_control args;
504 	int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
505 	uint8_t frev, crev;
506 
507 	memset(&args, 0, sizeof(args));
508 
509 	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
510 		return;
511 
512 	/* some R4xx chips have the wrong frev */
513 	if (rdev->family <= CHIP_RV410)
514 		frev = 1;
515 
516 	switch (frev) {
517 	case 1:
518 		switch (crev) {
519 		case 1:
520 			/* R4xx, R5xx */
521 			args.ext_tmds.sXTmdsEncoder.ucEnable = action;
522 
523 			if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
524 				args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
525 
526 			args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
527 			break;
528 		case 2:
529 			/* RS600/690/740 */
530 			args.dvo.sDVOEncoder.ucAction = action;
531 			args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
532 			/* DFP1, CRT1, TV1 depending on the type of port */
533 			args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
534 
535 			if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
536 				args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
537 			break;
538 		case 3:
539 			/* R6xx */
540 			args.dvo_v3.ucAction = action;
541 			args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
542 			args.dvo_v3.ucDVOConfig = 0; /* XXX */
543 			break;
544 		case 4:
545 			/* DCE8 */
546 			args.dvo_v4.ucAction = action;
547 			args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
548 			args.dvo_v4.ucDVOConfig = 0; /* XXX */
549 			args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
550 			break;
551 		default:
552 			DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
553 			break;
554 		}
555 		break;
556 	default:
557 		DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
558 		break;
559 	}
560 
561 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
562 }
563 
564 union lvds_encoder_control {
565 	LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
566 	LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
567 };
568 
569 void
570 atombios_digital_setup(struct drm_encoder *encoder, int action)
571 {
572 	struct drm_device *dev = encoder->dev;
573 	struct radeon_device *rdev = dev->dev_private;
574 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
575 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
576 	union lvds_encoder_control args;
577 	int index = 0;
578 	int hdmi_detected = 0;
579 	uint8_t frev, crev;
580 
581 	if (!dig)
582 		return;
583 
584 	if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
585 		hdmi_detected = 1;
586 
587 	memset(&args, 0, sizeof(args));
588 
589 	switch (radeon_encoder->encoder_id) {
590 	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
591 		index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
592 		break;
593 	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
594 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
595 		index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
596 		break;
597 	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
598 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
599 			index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
600 		else
601 			index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
602 		break;
603 	}
604 
605 	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
606 		return;
607 
608 	switch (frev) {
609 	case 1:
610 	case 2:
611 		switch (crev) {
612 		case 1:
613 			args.v1.ucMisc = 0;
614 			args.v1.ucAction = action;
615 			if (hdmi_detected)
616 				args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
617 			args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
618 			if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
619 				if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
620 					args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
621 				if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
622 					args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
623 			} else {
624 				if (dig->linkb)
625 					args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
626 				if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
627 					args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
628 				/*if (pScrn->rgbBits == 8) */
629 				args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
630 			}
631 			break;
632 		case 2:
633 		case 3:
634 			args.v2.ucMisc = 0;
635 			args.v2.ucAction = action;
636 			if (crev == 3) {
637 				if (dig->coherent_mode)
638 					args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
639 			}
640 			if (hdmi_detected)
641 				args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
642 			args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
643 			args.v2.ucTruncate = 0;
644 			args.v2.ucSpatial = 0;
645 			args.v2.ucTemporal = 0;
646 			args.v2.ucFRC = 0;
647 			if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
648 				if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
649 					args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
650 				if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
651 					args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
652 					if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
653 						args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
654 				}
655 				if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
656 					args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
657 					if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
658 						args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
659 					if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
660 						args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
661 				}
662 			} else {
663 				if (dig->linkb)
664 					args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
665 				if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
666 					args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
667 			}
668 			break;
669 		default:
670 			DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
671 			break;
672 		}
673 		break;
674 	default:
675 		DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
676 		break;
677 	}
678 
679 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
680 }
681 
682 int
683 atombios_get_encoder_mode(struct drm_encoder *encoder)
684 {
685 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
686 	struct drm_connector *connector;
687 	struct radeon_connector *radeon_connector;
688 	struct radeon_connector_atom_dig *dig_connector;
689 
690 	/* dp bridges are always DP */
691 	if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
692 		return ATOM_ENCODER_MODE_DP;
693 
694 	/* DVO is always DVO */
695 	if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
696 	    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
697 		return ATOM_ENCODER_MODE_DVO;
698 
699 	connector = radeon_get_connector_for_encoder(encoder);
700 	/* if we don't have an active device yet, just use one of
701 	 * the connectors tied to the encoder.
702 	 */
703 	if (!connector)
704 		connector = radeon_get_connector_for_encoder_init(encoder);
705 	radeon_connector = to_radeon_connector(connector);
706 
707 	switch (connector->connector_type) {
708 	case DRM_MODE_CONNECTOR_DVII:
709 	case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
710 		if ((radeon_connector->audio == RADEON_AUDIO_ENABLE) ||
711 		    (drm_detect_hdmi_monitor(radeon_connector->edid) &&
712 		     (radeon_connector->audio == RADEON_AUDIO_AUTO)))
713 			return ATOM_ENCODER_MODE_HDMI;
714 		else if (radeon_connector->use_digital)
715 			return ATOM_ENCODER_MODE_DVI;
716 		else
717 			return ATOM_ENCODER_MODE_CRT;
718 		break;
719 	case DRM_MODE_CONNECTOR_DVID:
720 	case DRM_MODE_CONNECTOR_HDMIA:
721 	default:
722 		if ((radeon_connector->audio == RADEON_AUDIO_ENABLE) ||
723 		    (drm_detect_hdmi_monitor(radeon_connector->edid) &&
724 		     (radeon_connector->audio == RADEON_AUDIO_AUTO)))
725 			return ATOM_ENCODER_MODE_HDMI;
726 		else
727 			return ATOM_ENCODER_MODE_DVI;
728 		break;
729 	case DRM_MODE_CONNECTOR_LVDS:
730 		return ATOM_ENCODER_MODE_LVDS;
731 		break;
732 	case DRM_MODE_CONNECTOR_DisplayPort:
733 		dig_connector = radeon_connector->con_priv;
734 		if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
735 		    (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
736 			return ATOM_ENCODER_MODE_DP;
737 		else if ((radeon_connector->audio == RADEON_AUDIO_ENABLE) ||
738 			 (drm_detect_hdmi_monitor(radeon_connector->edid) &&
739 			  (radeon_connector->audio == RADEON_AUDIO_AUTO)))
740 			return ATOM_ENCODER_MODE_HDMI;
741 		else
742 			return ATOM_ENCODER_MODE_DVI;
743 		break;
744 	case DRM_MODE_CONNECTOR_eDP:
745 		return ATOM_ENCODER_MODE_DP;
746 	case DRM_MODE_CONNECTOR_DVIA:
747 	case DRM_MODE_CONNECTOR_VGA:
748 		return ATOM_ENCODER_MODE_CRT;
749 		break;
750 	case DRM_MODE_CONNECTOR_Composite:
751 	case DRM_MODE_CONNECTOR_SVIDEO:
752 	case DRM_MODE_CONNECTOR_9PinDIN:
753 		/* fix me */
754 		return ATOM_ENCODER_MODE_TV;
755 		/*return ATOM_ENCODER_MODE_CV;*/
756 		break;
757 	}
758 }
759 
760 /*
761  * DIG Encoder/Transmitter Setup
762  *
763  * DCE 3.0/3.1
764  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
765  * Supports up to 3 digital outputs
766  * - 2 DIG encoder blocks.
767  * DIG1 can drive UNIPHY link A or link B
768  * DIG2 can drive UNIPHY link B or LVTMA
769  *
770  * DCE 3.2
771  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
772  * Supports up to 5 digital outputs
773  * - 2 DIG encoder blocks.
774  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
775  *
776  * DCE 4.0/5.0/6.0
777  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
778  * Supports up to 6 digital outputs
779  * - 6 DIG encoder blocks.
780  * - DIG to PHY mapping is hardcoded
781  * DIG1 drives UNIPHY0 link A, A+B
782  * DIG2 drives UNIPHY0 link B
783  * DIG3 drives UNIPHY1 link A, A+B
784  * DIG4 drives UNIPHY1 link B
785  * DIG5 drives UNIPHY2 link A, A+B
786  * DIG6 drives UNIPHY2 link B
787  *
788  * DCE 4.1
789  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
790  * Supports up to 6 digital outputs
791  * - 2 DIG encoder blocks.
792  * llano
793  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
794  * ontario
795  * DIG1 drives UNIPHY0/1/2 link A
796  * DIG2 drives UNIPHY0/1/2 link B
797  *
798  * Routing
799  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
800  * Examples:
801  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
802  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
803  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
804  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
805  */
806 
807 union dig_encoder_control {
808 	DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
809 	DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
810 	DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
811 	DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
812 };
813 
814 void
815 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
816 {
817 	struct drm_device *dev = encoder->dev;
818 	struct radeon_device *rdev = dev->dev_private;
819 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
820 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
821 	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
822 	union dig_encoder_control args;
823 	int index = 0;
824 	uint8_t frev, crev;
825 	int dp_clock = 0;
826 	int dp_lane_count = 0;
827 	int hpd_id = RADEON_HPD_NONE;
828 
829 	if (connector) {
830 		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
831 		struct radeon_connector_atom_dig *dig_connector =
832 			radeon_connector->con_priv;
833 
834 		dp_clock = dig_connector->dp_clock;
835 		dp_lane_count = dig_connector->dp_lane_count;
836 		hpd_id = radeon_connector->hpd.hpd;
837 	}
838 
839 	/* no dig encoder assigned */
840 	if (dig->dig_encoder == -1)
841 		return;
842 
843 	memset(&args, 0, sizeof(args));
844 
845 	if (ASIC_IS_DCE4(rdev))
846 		index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
847 	else {
848 		if (dig->dig_encoder)
849 			index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
850 		else
851 			index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
852 	}
853 
854 	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
855 		return;
856 
857 	switch (frev) {
858 	case 1:
859 		switch (crev) {
860 		case 1:
861 			args.v1.ucAction = action;
862 			args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
863 			if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
864 				args.v3.ucPanelMode = panel_mode;
865 			else
866 				args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
867 
868 			if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
869 				args.v1.ucLaneNum = dp_lane_count;
870 			else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
871 				args.v1.ucLaneNum = 8;
872 			else
873 				args.v1.ucLaneNum = 4;
874 
875 			if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
876 				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
877 			switch (radeon_encoder->encoder_id) {
878 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
879 				args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
880 				break;
881 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
882 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
883 				args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
884 				break;
885 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
886 				args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
887 				break;
888 			}
889 			if (dig->linkb)
890 				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
891 			else
892 				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
893 			break;
894 		case 2:
895 		case 3:
896 			args.v3.ucAction = action;
897 			args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
898 			if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
899 				args.v3.ucPanelMode = panel_mode;
900 			else
901 				args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
902 
903 			if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
904 				args.v3.ucLaneNum = dp_lane_count;
905 			else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
906 				args.v3.ucLaneNum = 8;
907 			else
908 				args.v3.ucLaneNum = 4;
909 
910 			if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
911 				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
912 			args.v3.acConfig.ucDigSel = dig->dig_encoder;
913 			args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
914 			break;
915 		case 4:
916 			args.v4.ucAction = action;
917 			args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
918 			if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
919 				args.v4.ucPanelMode = panel_mode;
920 			else
921 				args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
922 
923 			if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
924 				args.v4.ucLaneNum = dp_lane_count;
925 			else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
926 				args.v4.ucLaneNum = 8;
927 			else
928 				args.v4.ucLaneNum = 4;
929 
930 			if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
931 				if (dp_clock == 540000)
932 					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
933 				else if (dp_clock == 324000)
934 					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
935 				else if (dp_clock == 270000)
936 					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
937 				else
938 					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
939 			}
940 			args.v4.acConfig.ucDigSel = dig->dig_encoder;
941 			args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
942 			if (hpd_id == RADEON_HPD_NONE)
943 				args.v4.ucHPD_ID = 0;
944 			else
945 				args.v4.ucHPD_ID = hpd_id + 1;
946 			break;
947 		default:
948 			DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
949 			break;
950 		}
951 		break;
952 	default:
953 		DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
954 		break;
955 	}
956 
957 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
958 
959 }
960 
961 union dig_transmitter_control {
962 	DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
963 	DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
964 	DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
965 	DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
966 	DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
967 };
968 
969 void
970 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
971 {
972 	struct drm_device *dev = encoder->dev;
973 	struct radeon_device *rdev = dev->dev_private;
974 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
975 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
976 	struct drm_connector *connector;
977 	union dig_transmitter_control args;
978 	int index = 0;
979 	uint8_t frev, crev;
980 	bool is_dp = false;
981 	int pll_id = 0;
982 	int dp_clock = 0;
983 	int dp_lane_count = 0;
984 	int connector_object_id = 0;
985 	int igp_lane_info = 0;
986 	int dig_encoder = dig->dig_encoder;
987 	int hpd_id = RADEON_HPD_NONE;
988 
989 	if (action == ATOM_TRANSMITTER_ACTION_INIT) {
990 		connector = radeon_get_connector_for_encoder_init(encoder);
991 		/* just needed to avoid bailing in the encoder check.  the encoder
992 		 * isn't used for init
993 		 */
994 		dig_encoder = 0;
995 	} else
996 		connector = radeon_get_connector_for_encoder(encoder);
997 
998 	if (connector) {
999 		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1000 		struct radeon_connector_atom_dig *dig_connector =
1001 			radeon_connector->con_priv;
1002 
1003 		hpd_id = radeon_connector->hpd.hpd;
1004 		dp_clock = dig_connector->dp_clock;
1005 		dp_lane_count = dig_connector->dp_lane_count;
1006 		connector_object_id =
1007 			(radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1008 		igp_lane_info = dig_connector->igp_lane_info;
1009 	}
1010 
1011 	if (encoder->crtc) {
1012 		struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1013 		pll_id = radeon_crtc->pll_id;
1014 	}
1015 
1016 	/* no dig encoder assigned */
1017 	if (dig_encoder == -1)
1018 		return;
1019 
1020 	if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1021 		is_dp = true;
1022 
1023 	memset(&args, 0, sizeof(args));
1024 
1025 	switch (radeon_encoder->encoder_id) {
1026 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1027 		index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1028 		break;
1029 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1030 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1031 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1032 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1033 		index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1034 		break;
1035 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1036 		index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1037 		break;
1038 	}
1039 
1040 	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1041 		return;
1042 
1043 	switch (frev) {
1044 	case 1:
1045 		switch (crev) {
1046 		case 1:
1047 			args.v1.ucAction = action;
1048 			if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1049 				args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1050 			} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1051 				args.v1.asMode.ucLaneSel = lane_num;
1052 				args.v1.asMode.ucLaneSet = lane_set;
1053 			} else {
1054 				if (is_dp)
1055 					args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1056 				else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1057 					args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1058 				else
1059 					args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1060 			}
1061 
1062 			args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1063 
1064 			if (dig_encoder)
1065 				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1066 			else
1067 				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1068 
1069 			if ((rdev->flags & RADEON_IS_IGP) &&
1070 			    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1071 				if (is_dp ||
1072 				    !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1073 					if (igp_lane_info & 0x1)
1074 						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1075 					else if (igp_lane_info & 0x2)
1076 						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1077 					else if (igp_lane_info & 0x4)
1078 						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1079 					else if (igp_lane_info & 0x8)
1080 						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1081 				} else {
1082 					if (igp_lane_info & 0x3)
1083 						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1084 					else if (igp_lane_info & 0xc)
1085 						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1086 				}
1087 			}
1088 
1089 			if (dig->linkb)
1090 				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1091 			else
1092 				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1093 
1094 			if (is_dp)
1095 				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1096 			else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1097 				if (dig->coherent_mode)
1098 					args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1099 				if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1100 					args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1101 			}
1102 			break;
1103 		case 2:
1104 			args.v2.ucAction = action;
1105 			if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1106 				args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1107 			} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1108 				args.v2.asMode.ucLaneSel = lane_num;
1109 				args.v2.asMode.ucLaneSet = lane_set;
1110 			} else {
1111 				if (is_dp)
1112 					args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1113 				else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1114 					args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1115 				else
1116 					args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1117 			}
1118 
1119 			args.v2.acConfig.ucEncoderSel = dig_encoder;
1120 			if (dig->linkb)
1121 				args.v2.acConfig.ucLinkSel = 1;
1122 
1123 			switch (radeon_encoder->encoder_id) {
1124 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1125 				args.v2.acConfig.ucTransmitterSel = 0;
1126 				break;
1127 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1128 				args.v2.acConfig.ucTransmitterSel = 1;
1129 				break;
1130 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1131 				args.v2.acConfig.ucTransmitterSel = 2;
1132 				break;
1133 			}
1134 
1135 			if (is_dp) {
1136 				args.v2.acConfig.fCoherentMode = 1;
1137 				args.v2.acConfig.fDPConnector = 1;
1138 			} else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1139 				if (dig->coherent_mode)
1140 					args.v2.acConfig.fCoherentMode = 1;
1141 				if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1142 					args.v2.acConfig.fDualLinkConnector = 1;
1143 			}
1144 			break;
1145 		case 3:
1146 			args.v3.ucAction = action;
1147 			if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1148 				args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1149 			} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1150 				args.v3.asMode.ucLaneSel = lane_num;
1151 				args.v3.asMode.ucLaneSet = lane_set;
1152 			} else {
1153 				if (is_dp)
1154 					args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1155 				else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1156 					args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1157 				else
1158 					args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1159 			}
1160 
1161 			if (is_dp)
1162 				args.v3.ucLaneNum = dp_lane_count;
1163 			else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1164 				args.v3.ucLaneNum = 8;
1165 			else
1166 				args.v3.ucLaneNum = 4;
1167 
1168 			if (dig->linkb)
1169 				args.v3.acConfig.ucLinkSel = 1;
1170 			if (dig_encoder & 1)
1171 				args.v3.acConfig.ucEncoderSel = 1;
1172 
1173 			/* Select the PLL for the PHY
1174 			 * DP PHY should be clocked from external src if there is
1175 			 * one.
1176 			 */
1177 			/* On DCE4, if there is an external clock, it generates the DP ref clock */
1178 			if (is_dp && rdev->clock.dp_extclk)
1179 				args.v3.acConfig.ucRefClkSource = 2; /* external src */
1180 			else
1181 				args.v3.acConfig.ucRefClkSource = pll_id;
1182 
1183 			switch (radeon_encoder->encoder_id) {
1184 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1185 				args.v3.acConfig.ucTransmitterSel = 0;
1186 				break;
1187 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1188 				args.v3.acConfig.ucTransmitterSel = 1;
1189 				break;
1190 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1191 				args.v3.acConfig.ucTransmitterSel = 2;
1192 				break;
1193 			}
1194 
1195 			if (is_dp)
1196 				args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1197 			else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1198 				if (dig->coherent_mode)
1199 					args.v3.acConfig.fCoherentMode = 1;
1200 				if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1201 					args.v3.acConfig.fDualLinkConnector = 1;
1202 			}
1203 			break;
1204 		case 4:
1205 			args.v4.ucAction = action;
1206 			if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1207 				args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1208 			} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1209 				args.v4.asMode.ucLaneSel = lane_num;
1210 				args.v4.asMode.ucLaneSet = lane_set;
1211 			} else {
1212 				if (is_dp)
1213 					args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1214 				else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1215 					args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1216 				else
1217 					args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1218 			}
1219 
1220 			if (is_dp)
1221 				args.v4.ucLaneNum = dp_lane_count;
1222 			else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1223 				args.v4.ucLaneNum = 8;
1224 			else
1225 				args.v4.ucLaneNum = 4;
1226 
1227 			if (dig->linkb)
1228 				args.v4.acConfig.ucLinkSel = 1;
1229 			if (dig_encoder & 1)
1230 				args.v4.acConfig.ucEncoderSel = 1;
1231 
1232 			/* Select the PLL for the PHY
1233 			 * DP PHY should be clocked from external src if there is
1234 			 * one.
1235 			 */
1236 			/* On DCE5 DCPLL usually generates the DP ref clock */
1237 			if (is_dp) {
1238 				if (rdev->clock.dp_extclk)
1239 					args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1240 				else
1241 					args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1242 			} else
1243 				args.v4.acConfig.ucRefClkSource = pll_id;
1244 
1245 			switch (radeon_encoder->encoder_id) {
1246 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1247 				args.v4.acConfig.ucTransmitterSel = 0;
1248 				break;
1249 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1250 				args.v4.acConfig.ucTransmitterSel = 1;
1251 				break;
1252 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1253 				args.v4.acConfig.ucTransmitterSel = 2;
1254 				break;
1255 			}
1256 
1257 			if (is_dp)
1258 				args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1259 			else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1260 				if (dig->coherent_mode)
1261 					args.v4.acConfig.fCoherentMode = 1;
1262 				if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1263 					args.v4.acConfig.fDualLinkConnector = 1;
1264 			}
1265 			break;
1266 		case 5:
1267 			args.v5.ucAction = action;
1268 			if (is_dp)
1269 				args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1270 			else
1271 				args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1272 
1273 			switch (radeon_encoder->encoder_id) {
1274 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1275 				if (dig->linkb)
1276 					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1277 				else
1278 					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1279 				break;
1280 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1281 				if (dig->linkb)
1282 					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1283 				else
1284 					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1285 				break;
1286 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1287 				if (dig->linkb)
1288 					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1289 				else
1290 					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1291 				break;
1292 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1293 				args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1294 				break;
1295 			}
1296 			if (is_dp)
1297 				args.v5.ucLaneNum = dp_lane_count;
1298 			else if (radeon_encoder->pixel_clock > 165000)
1299 				args.v5.ucLaneNum = 8;
1300 			else
1301 				args.v5.ucLaneNum = 4;
1302 			args.v5.ucConnObjId = connector_object_id;
1303 			args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1304 
1305 			if (is_dp && rdev->clock.dp_extclk)
1306 				args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1307 			else
1308 				args.v5.asConfig.ucPhyClkSrcId = pll_id;
1309 
1310 			if (is_dp)
1311 				args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1312 			else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1313 				if (dig->coherent_mode)
1314 					args.v5.asConfig.ucCoherentMode = 1;
1315 			}
1316 			if (hpd_id == RADEON_HPD_NONE)
1317 				args.v5.asConfig.ucHPDSel = 0;
1318 			else
1319 				args.v5.asConfig.ucHPDSel = hpd_id + 1;
1320 			args.v5.ucDigEncoderSel = 1 << dig_encoder;
1321 			args.v5.ucDPLaneSet = lane_set;
1322 			break;
1323 		default:
1324 			DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1325 			break;
1326 		}
1327 		break;
1328 	default:
1329 		DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1330 		break;
1331 	}
1332 
1333 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1334 }
1335 
1336 bool
1337 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1338 {
1339 	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1340 	struct drm_device *dev = radeon_connector->base.dev;
1341 	struct radeon_device *rdev = dev->dev_private;
1342 	union dig_transmitter_control args;
1343 	int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1344 	uint8_t frev, crev;
1345 
1346 	if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1347 		goto done;
1348 
1349 	if (!ASIC_IS_DCE4(rdev))
1350 		goto done;
1351 
1352 	if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1353 	    (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1354 		goto done;
1355 
1356 	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1357 		goto done;
1358 
1359 	memset(&args, 0, sizeof(args));
1360 
1361 	args.v1.ucAction = action;
1362 
1363 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1364 
1365 	/* wait for the panel to power up */
1366 	if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1367 		int i;
1368 
1369 		for (i = 0; i < 300; i++) {
1370 			if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1371 				return true;
1372 			mdelay(1);
1373 		}
1374 		return false;
1375 	}
1376 done:
1377 	return true;
1378 }
1379 
1380 union external_encoder_control {
1381 	EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1382 	EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1383 };
1384 
1385 static void
1386 atombios_external_encoder_setup(struct drm_encoder *encoder,
1387 				struct drm_encoder *ext_encoder,
1388 				int action)
1389 {
1390 	struct drm_device *dev = encoder->dev;
1391 	struct radeon_device *rdev = dev->dev_private;
1392 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1393 	struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1394 	union external_encoder_control args;
1395 	struct drm_connector *connector;
1396 	int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1397 	u8 frev, crev;
1398 	int dp_clock = 0;
1399 	int dp_lane_count = 0;
1400 	int connector_object_id = 0;
1401 	u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1402 
1403 	if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1404 		connector = radeon_get_connector_for_encoder_init(encoder);
1405 	else
1406 		connector = radeon_get_connector_for_encoder(encoder);
1407 
1408 	if (connector) {
1409 		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1410 		struct radeon_connector_atom_dig *dig_connector =
1411 			radeon_connector->con_priv;
1412 
1413 		dp_clock = dig_connector->dp_clock;
1414 		dp_lane_count = dig_connector->dp_lane_count;
1415 		connector_object_id =
1416 			(radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1417 	}
1418 
1419 	memset(&args, 0, sizeof(args));
1420 
1421 	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1422 		return;
1423 
1424 	switch (frev) {
1425 	case 1:
1426 		/* no params on frev 1 */
1427 		break;
1428 	case 2:
1429 		switch (crev) {
1430 		case 1:
1431 		case 2:
1432 			args.v1.sDigEncoder.ucAction = action;
1433 			args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1434 			args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1435 
1436 			if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1437 				if (dp_clock == 270000)
1438 					args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1439 				args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1440 			} else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1441 				args.v1.sDigEncoder.ucLaneNum = 8;
1442 			else
1443 				args.v1.sDigEncoder.ucLaneNum = 4;
1444 			break;
1445 		case 3:
1446 			args.v3.sExtEncoder.ucAction = action;
1447 			if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1448 				args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1449 			else
1450 				args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1451 			args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1452 
1453 			if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1454 				if (dp_clock == 270000)
1455 					args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1456 				else if (dp_clock == 540000)
1457 					args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1458 				args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1459 			} else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1460 				args.v3.sExtEncoder.ucLaneNum = 8;
1461 			else
1462 				args.v3.sExtEncoder.ucLaneNum = 4;
1463 			switch (ext_enum) {
1464 			case GRAPH_OBJECT_ENUM_ID1:
1465 				args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1466 				break;
1467 			case GRAPH_OBJECT_ENUM_ID2:
1468 				args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1469 				break;
1470 			case GRAPH_OBJECT_ENUM_ID3:
1471 				args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1472 				break;
1473 			}
1474 			args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1475 			break;
1476 		default:
1477 			DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1478 			return;
1479 		}
1480 		break;
1481 	default:
1482 		DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1483 		return;
1484 	}
1485 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1486 }
1487 
1488 static void
1489 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1490 {
1491 	struct drm_device *dev = encoder->dev;
1492 	struct radeon_device *rdev = dev->dev_private;
1493 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1494 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1495 	ENABLE_YUV_PS_ALLOCATION args;
1496 	int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1497 	uint32_t temp, reg;
1498 
1499 	memset(&args, 0, sizeof(args));
1500 
1501 	if (rdev->family >= CHIP_R600)
1502 		reg = R600_BIOS_3_SCRATCH;
1503 	else
1504 		reg = RADEON_BIOS_3_SCRATCH;
1505 
1506 	/* XXX: fix up scratch reg handling */
1507 	temp = RREG32(reg);
1508 	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1509 		WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1510 			     (radeon_crtc->crtc_id << 18)));
1511 	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1512 		WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1513 	else
1514 		WREG32(reg, 0);
1515 
1516 	if (enable)
1517 		args.ucEnable = ATOM_ENABLE;
1518 	args.ucCRTC = radeon_crtc->crtc_id;
1519 
1520 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1521 
1522 	WREG32(reg, temp);
1523 }
1524 
1525 static void
1526 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1527 {
1528 	struct drm_device *dev = encoder->dev;
1529 	struct radeon_device *rdev = dev->dev_private;
1530 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1531 	DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1532 	int index = 0;
1533 
1534 	memset(&args, 0, sizeof(args));
1535 
1536 	switch (radeon_encoder->encoder_id) {
1537 	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1538 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1539 		index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1540 		break;
1541 	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1542 	case ENCODER_OBJECT_ID_INTERNAL_DDI:
1543 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1544 		index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1545 		break;
1546 	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1547 		index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1548 		break;
1549 	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1550 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1551 			index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1552 		else
1553 			index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1554 		break;
1555 	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1556 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1557 		if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1558 			index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1559 		else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1560 			index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1561 		else
1562 			index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1563 		break;
1564 	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1565 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1566 		if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1567 			index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1568 		else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1569 			index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1570 		else
1571 			index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1572 		break;
1573 	default:
1574 		return;
1575 	}
1576 
1577 	switch (mode) {
1578 	case DRM_MODE_DPMS_ON:
1579 		args.ucAction = ATOM_ENABLE;
1580 		/* workaround for DVOOutputControl on some RS690 systems */
1581 		if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1582 			u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1583 			WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1584 			atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1585 			WREG32(RADEON_BIOS_3_SCRATCH, reg);
1586 		} else
1587 			atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1588 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1589 			args.ucAction = ATOM_LCD_BLON;
1590 			atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1591 		}
1592 		break;
1593 	case DRM_MODE_DPMS_STANDBY:
1594 	case DRM_MODE_DPMS_SUSPEND:
1595 	case DRM_MODE_DPMS_OFF:
1596 		args.ucAction = ATOM_DISABLE;
1597 		atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1598 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1599 			args.ucAction = ATOM_LCD_BLOFF;
1600 			atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1601 		}
1602 		break;
1603 	}
1604 }
1605 
1606 static void
1607 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1608 {
1609 	struct drm_device *dev = encoder->dev;
1610 	struct radeon_device *rdev = dev->dev_private;
1611 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1612 	struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1613 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1614 	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1615 	struct radeon_connector *radeon_connector = NULL;
1616 	struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1617 
1618 	if (connector) {
1619 		radeon_connector = to_radeon_connector(connector);
1620 		radeon_dig_connector = radeon_connector->con_priv;
1621 	}
1622 
1623 	switch (mode) {
1624 	case DRM_MODE_DPMS_ON:
1625 		if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1626 			if (!connector)
1627 				dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1628 			else
1629 				dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1630 
1631 			/* setup and enable the encoder */
1632 			atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1633 			atombios_dig_encoder_setup(encoder,
1634 						   ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1635 						   dig->panel_mode);
1636 			if (ext_encoder) {
1637 				if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1638 					atombios_external_encoder_setup(encoder, ext_encoder,
1639 									EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1640 			}
1641 			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1642 		} else if (ASIC_IS_DCE4(rdev)) {
1643 			/* setup and enable the encoder */
1644 			atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1645 			/* enable the transmitter */
1646 			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1647 			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1648 		} else {
1649 			/* setup and enable the encoder and transmitter */
1650 			atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1651 			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1652 			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1653 			/* some dce3.x boards have a bug in their transmitter control table.
1654 			 * ACTION_ENABLE_OUTPUT can probably be dropped since ACTION_ENABLE
1655 			 * does the same thing and more.
1656 			 */
1657 			if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730) &&
1658 			    (rdev->family != CHIP_RS880))
1659 				atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1660 		}
1661 		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1662 			if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1663 				atombios_set_edp_panel_power(connector,
1664 							     ATOM_TRANSMITTER_ACTION_POWER_ON);
1665 				radeon_dig_connector->edp_on = true;
1666 			}
1667 			radeon_dp_link_train(encoder, connector);
1668 			if (ASIC_IS_DCE4(rdev))
1669 				atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1670 		}
1671 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1672 			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1673 		break;
1674 	case DRM_MODE_DPMS_STANDBY:
1675 	case DRM_MODE_DPMS_SUSPEND:
1676 	case DRM_MODE_DPMS_OFF:
1677 		if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1678 			/* disable the transmitter */
1679 			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1680 		} else if (ASIC_IS_DCE4(rdev)) {
1681 			/* disable the transmitter */
1682 			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1683 			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1684 		} else {
1685 			/* disable the encoder and transmitter */
1686 			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1687 			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1688 			atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1689 		}
1690 		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1691 			if (ASIC_IS_DCE4(rdev))
1692 				atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1693 			if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1694 				atombios_set_edp_panel_power(connector,
1695 							     ATOM_TRANSMITTER_ACTION_POWER_OFF);
1696 				radeon_dig_connector->edp_on = false;
1697 			}
1698 		}
1699 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1700 			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1701 		break;
1702 	}
1703 }
1704 
1705 static void
1706 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1707 			     struct drm_encoder *ext_encoder,
1708 			     int mode)
1709 {
1710 	struct drm_device *dev = encoder->dev;
1711 	struct radeon_device *rdev = dev->dev_private;
1712 
1713 	switch (mode) {
1714 	case DRM_MODE_DPMS_ON:
1715 	default:
1716 		if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1717 			atombios_external_encoder_setup(encoder, ext_encoder,
1718 							EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1719 			atombios_external_encoder_setup(encoder, ext_encoder,
1720 							EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1721 		} else
1722 			atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1723 		break;
1724 	case DRM_MODE_DPMS_STANDBY:
1725 	case DRM_MODE_DPMS_SUSPEND:
1726 	case DRM_MODE_DPMS_OFF:
1727 		if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1728 			atombios_external_encoder_setup(encoder, ext_encoder,
1729 							EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1730 			atombios_external_encoder_setup(encoder, ext_encoder,
1731 							EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1732 		} else
1733 			atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1734 		break;
1735 	}
1736 }
1737 
1738 static void
1739 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1740 {
1741 	struct drm_device *dev = encoder->dev;
1742 	struct radeon_device *rdev = dev->dev_private;
1743 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1744 	struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1745 
1746 	DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1747 		  radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1748 		  radeon_encoder->active_device);
1749 	switch (radeon_encoder->encoder_id) {
1750 	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1751 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1752 	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1753 	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1754 	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1755 	case ENCODER_OBJECT_ID_INTERNAL_DDI:
1756 	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1757 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1758 		radeon_atom_encoder_dpms_avivo(encoder, mode);
1759 		break;
1760 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1761 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1762 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1763 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1764 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1765 		radeon_atom_encoder_dpms_dig(encoder, mode);
1766 		break;
1767 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1768 		if (ASIC_IS_DCE5(rdev)) {
1769 			switch (mode) {
1770 			case DRM_MODE_DPMS_ON:
1771 				atombios_dvo_setup(encoder, ATOM_ENABLE);
1772 				break;
1773 			case DRM_MODE_DPMS_STANDBY:
1774 			case DRM_MODE_DPMS_SUSPEND:
1775 			case DRM_MODE_DPMS_OFF:
1776 				atombios_dvo_setup(encoder, ATOM_DISABLE);
1777 				break;
1778 			}
1779 		} else if (ASIC_IS_DCE3(rdev))
1780 			radeon_atom_encoder_dpms_dig(encoder, mode);
1781 		else
1782 			radeon_atom_encoder_dpms_avivo(encoder, mode);
1783 		break;
1784 	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1785 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1786 		if (ASIC_IS_DCE5(rdev)) {
1787 			switch (mode) {
1788 			case DRM_MODE_DPMS_ON:
1789 				atombios_dac_setup(encoder, ATOM_ENABLE);
1790 				break;
1791 			case DRM_MODE_DPMS_STANDBY:
1792 			case DRM_MODE_DPMS_SUSPEND:
1793 			case DRM_MODE_DPMS_OFF:
1794 				atombios_dac_setup(encoder, ATOM_DISABLE);
1795 				break;
1796 			}
1797 		} else
1798 			radeon_atom_encoder_dpms_avivo(encoder, mode);
1799 		break;
1800 	default:
1801 		return;
1802 	}
1803 
1804 	if (ext_encoder)
1805 		radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1806 
1807 	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1808 
1809 }
1810 
1811 union crtc_source_param {
1812 	SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1813 	SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1814 };
1815 
1816 static void
1817 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1818 {
1819 	struct drm_device *dev = encoder->dev;
1820 	struct radeon_device *rdev = dev->dev_private;
1821 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1822 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1823 	union crtc_source_param args;
1824 	int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1825 	uint8_t frev, crev;
1826 	struct radeon_encoder_atom_dig *dig;
1827 
1828 	memset(&args, 0, sizeof(args));
1829 
1830 	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1831 		return;
1832 
1833 	switch (frev) {
1834 	case 1:
1835 		switch (crev) {
1836 		case 1:
1837 		default:
1838 			if (ASIC_IS_AVIVO(rdev))
1839 				args.v1.ucCRTC = radeon_crtc->crtc_id;
1840 			else {
1841 				if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1842 					args.v1.ucCRTC = radeon_crtc->crtc_id;
1843 				} else {
1844 					args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1845 				}
1846 			}
1847 			switch (radeon_encoder->encoder_id) {
1848 			case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1849 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1850 				args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1851 				break;
1852 			case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1853 			case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1854 				if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1855 					args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1856 				else
1857 					args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1858 				break;
1859 			case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1860 			case ENCODER_OBJECT_ID_INTERNAL_DDI:
1861 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1862 				args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1863 				break;
1864 			case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1865 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1866 				if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1867 					args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1868 				else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1869 					args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1870 				else
1871 					args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1872 				break;
1873 			case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1874 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1875 				if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1876 					args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1877 				else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1878 					args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1879 				else
1880 					args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1881 				break;
1882 			}
1883 			break;
1884 		case 2:
1885 			args.v2.ucCRTC = radeon_crtc->crtc_id;
1886 			if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1887 				struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1888 
1889 				if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1890 					args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1891 				else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1892 					args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1893 				else
1894 					args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1895 			} else
1896 				args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1897 			switch (radeon_encoder->encoder_id) {
1898 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1899 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1900 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1901 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1902 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1903 				dig = radeon_encoder->enc_priv;
1904 				switch (dig->dig_encoder) {
1905 				case 0:
1906 					args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1907 					break;
1908 				case 1:
1909 					args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1910 					break;
1911 				case 2:
1912 					args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1913 					break;
1914 				case 3:
1915 					args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1916 					break;
1917 				case 4:
1918 					args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1919 					break;
1920 				case 5:
1921 					args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1922 					break;
1923 				case 6:
1924 					args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1925 					break;
1926 				}
1927 				break;
1928 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1929 				args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1930 				break;
1931 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1932 				if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1933 					args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1934 				else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1935 					args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1936 				else
1937 					args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1938 				break;
1939 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1940 				if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1941 					args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1942 				else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1943 					args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1944 				else
1945 					args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1946 				break;
1947 			}
1948 			break;
1949 		}
1950 		break;
1951 	default:
1952 		DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1953 		return;
1954 	}
1955 
1956 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1957 
1958 	/* update scratch regs with new routing */
1959 	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1960 }
1961 
1962 static void
1963 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1964 			      struct drm_display_mode *mode)
1965 {
1966 	struct drm_device *dev = encoder->dev;
1967 	struct radeon_device *rdev = dev->dev_private;
1968 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1969 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1970 
1971 	/* Funky macbooks */
1972 	if ((dev->pdev->device == 0x71C5) &&
1973 	    (dev->pdev->subsystem_vendor == 0x106b) &&
1974 	    (dev->pdev->subsystem_device == 0x0080)) {
1975 		if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1976 			uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1977 
1978 			lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1979 			lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1980 
1981 			WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1982 		}
1983 	}
1984 
1985 	/* set scaler clears this on some chips */
1986 	if (ASIC_IS_AVIVO(rdev) &&
1987 	    (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1988 		if (ASIC_IS_DCE8(rdev)) {
1989 			if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1990 				WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
1991 				       CIK_INTERLEAVE_EN);
1992 			else
1993 				WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1994 		} else if (ASIC_IS_DCE4(rdev)) {
1995 			if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1996 				WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1997 				       EVERGREEN_INTERLEAVE_EN);
1998 			else
1999 				WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2000 		} else {
2001 			if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2002 				WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
2003 				       AVIVO_D1MODE_INTERLEAVE_EN);
2004 			else
2005 				WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2006 		}
2007 	}
2008 }
2009 
2010 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
2011 {
2012 	struct drm_device *dev = encoder->dev;
2013 	struct radeon_device *rdev = dev->dev_private;
2014 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2015 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2016 	struct drm_encoder *test_encoder;
2017 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2018 	uint32_t dig_enc_in_use = 0;
2019 
2020 	if (ASIC_IS_DCE6(rdev)) {
2021 		/* DCE6 */
2022 		switch (radeon_encoder->encoder_id) {
2023 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2024 			if (dig->linkb)
2025 				return 1;
2026 			else
2027 				return 0;
2028 			break;
2029 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2030 			if (dig->linkb)
2031 				return 3;
2032 			else
2033 				return 2;
2034 			break;
2035 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2036 			if (dig->linkb)
2037 				return 5;
2038 			else
2039 				return 4;
2040 			break;
2041 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2042 			return 6;
2043 			break;
2044 		}
2045 	} else if (ASIC_IS_DCE4(rdev)) {
2046 		/* DCE4/5 */
2047 		if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2048 			/* ontario follows DCE4 */
2049 			if (rdev->family == CHIP_PALM) {
2050 				if (dig->linkb)
2051 					return 1;
2052 				else
2053 					return 0;
2054 			} else
2055 				/* llano follows DCE3.2 */
2056 				return radeon_crtc->crtc_id;
2057 		} else {
2058 			switch (radeon_encoder->encoder_id) {
2059 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2060 				if (dig->linkb)
2061 					return 1;
2062 				else
2063 					return 0;
2064 				break;
2065 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2066 				if (dig->linkb)
2067 					return 3;
2068 				else
2069 					return 2;
2070 				break;
2071 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2072 				if (dig->linkb)
2073 					return 5;
2074 				else
2075 					return 4;
2076 				break;
2077 			}
2078 		}
2079 	}
2080 
2081 	/* on DCE32 and encoder can driver any block so just crtc id */
2082 	if (ASIC_IS_DCE32(rdev)) {
2083 		return radeon_crtc->crtc_id;
2084 	}
2085 
2086 	/* on DCE3 - LVTMA can only be driven by DIGB */
2087 	list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2088 		struct radeon_encoder *radeon_test_encoder;
2089 
2090 		if (encoder == test_encoder)
2091 			continue;
2092 
2093 		if (!radeon_encoder_is_digital(test_encoder))
2094 			continue;
2095 
2096 		radeon_test_encoder = to_radeon_encoder(test_encoder);
2097 		dig = radeon_test_encoder->enc_priv;
2098 
2099 		if (dig->dig_encoder >= 0)
2100 			dig_enc_in_use |= (1 << dig->dig_encoder);
2101 	}
2102 
2103 	if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2104 		if (dig_enc_in_use & 0x2)
2105 			DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2106 		return 1;
2107 	}
2108 	if (!(dig_enc_in_use & 1))
2109 		return 0;
2110 	return 1;
2111 }
2112 
2113 /* This only needs to be called once at startup */
2114 void
2115 radeon_atom_encoder_init(struct radeon_device *rdev)
2116 {
2117 	struct drm_device *dev = rdev->ddev;
2118 	struct drm_encoder *encoder;
2119 
2120 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2121 		struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2122 		struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2123 
2124 		switch (radeon_encoder->encoder_id) {
2125 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2126 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2127 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2128 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2129 		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2130 			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2131 			break;
2132 		default:
2133 			break;
2134 		}
2135 
2136 		if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2137 			atombios_external_encoder_setup(encoder, ext_encoder,
2138 							EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2139 	}
2140 }
2141 
2142 static void
2143 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2144 			     struct drm_display_mode *mode,
2145 			     struct drm_display_mode *adjusted_mode)
2146 {
2147 	struct drm_device *dev = encoder->dev;
2148 	struct radeon_device *rdev = dev->dev_private;
2149 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2150 
2151 	radeon_encoder->pixel_clock = adjusted_mode->clock;
2152 
2153 	/* need to call this here rather than in prepare() since we need some crtc info */
2154 	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2155 
2156 	if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2157 		if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2158 			atombios_yuv_setup(encoder, true);
2159 		else
2160 			atombios_yuv_setup(encoder, false);
2161 	}
2162 
2163 	switch (radeon_encoder->encoder_id) {
2164 	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2165 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2166 	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2167 	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2168 		atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2169 		break;
2170 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2171 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2172 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2173 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2174 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2175 		/* handled in dpms */
2176 		break;
2177 	case ENCODER_OBJECT_ID_INTERNAL_DDI:
2178 	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2179 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2180 		atombios_dvo_setup(encoder, ATOM_ENABLE);
2181 		break;
2182 	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2183 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2184 	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2185 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2186 		atombios_dac_setup(encoder, ATOM_ENABLE);
2187 		if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2188 			if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2189 				atombios_tv_setup(encoder, ATOM_ENABLE);
2190 			else
2191 				atombios_tv_setup(encoder, ATOM_DISABLE);
2192 		}
2193 		break;
2194 	}
2195 
2196 	atombios_apply_encoder_quirks(encoder, adjusted_mode);
2197 
2198 	if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2199 		if (rdev->asic->display.hdmi_enable)
2200 			radeon_hdmi_enable(rdev, encoder, true);
2201 		if (rdev->asic->display.hdmi_setmode)
2202 			radeon_hdmi_setmode(rdev, encoder, adjusted_mode);
2203 	}
2204 }
2205 
2206 static bool
2207 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2208 {
2209 	struct drm_device *dev = encoder->dev;
2210 	struct radeon_device *rdev = dev->dev_private;
2211 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2212 	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2213 
2214 	if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2215 				       ATOM_DEVICE_CV_SUPPORT |
2216 				       ATOM_DEVICE_CRT_SUPPORT)) {
2217 		DAC_LOAD_DETECTION_PS_ALLOCATION args;
2218 		int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2219 		uint8_t frev, crev;
2220 
2221 		memset(&args, 0, sizeof(args));
2222 
2223 		if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2224 			return false;
2225 
2226 		args.sDacload.ucMisc = 0;
2227 
2228 		if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2229 		    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2230 			args.sDacload.ucDacType = ATOM_DAC_A;
2231 		else
2232 			args.sDacload.ucDacType = ATOM_DAC_B;
2233 
2234 		if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2235 			args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2236 		else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2237 			args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2238 		else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2239 			args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2240 			if (crev >= 3)
2241 				args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2242 		} else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2243 			args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2244 			if (crev >= 3)
2245 				args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2246 		}
2247 
2248 		atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2249 
2250 		return true;
2251 	} else
2252 		return false;
2253 }
2254 
2255 static enum drm_connector_status
2256 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2257 {
2258 	struct drm_device *dev = encoder->dev;
2259 	struct radeon_device *rdev = dev->dev_private;
2260 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2261 	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2262 	uint32_t bios_0_scratch;
2263 
2264 	if (!atombios_dac_load_detect(encoder, connector)) {
2265 		DRM_DEBUG_KMS("detect returned false \n");
2266 		return connector_status_unknown;
2267 	}
2268 
2269 	if (rdev->family >= CHIP_R600)
2270 		bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2271 	else
2272 		bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2273 
2274 	DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2275 	if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2276 		if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2277 			return connector_status_connected;
2278 	}
2279 	if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2280 		if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2281 			return connector_status_connected;
2282 	}
2283 	if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2284 		if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2285 			return connector_status_connected;
2286 	}
2287 	if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2288 		if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2289 			return connector_status_connected; /* CTV */
2290 		else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2291 			return connector_status_connected; /* STV */
2292 	}
2293 	return connector_status_disconnected;
2294 }
2295 
2296 static enum drm_connector_status
2297 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2298 {
2299 	struct drm_device *dev = encoder->dev;
2300 	struct radeon_device *rdev = dev->dev_private;
2301 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2302 	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2303 	struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2304 	u32 bios_0_scratch;
2305 
2306 	if (!ASIC_IS_DCE4(rdev))
2307 		return connector_status_unknown;
2308 
2309 	if (!ext_encoder)
2310 		return connector_status_unknown;
2311 
2312 	if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2313 		return connector_status_unknown;
2314 
2315 	/* load detect on the dp bridge */
2316 	atombios_external_encoder_setup(encoder, ext_encoder,
2317 					EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2318 
2319 	bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2320 
2321 	DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2322 	if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2323 		if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2324 			return connector_status_connected;
2325 	}
2326 	if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2327 		if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2328 			return connector_status_connected;
2329 	}
2330 	if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2331 		if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2332 			return connector_status_connected;
2333 	}
2334 	if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2335 		if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2336 			return connector_status_connected; /* CTV */
2337 		else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2338 			return connector_status_connected; /* STV */
2339 	}
2340 	return connector_status_disconnected;
2341 }
2342 
2343 void
2344 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2345 {
2346 	struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2347 
2348 	if (ext_encoder)
2349 		/* ddc_setup on the dp bridge */
2350 		atombios_external_encoder_setup(encoder, ext_encoder,
2351 						EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2352 
2353 }
2354 
2355 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2356 {
2357 	struct radeon_device *rdev = encoder->dev->dev_private;
2358 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2359 	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2360 
2361 	if ((radeon_encoder->active_device &
2362 	     (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2363 	    (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2364 	     ENCODER_OBJECT_ID_NONE)) {
2365 		struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2366 		if (dig) {
2367 			dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2368 			if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2369 				if (rdev->family >= CHIP_R600)
2370 					dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2371 				else
2372 					/* RS600/690/740 have only 1 afmt block */
2373 					dig->afmt = rdev->mode_info.afmt[0];
2374 			}
2375 		}
2376 	}
2377 
2378 	radeon_atom_output_lock(encoder, true);
2379 
2380 	if (connector) {
2381 		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2382 
2383 		/* select the clock/data port if it uses a router */
2384 		if (radeon_connector->router.cd_valid)
2385 			radeon_router_select_cd_port(radeon_connector);
2386 
2387 		/* turn eDP panel on for mode set */
2388 		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2389 			atombios_set_edp_panel_power(connector,
2390 						     ATOM_TRANSMITTER_ACTION_POWER_ON);
2391 	}
2392 
2393 	/* this is needed for the pll/ss setup to work correctly in some cases */
2394 	atombios_set_encoder_crtc_source(encoder);
2395 }
2396 
2397 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2398 {
2399 	/* need to call this here as we need the crtc set up */
2400 	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2401 	radeon_atom_output_lock(encoder, false);
2402 }
2403 
2404 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2405 {
2406 	struct drm_device *dev = encoder->dev;
2407 	struct radeon_device *rdev = dev->dev_private;
2408 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2409 	struct radeon_encoder_atom_dig *dig;
2410 
2411 	/* check for pre-DCE3 cards with shared encoders;
2412 	 * can't really use the links individually, so don't disable
2413 	 * the encoder if it's in use by another connector
2414 	 */
2415 	if (!ASIC_IS_DCE3(rdev)) {
2416 		struct drm_encoder *other_encoder;
2417 		struct radeon_encoder *other_radeon_encoder;
2418 
2419 		list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2420 			other_radeon_encoder = to_radeon_encoder(other_encoder);
2421 			if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2422 			    drm_helper_encoder_in_use(other_encoder))
2423 				goto disable_done;
2424 		}
2425 	}
2426 
2427 	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2428 
2429 	switch (radeon_encoder->encoder_id) {
2430 	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2431 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2432 	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2433 	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2434 		atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2435 		break;
2436 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2437 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2438 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2439 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2440 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2441 		/* handled in dpms */
2442 		break;
2443 	case ENCODER_OBJECT_ID_INTERNAL_DDI:
2444 	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2445 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2446 		atombios_dvo_setup(encoder, ATOM_DISABLE);
2447 		break;
2448 	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2449 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2450 	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2451 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2452 		atombios_dac_setup(encoder, ATOM_DISABLE);
2453 		if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2454 			atombios_tv_setup(encoder, ATOM_DISABLE);
2455 		break;
2456 	}
2457 
2458 disable_done:
2459 	if (radeon_encoder_is_digital(encoder)) {
2460 		if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2461 			if (rdev->asic->display.hdmi_enable)
2462 				radeon_hdmi_enable(rdev, encoder, false);
2463 		}
2464 		dig = radeon_encoder->enc_priv;
2465 		dig->dig_encoder = -1;
2466 	}
2467 	radeon_encoder->active_device = 0;
2468 }
2469 
2470 /* these are handled by the primary encoders */
2471 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2472 {
2473 
2474 }
2475 
2476 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2477 {
2478 
2479 }
2480 
2481 static void
2482 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2483 			 struct drm_display_mode *mode,
2484 			 struct drm_display_mode *adjusted_mode)
2485 {
2486 
2487 }
2488 
2489 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2490 {
2491 
2492 }
2493 
2494 static void
2495 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2496 {
2497 
2498 }
2499 
2500 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2501 				       const struct drm_display_mode *mode,
2502 				       struct drm_display_mode *adjusted_mode)
2503 {
2504 	return true;
2505 }
2506 
2507 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2508 	.dpms = radeon_atom_ext_dpms,
2509 	.mode_fixup = radeon_atom_ext_mode_fixup,
2510 	.prepare = radeon_atom_ext_prepare,
2511 	.mode_set = radeon_atom_ext_mode_set,
2512 	.commit = radeon_atom_ext_commit,
2513 	.disable = radeon_atom_ext_disable,
2514 	/* no detect for TMDS/LVDS yet */
2515 };
2516 
2517 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2518 	.dpms = radeon_atom_encoder_dpms,
2519 	.mode_fixup = radeon_atom_mode_fixup,
2520 	.prepare = radeon_atom_encoder_prepare,
2521 	.mode_set = radeon_atom_encoder_mode_set,
2522 	.commit = radeon_atom_encoder_commit,
2523 	.disable = radeon_atom_encoder_disable,
2524 	.detect = radeon_atom_dig_detect,
2525 };
2526 
2527 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2528 	.dpms = radeon_atom_encoder_dpms,
2529 	.mode_fixup = radeon_atom_mode_fixup,
2530 	.prepare = radeon_atom_encoder_prepare,
2531 	.mode_set = radeon_atom_encoder_mode_set,
2532 	.commit = radeon_atom_encoder_commit,
2533 	.detect = radeon_atom_dac_detect,
2534 };
2535 
2536 void radeon_enc_destroy(struct drm_encoder *encoder)
2537 {
2538 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2539 	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2540 		radeon_atom_backlight_exit(radeon_encoder);
2541 	kfree(radeon_encoder->enc_priv);
2542 	drm_encoder_cleanup(encoder);
2543 	kfree(radeon_encoder);
2544 }
2545 
2546 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2547 	.destroy = radeon_enc_destroy,
2548 };
2549 
2550 static struct radeon_encoder_atom_dac *
2551 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2552 {
2553 	struct drm_device *dev = radeon_encoder->base.dev;
2554 	struct radeon_device *rdev = dev->dev_private;
2555 	struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2556 
2557 	if (!dac)
2558 		return NULL;
2559 
2560 	dac->tv_std = radeon_atombios_get_tv_info(rdev);
2561 	return dac;
2562 }
2563 
2564 static struct radeon_encoder_atom_dig *
2565 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2566 {
2567 	int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2568 	struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2569 
2570 	if (!dig)
2571 		return NULL;
2572 
2573 	/* coherent mode by default */
2574 	dig->coherent_mode = true;
2575 	dig->dig_encoder = -1;
2576 
2577 	if (encoder_enum == 2)
2578 		dig->linkb = true;
2579 	else
2580 		dig->linkb = false;
2581 
2582 	return dig;
2583 }
2584 
2585 void
2586 radeon_add_atom_encoder(struct drm_device *dev,
2587 			uint32_t encoder_enum,
2588 			uint32_t supported_device,
2589 			u16 caps)
2590 {
2591 	struct radeon_device *rdev = dev->dev_private;
2592 	struct drm_encoder *encoder;
2593 	struct radeon_encoder *radeon_encoder;
2594 
2595 	/* see if we already added it */
2596 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2597 		radeon_encoder = to_radeon_encoder(encoder);
2598 		if (radeon_encoder->encoder_enum == encoder_enum) {
2599 			radeon_encoder->devices |= supported_device;
2600 			return;
2601 		}
2602 
2603 	}
2604 
2605 	/* add a new one */
2606 	radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2607 	if (!radeon_encoder)
2608 		return;
2609 
2610 	encoder = &radeon_encoder->base;
2611 	switch (rdev->num_crtc) {
2612 	case 1:
2613 		encoder->possible_crtcs = 0x1;
2614 		break;
2615 	case 2:
2616 	default:
2617 		encoder->possible_crtcs = 0x3;
2618 		break;
2619 	case 4:
2620 		encoder->possible_crtcs = 0xf;
2621 		break;
2622 	case 6:
2623 		encoder->possible_crtcs = 0x3f;
2624 		break;
2625 	}
2626 
2627 	radeon_encoder->enc_priv = NULL;
2628 
2629 	radeon_encoder->encoder_enum = encoder_enum;
2630 	radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2631 	radeon_encoder->devices = supported_device;
2632 	radeon_encoder->rmx_type = RMX_OFF;
2633 	radeon_encoder->underscan_type = UNDERSCAN_OFF;
2634 	radeon_encoder->is_ext_encoder = false;
2635 	radeon_encoder->caps = caps;
2636 
2637 	switch (radeon_encoder->encoder_id) {
2638 	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2639 	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2640 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2641 	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2642 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2643 			radeon_encoder->rmx_type = RMX_FULL;
2644 			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2645 			radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2646 		} else {
2647 			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2648 			radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2649 		}
2650 		drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2651 		break;
2652 	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2653 		drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2654 		radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2655 		drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2656 		break;
2657 	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2658 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2659 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2660 		drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2661 		radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2662 		drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2663 		break;
2664 	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2665 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2666 	case ENCODER_OBJECT_ID_INTERNAL_DDI:
2667 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2668 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2669 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2670 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2671 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2672 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2673 			radeon_encoder->rmx_type = RMX_FULL;
2674 			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2675 			radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2676 		} else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2677 			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2678 			radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2679 		} else {
2680 			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2681 			radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2682 		}
2683 		drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2684 		break;
2685 	case ENCODER_OBJECT_ID_SI170B:
2686 	case ENCODER_OBJECT_ID_CH7303:
2687 	case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2688 	case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2689 	case ENCODER_OBJECT_ID_TITFP513:
2690 	case ENCODER_OBJECT_ID_VT1623:
2691 	case ENCODER_OBJECT_ID_HDMI_SI1930:
2692 	case ENCODER_OBJECT_ID_TRAVIS:
2693 	case ENCODER_OBJECT_ID_NUTMEG:
2694 		/* these are handled by the primary encoders */
2695 		radeon_encoder->is_ext_encoder = true;
2696 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2697 			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2698 		else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2699 			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2700 		else
2701 			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2702 		drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2703 		break;
2704 	}
2705 }
2706