1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 */ 27 #include <drm/drmP.h> 28 #include <drm/radeon_drm.h> 29 #include "radeon.h" 30 31 #include "atom.h" 32 #include "atom-bits.h" 33 #include <drm/drm_dp_helper.h> 34 35 /* move these to drm_dp_helper.c/h */ 36 #define DP_LINK_CONFIGURATION_SIZE 9 37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE 38 39 static char *voltage_names[] = { 40 "0.4V", "0.6V", "0.8V", "1.2V" 41 }; 42 static char *pre_emph_names[] = { 43 "0dB", "3.5dB", "6dB", "9.5dB" 44 }; 45 46 /***** radeon AUX functions *****/ 47 48 /* Atom needs data in little endian format 49 * so swap as appropriate when copying data to 50 * or from atom. Note that atom operates on 51 * dw units. 52 */ 53 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le) 54 { 55 #ifdef __BIG_ENDIAN 56 u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */ 57 u32 *dst32, *src32; 58 int i; 59 60 memcpy(src_tmp, src, num_bytes); 61 src32 = (u32 *)src_tmp; 62 dst32 = (u32 *)dst_tmp; 63 if (to_le) { 64 for (i = 0; i < ((num_bytes + 3) / 4); i++) 65 dst32[i] = cpu_to_le32(src32[i]); 66 memcpy(dst, dst_tmp, num_bytes); 67 } else { 68 u8 dws = num_bytes & ~3; 69 for (i = 0; i < ((num_bytes + 3) / 4); i++) 70 dst32[i] = le32_to_cpu(src32[i]); 71 memcpy(dst, dst_tmp, dws); 72 if (num_bytes % 4) { 73 for (i = 0; i < (num_bytes % 4); i++) 74 dst[dws+i] = dst_tmp[dws+i]; 75 } 76 } 77 #else 78 memcpy(dst, src, num_bytes); 79 #endif 80 } 81 82 union aux_channel_transaction { 83 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; 84 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; 85 }; 86 87 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan, 88 u8 *send, int send_bytes, 89 u8 *recv, int recv_size, 90 u8 delay, u8 *ack) 91 { 92 struct drm_device *dev = chan->dev; 93 struct radeon_device *rdev = dev->dev_private; 94 union aux_channel_transaction args; 95 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); 96 unsigned char *base; 97 int recv_bytes; 98 int r = 0; 99 100 memset(&args, 0, sizeof(args)); 101 102 mutex_lock(&chan->mutex); 103 mutex_lock(&rdev->mode_info.atom_context->scratch_mutex); 104 105 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); 106 107 radeon_atom_copy_swap(base, send, send_bytes, true); 108 109 args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4)); 110 args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4)); 111 args.v1.ucDataOutLen = 0; 112 args.v1.ucChannelID = chan->rec.i2c_id; 113 args.v1.ucDelay = delay / 10; 114 if (ASIC_IS_DCE4(rdev)) 115 args.v2.ucHPD_ID = chan->rec.hpd; 116 117 atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args); 118 119 *ack = args.v1.ucReplyStatus; 120 121 /* timeout */ 122 if (args.v1.ucReplyStatus == 1) { 123 DRM_DEBUG_KMS("dp_aux_ch timeout\n"); 124 r = -ETIMEDOUT; 125 goto done; 126 } 127 128 /* flags not zero */ 129 if (args.v1.ucReplyStatus == 2) { 130 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n"); 131 r = -EIO; 132 goto done; 133 } 134 135 /* error */ 136 if (args.v1.ucReplyStatus == 3) { 137 DRM_DEBUG_KMS("dp_aux_ch error\n"); 138 r = -EIO; 139 goto done; 140 } 141 142 recv_bytes = args.v1.ucDataOutLen; 143 if (recv_bytes > recv_size) 144 recv_bytes = recv_size; 145 146 if (recv && recv_size) 147 radeon_atom_copy_swap(recv, base + 16, recv_bytes, false); 148 149 r = recv_bytes; 150 done: 151 mutex_unlock(&rdev->mode_info.atom_context->scratch_mutex); 152 mutex_unlock(&chan->mutex); 153 154 return r; 155 } 156 157 #define BARE_ADDRESS_SIZE 3 158 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 159 160 static ssize_t 161 radeon_dp_aux_transfer_atom(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 162 { 163 struct radeon_i2c_chan *chan = 164 container_of(aux, struct radeon_i2c_chan, aux); 165 int ret; 166 u8 tx_buf[20]; 167 size_t tx_size; 168 u8 ack, delay = 0; 169 170 if (WARN_ON(msg->size > 16)) 171 return -E2BIG; 172 173 tx_buf[0] = msg->address & 0xff; 174 tx_buf[1] = (msg->address >> 8) & 0xff; 175 tx_buf[2] = (msg->request << 4) | 176 ((msg->address >> 16) & 0xf); 177 tx_buf[3] = msg->size ? (msg->size - 1) : 0; 178 179 switch (msg->request & ~DP_AUX_I2C_MOT) { 180 case DP_AUX_NATIVE_WRITE: 181 case DP_AUX_I2C_WRITE: 182 /* The atom implementation only supports writes with a max payload of 183 * 12 bytes since it uses 4 bits for the total count (header + payload) 184 * in the parameter space. The atom interface supports 16 byte 185 * payloads for reads. The hw itself supports up to 16 bytes of payload. 186 */ 187 if (WARN_ON_ONCE(msg->size > 12)) 188 return -E2BIG; 189 /* tx_size needs to be 4 even for bare address packets since the atom 190 * table needs the info in tx_buf[3]. 191 */ 192 tx_size = HEADER_SIZE + msg->size; 193 if (msg->size == 0) 194 tx_buf[3] |= BARE_ADDRESS_SIZE << 4; 195 else 196 tx_buf[3] |= tx_size << 4; 197 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size); 198 ret = radeon_process_aux_ch(chan, 199 tx_buf, tx_size, NULL, 0, delay, &ack); 200 if (ret >= 0) 201 /* Return payload size. */ 202 ret = msg->size; 203 break; 204 case DP_AUX_NATIVE_READ: 205 case DP_AUX_I2C_READ: 206 /* tx_size needs to be 4 even for bare address packets since the atom 207 * table needs the info in tx_buf[3]. 208 */ 209 tx_size = HEADER_SIZE; 210 if (msg->size == 0) 211 tx_buf[3] |= BARE_ADDRESS_SIZE << 4; 212 else 213 tx_buf[3] |= tx_size << 4; 214 ret = radeon_process_aux_ch(chan, 215 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack); 216 break; 217 default: 218 ret = -EINVAL; 219 break; 220 } 221 222 if (ret >= 0) 223 msg->reply = ack >> 4; 224 225 return ret; 226 } 227 228 void radeon_dp_aux_init(struct radeon_connector *radeon_connector) 229 { 230 struct drm_device *dev = radeon_connector->base.dev; 231 struct radeon_device *rdev = dev->dev_private; 232 int ret; 233 234 radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd; 235 radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev; 236 if (ASIC_IS_DCE5(rdev)) { 237 if (radeon_auxch) 238 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_native; 239 else 240 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom; 241 } else { 242 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom; 243 } 244 245 ret = drm_dp_aux_register(&radeon_connector->ddc_bus->aux); 246 if (!ret) 247 radeon_connector->ddc_bus->has_aux = true; 248 249 WARN(ret, "drm_dp_aux_register() failed with error %d\n", ret); 250 } 251 252 /***** general DP utility functions *****/ 253 254 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3 255 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3 256 257 static void dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE], 258 int lane_count, 259 u8 train_set[4]) 260 { 261 u8 v = 0; 262 u8 p = 0; 263 int lane; 264 265 for (lane = 0; lane < lane_count; lane++) { 266 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 267 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 268 269 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", 270 lane, 271 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 272 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 273 274 if (this_v > v) 275 v = this_v; 276 if (this_p > p) 277 p = this_p; 278 } 279 280 if (v >= DP_VOLTAGE_MAX) 281 v |= DP_TRAIN_MAX_SWING_REACHED; 282 283 if (p >= DP_PRE_EMPHASIS_MAX) 284 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 285 286 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n", 287 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 288 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 289 290 for (lane = 0; lane < 4; lane++) 291 train_set[lane] = v | p; 292 } 293 294 /* convert bits per color to bits per pixel */ 295 /* get bpc from the EDID */ 296 static int convert_bpc_to_bpp(int bpc) 297 { 298 if (bpc == 0) 299 return 24; 300 else 301 return bpc * 3; 302 } 303 304 /* get the max pix clock supported by the link rate and lane num */ 305 static int dp_get_max_dp_pix_clock(int link_rate, 306 int lane_num, 307 int bpp) 308 { 309 return (link_rate * lane_num * 8) / bpp; 310 } 311 312 /***** radeon specific DP functions *****/ 313 314 int radeon_dp_get_max_link_rate(struct drm_connector *connector, 315 const u8 dpcd[DP_DPCD_SIZE]) 316 { 317 int max_link_rate; 318 319 if (radeon_connector_is_dp12_capable(connector)) 320 max_link_rate = min(drm_dp_max_link_rate(dpcd), 540000); 321 else 322 max_link_rate = min(drm_dp_max_link_rate(dpcd), 270000); 323 324 return max_link_rate; 325 } 326 327 /* First get the min lane# when low rate is used according to pixel clock 328 * (prefer low rate), second check max lane# supported by DP panel, 329 * if the max lane# < low rate lane# then use max lane# instead. 330 */ 331 static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, 332 const u8 dpcd[DP_DPCD_SIZE], 333 int pix_clock) 334 { 335 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); 336 int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd); 337 int max_lane_num = drm_dp_max_lane_count(dpcd); 338 int lane_num; 339 int max_dp_pix_clock; 340 341 for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) { 342 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp); 343 if (pix_clock <= max_dp_pix_clock) 344 break; 345 } 346 347 return lane_num; 348 } 349 350 static int radeon_dp_get_dp_link_clock(struct drm_connector *connector, 351 const u8 dpcd[DP_DPCD_SIZE], 352 int pix_clock) 353 { 354 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); 355 int lane_num, max_pix_clock; 356 357 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 358 ENCODER_OBJECT_ID_NUTMEG) 359 return 270000; 360 361 lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock); 362 max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp); 363 if (pix_clock <= max_pix_clock) 364 return 162000; 365 max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp); 366 if (pix_clock <= max_pix_clock) 367 return 270000; 368 if (radeon_connector_is_dp12_capable(connector)) { 369 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp); 370 if (pix_clock <= max_pix_clock) 371 return 540000; 372 } 373 374 return radeon_dp_get_max_link_rate(connector, dpcd); 375 } 376 377 static u8 radeon_dp_encoder_service(struct radeon_device *rdev, 378 int action, int dp_clock, 379 u8 ucconfig, u8 lane_num) 380 { 381 DP_ENCODER_SERVICE_PARAMETERS args; 382 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); 383 384 memset(&args, 0, sizeof(args)); 385 args.ucLinkClock = dp_clock / 10; 386 args.ucConfig = ucconfig; 387 args.ucAction = action; 388 args.ucLaneNum = lane_num; 389 args.ucStatus = 0; 390 391 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 392 return args.ucStatus; 393 } 394 395 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector) 396 { 397 struct drm_device *dev = radeon_connector->base.dev; 398 struct radeon_device *rdev = dev->dev_private; 399 400 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, 401 radeon_connector->ddc_bus->rec.i2c_id, 0); 402 } 403 404 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector) 405 { 406 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 407 u8 buf[3]; 408 409 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 410 return; 411 412 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3) 413 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 414 buf[0], buf[1], buf[2]); 415 416 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3) 417 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 418 buf[0], buf[1], buf[2]); 419 } 420 421 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) 422 { 423 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 424 u8 msg[DP_DPCD_SIZE]; 425 int ret, i; 426 427 for (i = 0; i < 7; i++) { 428 ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg, 429 DP_DPCD_SIZE); 430 if (ret == DP_DPCD_SIZE) { 431 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); 432 433 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), 434 dig_connector->dpcd); 435 436 radeon_dp_probe_oui(radeon_connector); 437 438 return true; 439 } 440 } 441 dig_connector->dpcd[0] = 0; 442 return false; 443 } 444 445 int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 446 struct drm_connector *connector) 447 { 448 struct drm_device *dev = encoder->dev; 449 struct radeon_device *rdev = dev->dev_private; 450 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 451 struct radeon_connector_atom_dig *dig_connector; 452 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 453 u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector); 454 u8 tmp; 455 456 if (!ASIC_IS_DCE4(rdev)) 457 return panel_mode; 458 459 if (!radeon_connector->con_priv) 460 return panel_mode; 461 462 dig_connector = radeon_connector->con_priv; 463 464 if (dp_bridge != ENCODER_OBJECT_ID_NONE) { 465 /* DP bridge chips */ 466 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, 467 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { 468 if (tmp & 1) 469 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 470 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || 471 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) 472 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; 473 else 474 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 475 } 476 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 477 /* eDP */ 478 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, 479 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { 480 if (tmp & 1) 481 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 482 } 483 } 484 485 return panel_mode; 486 } 487 488 void radeon_dp_set_link_config(struct drm_connector *connector, 489 const struct drm_display_mode *mode) 490 { 491 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 492 struct radeon_connector_atom_dig *dig_connector; 493 494 if (!radeon_connector->con_priv) 495 return; 496 dig_connector = radeon_connector->con_priv; 497 498 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 499 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 500 dig_connector->dp_clock = 501 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); 502 dig_connector->dp_lane_count = 503 radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock); 504 } 505 } 506 507 int radeon_dp_mode_valid_helper(struct drm_connector *connector, 508 struct drm_display_mode *mode) 509 { 510 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 511 struct radeon_connector_atom_dig *dig_connector; 512 int dp_clock; 513 514 if ((mode->clock > 340000) && 515 (!radeon_connector_is_dp12_capable(connector))) 516 return MODE_CLOCK_HIGH; 517 518 if (!radeon_connector->con_priv) 519 return MODE_CLOCK_HIGH; 520 dig_connector = radeon_connector->con_priv; 521 522 dp_clock = 523 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); 524 525 if ((dp_clock == 540000) && 526 (!radeon_connector_is_dp12_capable(connector))) 527 return MODE_CLOCK_HIGH; 528 529 return MODE_OK; 530 } 531 532 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector) 533 { 534 u8 link_status[DP_LINK_STATUS_SIZE]; 535 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 536 537 if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status) 538 <= 0) 539 return false; 540 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count)) 541 return false; 542 return true; 543 } 544 545 void radeon_dp_set_rx_power_state(struct drm_connector *connector, 546 u8 power_state) 547 { 548 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 549 struct radeon_connector_atom_dig *dig_connector; 550 551 if (!radeon_connector->con_priv) 552 return; 553 554 dig_connector = radeon_connector->con_priv; 555 556 /* power up/down the sink */ 557 if (dig_connector->dpcd[0] >= 0x11) { 558 drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux, 559 DP_SET_POWER, power_state); 560 usleep_range(1000, 2000); 561 } 562 } 563 564 565 struct radeon_dp_link_train_info { 566 struct radeon_device *rdev; 567 struct drm_encoder *encoder; 568 struct drm_connector *connector; 569 int enc_id; 570 int dp_clock; 571 int dp_lane_count; 572 bool tp3_supported; 573 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 574 u8 train_set[4]; 575 u8 link_status[DP_LINK_STATUS_SIZE]; 576 u8 tries; 577 bool use_dpencoder; 578 struct drm_dp_aux *aux; 579 }; 580 581 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) 582 { 583 /* set the initial vs/emph on the source */ 584 atombios_dig_transmitter_setup(dp_info->encoder, 585 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, 586 0, dp_info->train_set[0]); /* sets all lanes at once */ 587 588 /* set the vs/emph on the sink */ 589 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET, 590 dp_info->train_set, dp_info->dp_lane_count); 591 } 592 593 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp) 594 { 595 int rtp = 0; 596 597 /* set training pattern on the source */ 598 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) { 599 switch (tp) { 600 case DP_TRAINING_PATTERN_1: 601 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; 602 break; 603 case DP_TRAINING_PATTERN_2: 604 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2; 605 break; 606 case DP_TRAINING_PATTERN_3: 607 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; 608 break; 609 } 610 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0); 611 } else { 612 switch (tp) { 613 case DP_TRAINING_PATTERN_1: 614 rtp = 0; 615 break; 616 case DP_TRAINING_PATTERN_2: 617 rtp = 1; 618 break; 619 } 620 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, 621 dp_info->dp_clock, dp_info->enc_id, rtp); 622 } 623 624 /* enable training pattern on the sink */ 625 drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp); 626 } 627 628 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) 629 { 630 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder); 631 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 632 u8 tmp; 633 634 /* power up the sink */ 635 radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0); 636 637 /* possibly enable downspread on the sink */ 638 if (dp_info->dpcd[3] & 0x1) 639 drm_dp_dpcd_writeb(dp_info->aux, 640 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); 641 else 642 drm_dp_dpcd_writeb(dp_info->aux, 643 DP_DOWNSPREAD_CTRL, 0); 644 645 if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE) 646 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1); 647 648 /* set the lane count on the sink */ 649 tmp = dp_info->dp_lane_count; 650 if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) 651 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 652 drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp); 653 654 /* set the link rate on the sink */ 655 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock); 656 drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp); 657 658 /* start training on the source */ 659 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) 660 atombios_dig_encoder_setup(dp_info->encoder, 661 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0); 662 else 663 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START, 664 dp_info->dp_clock, dp_info->enc_id, 0); 665 666 /* disable the training pattern on the sink */ 667 drm_dp_dpcd_writeb(dp_info->aux, 668 DP_TRAINING_PATTERN_SET, 669 DP_TRAINING_PATTERN_DISABLE); 670 671 return 0; 672 } 673 674 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info) 675 { 676 udelay(400); 677 678 /* disable the training pattern on the sink */ 679 drm_dp_dpcd_writeb(dp_info->aux, 680 DP_TRAINING_PATTERN_SET, 681 DP_TRAINING_PATTERN_DISABLE); 682 683 /* disable the training pattern on the source */ 684 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) 685 atombios_dig_encoder_setup(dp_info->encoder, 686 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0); 687 else 688 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, 689 dp_info->dp_clock, dp_info->enc_id, 0); 690 691 return 0; 692 } 693 694 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info) 695 { 696 bool clock_recovery; 697 u8 voltage; 698 int i; 699 700 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); 701 memset(dp_info->train_set, 0, 4); 702 radeon_dp_update_vs_emph(dp_info); 703 704 udelay(400); 705 706 /* clock recovery loop */ 707 clock_recovery = false; 708 dp_info->tries = 0; 709 voltage = 0xff; 710 while (1) { 711 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); 712 713 if (drm_dp_dpcd_read_link_status(dp_info->aux, 714 dp_info->link_status) <= 0) { 715 DRM_ERROR("displayport link status failed\n"); 716 break; 717 } 718 719 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { 720 clock_recovery = true; 721 break; 722 } 723 724 for (i = 0; i < dp_info->dp_lane_count; i++) { 725 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 726 break; 727 } 728 if (i == dp_info->dp_lane_count) { 729 DRM_ERROR("clock recovery reached max voltage\n"); 730 break; 731 } 732 733 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 734 ++dp_info->tries; 735 if (dp_info->tries == 5) { 736 DRM_ERROR("clock recovery tried 5 times\n"); 737 break; 738 } 739 } else 740 dp_info->tries = 0; 741 742 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 743 744 /* Compute new train_set as requested by sink */ 745 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); 746 747 radeon_dp_update_vs_emph(dp_info); 748 } 749 if (!clock_recovery) { 750 DRM_ERROR("clock recovery failed\n"); 751 return -1; 752 } else { 753 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", 754 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 755 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> 756 DP_TRAIN_PRE_EMPHASIS_SHIFT); 757 return 0; 758 } 759 } 760 761 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) 762 { 763 bool channel_eq; 764 765 if (dp_info->tp3_supported) 766 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3); 767 else 768 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2); 769 770 /* channel equalization loop */ 771 dp_info->tries = 0; 772 channel_eq = false; 773 while (1) { 774 drm_dp_link_train_channel_eq_delay(dp_info->dpcd); 775 776 if (drm_dp_dpcd_read_link_status(dp_info->aux, 777 dp_info->link_status) <= 0) { 778 DRM_ERROR("displayport link status failed\n"); 779 break; 780 } 781 782 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { 783 channel_eq = true; 784 break; 785 } 786 787 /* Try 5 times */ 788 if (dp_info->tries > 5) { 789 DRM_ERROR("channel eq failed: 5 tries\n"); 790 break; 791 } 792 793 /* Compute new train_set as requested by sink */ 794 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); 795 796 radeon_dp_update_vs_emph(dp_info); 797 dp_info->tries++; 798 } 799 800 if (!channel_eq) { 801 DRM_ERROR("channel eq failed\n"); 802 return -1; 803 } else { 804 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", 805 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 806 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) 807 >> DP_TRAIN_PRE_EMPHASIS_SHIFT); 808 return 0; 809 } 810 } 811 812 void radeon_dp_link_train(struct drm_encoder *encoder, 813 struct drm_connector *connector) 814 { 815 struct drm_device *dev = encoder->dev; 816 struct radeon_device *rdev = dev->dev_private; 817 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 818 struct radeon_encoder_atom_dig *dig; 819 struct radeon_connector *radeon_connector; 820 struct radeon_connector_atom_dig *dig_connector; 821 struct radeon_dp_link_train_info dp_info; 822 int index; 823 u8 tmp, frev, crev; 824 825 if (!radeon_encoder->enc_priv) 826 return; 827 dig = radeon_encoder->enc_priv; 828 829 radeon_connector = to_radeon_connector(connector); 830 if (!radeon_connector->con_priv) 831 return; 832 dig_connector = radeon_connector->con_priv; 833 834 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && 835 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) 836 return; 837 838 /* DPEncoderService newer than 1.1 can't program properly the 839 * training pattern. When facing such version use the 840 * DIGXEncoderControl (X== 1 | 2) 841 */ 842 dp_info.use_dpencoder = true; 843 index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); 844 if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) { 845 if (crev > 1) { 846 dp_info.use_dpencoder = false; 847 } 848 } 849 850 dp_info.enc_id = 0; 851 if (dig->dig_encoder) 852 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; 853 else 854 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; 855 if (dig->linkb) 856 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B; 857 else 858 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; 859 860 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp) 861 == 1) { 862 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) 863 dp_info.tp3_supported = true; 864 else 865 dp_info.tp3_supported = false; 866 } else { 867 dp_info.tp3_supported = false; 868 } 869 870 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); 871 dp_info.rdev = rdev; 872 dp_info.encoder = encoder; 873 dp_info.connector = connector; 874 dp_info.dp_lane_count = dig_connector->dp_lane_count; 875 dp_info.dp_clock = dig_connector->dp_clock; 876 dp_info.aux = &radeon_connector->ddc_bus->aux; 877 878 if (radeon_dp_link_train_init(&dp_info)) 879 goto done; 880 if (radeon_dp_link_train_cr(&dp_info)) 881 goto done; 882 if (radeon_dp_link_train_ce(&dp_info)) 883 goto done; 884 done: 885 if (radeon_dp_link_train_finish(&dp_info)) 886 return; 887 } 888