1 /*
2  * Copyright 2007-8 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: Dave Airlie
24  *          Alex Deucher
25  *          Jerome Glisse
26  */
27 #include <drm/drmP.h>
28 #include <drm/radeon_drm.h>
29 #include "radeon.h"
30 
31 #include "atom.h"
32 #include "atom-bits.h"
33 #include <drm/drm_dp_helper.h>
34 
35 /* move these to drm_dp_helper.c/h */
36 #define DP_LINK_CONFIGURATION_SIZE 9
37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
38 
39 static char *voltage_names[] = {
40         "0.4V", "0.6V", "0.8V", "1.2V"
41 };
42 static char *pre_emph_names[] = {
43         "0dB", "3.5dB", "6dB", "9.5dB"
44 };
45 
46 /***** radeon AUX functions *****/
47 
48 /* Atom needs data in little endian format
49  * so swap as appropriate when copying data to
50  * or from atom. Note that atom operates on
51  * dw units.
52  */
53 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
54 {
55 #ifdef __BIG_ENDIAN
56 	u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
57 	u32 *dst32, *src32;
58 	int i;
59 
60 	memcpy(src_tmp, src, num_bytes);
61 	src32 = (u32 *)src_tmp;
62 	dst32 = (u32 *)dst_tmp;
63 	if (to_le) {
64 		for (i = 0; i < ((num_bytes + 3) / 4); i++)
65 			dst32[i] = cpu_to_le32(src32[i]);
66 		memcpy(dst, dst_tmp, num_bytes);
67 	} else {
68 		u8 dws = num_bytes & ~3;
69 		for (i = 0; i < ((num_bytes + 3) / 4); i++)
70 			dst32[i] = le32_to_cpu(src32[i]);
71 		memcpy(dst, dst_tmp, dws);
72 		if (num_bytes % 4) {
73 			for (i = 0; i < (num_bytes % 4); i++)
74 				dst[dws+i] = dst_tmp[dws+i];
75 		}
76 	}
77 #else
78 	memcpy(dst, src, num_bytes);
79 #endif
80 }
81 
82 union aux_channel_transaction {
83 	PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
84 	PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
85 };
86 
87 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
88 				 u8 *send, int send_bytes,
89 				 u8 *recv, int recv_size,
90 				 u8 delay, u8 *ack)
91 {
92 	struct drm_device *dev = chan->dev;
93 	struct radeon_device *rdev = dev->dev_private;
94 	union aux_channel_transaction args;
95 	int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
96 	unsigned char *base;
97 	int recv_bytes;
98 	int r = 0;
99 
100 	memset(&args, 0, sizeof(args));
101 
102 	mutex_lock(&chan->mutex);
103 
104 	base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
105 
106 	radeon_atom_copy_swap(base, send, send_bytes, true);
107 
108 	args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
109 	args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4));
110 	args.v1.ucDataOutLen = 0;
111 	args.v1.ucChannelID = chan->rec.i2c_id;
112 	args.v1.ucDelay = delay / 10;
113 	if (ASIC_IS_DCE4(rdev))
114 		args.v2.ucHPD_ID = chan->rec.hpd;
115 
116 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
117 
118 	*ack = args.v1.ucReplyStatus;
119 
120 	/* timeout */
121 	if (args.v1.ucReplyStatus == 1) {
122 		DRM_DEBUG_KMS("dp_aux_ch timeout\n");
123 		r = -ETIMEDOUT;
124 		goto done;
125 	}
126 
127 	/* flags not zero */
128 	if (args.v1.ucReplyStatus == 2) {
129 		DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
130 		r = -EBUSY;
131 		goto done;
132 	}
133 
134 	/* error */
135 	if (args.v1.ucReplyStatus == 3) {
136 		DRM_DEBUG_KMS("dp_aux_ch error\n");
137 		r = -EIO;
138 		goto done;
139 	}
140 
141 	recv_bytes = args.v1.ucDataOutLen;
142 	if (recv_bytes > recv_size)
143 		recv_bytes = recv_size;
144 
145 	if (recv && recv_size)
146 		radeon_atom_copy_swap(recv, base + 16, recv_bytes, false);
147 
148 	r = recv_bytes;
149 done:
150 	mutex_unlock(&chan->mutex);
151 
152 	return r;
153 }
154 
155 #define BARE_ADDRESS_SIZE 3
156 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
157 
158 static ssize_t
159 radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
160 {
161 	struct radeon_i2c_chan *chan =
162 		container_of(aux, struct radeon_i2c_chan, aux);
163 	int ret;
164 	u8 tx_buf[20];
165 	size_t tx_size;
166 	u8 ack, delay = 0;
167 
168 	if (WARN_ON(msg->size > 16))
169 		return -E2BIG;
170 
171 	tx_buf[0] = msg->address & 0xff;
172 	tx_buf[1] = msg->address >> 8;
173 	tx_buf[2] = msg->request << 4;
174 	tx_buf[3] = msg->size ? (msg->size - 1) : 0;
175 
176 	switch (msg->request & ~DP_AUX_I2C_MOT) {
177 	case DP_AUX_NATIVE_WRITE:
178 	case DP_AUX_I2C_WRITE:
179 		/* tx_size needs to be 4 even for bare address packets since the atom
180 		 * table needs the info in tx_buf[3].
181 		 */
182 		tx_size = HEADER_SIZE + msg->size;
183 		if (msg->size == 0)
184 			tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
185 		else
186 			tx_buf[3] |= tx_size << 4;
187 		memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
188 		ret = radeon_process_aux_ch(chan,
189 					    tx_buf, tx_size, NULL, 0, delay, &ack);
190 		if (ret >= 0)
191 			/* Return payload size. */
192 			ret = msg->size;
193 		break;
194 	case DP_AUX_NATIVE_READ:
195 	case DP_AUX_I2C_READ:
196 		/* tx_size needs to be 4 even for bare address packets since the atom
197 		 * table needs the info in tx_buf[3].
198 		 */
199 		tx_size = HEADER_SIZE;
200 		if (msg->size == 0)
201 			tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
202 		else
203 			tx_buf[3] |= tx_size << 4;
204 		ret = radeon_process_aux_ch(chan,
205 					    tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
206 		break;
207 	default:
208 		ret = -EINVAL;
209 		break;
210 	}
211 
212 	if (ret >= 0)
213 		msg->reply = ack >> 4;
214 
215 	return ret;
216 }
217 
218 void radeon_dp_aux_init(struct radeon_connector *radeon_connector)
219 {
220 	int ret;
221 
222 	radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd;
223 	radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev;
224 	radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer;
225 
226 	ret = drm_dp_aux_register(&radeon_connector->ddc_bus->aux);
227 	if (!ret)
228 		radeon_connector->ddc_bus->has_aux = true;
229 
230 	WARN(ret, "drm_dp_aux_register() failed with error %d\n", ret);
231 }
232 
233 /***** general DP utility functions *****/
234 
235 #define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_1200
236 #define DP_PRE_EMPHASIS_MAX    DP_TRAIN_PRE_EMPHASIS_9_5
237 
238 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
239 				int lane_count,
240 				u8 train_set[4])
241 {
242 	u8 v = 0;
243 	u8 p = 0;
244 	int lane;
245 
246 	for (lane = 0; lane < lane_count; lane++) {
247 		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
248 		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
249 
250 		DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
251 			  lane,
252 			  voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
253 			  pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
254 
255 		if (this_v > v)
256 			v = this_v;
257 		if (this_p > p)
258 			p = this_p;
259 	}
260 
261 	if (v >= DP_VOLTAGE_MAX)
262 		v |= DP_TRAIN_MAX_SWING_REACHED;
263 
264 	if (p >= DP_PRE_EMPHASIS_MAX)
265 		p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
266 
267 	DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
268 		  voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
269 		  pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
270 
271 	for (lane = 0; lane < 4; lane++)
272 		train_set[lane] = v | p;
273 }
274 
275 /* convert bits per color to bits per pixel */
276 /* get bpc from the EDID */
277 static int convert_bpc_to_bpp(int bpc)
278 {
279 	if (bpc == 0)
280 		return 24;
281 	else
282 		return bpc * 3;
283 }
284 
285 /* get the max pix clock supported by the link rate and lane num */
286 static int dp_get_max_dp_pix_clock(int link_rate,
287 				   int lane_num,
288 				   int bpp)
289 {
290 	return (link_rate * lane_num * 8) / bpp;
291 }
292 
293 /***** radeon specific DP functions *****/
294 
295 static int radeon_dp_get_max_link_rate(struct drm_connector *connector,
296 				       u8 dpcd[DP_DPCD_SIZE])
297 {
298 	int max_link_rate;
299 
300 	if (radeon_connector_is_dp12_capable(connector))
301 		max_link_rate = min(drm_dp_max_link_rate(dpcd), 540000);
302 	else
303 		max_link_rate = min(drm_dp_max_link_rate(dpcd), 270000);
304 
305 	return max_link_rate;
306 }
307 
308 /* First get the min lane# when low rate is used according to pixel clock
309  * (prefer low rate), second check max lane# supported by DP panel,
310  * if the max lane# < low rate lane# then use max lane# instead.
311  */
312 static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
313 					u8 dpcd[DP_DPCD_SIZE],
314 					int pix_clock)
315 {
316 	int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
317 	int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd);
318 	int max_lane_num = drm_dp_max_lane_count(dpcd);
319 	int lane_num;
320 	int max_dp_pix_clock;
321 
322 	for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
323 		max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
324 		if (pix_clock <= max_dp_pix_clock)
325 			break;
326 	}
327 
328 	return lane_num;
329 }
330 
331 static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
332 				       u8 dpcd[DP_DPCD_SIZE],
333 				       int pix_clock)
334 {
335 	int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
336 	int lane_num, max_pix_clock;
337 
338 	if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
339 	    ENCODER_OBJECT_ID_NUTMEG)
340 		return 270000;
341 
342 	lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
343 	max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
344 	if (pix_clock <= max_pix_clock)
345 		return 162000;
346 	max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
347 	if (pix_clock <= max_pix_clock)
348 		return 270000;
349 	if (radeon_connector_is_dp12_capable(connector)) {
350 		max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
351 		if (pix_clock <= max_pix_clock)
352 			return 540000;
353 	}
354 
355 	return radeon_dp_get_max_link_rate(connector, dpcd);
356 }
357 
358 static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
359 				    int action, int dp_clock,
360 				    u8 ucconfig, u8 lane_num)
361 {
362 	DP_ENCODER_SERVICE_PARAMETERS args;
363 	int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
364 
365 	memset(&args, 0, sizeof(args));
366 	args.ucLinkClock = dp_clock / 10;
367 	args.ucConfig = ucconfig;
368 	args.ucAction = action;
369 	args.ucLaneNum = lane_num;
370 	args.ucStatus = 0;
371 
372 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
373 	return args.ucStatus;
374 }
375 
376 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
377 {
378 	struct drm_device *dev = radeon_connector->base.dev;
379 	struct radeon_device *rdev = dev->dev_private;
380 
381 	return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
382 					 radeon_connector->ddc_bus->rec.i2c_id, 0);
383 }
384 
385 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
386 {
387 	struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
388 	u8 buf[3];
389 
390 	if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
391 		return;
392 
393 	if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
394 		DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
395 			      buf[0], buf[1], buf[2]);
396 
397 	if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
398 		DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
399 			      buf[0], buf[1], buf[2]);
400 }
401 
402 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
403 {
404 	struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
405 	u8 msg[DP_DPCD_SIZE];
406 	int ret, i;
407 
408 	ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
409 			       DP_DPCD_SIZE);
410 	if (ret > 0) {
411 		memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
412 		DRM_DEBUG_KMS("DPCD: ");
413 		for (i = 0; i < DP_DPCD_SIZE; i++)
414 			DRM_DEBUG_KMS("%02x ", msg[i]);
415 		DRM_DEBUG_KMS("\n");
416 
417 		radeon_dp_probe_oui(radeon_connector);
418 
419 		return true;
420 	}
421 	dig_connector->dpcd[0] = 0;
422 	return false;
423 }
424 
425 int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
426 			     struct drm_connector *connector)
427 {
428 	struct drm_device *dev = encoder->dev;
429 	struct radeon_device *rdev = dev->dev_private;
430 	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
431 	struct radeon_connector_atom_dig *dig_connector;
432 	int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
433 	u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
434 	u8 tmp;
435 
436 	if (!ASIC_IS_DCE4(rdev))
437 		return panel_mode;
438 
439 	if (!radeon_connector->con_priv)
440 		return panel_mode;
441 
442 	dig_connector = radeon_connector->con_priv;
443 
444 	if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
445 		/* DP bridge chips */
446 		if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
447 				      DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
448 			if (tmp & 1)
449 				panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
450 			else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
451 				 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
452 				panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
453 			else
454 				panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
455 		}
456 	} else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
457 		/* eDP */
458 		if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
459 				      DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
460 			if (tmp & 1)
461 				panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
462 		}
463 	}
464 
465 	return panel_mode;
466 }
467 
468 void radeon_dp_set_link_config(struct drm_connector *connector,
469 			       const struct drm_display_mode *mode)
470 {
471 	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
472 	struct radeon_connector_atom_dig *dig_connector;
473 
474 	if (!radeon_connector->con_priv)
475 		return;
476 	dig_connector = radeon_connector->con_priv;
477 
478 	if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
479 	    (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
480 		dig_connector->dp_clock =
481 			radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
482 		dig_connector->dp_lane_count =
483 			radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
484 	}
485 }
486 
487 int radeon_dp_mode_valid_helper(struct drm_connector *connector,
488 				struct drm_display_mode *mode)
489 {
490 	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
491 	struct radeon_connector_atom_dig *dig_connector;
492 	int dp_clock;
493 
494 	if (!radeon_connector->con_priv)
495 		return MODE_CLOCK_HIGH;
496 	dig_connector = radeon_connector->con_priv;
497 
498 	dp_clock =
499 		radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
500 
501 	if ((dp_clock == 540000) &&
502 	    (!radeon_connector_is_dp12_capable(connector)))
503 		return MODE_CLOCK_HIGH;
504 
505 	return MODE_OK;
506 }
507 
508 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
509 {
510 	u8 link_status[DP_LINK_STATUS_SIZE];
511 	struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
512 
513 	if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status)
514 	    <= 0)
515 		return false;
516 	if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
517 		return false;
518 	return true;
519 }
520 
521 void radeon_dp_set_rx_power_state(struct drm_connector *connector,
522 				  u8 power_state)
523 {
524 	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
525 	struct radeon_connector_atom_dig *dig_connector;
526 
527 	if (!radeon_connector->con_priv)
528 		return;
529 
530 	dig_connector = radeon_connector->con_priv;
531 
532 	/* power up/down the sink */
533 	if (dig_connector->dpcd[0] >= 0x11) {
534 		drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux,
535 				   DP_SET_POWER, power_state);
536 		usleep_range(1000, 2000);
537 	}
538 }
539 
540 
541 struct radeon_dp_link_train_info {
542 	struct radeon_device *rdev;
543 	struct drm_encoder *encoder;
544 	struct drm_connector *connector;
545 	int enc_id;
546 	int dp_clock;
547 	int dp_lane_count;
548 	bool tp3_supported;
549 	u8 dpcd[DP_RECEIVER_CAP_SIZE];
550 	u8 train_set[4];
551 	u8 link_status[DP_LINK_STATUS_SIZE];
552 	u8 tries;
553 	bool use_dpencoder;
554 	struct drm_dp_aux *aux;
555 };
556 
557 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
558 {
559 	/* set the initial vs/emph on the source */
560 	atombios_dig_transmitter_setup(dp_info->encoder,
561 				       ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
562 				       0, dp_info->train_set[0]); /* sets all lanes at once */
563 
564 	/* set the vs/emph on the sink */
565 	drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
566 			  dp_info->train_set, dp_info->dp_lane_count);
567 }
568 
569 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
570 {
571 	int rtp = 0;
572 
573 	/* set training pattern on the source */
574 	if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
575 		switch (tp) {
576 		case DP_TRAINING_PATTERN_1:
577 			rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
578 			break;
579 		case DP_TRAINING_PATTERN_2:
580 			rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
581 			break;
582 		case DP_TRAINING_PATTERN_3:
583 			rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
584 			break;
585 		}
586 		atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
587 	} else {
588 		switch (tp) {
589 		case DP_TRAINING_PATTERN_1:
590 			rtp = 0;
591 			break;
592 		case DP_TRAINING_PATTERN_2:
593 			rtp = 1;
594 			break;
595 		}
596 		radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
597 					  dp_info->dp_clock, dp_info->enc_id, rtp);
598 	}
599 
600 	/* enable training pattern on the sink */
601 	drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
602 }
603 
604 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
605 {
606 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
607 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
608 	u8 tmp;
609 
610 	/* power up the sink */
611 	radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
612 
613 	/* possibly enable downspread on the sink */
614 	if (dp_info->dpcd[3] & 0x1)
615 		drm_dp_dpcd_writeb(dp_info->aux,
616 				   DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
617 	else
618 		drm_dp_dpcd_writeb(dp_info->aux,
619 				   DP_DOWNSPREAD_CTRL, 0);
620 
621 	if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
622 	    (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
623 		drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
624 	}
625 
626 	/* set the lane count on the sink */
627 	tmp = dp_info->dp_lane_count;
628 	if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
629 		tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
630 	drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
631 
632 	/* set the link rate on the sink */
633 	tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
634 	drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
635 
636 	/* start training on the source */
637 	if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
638 		atombios_dig_encoder_setup(dp_info->encoder,
639 					   ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
640 	else
641 		radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
642 					  dp_info->dp_clock, dp_info->enc_id, 0);
643 
644 	/* disable the training pattern on the sink */
645 	drm_dp_dpcd_writeb(dp_info->aux,
646 			   DP_TRAINING_PATTERN_SET,
647 			   DP_TRAINING_PATTERN_DISABLE);
648 
649 	return 0;
650 }
651 
652 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
653 {
654 	udelay(400);
655 
656 	/* disable the training pattern on the sink */
657 	drm_dp_dpcd_writeb(dp_info->aux,
658 			   DP_TRAINING_PATTERN_SET,
659 			   DP_TRAINING_PATTERN_DISABLE);
660 
661 	/* disable the training pattern on the source */
662 	if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
663 		atombios_dig_encoder_setup(dp_info->encoder,
664 					   ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
665 	else
666 		radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
667 					  dp_info->dp_clock, dp_info->enc_id, 0);
668 
669 	return 0;
670 }
671 
672 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
673 {
674 	bool clock_recovery;
675  	u8 voltage;
676 	int i;
677 
678 	radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
679 	memset(dp_info->train_set, 0, 4);
680 	radeon_dp_update_vs_emph(dp_info);
681 
682 	udelay(400);
683 
684 	/* clock recovery loop */
685 	clock_recovery = false;
686 	dp_info->tries = 0;
687 	voltage = 0xff;
688 	while (1) {
689 		drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
690 
691 		if (drm_dp_dpcd_read_link_status(dp_info->aux,
692 						 dp_info->link_status) <= 0) {
693 			DRM_ERROR("displayport link status failed\n");
694 			break;
695 		}
696 
697 		if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
698 			clock_recovery = true;
699 			break;
700 		}
701 
702 		for (i = 0; i < dp_info->dp_lane_count; i++) {
703 			if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
704 				break;
705 		}
706 		if (i == dp_info->dp_lane_count) {
707 			DRM_ERROR("clock recovery reached max voltage\n");
708 			break;
709 		}
710 
711 		if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
712 			++dp_info->tries;
713 			if (dp_info->tries == 5) {
714 				DRM_ERROR("clock recovery tried 5 times\n");
715 				break;
716 			}
717 		} else
718 			dp_info->tries = 0;
719 
720 		voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
721 
722 		/* Compute new train_set as requested by sink */
723 		dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
724 
725 		radeon_dp_update_vs_emph(dp_info);
726 	}
727 	if (!clock_recovery) {
728 		DRM_ERROR("clock recovery failed\n");
729 		return -1;
730 	} else {
731 		DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
732 			  dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
733 			  (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
734 			  DP_TRAIN_PRE_EMPHASIS_SHIFT);
735 		return 0;
736 	}
737 }
738 
739 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
740 {
741 	bool channel_eq;
742 
743 	if (dp_info->tp3_supported)
744 		radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
745 	else
746 		radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
747 
748 	/* channel equalization loop */
749 	dp_info->tries = 0;
750 	channel_eq = false;
751 	while (1) {
752 		drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
753 
754 		if (drm_dp_dpcd_read_link_status(dp_info->aux,
755 						 dp_info->link_status) <= 0) {
756 			DRM_ERROR("displayport link status failed\n");
757 			break;
758 		}
759 
760 		if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
761 			channel_eq = true;
762 			break;
763 		}
764 
765 		/* Try 5 times */
766 		if (dp_info->tries > 5) {
767 			DRM_ERROR("channel eq failed: 5 tries\n");
768 			break;
769 		}
770 
771 		/* Compute new train_set as requested by sink */
772 		dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
773 
774 		radeon_dp_update_vs_emph(dp_info);
775 		dp_info->tries++;
776 	}
777 
778 	if (!channel_eq) {
779 		DRM_ERROR("channel eq failed\n");
780 		return -1;
781 	} else {
782 		DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
783 			  dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
784 			  (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
785 			  >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
786 		return 0;
787 	}
788 }
789 
790 void radeon_dp_link_train(struct drm_encoder *encoder,
791 			  struct drm_connector *connector)
792 {
793 	struct drm_device *dev = encoder->dev;
794 	struct radeon_device *rdev = dev->dev_private;
795 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
796 	struct radeon_encoder_atom_dig *dig;
797 	struct radeon_connector *radeon_connector;
798 	struct radeon_connector_atom_dig *dig_connector;
799 	struct radeon_dp_link_train_info dp_info;
800 	int index;
801 	u8 tmp, frev, crev;
802 
803 	if (!radeon_encoder->enc_priv)
804 		return;
805 	dig = radeon_encoder->enc_priv;
806 
807 	radeon_connector = to_radeon_connector(connector);
808 	if (!radeon_connector->con_priv)
809 		return;
810 	dig_connector = radeon_connector->con_priv;
811 
812 	if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
813 	    (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
814 		return;
815 
816 	/* DPEncoderService newer than 1.1 can't program properly the
817 	 * training pattern. When facing such version use the
818 	 * DIGXEncoderControl (X== 1 | 2)
819 	 */
820 	dp_info.use_dpencoder = true;
821 	index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
822 	if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
823 		if (crev > 1) {
824 			dp_info.use_dpencoder = false;
825 		}
826 	}
827 
828 	dp_info.enc_id = 0;
829 	if (dig->dig_encoder)
830 		dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
831 	else
832 		dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
833 	if (dig->linkb)
834 		dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
835 	else
836 		dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
837 
838 	if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
839 	    == 1) {
840 		if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
841 			dp_info.tp3_supported = true;
842 		else
843 			dp_info.tp3_supported = false;
844 	} else {
845 		dp_info.tp3_supported = false;
846 	}
847 
848 	memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
849 	dp_info.rdev = rdev;
850 	dp_info.encoder = encoder;
851 	dp_info.connector = connector;
852 	dp_info.dp_lane_count = dig_connector->dp_lane_count;
853 	dp_info.dp_clock = dig_connector->dp_clock;
854 	dp_info.aux = &radeon_connector->ddc_bus->aux;
855 
856 	if (radeon_dp_link_train_init(&dp_info))
857 		goto done;
858 	if (radeon_dp_link_train_cr(&dp_info))
859 		goto done;
860 	if (radeon_dp_link_train_ce(&dp_info))
861 		goto done;
862 done:
863 	if (radeon_dp_link_train_finish(&dp_info))
864 		return;
865 }
866