1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 */ 27 #include <drm/drmP.h> 28 #include <drm/radeon_drm.h> 29 #include "radeon.h" 30 31 #include "atom.h" 32 #include "atom-bits.h" 33 #include <drm/drm_dp_helper.h> 34 35 /* move these to drm_dp_helper.c/h */ 36 #define DP_LINK_CONFIGURATION_SIZE 9 37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE 38 39 static char *voltage_names[] = { 40 "0.4V", "0.6V", "0.8V", "1.2V" 41 }; 42 static char *pre_emph_names[] = { 43 "0dB", "3.5dB", "6dB", "9.5dB" 44 }; 45 46 /***** radeon AUX functions *****/ 47 48 /* Atom needs data in little endian format 49 * so swap as appropriate when copying data to 50 * or from atom. Note that atom operates on 51 * dw units. 52 */ 53 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le) 54 { 55 #ifdef __BIG_ENDIAN 56 u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */ 57 u32 *dst32, *src32; 58 int i; 59 60 memcpy(src_tmp, src, num_bytes); 61 src32 = (u32 *)src_tmp; 62 dst32 = (u32 *)dst_tmp; 63 if (to_le) { 64 for (i = 0; i < ((num_bytes + 3) / 4); i++) 65 dst32[i] = cpu_to_le32(src32[i]); 66 memcpy(dst, dst_tmp, num_bytes); 67 } else { 68 u8 dws = num_bytes & ~3; 69 for (i = 0; i < ((num_bytes + 3) / 4); i++) 70 dst32[i] = le32_to_cpu(src32[i]); 71 memcpy(dst, dst_tmp, dws); 72 if (num_bytes % 4) { 73 for (i = 0; i < (num_bytes % 4); i++) 74 dst[dws+i] = dst_tmp[dws+i]; 75 } 76 } 77 #else 78 memcpy(dst, src, num_bytes); 79 #endif 80 } 81 82 union aux_channel_transaction { 83 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; 84 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; 85 }; 86 87 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan, 88 u8 *send, int send_bytes, 89 u8 *recv, int recv_size, 90 u8 delay, u8 *ack) 91 { 92 struct drm_device *dev = chan->dev; 93 struct radeon_device *rdev = dev->dev_private; 94 union aux_channel_transaction args; 95 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); 96 unsigned char *base; 97 int recv_bytes; 98 int r = 0; 99 100 memset(&args, 0, sizeof(args)); 101 102 mutex_lock(&chan->mutex); 103 mutex_lock(&rdev->mode_info.atom_context->scratch_mutex); 104 105 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); 106 107 radeon_atom_copy_swap(base, send, send_bytes, true); 108 109 args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4)); 110 args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4)); 111 args.v1.ucDataOutLen = 0; 112 args.v1.ucChannelID = chan->rec.i2c_id; 113 args.v1.ucDelay = delay / 10; 114 if (ASIC_IS_DCE4(rdev)) 115 args.v2.ucHPD_ID = chan->rec.hpd; 116 117 atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args); 118 119 *ack = args.v1.ucReplyStatus; 120 121 /* timeout */ 122 if (args.v1.ucReplyStatus == 1) { 123 DRM_DEBUG_KMS("dp_aux_ch timeout\n"); 124 r = -ETIMEDOUT; 125 goto done; 126 } 127 128 /* flags not zero */ 129 if (args.v1.ucReplyStatus == 2) { 130 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n"); 131 r = -EIO; 132 goto done; 133 } 134 135 /* error */ 136 if (args.v1.ucReplyStatus == 3) { 137 DRM_DEBUG_KMS("dp_aux_ch error\n"); 138 r = -EIO; 139 goto done; 140 } 141 142 recv_bytes = args.v1.ucDataOutLen; 143 if (recv_bytes > recv_size) 144 recv_bytes = recv_size; 145 146 if (recv && recv_size) 147 radeon_atom_copy_swap(recv, base + 16, recv_bytes, false); 148 149 r = recv_bytes; 150 done: 151 mutex_unlock(&rdev->mode_info.atom_context->scratch_mutex); 152 mutex_unlock(&chan->mutex); 153 154 return r; 155 } 156 157 #define BARE_ADDRESS_SIZE 3 158 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 159 160 static ssize_t 161 radeon_dp_aux_transfer_atom(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 162 { 163 struct radeon_i2c_chan *chan = 164 container_of(aux, struct radeon_i2c_chan, aux); 165 int ret; 166 u8 tx_buf[20]; 167 size_t tx_size; 168 u8 ack, delay = 0; 169 170 if (WARN_ON(msg->size > 16)) 171 return -E2BIG; 172 173 tx_buf[0] = msg->address & 0xff; 174 tx_buf[1] = (msg->address >> 8) & 0xff; 175 tx_buf[2] = (msg->request << 4) | 176 ((msg->address >> 16) & 0xf); 177 tx_buf[3] = msg->size ? (msg->size - 1) : 0; 178 179 switch (msg->request & ~DP_AUX_I2C_MOT) { 180 case DP_AUX_NATIVE_WRITE: 181 case DP_AUX_I2C_WRITE: 182 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 183 /* The atom implementation only supports writes with a max payload of 184 * 12 bytes since it uses 4 bits for the total count (header + payload) 185 * in the parameter space. The atom interface supports 16 byte 186 * payloads for reads. The hw itself supports up to 16 bytes of payload. 187 */ 188 if (WARN_ON_ONCE(msg->size > 12)) 189 return -E2BIG; 190 /* tx_size needs to be 4 even for bare address packets since the atom 191 * table needs the info in tx_buf[3]. 192 */ 193 tx_size = HEADER_SIZE + msg->size; 194 if (msg->size == 0) 195 tx_buf[3] |= BARE_ADDRESS_SIZE << 4; 196 else 197 tx_buf[3] |= tx_size << 4; 198 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size); 199 ret = radeon_process_aux_ch(chan, 200 tx_buf, tx_size, NULL, 0, delay, &ack); 201 if (ret >= 0) 202 /* Return payload size. */ 203 ret = msg->size; 204 break; 205 case DP_AUX_NATIVE_READ: 206 case DP_AUX_I2C_READ: 207 /* tx_size needs to be 4 even for bare address packets since the atom 208 * table needs the info in tx_buf[3]. 209 */ 210 tx_size = HEADER_SIZE; 211 if (msg->size == 0) 212 tx_buf[3] |= BARE_ADDRESS_SIZE << 4; 213 else 214 tx_buf[3] |= tx_size << 4; 215 ret = radeon_process_aux_ch(chan, 216 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack); 217 break; 218 default: 219 ret = -EINVAL; 220 break; 221 } 222 223 if (ret >= 0) 224 msg->reply = ack >> 4; 225 226 return ret; 227 } 228 229 void radeon_dp_aux_init(struct radeon_connector *radeon_connector) 230 { 231 struct drm_device *dev = radeon_connector->base.dev; 232 struct radeon_device *rdev = dev->dev_private; 233 int ret; 234 235 radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd; 236 radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev; 237 if (ASIC_IS_DCE5(rdev)) { 238 if (radeon_auxch) 239 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_native; 240 else 241 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom; 242 } else { 243 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom; 244 } 245 246 ret = drm_dp_aux_register(&radeon_connector->ddc_bus->aux); 247 if (!ret) 248 radeon_connector->ddc_bus->has_aux = true; 249 250 WARN(ret, "drm_dp_aux_register() failed with error %d\n", ret); 251 } 252 253 /***** general DP utility functions *****/ 254 255 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3 256 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3 257 258 static void dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE], 259 int lane_count, 260 u8 train_set[4]) 261 { 262 u8 v = 0; 263 u8 p = 0; 264 int lane; 265 266 for (lane = 0; lane < lane_count; lane++) { 267 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 268 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 269 270 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", 271 lane, 272 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 273 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 274 275 if (this_v > v) 276 v = this_v; 277 if (this_p > p) 278 p = this_p; 279 } 280 281 if (v >= DP_VOLTAGE_MAX) 282 v |= DP_TRAIN_MAX_SWING_REACHED; 283 284 if (p >= DP_PRE_EMPHASIS_MAX) 285 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 286 287 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n", 288 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 289 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 290 291 for (lane = 0; lane < 4; lane++) 292 train_set[lane] = v | p; 293 } 294 295 /* convert bits per color to bits per pixel */ 296 /* get bpc from the EDID */ 297 static int convert_bpc_to_bpp(int bpc) 298 { 299 if (bpc == 0) 300 return 24; 301 else 302 return bpc * 3; 303 } 304 305 /* get the max pix clock supported by the link rate and lane num */ 306 static int dp_get_max_dp_pix_clock(int link_rate, 307 int lane_num, 308 int bpp) 309 { 310 return (link_rate * lane_num * 8) / bpp; 311 } 312 313 /***** radeon specific DP functions *****/ 314 315 int radeon_dp_get_max_link_rate(struct drm_connector *connector, 316 const u8 dpcd[DP_DPCD_SIZE]) 317 { 318 int max_link_rate; 319 320 if (radeon_connector_is_dp12_capable(connector)) 321 max_link_rate = min(drm_dp_max_link_rate(dpcd), 540000); 322 else 323 max_link_rate = min(drm_dp_max_link_rate(dpcd), 270000); 324 325 return max_link_rate; 326 } 327 328 /* First get the min lane# when low rate is used according to pixel clock 329 * (prefer low rate), second check max lane# supported by DP panel, 330 * if the max lane# < low rate lane# then use max lane# instead. 331 */ 332 static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, 333 const u8 dpcd[DP_DPCD_SIZE], 334 int pix_clock) 335 { 336 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); 337 int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd); 338 int max_lane_num = drm_dp_max_lane_count(dpcd); 339 int lane_num; 340 int max_dp_pix_clock; 341 342 for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) { 343 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp); 344 if (pix_clock <= max_dp_pix_clock) 345 break; 346 } 347 348 return lane_num; 349 } 350 351 static int radeon_dp_get_dp_link_clock(struct drm_connector *connector, 352 const u8 dpcd[DP_DPCD_SIZE], 353 int pix_clock) 354 { 355 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); 356 int lane_num, max_pix_clock; 357 358 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 359 ENCODER_OBJECT_ID_NUTMEG) 360 return 270000; 361 362 lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock); 363 max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp); 364 if (pix_clock <= max_pix_clock) 365 return 162000; 366 max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp); 367 if (pix_clock <= max_pix_clock) 368 return 270000; 369 if (radeon_connector_is_dp12_capable(connector)) { 370 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp); 371 if (pix_clock <= max_pix_clock) 372 return 540000; 373 } 374 375 return radeon_dp_get_max_link_rate(connector, dpcd); 376 } 377 378 static u8 radeon_dp_encoder_service(struct radeon_device *rdev, 379 int action, int dp_clock, 380 u8 ucconfig, u8 lane_num) 381 { 382 DP_ENCODER_SERVICE_PARAMETERS args; 383 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); 384 385 memset(&args, 0, sizeof(args)); 386 args.ucLinkClock = dp_clock / 10; 387 args.ucConfig = ucconfig; 388 args.ucAction = action; 389 args.ucLaneNum = lane_num; 390 args.ucStatus = 0; 391 392 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 393 return args.ucStatus; 394 } 395 396 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector) 397 { 398 struct drm_device *dev = radeon_connector->base.dev; 399 struct radeon_device *rdev = dev->dev_private; 400 401 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, 402 radeon_connector->ddc_bus->rec.i2c_id, 0); 403 } 404 405 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector) 406 { 407 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 408 u8 buf[3]; 409 410 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 411 return; 412 413 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3) 414 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 415 buf[0], buf[1], buf[2]); 416 417 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3) 418 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 419 buf[0], buf[1], buf[2]); 420 } 421 422 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) 423 { 424 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 425 u8 msg[DP_DPCD_SIZE]; 426 int ret, i; 427 428 for (i = 0; i < 7; i++) { 429 ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg, 430 DP_DPCD_SIZE); 431 if (ret == DP_DPCD_SIZE) { 432 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); 433 434 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), 435 dig_connector->dpcd); 436 437 radeon_dp_probe_oui(radeon_connector); 438 439 return true; 440 } 441 } 442 dig_connector->dpcd[0] = 0; 443 return false; 444 } 445 446 int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 447 struct drm_connector *connector) 448 { 449 struct drm_device *dev = encoder->dev; 450 struct radeon_device *rdev = dev->dev_private; 451 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 452 struct radeon_connector_atom_dig *dig_connector; 453 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 454 u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector); 455 u8 tmp; 456 457 if (!ASIC_IS_DCE4(rdev)) 458 return panel_mode; 459 460 if (!radeon_connector->con_priv) 461 return panel_mode; 462 463 dig_connector = radeon_connector->con_priv; 464 465 if (dp_bridge != ENCODER_OBJECT_ID_NONE) { 466 /* DP bridge chips */ 467 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, 468 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { 469 if (tmp & 1) 470 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 471 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || 472 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) 473 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; 474 else 475 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 476 } 477 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 478 /* eDP */ 479 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, 480 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { 481 if (tmp & 1) 482 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 483 } 484 } 485 486 return panel_mode; 487 } 488 489 void radeon_dp_set_link_config(struct drm_connector *connector, 490 const struct drm_display_mode *mode) 491 { 492 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 493 struct radeon_connector_atom_dig *dig_connector; 494 495 if (!radeon_connector->con_priv) 496 return; 497 dig_connector = radeon_connector->con_priv; 498 499 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 500 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 501 dig_connector->dp_clock = 502 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); 503 dig_connector->dp_lane_count = 504 radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock); 505 } 506 } 507 508 int radeon_dp_mode_valid_helper(struct drm_connector *connector, 509 struct drm_display_mode *mode) 510 { 511 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 512 struct radeon_connector_atom_dig *dig_connector; 513 int dp_clock; 514 515 if ((mode->clock > 340000) && 516 (!radeon_connector_is_dp12_capable(connector))) 517 return MODE_CLOCK_HIGH; 518 519 if (!radeon_connector->con_priv) 520 return MODE_CLOCK_HIGH; 521 dig_connector = radeon_connector->con_priv; 522 523 dp_clock = 524 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); 525 526 if ((dp_clock == 540000) && 527 (!radeon_connector_is_dp12_capable(connector))) 528 return MODE_CLOCK_HIGH; 529 530 return MODE_OK; 531 } 532 533 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector) 534 { 535 u8 link_status[DP_LINK_STATUS_SIZE]; 536 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 537 538 if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status) 539 <= 0) 540 return false; 541 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count)) 542 return false; 543 return true; 544 } 545 546 void radeon_dp_set_rx_power_state(struct drm_connector *connector, 547 u8 power_state) 548 { 549 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 550 struct radeon_connector_atom_dig *dig_connector; 551 552 if (!radeon_connector->con_priv) 553 return; 554 555 dig_connector = radeon_connector->con_priv; 556 557 /* power up/down the sink */ 558 if (dig_connector->dpcd[0] >= 0x11) { 559 drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux, 560 DP_SET_POWER, power_state); 561 usleep_range(1000, 2000); 562 } 563 } 564 565 566 struct radeon_dp_link_train_info { 567 struct radeon_device *rdev; 568 struct drm_encoder *encoder; 569 struct drm_connector *connector; 570 int enc_id; 571 int dp_clock; 572 int dp_lane_count; 573 bool tp3_supported; 574 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 575 u8 train_set[4]; 576 u8 link_status[DP_LINK_STATUS_SIZE]; 577 u8 tries; 578 bool use_dpencoder; 579 struct drm_dp_aux *aux; 580 }; 581 582 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) 583 { 584 /* set the initial vs/emph on the source */ 585 atombios_dig_transmitter_setup(dp_info->encoder, 586 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, 587 0, dp_info->train_set[0]); /* sets all lanes at once */ 588 589 /* set the vs/emph on the sink */ 590 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET, 591 dp_info->train_set, dp_info->dp_lane_count); 592 } 593 594 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp) 595 { 596 int rtp = 0; 597 598 /* set training pattern on the source */ 599 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) { 600 switch (tp) { 601 case DP_TRAINING_PATTERN_1: 602 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; 603 break; 604 case DP_TRAINING_PATTERN_2: 605 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2; 606 break; 607 case DP_TRAINING_PATTERN_3: 608 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; 609 break; 610 } 611 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0); 612 } else { 613 switch (tp) { 614 case DP_TRAINING_PATTERN_1: 615 rtp = 0; 616 break; 617 case DP_TRAINING_PATTERN_2: 618 rtp = 1; 619 break; 620 } 621 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, 622 dp_info->dp_clock, dp_info->enc_id, rtp); 623 } 624 625 /* enable training pattern on the sink */ 626 drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp); 627 } 628 629 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) 630 { 631 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder); 632 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 633 u8 tmp; 634 635 /* power up the sink */ 636 radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0); 637 638 /* possibly enable downspread on the sink */ 639 if (dp_info->dpcd[3] & 0x1) 640 drm_dp_dpcd_writeb(dp_info->aux, 641 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); 642 else 643 drm_dp_dpcd_writeb(dp_info->aux, 644 DP_DOWNSPREAD_CTRL, 0); 645 646 if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE) 647 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1); 648 649 /* set the lane count on the sink */ 650 tmp = dp_info->dp_lane_count; 651 if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) 652 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 653 drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp); 654 655 /* set the link rate on the sink */ 656 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock); 657 drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp); 658 659 /* start training on the source */ 660 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) 661 atombios_dig_encoder_setup(dp_info->encoder, 662 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0); 663 else 664 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START, 665 dp_info->dp_clock, dp_info->enc_id, 0); 666 667 /* disable the training pattern on the sink */ 668 drm_dp_dpcd_writeb(dp_info->aux, 669 DP_TRAINING_PATTERN_SET, 670 DP_TRAINING_PATTERN_DISABLE); 671 672 return 0; 673 } 674 675 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info) 676 { 677 udelay(400); 678 679 /* disable the training pattern on the sink */ 680 drm_dp_dpcd_writeb(dp_info->aux, 681 DP_TRAINING_PATTERN_SET, 682 DP_TRAINING_PATTERN_DISABLE); 683 684 /* disable the training pattern on the source */ 685 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) 686 atombios_dig_encoder_setup(dp_info->encoder, 687 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0); 688 else 689 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, 690 dp_info->dp_clock, dp_info->enc_id, 0); 691 692 return 0; 693 } 694 695 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info) 696 { 697 bool clock_recovery; 698 u8 voltage; 699 int i; 700 701 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); 702 memset(dp_info->train_set, 0, 4); 703 radeon_dp_update_vs_emph(dp_info); 704 705 udelay(400); 706 707 /* clock recovery loop */ 708 clock_recovery = false; 709 dp_info->tries = 0; 710 voltage = 0xff; 711 while (1) { 712 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); 713 714 if (drm_dp_dpcd_read_link_status(dp_info->aux, 715 dp_info->link_status) <= 0) { 716 DRM_ERROR("displayport link status failed\n"); 717 break; 718 } 719 720 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { 721 clock_recovery = true; 722 break; 723 } 724 725 for (i = 0; i < dp_info->dp_lane_count; i++) { 726 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 727 break; 728 } 729 if (i == dp_info->dp_lane_count) { 730 DRM_ERROR("clock recovery reached max voltage\n"); 731 break; 732 } 733 734 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 735 ++dp_info->tries; 736 if (dp_info->tries == 5) { 737 DRM_ERROR("clock recovery tried 5 times\n"); 738 break; 739 } 740 } else 741 dp_info->tries = 0; 742 743 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 744 745 /* Compute new train_set as requested by sink */ 746 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); 747 748 radeon_dp_update_vs_emph(dp_info); 749 } 750 if (!clock_recovery) { 751 DRM_ERROR("clock recovery failed\n"); 752 return -1; 753 } else { 754 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", 755 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 756 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> 757 DP_TRAIN_PRE_EMPHASIS_SHIFT); 758 return 0; 759 } 760 } 761 762 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) 763 { 764 bool channel_eq; 765 766 if (dp_info->tp3_supported) 767 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3); 768 else 769 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2); 770 771 /* channel equalization loop */ 772 dp_info->tries = 0; 773 channel_eq = false; 774 while (1) { 775 drm_dp_link_train_channel_eq_delay(dp_info->dpcd); 776 777 if (drm_dp_dpcd_read_link_status(dp_info->aux, 778 dp_info->link_status) <= 0) { 779 DRM_ERROR("displayport link status failed\n"); 780 break; 781 } 782 783 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { 784 channel_eq = true; 785 break; 786 } 787 788 /* Try 5 times */ 789 if (dp_info->tries > 5) { 790 DRM_ERROR("channel eq failed: 5 tries\n"); 791 break; 792 } 793 794 /* Compute new train_set as requested by sink */ 795 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); 796 797 radeon_dp_update_vs_emph(dp_info); 798 dp_info->tries++; 799 } 800 801 if (!channel_eq) { 802 DRM_ERROR("channel eq failed\n"); 803 return -1; 804 } else { 805 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", 806 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 807 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) 808 >> DP_TRAIN_PRE_EMPHASIS_SHIFT); 809 return 0; 810 } 811 } 812 813 void radeon_dp_link_train(struct drm_encoder *encoder, 814 struct drm_connector *connector) 815 { 816 struct drm_device *dev = encoder->dev; 817 struct radeon_device *rdev = dev->dev_private; 818 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 819 struct radeon_encoder_atom_dig *dig; 820 struct radeon_connector *radeon_connector; 821 struct radeon_connector_atom_dig *dig_connector; 822 struct radeon_dp_link_train_info dp_info; 823 int index; 824 u8 tmp, frev, crev; 825 826 if (!radeon_encoder->enc_priv) 827 return; 828 dig = radeon_encoder->enc_priv; 829 830 radeon_connector = to_radeon_connector(connector); 831 if (!radeon_connector->con_priv) 832 return; 833 dig_connector = radeon_connector->con_priv; 834 835 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && 836 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) 837 return; 838 839 /* DPEncoderService newer than 1.1 can't program properly the 840 * training pattern. When facing such version use the 841 * DIGXEncoderControl (X== 1 | 2) 842 */ 843 dp_info.use_dpencoder = true; 844 index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); 845 if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) { 846 if (crev > 1) { 847 dp_info.use_dpencoder = false; 848 } 849 } 850 851 dp_info.enc_id = 0; 852 if (dig->dig_encoder) 853 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; 854 else 855 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; 856 if (dig->linkb) 857 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B; 858 else 859 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; 860 861 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp) 862 == 1) { 863 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) 864 dp_info.tp3_supported = true; 865 else 866 dp_info.tp3_supported = false; 867 } else { 868 dp_info.tp3_supported = false; 869 } 870 871 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); 872 dp_info.rdev = rdev; 873 dp_info.encoder = encoder; 874 dp_info.connector = connector; 875 dp_info.dp_lane_count = dig_connector->dp_lane_count; 876 dp_info.dp_clock = dig_connector->dp_clock; 877 dp_info.aux = &radeon_connector->ddc_bus->aux; 878 879 if (radeon_dp_link_train_init(&dp_info)) 880 goto done; 881 if (radeon_dp_link_train_cr(&dp_info)) 882 goto done; 883 if (radeon_dp_link_train_ce(&dp_info)) 884 goto done; 885 done: 886 if (radeon_dp_link_train_finish(&dp_info)) 887 return; 888 } 889