1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 */ 27 #include <drm/drmP.h> 28 #include <drm/radeon_drm.h> 29 #include "radeon.h" 30 31 #include "atom.h" 32 #include "atom-bits.h" 33 #include <drm/drm_dp_helper.h> 34 35 /* move these to drm_dp_helper.c/h */ 36 #define DP_LINK_CONFIGURATION_SIZE 9 37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE 38 39 static char *voltage_names[] = { 40 "0.4V", "0.6V", "0.8V", "1.2V" 41 }; 42 static char *pre_emph_names[] = { 43 "0dB", "3.5dB", "6dB", "9.5dB" 44 }; 45 46 /***** radeon AUX functions *****/ 47 48 /* Atom needs data in little endian format 49 * so swap as appropriate when copying data to 50 * or from atom. Note that atom operates on 51 * dw units. 52 */ 53 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le) 54 { 55 #ifdef __BIG_ENDIAN 56 u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */ 57 u32 *dst32, *src32; 58 int i; 59 60 memcpy(src_tmp, src, num_bytes); 61 src32 = (u32 *)src_tmp; 62 dst32 = (u32 *)dst_tmp; 63 if (to_le) { 64 for (i = 0; i < ((num_bytes + 3) / 4); i++) 65 dst32[i] = cpu_to_le32(src32[i]); 66 memcpy(dst, dst_tmp, num_bytes); 67 } else { 68 u8 dws = num_bytes & ~3; 69 for (i = 0; i < ((num_bytes + 3) / 4); i++) 70 dst32[i] = le32_to_cpu(src32[i]); 71 memcpy(dst, dst_tmp, dws); 72 if (num_bytes % 4) { 73 for (i = 0; i < (num_bytes % 4); i++) 74 dst[dws+i] = dst_tmp[dws+i]; 75 } 76 } 77 #else 78 memcpy(dst, src, num_bytes); 79 #endif 80 } 81 82 union aux_channel_transaction { 83 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; 84 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; 85 }; 86 87 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan, 88 u8 *send, int send_bytes, 89 u8 *recv, int recv_size, 90 u8 delay, u8 *ack) 91 { 92 struct drm_device *dev = chan->dev; 93 struct radeon_device *rdev = dev->dev_private; 94 union aux_channel_transaction args; 95 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); 96 unsigned char *base; 97 int recv_bytes; 98 99 memset(&args, 0, sizeof(args)); 100 101 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); 102 103 radeon_atom_copy_swap(base, send, send_bytes, true); 104 105 args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4)); 106 args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4)); 107 args.v1.ucDataOutLen = 0; 108 args.v1.ucChannelID = chan->rec.i2c_id; 109 args.v1.ucDelay = delay / 10; 110 if (ASIC_IS_DCE4(rdev)) 111 args.v2.ucHPD_ID = chan->rec.hpd; 112 113 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 114 115 *ack = args.v1.ucReplyStatus; 116 117 /* timeout */ 118 if (args.v1.ucReplyStatus == 1) { 119 DRM_DEBUG_KMS("dp_aux_ch timeout\n"); 120 return -ETIMEDOUT; 121 } 122 123 /* flags not zero */ 124 if (args.v1.ucReplyStatus == 2) { 125 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n"); 126 return -EBUSY; 127 } 128 129 /* error */ 130 if (args.v1.ucReplyStatus == 3) { 131 DRM_DEBUG_KMS("dp_aux_ch error\n"); 132 return -EIO; 133 } 134 135 recv_bytes = args.v1.ucDataOutLen; 136 if (recv_bytes > recv_size) 137 recv_bytes = recv_size; 138 139 if (recv && recv_size) 140 radeon_atom_copy_swap(recv, base + 16, recv_bytes, false); 141 142 return recv_bytes; 143 } 144 145 #define BARE_ADDRESS_SIZE 3 146 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 147 148 static ssize_t 149 radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 150 { 151 struct radeon_i2c_chan *chan = 152 container_of(aux, struct radeon_i2c_chan, aux); 153 int ret; 154 u8 tx_buf[20]; 155 size_t tx_size; 156 u8 ack, delay = 0; 157 158 if (WARN_ON(msg->size > 16)) 159 return -E2BIG; 160 161 tx_buf[0] = msg->address & 0xff; 162 tx_buf[1] = msg->address >> 8; 163 tx_buf[2] = msg->request << 4; 164 tx_buf[3] = msg->size ? (msg->size - 1) : 0; 165 166 switch (msg->request & ~DP_AUX_I2C_MOT) { 167 case DP_AUX_NATIVE_WRITE: 168 case DP_AUX_I2C_WRITE: 169 /* tx_size needs to be 4 even for bare address packets since the atom 170 * table needs the info in tx_buf[3]. 171 */ 172 tx_size = HEADER_SIZE + msg->size; 173 if (msg->size == 0) 174 tx_buf[3] |= BARE_ADDRESS_SIZE << 4; 175 else 176 tx_buf[3] |= tx_size << 4; 177 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size); 178 ret = radeon_process_aux_ch(chan, 179 tx_buf, tx_size, NULL, 0, delay, &ack); 180 if (ret >= 0) 181 /* Return payload size. */ 182 ret = msg->size; 183 break; 184 case DP_AUX_NATIVE_READ: 185 case DP_AUX_I2C_READ: 186 /* tx_size needs to be 4 even for bare address packets since the atom 187 * table needs the info in tx_buf[3]. 188 */ 189 tx_size = HEADER_SIZE; 190 if (msg->size == 0) 191 tx_buf[3] |= BARE_ADDRESS_SIZE << 4; 192 else 193 tx_buf[3] |= tx_size << 4; 194 ret = radeon_process_aux_ch(chan, 195 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack); 196 break; 197 default: 198 ret = -EINVAL; 199 break; 200 } 201 202 if (ret >= 0) 203 msg->reply = ack >> 4; 204 205 return ret; 206 } 207 208 void radeon_dp_aux_init(struct radeon_connector *radeon_connector) 209 { 210 int ret; 211 212 radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd; 213 radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev; 214 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer; 215 ret = drm_dp_aux_register_i2c_bus(&radeon_connector->ddc_bus->aux); 216 if (!ret) 217 radeon_connector->ddc_bus->has_aux = true; 218 219 WARN(ret, "drm_dp_aux_register_i2c_bus() failed with error %d\n", ret); 220 } 221 222 /***** general DP utility functions *****/ 223 224 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200 225 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5 226 227 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], 228 int lane_count, 229 u8 train_set[4]) 230 { 231 u8 v = 0; 232 u8 p = 0; 233 int lane; 234 235 for (lane = 0; lane < lane_count; lane++) { 236 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 237 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 238 239 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", 240 lane, 241 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 242 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 243 244 if (this_v > v) 245 v = this_v; 246 if (this_p > p) 247 p = this_p; 248 } 249 250 if (v >= DP_VOLTAGE_MAX) 251 v |= DP_TRAIN_MAX_SWING_REACHED; 252 253 if (p >= DP_PRE_EMPHASIS_MAX) 254 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 255 256 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n", 257 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 258 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 259 260 for (lane = 0; lane < 4; lane++) 261 train_set[lane] = v | p; 262 } 263 264 /* convert bits per color to bits per pixel */ 265 /* get bpc from the EDID */ 266 static int convert_bpc_to_bpp(int bpc) 267 { 268 if (bpc == 0) 269 return 24; 270 else 271 return bpc * 3; 272 } 273 274 /* get the max pix clock supported by the link rate and lane num */ 275 static int dp_get_max_dp_pix_clock(int link_rate, 276 int lane_num, 277 int bpp) 278 { 279 return (link_rate * lane_num * 8) / bpp; 280 } 281 282 /***** radeon specific DP functions *****/ 283 284 /* First get the min lane# when low rate is used according to pixel clock 285 * (prefer low rate), second check max lane# supported by DP panel, 286 * if the max lane# < low rate lane# then use max lane# instead. 287 */ 288 static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, 289 u8 dpcd[DP_DPCD_SIZE], 290 int pix_clock) 291 { 292 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); 293 int max_link_rate = drm_dp_max_link_rate(dpcd); 294 int max_lane_num = drm_dp_max_lane_count(dpcd); 295 int lane_num; 296 int max_dp_pix_clock; 297 298 for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) { 299 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp); 300 if (pix_clock <= max_dp_pix_clock) 301 break; 302 } 303 304 return lane_num; 305 } 306 307 static int radeon_dp_get_dp_link_clock(struct drm_connector *connector, 308 u8 dpcd[DP_DPCD_SIZE], 309 int pix_clock) 310 { 311 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); 312 int lane_num, max_pix_clock; 313 314 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 315 ENCODER_OBJECT_ID_NUTMEG) 316 return 270000; 317 318 lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock); 319 max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp); 320 if (pix_clock <= max_pix_clock) 321 return 162000; 322 max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp); 323 if (pix_clock <= max_pix_clock) 324 return 270000; 325 if (radeon_connector_is_dp12_capable(connector)) { 326 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp); 327 if (pix_clock <= max_pix_clock) 328 return 540000; 329 } 330 331 return drm_dp_max_link_rate(dpcd); 332 } 333 334 static u8 radeon_dp_encoder_service(struct radeon_device *rdev, 335 int action, int dp_clock, 336 u8 ucconfig, u8 lane_num) 337 { 338 DP_ENCODER_SERVICE_PARAMETERS args; 339 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); 340 341 memset(&args, 0, sizeof(args)); 342 args.ucLinkClock = dp_clock / 10; 343 args.ucConfig = ucconfig; 344 args.ucAction = action; 345 args.ucLaneNum = lane_num; 346 args.ucStatus = 0; 347 348 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 349 return args.ucStatus; 350 } 351 352 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector) 353 { 354 struct drm_device *dev = radeon_connector->base.dev; 355 struct radeon_device *rdev = dev->dev_private; 356 357 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, 358 radeon_connector->ddc_bus->rec.i2c_id, 0); 359 } 360 361 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector) 362 { 363 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 364 u8 buf[3]; 365 366 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 367 return; 368 369 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3) 370 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 371 buf[0], buf[1], buf[2]); 372 373 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3) 374 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 375 buf[0], buf[1], buf[2]); 376 } 377 378 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) 379 { 380 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 381 u8 msg[DP_DPCD_SIZE]; 382 int ret, i; 383 384 ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg, 385 DP_DPCD_SIZE); 386 if (ret > 0) { 387 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); 388 DRM_DEBUG_KMS("DPCD: "); 389 for (i = 0; i < DP_DPCD_SIZE; i++) 390 DRM_DEBUG_KMS("%02x ", msg[i]); 391 DRM_DEBUG_KMS("\n"); 392 393 radeon_dp_probe_oui(radeon_connector); 394 395 return true; 396 } 397 dig_connector->dpcd[0] = 0; 398 return false; 399 } 400 401 int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 402 struct drm_connector *connector) 403 { 404 struct drm_device *dev = encoder->dev; 405 struct radeon_device *rdev = dev->dev_private; 406 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 407 struct radeon_connector_atom_dig *dig_connector; 408 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 409 u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector); 410 u8 tmp; 411 412 if (!ASIC_IS_DCE4(rdev)) 413 return panel_mode; 414 415 if (!radeon_connector->con_priv) 416 return panel_mode; 417 418 dig_connector = radeon_connector->con_priv; 419 420 if (dp_bridge != ENCODER_OBJECT_ID_NONE) { 421 /* DP bridge chips */ 422 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, 423 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { 424 if (tmp & 1) 425 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 426 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || 427 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) 428 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; 429 else 430 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 431 } 432 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 433 /* eDP */ 434 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, 435 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { 436 if (tmp & 1) 437 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 438 } 439 } 440 441 return panel_mode; 442 } 443 444 void radeon_dp_set_link_config(struct drm_connector *connector, 445 const struct drm_display_mode *mode) 446 { 447 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 448 struct radeon_connector_atom_dig *dig_connector; 449 450 if (!radeon_connector->con_priv) 451 return; 452 dig_connector = radeon_connector->con_priv; 453 454 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 455 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 456 dig_connector->dp_clock = 457 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); 458 dig_connector->dp_lane_count = 459 radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock); 460 } 461 } 462 463 int radeon_dp_mode_valid_helper(struct drm_connector *connector, 464 struct drm_display_mode *mode) 465 { 466 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 467 struct radeon_connector_atom_dig *dig_connector; 468 int dp_clock; 469 470 if (!radeon_connector->con_priv) 471 return MODE_CLOCK_HIGH; 472 dig_connector = radeon_connector->con_priv; 473 474 dp_clock = 475 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); 476 477 if ((dp_clock == 540000) && 478 (!radeon_connector_is_dp12_capable(connector))) 479 return MODE_CLOCK_HIGH; 480 481 return MODE_OK; 482 } 483 484 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector) 485 { 486 u8 link_status[DP_LINK_STATUS_SIZE]; 487 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 488 489 if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status) 490 <= 0) 491 return false; 492 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count)) 493 return false; 494 return true; 495 } 496 497 void radeon_dp_set_rx_power_state(struct drm_connector *connector, 498 u8 power_state) 499 { 500 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 501 struct radeon_connector_atom_dig *dig_connector; 502 503 if (!radeon_connector->con_priv) 504 return; 505 506 dig_connector = radeon_connector->con_priv; 507 508 /* power up/down the sink */ 509 if (dig_connector->dpcd[0] >= 0x11) { 510 drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux, 511 DP_SET_POWER, power_state); 512 usleep_range(1000, 2000); 513 } 514 } 515 516 517 struct radeon_dp_link_train_info { 518 struct radeon_device *rdev; 519 struct drm_encoder *encoder; 520 struct drm_connector *connector; 521 int enc_id; 522 int dp_clock; 523 int dp_lane_count; 524 bool tp3_supported; 525 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 526 u8 train_set[4]; 527 u8 link_status[DP_LINK_STATUS_SIZE]; 528 u8 tries; 529 bool use_dpencoder; 530 struct drm_dp_aux *aux; 531 }; 532 533 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) 534 { 535 /* set the initial vs/emph on the source */ 536 atombios_dig_transmitter_setup(dp_info->encoder, 537 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, 538 0, dp_info->train_set[0]); /* sets all lanes at once */ 539 540 /* set the vs/emph on the sink */ 541 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET, 542 dp_info->train_set, dp_info->dp_lane_count); 543 } 544 545 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp) 546 { 547 int rtp = 0; 548 549 /* set training pattern on the source */ 550 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) { 551 switch (tp) { 552 case DP_TRAINING_PATTERN_1: 553 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; 554 break; 555 case DP_TRAINING_PATTERN_2: 556 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2; 557 break; 558 case DP_TRAINING_PATTERN_3: 559 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; 560 break; 561 } 562 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0); 563 } else { 564 switch (tp) { 565 case DP_TRAINING_PATTERN_1: 566 rtp = 0; 567 break; 568 case DP_TRAINING_PATTERN_2: 569 rtp = 1; 570 break; 571 } 572 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, 573 dp_info->dp_clock, dp_info->enc_id, rtp); 574 } 575 576 /* enable training pattern on the sink */ 577 drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp); 578 } 579 580 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) 581 { 582 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder); 583 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 584 u8 tmp; 585 586 /* power up the sink */ 587 radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0); 588 589 /* possibly enable downspread on the sink */ 590 if (dp_info->dpcd[3] & 0x1) 591 drm_dp_dpcd_writeb(dp_info->aux, 592 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); 593 else 594 drm_dp_dpcd_writeb(dp_info->aux, 595 DP_DOWNSPREAD_CTRL, 0); 596 597 if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) && 598 (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) { 599 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1); 600 } 601 602 /* set the lane count on the sink */ 603 tmp = dp_info->dp_lane_count; 604 if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) 605 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 606 drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp); 607 608 /* set the link rate on the sink */ 609 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock); 610 drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp); 611 612 /* start training on the source */ 613 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) 614 atombios_dig_encoder_setup(dp_info->encoder, 615 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0); 616 else 617 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START, 618 dp_info->dp_clock, dp_info->enc_id, 0); 619 620 /* disable the training pattern on the sink */ 621 drm_dp_dpcd_writeb(dp_info->aux, 622 DP_TRAINING_PATTERN_SET, 623 DP_TRAINING_PATTERN_DISABLE); 624 625 return 0; 626 } 627 628 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info) 629 { 630 udelay(400); 631 632 /* disable the training pattern on the sink */ 633 drm_dp_dpcd_writeb(dp_info->aux, 634 DP_TRAINING_PATTERN_SET, 635 DP_TRAINING_PATTERN_DISABLE); 636 637 /* disable the training pattern on the source */ 638 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) 639 atombios_dig_encoder_setup(dp_info->encoder, 640 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0); 641 else 642 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, 643 dp_info->dp_clock, dp_info->enc_id, 0); 644 645 return 0; 646 } 647 648 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info) 649 { 650 bool clock_recovery; 651 u8 voltage; 652 int i; 653 654 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); 655 memset(dp_info->train_set, 0, 4); 656 radeon_dp_update_vs_emph(dp_info); 657 658 udelay(400); 659 660 /* clock recovery loop */ 661 clock_recovery = false; 662 dp_info->tries = 0; 663 voltage = 0xff; 664 while (1) { 665 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); 666 667 if (drm_dp_dpcd_read_link_status(dp_info->aux, 668 dp_info->link_status) <= 0) { 669 DRM_ERROR("displayport link status failed\n"); 670 break; 671 } 672 673 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { 674 clock_recovery = true; 675 break; 676 } 677 678 for (i = 0; i < dp_info->dp_lane_count; i++) { 679 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 680 break; 681 } 682 if (i == dp_info->dp_lane_count) { 683 DRM_ERROR("clock recovery reached max voltage\n"); 684 break; 685 } 686 687 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 688 ++dp_info->tries; 689 if (dp_info->tries == 5) { 690 DRM_ERROR("clock recovery tried 5 times\n"); 691 break; 692 } 693 } else 694 dp_info->tries = 0; 695 696 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 697 698 /* Compute new train_set as requested by sink */ 699 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); 700 701 radeon_dp_update_vs_emph(dp_info); 702 } 703 if (!clock_recovery) { 704 DRM_ERROR("clock recovery failed\n"); 705 return -1; 706 } else { 707 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", 708 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 709 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> 710 DP_TRAIN_PRE_EMPHASIS_SHIFT); 711 return 0; 712 } 713 } 714 715 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) 716 { 717 bool channel_eq; 718 719 if (dp_info->tp3_supported) 720 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3); 721 else 722 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2); 723 724 /* channel equalization loop */ 725 dp_info->tries = 0; 726 channel_eq = false; 727 while (1) { 728 drm_dp_link_train_channel_eq_delay(dp_info->dpcd); 729 730 if (drm_dp_dpcd_read_link_status(dp_info->aux, 731 dp_info->link_status) <= 0) { 732 DRM_ERROR("displayport link status failed\n"); 733 break; 734 } 735 736 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { 737 channel_eq = true; 738 break; 739 } 740 741 /* Try 5 times */ 742 if (dp_info->tries > 5) { 743 DRM_ERROR("channel eq failed: 5 tries\n"); 744 break; 745 } 746 747 /* Compute new train_set as requested by sink */ 748 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); 749 750 radeon_dp_update_vs_emph(dp_info); 751 dp_info->tries++; 752 } 753 754 if (!channel_eq) { 755 DRM_ERROR("channel eq failed\n"); 756 return -1; 757 } else { 758 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", 759 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 760 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) 761 >> DP_TRAIN_PRE_EMPHASIS_SHIFT); 762 return 0; 763 } 764 } 765 766 void radeon_dp_link_train(struct drm_encoder *encoder, 767 struct drm_connector *connector) 768 { 769 struct drm_device *dev = encoder->dev; 770 struct radeon_device *rdev = dev->dev_private; 771 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 772 struct radeon_encoder_atom_dig *dig; 773 struct radeon_connector *radeon_connector; 774 struct radeon_connector_atom_dig *dig_connector; 775 struct radeon_dp_link_train_info dp_info; 776 int index; 777 u8 tmp, frev, crev; 778 779 if (!radeon_encoder->enc_priv) 780 return; 781 dig = radeon_encoder->enc_priv; 782 783 radeon_connector = to_radeon_connector(connector); 784 if (!radeon_connector->con_priv) 785 return; 786 dig_connector = radeon_connector->con_priv; 787 788 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && 789 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) 790 return; 791 792 /* DPEncoderService newer than 1.1 can't program properly the 793 * training pattern. When facing such version use the 794 * DIGXEncoderControl (X== 1 | 2) 795 */ 796 dp_info.use_dpencoder = true; 797 index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); 798 if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) { 799 if (crev > 1) { 800 dp_info.use_dpencoder = false; 801 } 802 } 803 804 dp_info.enc_id = 0; 805 if (dig->dig_encoder) 806 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; 807 else 808 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; 809 if (dig->linkb) 810 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B; 811 else 812 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; 813 814 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp) 815 == 1) { 816 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) 817 dp_info.tp3_supported = true; 818 else 819 dp_info.tp3_supported = false; 820 } else { 821 dp_info.tp3_supported = false; 822 } 823 824 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); 825 dp_info.rdev = rdev; 826 dp_info.encoder = encoder; 827 dp_info.connector = connector; 828 dp_info.dp_lane_count = dig_connector->dp_lane_count; 829 dp_info.dp_clock = dig_connector->dp_clock; 830 dp_info.aux = &radeon_connector->ddc_bus->aux; 831 832 if (radeon_dp_link_train_init(&dp_info)) 833 goto done; 834 if (radeon_dp_link_train_cr(&dp_info)) 835 goto done; 836 if (radeon_dp_link_train_ce(&dp_info)) 837 goto done; 838 done: 839 if (radeon_dp_link_train_finish(&dp_info)) 840 return; 841 } 842