1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include "drmP.h" 27 #include "radeon_drm.h" 28 #include "radeon.h" 29 30 #include "atom.h" 31 #include "atom-bits.h" 32 #include "drm_dp_helper.h" 33 34 /* move these to drm_dp_helper.c/h */ 35 #define DP_LINK_CONFIGURATION_SIZE 9 36 #define DP_LINK_STATUS_SIZE 6 37 #define DP_DPCD_SIZE 8 38 39 static char *voltage_names[] = { 40 "0.4V", "0.6V", "0.8V", "1.2V" 41 }; 42 static char *pre_emph_names[] = { 43 "0dB", "3.5dB", "6dB", "9.5dB" 44 }; 45 46 static const int dp_clocks[] = { 47 54000, /* 1 lane, 1.62 Ghz */ 48 90000, /* 1 lane, 2.70 Ghz */ 49 108000, /* 2 lane, 1.62 Ghz */ 50 180000, /* 2 lane, 2.70 Ghz */ 51 216000, /* 4 lane, 1.62 Ghz */ 52 360000, /* 4 lane, 2.70 Ghz */ 53 }; 54 55 static const int num_dp_clocks = sizeof(dp_clocks) / sizeof(int); 56 57 /* common helper functions */ 58 static int dp_lanes_for_mode_clock(u8 dpcd[DP_DPCD_SIZE], int mode_clock) 59 { 60 int i; 61 u8 max_link_bw; 62 u8 max_lane_count; 63 64 if (!dpcd) 65 return 0; 66 67 max_link_bw = dpcd[DP_MAX_LINK_RATE]; 68 max_lane_count = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; 69 70 switch (max_link_bw) { 71 case DP_LINK_BW_1_62: 72 default: 73 for (i = 0; i < num_dp_clocks; i++) { 74 if (i % 2) 75 continue; 76 switch (max_lane_count) { 77 case 1: 78 if (i > 1) 79 return 0; 80 break; 81 case 2: 82 if (i > 3) 83 return 0; 84 break; 85 case 4: 86 default: 87 break; 88 } 89 if (dp_clocks[i] > mode_clock) { 90 if (i < 2) 91 return 1; 92 else if (i < 4) 93 return 2; 94 else 95 return 4; 96 } 97 } 98 break; 99 case DP_LINK_BW_2_7: 100 for (i = 0; i < num_dp_clocks; i++) { 101 switch (max_lane_count) { 102 case 1: 103 if (i > 1) 104 return 0; 105 break; 106 case 2: 107 if (i > 3) 108 return 0; 109 break; 110 case 4: 111 default: 112 break; 113 } 114 if (dp_clocks[i] > mode_clock) { 115 if (i < 2) 116 return 1; 117 else if (i < 4) 118 return 2; 119 else 120 return 4; 121 } 122 } 123 break; 124 } 125 126 return 0; 127 } 128 129 static int dp_link_clock_for_mode_clock(u8 dpcd[DP_DPCD_SIZE], int mode_clock) 130 { 131 int i; 132 u8 max_link_bw; 133 u8 max_lane_count; 134 135 if (!dpcd) 136 return 0; 137 138 max_link_bw = dpcd[DP_MAX_LINK_RATE]; 139 max_lane_count = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; 140 141 switch (max_link_bw) { 142 case DP_LINK_BW_1_62: 143 default: 144 for (i = 0; i < num_dp_clocks; i++) { 145 if (i % 2) 146 continue; 147 switch (max_lane_count) { 148 case 1: 149 if (i > 1) 150 return 0; 151 break; 152 case 2: 153 if (i > 3) 154 return 0; 155 break; 156 case 4: 157 default: 158 break; 159 } 160 if (dp_clocks[i] > mode_clock) 161 return 162000; 162 } 163 break; 164 case DP_LINK_BW_2_7: 165 for (i = 0; i < num_dp_clocks; i++) { 166 switch (max_lane_count) { 167 case 1: 168 if (i > 1) 169 return 0; 170 break; 171 case 2: 172 if (i > 3) 173 return 0; 174 break; 175 case 4: 176 default: 177 break; 178 } 179 if (dp_clocks[i] > mode_clock) 180 return (i % 2) ? 270000 : 162000; 181 } 182 } 183 184 return 0; 185 } 186 187 int dp_mode_valid(u8 dpcd[DP_DPCD_SIZE], int mode_clock) 188 { 189 int lanes = dp_lanes_for_mode_clock(dpcd, mode_clock); 190 int bw = dp_lanes_for_mode_clock(dpcd, mode_clock); 191 192 if ((lanes == 0) || (bw == 0)) 193 return MODE_CLOCK_HIGH; 194 195 return MODE_OK; 196 } 197 198 static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r) 199 { 200 return link_status[r - DP_LANE0_1_STATUS]; 201 } 202 203 static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE], 204 int lane) 205 { 206 int i = DP_LANE0_1_STATUS + (lane >> 1); 207 int s = (lane & 1) * 4; 208 u8 l = dp_link_status(link_status, i); 209 return (l >> s) & 0xf; 210 } 211 212 static bool dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE], 213 int lane_count) 214 { 215 int lane; 216 u8 lane_status; 217 218 for (lane = 0; lane < lane_count; lane++) { 219 lane_status = dp_get_lane_status(link_status, lane); 220 if ((lane_status & DP_LANE_CR_DONE) == 0) 221 return false; 222 } 223 return true; 224 } 225 226 static bool dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE], 227 int lane_count) 228 { 229 u8 lane_align; 230 u8 lane_status; 231 int lane; 232 233 lane_align = dp_link_status(link_status, 234 DP_LANE_ALIGN_STATUS_UPDATED); 235 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) 236 return false; 237 for (lane = 0; lane < lane_count; lane++) { 238 lane_status = dp_get_lane_status(link_status, lane); 239 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS) 240 return false; 241 } 242 return true; 243 } 244 245 static u8 dp_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], 246 int lane) 247 248 { 249 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 250 int s = ((lane & 1) ? 251 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 252 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); 253 u8 l = dp_link_status(link_status, i); 254 255 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 256 } 257 258 static u8 dp_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], 259 int lane) 260 { 261 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 262 int s = ((lane & 1) ? 263 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : 264 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); 265 u8 l = dp_link_status(link_status, i); 266 267 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 268 } 269 270 /* XXX fix me -- chip specific */ 271 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200 272 static u8 dp_pre_emphasis_max(u8 voltage_swing) 273 { 274 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 275 case DP_TRAIN_VOLTAGE_SWING_400: 276 return DP_TRAIN_PRE_EMPHASIS_6; 277 case DP_TRAIN_VOLTAGE_SWING_600: 278 return DP_TRAIN_PRE_EMPHASIS_6; 279 case DP_TRAIN_VOLTAGE_SWING_800: 280 return DP_TRAIN_PRE_EMPHASIS_3_5; 281 case DP_TRAIN_VOLTAGE_SWING_1200: 282 default: 283 return DP_TRAIN_PRE_EMPHASIS_0; 284 } 285 } 286 287 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], 288 int lane_count, 289 u8 train_set[4]) 290 { 291 u8 v = 0; 292 u8 p = 0; 293 int lane; 294 295 for (lane = 0; lane < lane_count; lane++) { 296 u8 this_v = dp_get_adjust_request_voltage(link_status, lane); 297 u8 this_p = dp_get_adjust_request_pre_emphasis(link_status, lane); 298 299 DRM_DEBUG("requested signal parameters: lane %d voltage %s pre_emph %s\n", 300 lane, 301 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 302 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 303 304 if (this_v > v) 305 v = this_v; 306 if (this_p > p) 307 p = this_p; 308 } 309 310 if (v >= DP_VOLTAGE_MAX) 311 v = DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; 312 313 if (p >= dp_pre_emphasis_max(v)) 314 p = dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 315 316 DRM_DEBUG("using signal parameters: voltage %s pre_emph %s\n", 317 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 318 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 319 320 for (lane = 0; lane < 4; lane++) 321 train_set[lane] = v | p; 322 } 323 324 325 /* radeon aux chan functions */ 326 bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes, 327 int num_bytes, u8 *read_byte, 328 u8 read_buf_len, u8 delay) 329 { 330 struct drm_device *dev = chan->dev; 331 struct radeon_device *rdev = dev->dev_private; 332 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION args; 333 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); 334 unsigned char *base; 335 336 memset(&args, 0, sizeof(args)); 337 338 base = (unsigned char *)rdev->mode_info.atom_context->scratch; 339 340 memcpy(base, req_bytes, num_bytes); 341 342 args.lpAuxRequest = 0; 343 args.lpDataOut = 16; 344 args.ucDataOutLen = 0; 345 args.ucChannelID = chan->rec.i2c_id; 346 args.ucDelay = delay / 10; 347 348 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 349 350 if (args.ucReplyStatus) { 351 DRM_DEBUG("failed to get auxch %02x%02x %02x %02x 0x%02x %02x\n", 352 req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3], 353 chan->rec.i2c_id, args.ucReplyStatus); 354 return false; 355 } 356 357 if (args.ucDataOutLen && read_byte && read_buf_len) { 358 if (read_buf_len < args.ucDataOutLen) { 359 DRM_ERROR("Buffer to small for return answer %d %d\n", 360 read_buf_len, args.ucDataOutLen); 361 return false; 362 } 363 { 364 int len = min(read_buf_len, args.ucDataOutLen); 365 memcpy(read_byte, base + 16, len); 366 } 367 } 368 return true; 369 } 370 371 bool radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, uint16_t address, 372 uint8_t send_bytes, uint8_t *send) 373 { 374 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 375 u8 msg[20]; 376 u8 msg_len, dp_msg_len; 377 bool ret; 378 379 dp_msg_len = 4; 380 msg[0] = address; 381 msg[1] = address >> 8; 382 msg[2] = AUX_NATIVE_WRITE << 4; 383 dp_msg_len += send_bytes; 384 msg[3] = (dp_msg_len << 4) | (send_bytes - 1); 385 386 if (send_bytes > 16) 387 return false; 388 389 memcpy(&msg[4], send, send_bytes); 390 msg_len = 4 + send_bytes; 391 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, msg, msg_len, NULL, 0, 0); 392 return ret; 393 } 394 395 bool radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, uint16_t address, 396 uint8_t delay, uint8_t expected_bytes, 397 uint8_t *read_p) 398 { 399 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 400 u8 msg[20]; 401 u8 msg_len, dp_msg_len; 402 bool ret = false; 403 msg_len = 4; 404 dp_msg_len = 4; 405 msg[0] = address; 406 msg[1] = address >> 8; 407 msg[2] = AUX_NATIVE_READ << 4; 408 msg[3] = (dp_msg_len) << 4; 409 msg[3] |= expected_bytes - 1; 410 411 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, msg, msg_len, read_p, expected_bytes, delay); 412 return ret; 413 } 414 415 /* radeon dp functions */ 416 static u8 radeon_dp_encoder_service(struct radeon_device *rdev, int action, int dp_clock, 417 uint8_t ucconfig, uint8_t lane_num) 418 { 419 DP_ENCODER_SERVICE_PARAMETERS args; 420 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); 421 422 memset(&args, 0, sizeof(args)); 423 args.ucLinkClock = dp_clock / 10; 424 args.ucConfig = ucconfig; 425 args.ucAction = action; 426 args.ucLaneNum = lane_num; 427 args.ucStatus = 0; 428 429 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 430 return args.ucStatus; 431 } 432 433 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector) 434 { 435 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 436 struct drm_device *dev = radeon_connector->base.dev; 437 struct radeon_device *rdev = dev->dev_private; 438 439 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, 440 dig_connector->dp_i2c_bus->rec.i2c_id, 0); 441 } 442 443 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) 444 { 445 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 446 u8 msg[25]; 447 int ret; 448 449 ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, 0, 8, msg); 450 if (ret) { 451 memcpy(dig_connector->dpcd, msg, 8); 452 { 453 int i; 454 DRM_DEBUG("DPCD: "); 455 for (i = 0; i < 8; i++) 456 DRM_DEBUG("%02x ", msg[i]); 457 DRM_DEBUG("\n"); 458 } 459 return true; 460 } 461 dig_connector->dpcd[0] = 0; 462 return false; 463 } 464 465 void radeon_dp_set_link_config(struct drm_connector *connector, 466 struct drm_display_mode *mode) 467 { 468 struct radeon_connector *radeon_connector; 469 struct radeon_connector_atom_dig *dig_connector; 470 471 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 472 return; 473 474 radeon_connector = to_radeon_connector(connector); 475 if (!radeon_connector->con_priv) 476 return; 477 dig_connector = radeon_connector->con_priv; 478 479 dig_connector->dp_clock = 480 dp_link_clock_for_mode_clock(dig_connector->dpcd, mode->clock); 481 dig_connector->dp_lane_count = 482 dp_lanes_for_mode_clock(dig_connector->dpcd, mode->clock); 483 } 484 485 int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector, 486 struct drm_display_mode *mode) 487 { 488 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 489 490 return dp_mode_valid(dig_connector->dpcd, mode->clock); 491 } 492 493 static bool atom_dp_get_link_status(struct radeon_connector *radeon_connector, 494 u8 link_status[DP_LINK_STATUS_SIZE]) 495 { 496 int ret; 497 ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS, 100, 498 DP_LINK_STATUS_SIZE, link_status); 499 if (!ret) { 500 DRM_ERROR("displayport link status failed\n"); 501 return false; 502 } 503 504 DRM_DEBUG("link status %02x %02x %02x %02x %02x %02x\n", 505 link_status[0], link_status[1], link_status[2], 506 link_status[3], link_status[4], link_status[5]); 507 return true; 508 } 509 510 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector) 511 { 512 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 513 u8 link_status[DP_LINK_STATUS_SIZE]; 514 515 if (!atom_dp_get_link_status(radeon_connector, link_status)) 516 return false; 517 if (dp_channel_eq_ok(link_status, dig_connector->dp_lane_count)) 518 return false; 519 return true; 520 } 521 522 static void dp_set_power(struct radeon_connector *radeon_connector, u8 power_state) 523 { 524 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 525 526 if (dig_connector->dpcd[0] >= 0x11) { 527 radeon_dp_aux_native_write(radeon_connector, DP_SET_POWER, 1, 528 &power_state); 529 } 530 } 531 532 static void dp_set_downspread(struct radeon_connector *radeon_connector, u8 downspread) 533 { 534 radeon_dp_aux_native_write(radeon_connector, DP_DOWNSPREAD_CTRL, 1, 535 &downspread); 536 } 537 538 static void dp_set_link_bw_lanes(struct radeon_connector *radeon_connector, 539 u8 link_configuration[DP_LINK_CONFIGURATION_SIZE]) 540 { 541 radeon_dp_aux_native_write(radeon_connector, DP_LINK_BW_SET, 2, 542 link_configuration); 543 } 544 545 static void dp_update_dpvs_emph(struct radeon_connector *radeon_connector, 546 struct drm_encoder *encoder, 547 u8 train_set[4]) 548 { 549 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 550 int i; 551 552 for (i = 0; i < dig_connector->dp_lane_count; i++) 553 atombios_dig_transmitter_setup(encoder, 554 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, 555 i, train_set[i]); 556 557 radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_LANE0_SET, 558 dig_connector->dp_lane_count, train_set); 559 } 560 561 static void dp_set_training(struct radeon_connector *radeon_connector, 562 u8 training) 563 { 564 radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_PATTERN_SET, 565 1, &training); 566 } 567 568 void dp_link_train(struct drm_encoder *encoder, 569 struct drm_connector *connector) 570 { 571 struct drm_device *dev = encoder->dev; 572 struct radeon_device *rdev = dev->dev_private; 573 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 574 struct radeon_encoder_atom_dig *dig; 575 struct radeon_connector *radeon_connector; 576 struct radeon_connector_atom_dig *dig_connector; 577 int enc_id = 0; 578 bool clock_recovery, channel_eq; 579 u8 link_status[DP_LINK_STATUS_SIZE]; 580 u8 link_configuration[DP_LINK_CONFIGURATION_SIZE]; 581 u8 tries, voltage; 582 u8 train_set[4]; 583 int i; 584 585 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 586 return; 587 588 if (!radeon_encoder->enc_priv) 589 return; 590 dig = radeon_encoder->enc_priv; 591 592 radeon_connector = to_radeon_connector(connector); 593 if (!radeon_connector->con_priv) 594 return; 595 dig_connector = radeon_connector->con_priv; 596 597 if (ASIC_IS_DCE32(rdev)) { 598 if (dig->dig_block) 599 enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; 600 else 601 enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; 602 if (dig_connector->linkb) 603 enc_id |= ATOM_DP_CONFIG_LINK_B; 604 else 605 enc_id |= ATOM_DP_CONFIG_LINK_A; 606 } else { 607 if (dig_connector->linkb) 608 enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER | ATOM_DP_CONFIG_LINK_B; 609 else 610 enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER | ATOM_DP_CONFIG_LINK_A; 611 } 612 613 memset(link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); 614 if (dig_connector->dp_clock == 270000) 615 link_configuration[0] = DP_LINK_BW_2_7; 616 else 617 link_configuration[0] = DP_LINK_BW_1_62; 618 link_configuration[1] = dig_connector->dp_lane_count; 619 if (dig_connector->dpcd[0] >= 0x11) 620 link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 621 622 /* power up the sink */ 623 dp_set_power(radeon_connector, DP_SET_POWER_D0); 624 /* disable the training pattern on the sink */ 625 dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE); 626 /* set link bw and lanes on the sink */ 627 dp_set_link_bw_lanes(radeon_connector, link_configuration); 628 /* disable downspread on the sink */ 629 dp_set_downspread(radeon_connector, 0); 630 /* start training on the source */ 631 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_START, 632 dig_connector->dp_clock, enc_id, 0); 633 /* set training pattern 1 on the source */ 634 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, 635 dig_connector->dp_clock, enc_id, 0); 636 637 /* set initial vs/emph */ 638 memset(train_set, 0, 4); 639 udelay(400); 640 /* set training pattern 1 on the sink */ 641 dp_set_training(radeon_connector, DP_TRAINING_PATTERN_1); 642 643 dp_update_dpvs_emph(radeon_connector, encoder, train_set); 644 645 /* clock recovery loop */ 646 clock_recovery = false; 647 tries = 0; 648 voltage = 0xff; 649 for (;;) { 650 udelay(100); 651 if (!atom_dp_get_link_status(radeon_connector, link_status)) 652 break; 653 654 if (dp_clock_recovery_ok(link_status, dig_connector->dp_lane_count)) { 655 clock_recovery = true; 656 break; 657 } 658 659 for (i = 0; i < dig_connector->dp_lane_count; i++) { 660 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 661 break; 662 } 663 if (i == dig_connector->dp_lane_count) { 664 DRM_ERROR("clock recovery reached max voltage\n"); 665 break; 666 } 667 668 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 669 ++tries; 670 if (tries == 5) { 671 DRM_ERROR("clock recovery tried 5 times\n"); 672 break; 673 } 674 } else 675 tries = 0; 676 677 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 678 679 /* Compute new train_set as requested by sink */ 680 dp_get_adjust_train(link_status, dig_connector->dp_lane_count, train_set); 681 dp_update_dpvs_emph(radeon_connector, encoder, train_set); 682 } 683 if (!clock_recovery) 684 DRM_ERROR("clock recovery failed\n"); 685 else 686 DRM_DEBUG("clock recovery at voltage %d pre-emphasis %d\n", 687 train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 688 (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> 689 DP_TRAIN_PRE_EMPHASIS_SHIFT); 690 691 692 /* set training pattern 2 on the sink */ 693 dp_set_training(radeon_connector, DP_TRAINING_PATTERN_2); 694 /* set training pattern 2 on the source */ 695 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, 696 dig_connector->dp_clock, enc_id, 1); 697 698 /* channel equalization loop */ 699 tries = 0; 700 channel_eq = false; 701 for (;;) { 702 udelay(400); 703 if (!atom_dp_get_link_status(radeon_connector, link_status)) 704 break; 705 706 if (dp_channel_eq_ok(link_status, dig_connector->dp_lane_count)) { 707 channel_eq = true; 708 break; 709 } 710 711 /* Try 5 times */ 712 if (tries > 5) { 713 DRM_ERROR("channel eq failed: 5 tries\n"); 714 break; 715 } 716 717 /* Compute new train_set as requested by sink */ 718 dp_get_adjust_train(link_status, dig_connector->dp_lane_count, train_set); 719 dp_update_dpvs_emph(radeon_connector, encoder, train_set); 720 721 tries++; 722 } 723 724 if (!channel_eq) 725 DRM_ERROR("channel eq failed\n"); 726 else 727 DRM_DEBUG("channel eq at voltage %d pre-emphasis %d\n", 728 train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 729 (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) 730 >> DP_TRAIN_PRE_EMPHASIS_SHIFT); 731 732 /* disable the training pattern on the sink */ 733 dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE); 734 735 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, 736 dig_connector->dp_clock, enc_id, 0); 737 } 738 739 int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 740 uint8_t write_byte, uint8_t *read_byte) 741 { 742 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; 743 struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter; 744 int ret = 0; 745 uint16_t address = algo_data->address; 746 uint8_t msg[5]; 747 uint8_t reply[2]; 748 int msg_len, dp_msg_len; 749 int reply_bytes; 750 751 /* Set up the command byte */ 752 if (mode & MODE_I2C_READ) 753 msg[2] = AUX_I2C_READ << 4; 754 else 755 msg[2] = AUX_I2C_WRITE << 4; 756 757 if (!(mode & MODE_I2C_STOP)) 758 msg[2] |= AUX_I2C_MOT << 4; 759 760 msg[0] = address; 761 msg[1] = address >> 8; 762 763 reply_bytes = 1; 764 765 msg_len = 4; 766 dp_msg_len = 3; 767 switch (mode) { 768 case MODE_I2C_WRITE: 769 msg[4] = write_byte; 770 msg_len++; 771 dp_msg_len += 2; 772 break; 773 case MODE_I2C_READ: 774 dp_msg_len += 1; 775 break; 776 default: 777 break; 778 } 779 780 msg[3] = (dp_msg_len) << 4; 781 ret = radeon_process_aux_ch(auxch, msg, msg_len, reply, reply_bytes, 0); 782 783 if (ret) { 784 if (read_byte) 785 *read_byte = reply[0]; 786 return reply_bytes; 787 } 788 return -EREMOTEIO; 789 } 790 791