1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 */ 27 #include <drm/drmP.h> 28 #include <drm/radeon_drm.h> 29 #include "radeon.h" 30 31 #include "atom.h" 32 #include "atom-bits.h" 33 #include <drm/drm_dp_helper.h> 34 35 /* move these to drm_dp_helper.c/h */ 36 #define DP_LINK_CONFIGURATION_SIZE 9 37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE 38 39 static char *voltage_names[] = { 40 "0.4V", "0.6V", "0.8V", "1.2V" 41 }; 42 static char *pre_emph_names[] = { 43 "0dB", "3.5dB", "6dB", "9.5dB" 44 }; 45 46 /***** radeon AUX functions *****/ 47 48 /* Atom needs data in little endian format 49 * so swap as appropriate when copying data to 50 * or from atom. Note that atom operates on 51 * dw units. 52 */ 53 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le) 54 { 55 #ifdef __BIG_ENDIAN 56 u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */ 57 u32 *dst32, *src32; 58 int i; 59 60 memcpy(src_tmp, src, num_bytes); 61 src32 = (u32 *)src_tmp; 62 dst32 = (u32 *)dst_tmp; 63 if (to_le) { 64 for (i = 0; i < ((num_bytes + 3) / 4); i++) 65 dst32[i] = cpu_to_le32(src32[i]); 66 memcpy(dst, dst_tmp, num_bytes); 67 } else { 68 u8 dws = num_bytes & ~3; 69 for (i = 0; i < ((num_bytes + 3) / 4); i++) 70 dst32[i] = le32_to_cpu(src32[i]); 71 memcpy(dst, dst_tmp, dws); 72 if (num_bytes % 4) { 73 for (i = 0; i < (num_bytes % 4); i++) 74 dst[dws+i] = dst_tmp[dws+i]; 75 } 76 } 77 #else 78 memcpy(dst, src, num_bytes); 79 #endif 80 } 81 82 union aux_channel_transaction { 83 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; 84 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; 85 }; 86 87 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan, 88 u8 *send, int send_bytes, 89 u8 *recv, int recv_size, 90 u8 delay, u8 *ack) 91 { 92 struct drm_device *dev = chan->dev; 93 struct radeon_device *rdev = dev->dev_private; 94 union aux_channel_transaction args; 95 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); 96 unsigned char *base; 97 int recv_bytes; 98 int r = 0; 99 100 memset(&args, 0, sizeof(args)); 101 102 mutex_lock(&chan->mutex); 103 mutex_lock(&rdev->mode_info.atom_context->scratch_mutex); 104 105 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); 106 107 radeon_atom_copy_swap(base, send, send_bytes, true); 108 109 args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4)); 110 args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4)); 111 args.v1.ucDataOutLen = 0; 112 args.v1.ucChannelID = chan->rec.i2c_id; 113 args.v1.ucDelay = delay / 10; 114 if (ASIC_IS_DCE4(rdev)) 115 args.v2.ucHPD_ID = chan->rec.hpd; 116 117 atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args); 118 119 *ack = args.v1.ucReplyStatus; 120 121 /* timeout */ 122 if (args.v1.ucReplyStatus == 1) { 123 DRM_DEBUG_KMS("dp_aux_ch timeout\n"); 124 r = -ETIMEDOUT; 125 goto done; 126 } 127 128 /* flags not zero */ 129 if (args.v1.ucReplyStatus == 2) { 130 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n"); 131 r = -EIO; 132 goto done; 133 } 134 135 /* error */ 136 if (args.v1.ucReplyStatus == 3) { 137 DRM_DEBUG_KMS("dp_aux_ch error\n"); 138 r = -EIO; 139 goto done; 140 } 141 142 recv_bytes = args.v1.ucDataOutLen; 143 if (recv_bytes > recv_size) 144 recv_bytes = recv_size; 145 146 if (recv && recv_size) 147 radeon_atom_copy_swap(recv, base + 16, recv_bytes, false); 148 149 r = recv_bytes; 150 done: 151 mutex_unlock(&rdev->mode_info.atom_context->scratch_mutex); 152 mutex_unlock(&chan->mutex); 153 154 return r; 155 } 156 157 #define BARE_ADDRESS_SIZE 3 158 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 159 160 static ssize_t 161 radeon_dp_aux_transfer_atom(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 162 { 163 struct radeon_i2c_chan *chan = 164 container_of(aux, struct radeon_i2c_chan, aux); 165 int ret; 166 u8 tx_buf[20]; 167 size_t tx_size; 168 u8 ack, delay = 0; 169 170 if (WARN_ON(msg->size > 16)) 171 return -E2BIG; 172 173 tx_buf[0] = msg->address & 0xff; 174 tx_buf[1] = msg->address >> 8; 175 tx_buf[2] = msg->request << 4; 176 tx_buf[3] = msg->size ? (msg->size - 1) : 0; 177 178 switch (msg->request & ~DP_AUX_I2C_MOT) { 179 case DP_AUX_NATIVE_WRITE: 180 case DP_AUX_I2C_WRITE: 181 /* The atom implementation only supports writes with a max payload of 182 * 12 bytes since it uses 4 bits for the total count (header + payload) 183 * in the parameter space. The atom interface supports 16 byte 184 * payloads for reads. The hw itself supports up to 16 bytes of payload. 185 */ 186 if (WARN_ON_ONCE(msg->size > 12)) 187 return -E2BIG; 188 /* tx_size needs to be 4 even for bare address packets since the atom 189 * table needs the info in tx_buf[3]. 190 */ 191 tx_size = HEADER_SIZE + msg->size; 192 if (msg->size == 0) 193 tx_buf[3] |= BARE_ADDRESS_SIZE << 4; 194 else 195 tx_buf[3] |= tx_size << 4; 196 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size); 197 ret = radeon_process_aux_ch(chan, 198 tx_buf, tx_size, NULL, 0, delay, &ack); 199 if (ret >= 0) 200 /* Return payload size. */ 201 ret = msg->size; 202 break; 203 case DP_AUX_NATIVE_READ: 204 case DP_AUX_I2C_READ: 205 /* tx_size needs to be 4 even for bare address packets since the atom 206 * table needs the info in tx_buf[3]. 207 */ 208 tx_size = HEADER_SIZE; 209 if (msg->size == 0) 210 tx_buf[3] |= BARE_ADDRESS_SIZE << 4; 211 else 212 tx_buf[3] |= tx_size << 4; 213 ret = radeon_process_aux_ch(chan, 214 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack); 215 break; 216 default: 217 ret = -EINVAL; 218 break; 219 } 220 221 if (ret >= 0) 222 msg->reply = ack >> 4; 223 224 return ret; 225 } 226 227 void radeon_dp_aux_init(struct radeon_connector *radeon_connector) 228 { 229 struct drm_device *dev = radeon_connector->base.dev; 230 struct radeon_device *rdev = dev->dev_private; 231 int ret; 232 233 radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd; 234 radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev; 235 if (ASIC_IS_DCE5(rdev)) { 236 if (radeon_auxch) 237 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_native; 238 else 239 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom; 240 } else { 241 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom; 242 } 243 244 ret = drm_dp_aux_register(&radeon_connector->ddc_bus->aux); 245 if (!ret) 246 radeon_connector->ddc_bus->has_aux = true; 247 248 WARN(ret, "drm_dp_aux_register() failed with error %d\n", ret); 249 } 250 251 /***** general DP utility functions *****/ 252 253 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3 254 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3 255 256 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], 257 int lane_count, 258 u8 train_set[4]) 259 { 260 u8 v = 0; 261 u8 p = 0; 262 int lane; 263 264 for (lane = 0; lane < lane_count; lane++) { 265 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 266 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 267 268 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", 269 lane, 270 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 271 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 272 273 if (this_v > v) 274 v = this_v; 275 if (this_p > p) 276 p = this_p; 277 } 278 279 if (v >= DP_VOLTAGE_MAX) 280 v |= DP_TRAIN_MAX_SWING_REACHED; 281 282 if (p >= DP_PRE_EMPHASIS_MAX) 283 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 284 285 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n", 286 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 287 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 288 289 for (lane = 0; lane < 4; lane++) 290 train_set[lane] = v | p; 291 } 292 293 /* convert bits per color to bits per pixel */ 294 /* get bpc from the EDID */ 295 static int convert_bpc_to_bpp(int bpc) 296 { 297 if (bpc == 0) 298 return 24; 299 else 300 return bpc * 3; 301 } 302 303 /* get the max pix clock supported by the link rate and lane num */ 304 static int dp_get_max_dp_pix_clock(int link_rate, 305 int lane_num, 306 int bpp) 307 { 308 return (link_rate * lane_num * 8) / bpp; 309 } 310 311 /***** radeon specific DP functions *****/ 312 313 int radeon_dp_get_max_link_rate(struct drm_connector *connector, 314 u8 dpcd[DP_DPCD_SIZE]) 315 { 316 int max_link_rate; 317 318 if (radeon_connector_is_dp12_capable(connector)) 319 max_link_rate = min(drm_dp_max_link_rate(dpcd), 540000); 320 else 321 max_link_rate = min(drm_dp_max_link_rate(dpcd), 270000); 322 323 return max_link_rate; 324 } 325 326 /* First get the min lane# when low rate is used according to pixel clock 327 * (prefer low rate), second check max lane# supported by DP panel, 328 * if the max lane# < low rate lane# then use max lane# instead. 329 */ 330 static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, 331 u8 dpcd[DP_DPCD_SIZE], 332 int pix_clock) 333 { 334 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); 335 int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd); 336 int max_lane_num = drm_dp_max_lane_count(dpcd); 337 int lane_num; 338 int max_dp_pix_clock; 339 340 for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) { 341 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp); 342 if (pix_clock <= max_dp_pix_clock) 343 break; 344 } 345 346 return lane_num; 347 } 348 349 static int radeon_dp_get_dp_link_clock(struct drm_connector *connector, 350 u8 dpcd[DP_DPCD_SIZE], 351 int pix_clock) 352 { 353 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); 354 int lane_num, max_pix_clock; 355 356 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 357 ENCODER_OBJECT_ID_NUTMEG) 358 return 270000; 359 360 lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock); 361 max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp); 362 if (pix_clock <= max_pix_clock) 363 return 162000; 364 max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp); 365 if (pix_clock <= max_pix_clock) 366 return 270000; 367 if (radeon_connector_is_dp12_capable(connector)) { 368 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp); 369 if (pix_clock <= max_pix_clock) 370 return 540000; 371 } 372 373 return radeon_dp_get_max_link_rate(connector, dpcd); 374 } 375 376 static u8 radeon_dp_encoder_service(struct radeon_device *rdev, 377 int action, int dp_clock, 378 u8 ucconfig, u8 lane_num) 379 { 380 DP_ENCODER_SERVICE_PARAMETERS args; 381 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); 382 383 memset(&args, 0, sizeof(args)); 384 args.ucLinkClock = dp_clock / 10; 385 args.ucConfig = ucconfig; 386 args.ucAction = action; 387 args.ucLaneNum = lane_num; 388 args.ucStatus = 0; 389 390 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 391 return args.ucStatus; 392 } 393 394 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector) 395 { 396 struct drm_device *dev = radeon_connector->base.dev; 397 struct radeon_device *rdev = dev->dev_private; 398 399 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, 400 radeon_connector->ddc_bus->rec.i2c_id, 0); 401 } 402 403 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector) 404 { 405 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 406 u8 buf[3]; 407 408 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 409 return; 410 411 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3) 412 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 413 buf[0], buf[1], buf[2]); 414 415 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3) 416 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 417 buf[0], buf[1], buf[2]); 418 } 419 420 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) 421 { 422 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 423 u8 msg[DP_DPCD_SIZE]; 424 int ret; 425 426 ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg, 427 DP_DPCD_SIZE); 428 if (ret > 0) { 429 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); 430 431 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), 432 dig_connector->dpcd); 433 434 radeon_dp_probe_oui(radeon_connector); 435 436 return true; 437 } 438 dig_connector->dpcd[0] = 0; 439 return false; 440 } 441 442 int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 443 struct drm_connector *connector) 444 { 445 struct drm_device *dev = encoder->dev; 446 struct radeon_device *rdev = dev->dev_private; 447 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 448 struct radeon_connector_atom_dig *dig_connector; 449 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 450 u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector); 451 u8 tmp; 452 453 if (!ASIC_IS_DCE4(rdev)) 454 return panel_mode; 455 456 if (!radeon_connector->con_priv) 457 return panel_mode; 458 459 dig_connector = radeon_connector->con_priv; 460 461 if (dp_bridge != ENCODER_OBJECT_ID_NONE) { 462 /* DP bridge chips */ 463 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, 464 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { 465 if (tmp & 1) 466 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 467 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || 468 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) 469 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; 470 else 471 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 472 } 473 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 474 /* eDP */ 475 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, 476 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { 477 if (tmp & 1) 478 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 479 } 480 } 481 482 return panel_mode; 483 } 484 485 void radeon_dp_set_link_config(struct drm_connector *connector, 486 const struct drm_display_mode *mode) 487 { 488 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 489 struct radeon_connector_atom_dig *dig_connector; 490 491 if (!radeon_connector->con_priv) 492 return; 493 dig_connector = radeon_connector->con_priv; 494 495 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 496 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 497 dig_connector->dp_clock = 498 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); 499 dig_connector->dp_lane_count = 500 radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock); 501 } 502 } 503 504 int radeon_dp_mode_valid_helper(struct drm_connector *connector, 505 struct drm_display_mode *mode) 506 { 507 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 508 struct radeon_connector_atom_dig *dig_connector; 509 int dp_clock; 510 511 if ((mode->clock > 340000) && 512 (!radeon_connector_is_dp12_capable(connector))) 513 return MODE_CLOCK_HIGH; 514 515 if (!radeon_connector->con_priv) 516 return MODE_CLOCK_HIGH; 517 dig_connector = radeon_connector->con_priv; 518 519 dp_clock = 520 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); 521 522 if ((dp_clock == 540000) && 523 (!radeon_connector_is_dp12_capable(connector))) 524 return MODE_CLOCK_HIGH; 525 526 return MODE_OK; 527 } 528 529 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector) 530 { 531 u8 link_status[DP_LINK_STATUS_SIZE]; 532 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 533 534 if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status) 535 <= 0) 536 return false; 537 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count)) 538 return false; 539 return true; 540 } 541 542 void radeon_dp_set_rx_power_state(struct drm_connector *connector, 543 u8 power_state) 544 { 545 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 546 struct radeon_connector_atom_dig *dig_connector; 547 548 if (!radeon_connector->con_priv) 549 return; 550 551 dig_connector = radeon_connector->con_priv; 552 553 /* power up/down the sink */ 554 if (dig_connector->dpcd[0] >= 0x11) { 555 drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux, 556 DP_SET_POWER, power_state); 557 usleep_range(1000, 2000); 558 } 559 } 560 561 562 struct radeon_dp_link_train_info { 563 struct radeon_device *rdev; 564 struct drm_encoder *encoder; 565 struct drm_connector *connector; 566 int enc_id; 567 int dp_clock; 568 int dp_lane_count; 569 bool tp3_supported; 570 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 571 u8 train_set[4]; 572 u8 link_status[DP_LINK_STATUS_SIZE]; 573 u8 tries; 574 bool use_dpencoder; 575 struct drm_dp_aux *aux; 576 }; 577 578 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) 579 { 580 /* set the initial vs/emph on the source */ 581 atombios_dig_transmitter_setup(dp_info->encoder, 582 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, 583 0, dp_info->train_set[0]); /* sets all lanes at once */ 584 585 /* set the vs/emph on the sink */ 586 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET, 587 dp_info->train_set, dp_info->dp_lane_count); 588 } 589 590 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp) 591 { 592 int rtp = 0; 593 594 /* set training pattern on the source */ 595 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) { 596 switch (tp) { 597 case DP_TRAINING_PATTERN_1: 598 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; 599 break; 600 case DP_TRAINING_PATTERN_2: 601 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2; 602 break; 603 case DP_TRAINING_PATTERN_3: 604 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; 605 break; 606 } 607 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0); 608 } else { 609 switch (tp) { 610 case DP_TRAINING_PATTERN_1: 611 rtp = 0; 612 break; 613 case DP_TRAINING_PATTERN_2: 614 rtp = 1; 615 break; 616 } 617 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, 618 dp_info->dp_clock, dp_info->enc_id, rtp); 619 } 620 621 /* enable training pattern on the sink */ 622 drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp); 623 } 624 625 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) 626 { 627 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder); 628 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 629 u8 tmp; 630 631 /* power up the sink */ 632 radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0); 633 634 /* possibly enable downspread on the sink */ 635 if (dp_info->dpcd[3] & 0x1) 636 drm_dp_dpcd_writeb(dp_info->aux, 637 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); 638 else 639 drm_dp_dpcd_writeb(dp_info->aux, 640 DP_DOWNSPREAD_CTRL, 0); 641 642 if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE) 643 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1); 644 645 /* set the lane count on the sink */ 646 tmp = dp_info->dp_lane_count; 647 if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) 648 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 649 drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp); 650 651 /* set the link rate on the sink */ 652 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock); 653 drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp); 654 655 /* start training on the source */ 656 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) 657 atombios_dig_encoder_setup(dp_info->encoder, 658 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0); 659 else 660 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START, 661 dp_info->dp_clock, dp_info->enc_id, 0); 662 663 /* disable the training pattern on the sink */ 664 drm_dp_dpcd_writeb(dp_info->aux, 665 DP_TRAINING_PATTERN_SET, 666 DP_TRAINING_PATTERN_DISABLE); 667 668 return 0; 669 } 670 671 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info) 672 { 673 udelay(400); 674 675 /* disable the training pattern on the sink */ 676 drm_dp_dpcd_writeb(dp_info->aux, 677 DP_TRAINING_PATTERN_SET, 678 DP_TRAINING_PATTERN_DISABLE); 679 680 /* disable the training pattern on the source */ 681 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) 682 atombios_dig_encoder_setup(dp_info->encoder, 683 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0); 684 else 685 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, 686 dp_info->dp_clock, dp_info->enc_id, 0); 687 688 return 0; 689 } 690 691 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info) 692 { 693 bool clock_recovery; 694 u8 voltage; 695 int i; 696 697 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); 698 memset(dp_info->train_set, 0, 4); 699 radeon_dp_update_vs_emph(dp_info); 700 701 udelay(400); 702 703 /* clock recovery loop */ 704 clock_recovery = false; 705 dp_info->tries = 0; 706 voltage = 0xff; 707 while (1) { 708 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); 709 710 if (drm_dp_dpcd_read_link_status(dp_info->aux, 711 dp_info->link_status) <= 0) { 712 DRM_ERROR("displayport link status failed\n"); 713 break; 714 } 715 716 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { 717 clock_recovery = true; 718 break; 719 } 720 721 for (i = 0; i < dp_info->dp_lane_count; i++) { 722 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 723 break; 724 } 725 if (i == dp_info->dp_lane_count) { 726 DRM_ERROR("clock recovery reached max voltage\n"); 727 break; 728 } 729 730 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 731 ++dp_info->tries; 732 if (dp_info->tries == 5) { 733 DRM_ERROR("clock recovery tried 5 times\n"); 734 break; 735 } 736 } else 737 dp_info->tries = 0; 738 739 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 740 741 /* Compute new train_set as requested by sink */ 742 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); 743 744 radeon_dp_update_vs_emph(dp_info); 745 } 746 if (!clock_recovery) { 747 DRM_ERROR("clock recovery failed\n"); 748 return -1; 749 } else { 750 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", 751 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 752 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> 753 DP_TRAIN_PRE_EMPHASIS_SHIFT); 754 return 0; 755 } 756 } 757 758 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) 759 { 760 bool channel_eq; 761 762 if (dp_info->tp3_supported) 763 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3); 764 else 765 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2); 766 767 /* channel equalization loop */ 768 dp_info->tries = 0; 769 channel_eq = false; 770 while (1) { 771 drm_dp_link_train_channel_eq_delay(dp_info->dpcd); 772 773 if (drm_dp_dpcd_read_link_status(dp_info->aux, 774 dp_info->link_status) <= 0) { 775 DRM_ERROR("displayport link status failed\n"); 776 break; 777 } 778 779 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { 780 channel_eq = true; 781 break; 782 } 783 784 /* Try 5 times */ 785 if (dp_info->tries > 5) { 786 DRM_ERROR("channel eq failed: 5 tries\n"); 787 break; 788 } 789 790 /* Compute new train_set as requested by sink */ 791 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); 792 793 radeon_dp_update_vs_emph(dp_info); 794 dp_info->tries++; 795 } 796 797 if (!channel_eq) { 798 DRM_ERROR("channel eq failed\n"); 799 return -1; 800 } else { 801 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", 802 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 803 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) 804 >> DP_TRAIN_PRE_EMPHASIS_SHIFT); 805 return 0; 806 } 807 } 808 809 void radeon_dp_link_train(struct drm_encoder *encoder, 810 struct drm_connector *connector) 811 { 812 struct drm_device *dev = encoder->dev; 813 struct radeon_device *rdev = dev->dev_private; 814 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 815 struct radeon_encoder_atom_dig *dig; 816 struct radeon_connector *radeon_connector; 817 struct radeon_connector_atom_dig *dig_connector; 818 struct radeon_dp_link_train_info dp_info; 819 int index; 820 u8 tmp, frev, crev; 821 822 if (!radeon_encoder->enc_priv) 823 return; 824 dig = radeon_encoder->enc_priv; 825 826 radeon_connector = to_radeon_connector(connector); 827 if (!radeon_connector->con_priv) 828 return; 829 dig_connector = radeon_connector->con_priv; 830 831 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && 832 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) 833 return; 834 835 /* DPEncoderService newer than 1.1 can't program properly the 836 * training pattern. When facing such version use the 837 * DIGXEncoderControl (X== 1 | 2) 838 */ 839 dp_info.use_dpencoder = true; 840 index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); 841 if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) { 842 if (crev > 1) { 843 dp_info.use_dpencoder = false; 844 } 845 } 846 847 dp_info.enc_id = 0; 848 if (dig->dig_encoder) 849 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; 850 else 851 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; 852 if (dig->linkb) 853 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B; 854 else 855 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; 856 857 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp) 858 == 1) { 859 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) 860 dp_info.tp3_supported = true; 861 else 862 dp_info.tp3_supported = false; 863 } else { 864 dp_info.tp3_supported = false; 865 } 866 867 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); 868 dp_info.rdev = rdev; 869 dp_info.encoder = encoder; 870 dp_info.connector = connector; 871 dp_info.dp_lane_count = dig_connector->dp_lane_count; 872 dp_info.dp_clock = dig_connector->dp_clock; 873 dp_info.aux = &radeon_connector->ddc_bus->aux; 874 875 if (radeon_dp_link_train_init(&dp_info)) 876 goto done; 877 if (radeon_dp_link_train_cr(&dp_info)) 878 goto done; 879 if (radeon_dp_link_train_ce(&dp_info)) 880 goto done; 881 done: 882 if (radeon_dp_link_train_finish(&dp_info)) 883 return; 884 } 885