1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_crtc_helper.h> 28 #include <drm/radeon_drm.h> 29 #include <drm/drm_fixed.h> 30 #include "radeon.h" 31 #include "atom.h" 32 #include "atom-bits.h" 33 34 static void atombios_overscan_setup(struct drm_crtc *crtc, 35 struct drm_display_mode *mode, 36 struct drm_display_mode *adjusted_mode) 37 { 38 struct drm_device *dev = crtc->dev; 39 struct radeon_device *rdev = dev->dev_private; 40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 41 SET_CRTC_OVERSCAN_PS_ALLOCATION args; 42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); 43 int a1, a2; 44 45 memset(&args, 0, sizeof(args)); 46 47 args.ucCRTC = radeon_crtc->crtc_id; 48 49 switch (radeon_crtc->rmx_type) { 50 case RMX_CENTER: 51 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 52 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 53 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 54 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 55 break; 56 case RMX_ASPECT: 57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; 58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; 59 60 if (a1 > a2) { 61 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 62 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 63 } else if (a2 > a1) { 64 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 65 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 66 } 67 break; 68 case RMX_FULL: 69 default: 70 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); 71 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); 72 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); 73 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); 74 break; 75 } 76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 77 } 78 79 static void atombios_scaler_setup(struct drm_crtc *crtc) 80 { 81 struct drm_device *dev = crtc->dev; 82 struct radeon_device *rdev = dev->dev_private; 83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 84 ENABLE_SCALER_PS_ALLOCATION args; 85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); 86 struct radeon_encoder *radeon_encoder = 87 to_radeon_encoder(radeon_crtc->encoder); 88 /* fixme - fill in enc_priv for atom dac */ 89 enum radeon_tv_std tv_std = TV_STD_NTSC; 90 bool is_tv = false, is_cv = false; 91 92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) 93 return; 94 95 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 96 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 97 tv_std = tv_dac->tv_std; 98 is_tv = true; 99 } 100 101 memset(&args, 0, sizeof(args)); 102 103 args.ucScaler = radeon_crtc->crtc_id; 104 105 if (is_tv) { 106 switch (tv_std) { 107 case TV_STD_NTSC: 108 default: 109 args.ucTVStandard = ATOM_TV_NTSC; 110 break; 111 case TV_STD_PAL: 112 args.ucTVStandard = ATOM_TV_PAL; 113 break; 114 case TV_STD_PAL_M: 115 args.ucTVStandard = ATOM_TV_PALM; 116 break; 117 case TV_STD_PAL_60: 118 args.ucTVStandard = ATOM_TV_PAL60; 119 break; 120 case TV_STD_NTSC_J: 121 args.ucTVStandard = ATOM_TV_NTSCJ; 122 break; 123 case TV_STD_SCART_PAL: 124 args.ucTVStandard = ATOM_TV_PAL; /* ??? */ 125 break; 126 case TV_STD_SECAM: 127 args.ucTVStandard = ATOM_TV_SECAM; 128 break; 129 case TV_STD_PAL_CN: 130 args.ucTVStandard = ATOM_TV_PALCN; 131 break; 132 } 133 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 134 } else if (is_cv) { 135 args.ucTVStandard = ATOM_TV_CV; 136 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 137 } else { 138 switch (radeon_crtc->rmx_type) { 139 case RMX_FULL: 140 args.ucEnable = ATOM_SCALER_EXPANSION; 141 break; 142 case RMX_CENTER: 143 args.ucEnable = ATOM_SCALER_CENTER; 144 break; 145 case RMX_ASPECT: 146 args.ucEnable = ATOM_SCALER_EXPANSION; 147 break; 148 default: 149 if (ASIC_IS_AVIVO(rdev)) 150 args.ucEnable = ATOM_SCALER_DISABLE; 151 else 152 args.ucEnable = ATOM_SCALER_CENTER; 153 break; 154 } 155 } 156 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 157 if ((is_tv || is_cv) 158 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { 159 atom_rv515_force_tv_scaler(rdev, radeon_crtc); 160 } 161 } 162 163 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) 164 { 165 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 166 struct drm_device *dev = crtc->dev; 167 struct radeon_device *rdev = dev->dev_private; 168 int index = 169 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); 170 ENABLE_CRTC_PS_ALLOCATION args; 171 172 memset(&args, 0, sizeof(args)); 173 174 args.ucCRTC = radeon_crtc->crtc_id; 175 args.ucEnable = lock; 176 177 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 178 } 179 180 static void atombios_enable_crtc(struct drm_crtc *crtc, int state) 181 { 182 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 183 struct drm_device *dev = crtc->dev; 184 struct radeon_device *rdev = dev->dev_private; 185 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); 186 ENABLE_CRTC_PS_ALLOCATION args; 187 188 memset(&args, 0, sizeof(args)); 189 190 args.ucCRTC = radeon_crtc->crtc_id; 191 args.ucEnable = state; 192 193 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 194 } 195 196 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) 197 { 198 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 199 struct drm_device *dev = crtc->dev; 200 struct radeon_device *rdev = dev->dev_private; 201 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); 202 ENABLE_CRTC_PS_ALLOCATION args; 203 204 memset(&args, 0, sizeof(args)); 205 206 args.ucCRTC = radeon_crtc->crtc_id; 207 args.ucEnable = state; 208 209 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 210 } 211 212 static void atombios_blank_crtc(struct drm_crtc *crtc, int state) 213 { 214 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 215 struct drm_device *dev = crtc->dev; 216 struct radeon_device *rdev = dev->dev_private; 217 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); 218 BLANK_CRTC_PS_ALLOCATION args; 219 220 memset(&args, 0, sizeof(args)); 221 222 args.ucCRTC = radeon_crtc->crtc_id; 223 args.ucBlanking = state; 224 225 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 226 } 227 228 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state) 229 { 230 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 231 struct drm_device *dev = crtc->dev; 232 struct radeon_device *rdev = dev->dev_private; 233 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating); 234 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args; 235 236 memset(&args, 0, sizeof(args)); 237 238 args.ucDispPipeId = radeon_crtc->crtc_id; 239 args.ucEnable = state; 240 241 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 242 } 243 244 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) 245 { 246 struct drm_device *dev = crtc->dev; 247 struct radeon_device *rdev = dev->dev_private; 248 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 249 250 switch (mode) { 251 case DRM_MODE_DPMS_ON: 252 radeon_crtc->enabled = true; 253 /* adjust pm to dpms changes BEFORE enabling crtcs */ 254 radeon_pm_compute_clocks(rdev); 255 atombios_enable_crtc(crtc, ATOM_ENABLE); 256 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) 257 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); 258 atombios_blank_crtc(crtc, ATOM_DISABLE); 259 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); 260 radeon_crtc_load_lut(crtc); 261 break; 262 case DRM_MODE_DPMS_STANDBY: 263 case DRM_MODE_DPMS_SUSPEND: 264 case DRM_MODE_DPMS_OFF: 265 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); 266 if (radeon_crtc->enabled) 267 atombios_blank_crtc(crtc, ATOM_ENABLE); 268 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) 269 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); 270 atombios_enable_crtc(crtc, ATOM_DISABLE); 271 radeon_crtc->enabled = false; 272 /* adjust pm to dpms changes AFTER disabling crtcs */ 273 radeon_pm_compute_clocks(rdev); 274 break; 275 } 276 } 277 278 static void 279 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, 280 struct drm_display_mode *mode) 281 { 282 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 283 struct drm_device *dev = crtc->dev; 284 struct radeon_device *rdev = dev->dev_private; 285 SET_CRTC_USING_DTD_TIMING_PARAMETERS args; 286 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); 287 u16 misc = 0; 288 289 memset(&args, 0, sizeof(args)); 290 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); 291 args.usH_Blanking_Time = 292 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); 293 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); 294 args.usV_Blanking_Time = 295 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); 296 args.usH_SyncOffset = 297 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); 298 args.usH_SyncWidth = 299 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 300 args.usV_SyncOffset = 301 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); 302 args.usV_SyncWidth = 303 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 304 args.ucH_Border = radeon_crtc->h_border; 305 args.ucV_Border = radeon_crtc->v_border; 306 307 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 308 misc |= ATOM_VSYNC_POLARITY; 309 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 310 misc |= ATOM_HSYNC_POLARITY; 311 if (mode->flags & DRM_MODE_FLAG_CSYNC) 312 misc |= ATOM_COMPOSITESYNC; 313 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 314 misc |= ATOM_INTERLACE; 315 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 316 misc |= ATOM_DOUBLE_CLOCK_MODE; 317 318 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 319 args.ucCRTC = radeon_crtc->crtc_id; 320 321 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 322 } 323 324 static void atombios_crtc_set_timing(struct drm_crtc *crtc, 325 struct drm_display_mode *mode) 326 { 327 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 328 struct drm_device *dev = crtc->dev; 329 struct radeon_device *rdev = dev->dev_private; 330 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; 331 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); 332 u16 misc = 0; 333 334 memset(&args, 0, sizeof(args)); 335 args.usH_Total = cpu_to_le16(mode->crtc_htotal); 336 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); 337 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); 338 args.usH_SyncWidth = 339 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 340 args.usV_Total = cpu_to_le16(mode->crtc_vtotal); 341 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); 342 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); 343 args.usV_SyncWidth = 344 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 345 346 args.ucOverscanRight = radeon_crtc->h_border; 347 args.ucOverscanLeft = radeon_crtc->h_border; 348 args.ucOverscanBottom = radeon_crtc->v_border; 349 args.ucOverscanTop = radeon_crtc->v_border; 350 351 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 352 misc |= ATOM_VSYNC_POLARITY; 353 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 354 misc |= ATOM_HSYNC_POLARITY; 355 if (mode->flags & DRM_MODE_FLAG_CSYNC) 356 misc |= ATOM_COMPOSITESYNC; 357 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 358 misc |= ATOM_INTERLACE; 359 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 360 misc |= ATOM_DOUBLE_CLOCK_MODE; 361 362 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 363 args.ucCRTC = radeon_crtc->crtc_id; 364 365 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 366 } 367 368 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id) 369 { 370 u32 ss_cntl; 371 372 if (ASIC_IS_DCE4(rdev)) { 373 switch (pll_id) { 374 case ATOM_PPLL1: 375 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); 376 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 377 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl); 378 break; 379 case ATOM_PPLL2: 380 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL); 381 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 382 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl); 383 break; 384 case ATOM_DCPLL: 385 case ATOM_PPLL_INVALID: 386 return; 387 } 388 } else if (ASIC_IS_AVIVO(rdev)) { 389 switch (pll_id) { 390 case ATOM_PPLL1: 391 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); 392 ss_cntl &= ~1; 393 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl); 394 break; 395 case ATOM_PPLL2: 396 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); 397 ss_cntl &= ~1; 398 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl); 399 break; 400 case ATOM_DCPLL: 401 case ATOM_PPLL_INVALID: 402 return; 403 } 404 } 405 } 406 407 408 union atom_enable_ss { 409 ENABLE_LVDS_SS_PARAMETERS lvds_ss; 410 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2; 411 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; 412 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2; 413 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; 414 }; 415 416 static void atombios_crtc_program_ss(struct radeon_device *rdev, 417 int enable, 418 int pll_id, 419 int crtc_id, 420 struct radeon_atom_ss *ss) 421 { 422 unsigned i; 423 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); 424 union atom_enable_ss args; 425 426 if (!enable) { 427 for (i = 0; i < rdev->num_crtc; i++) { 428 if (rdev->mode_info.crtcs[i] && 429 rdev->mode_info.crtcs[i]->enabled && 430 i != crtc_id && 431 pll_id == rdev->mode_info.crtcs[i]->pll_id) { 432 /* one other crtc is using this pll don't turn 433 * off spread spectrum as it might turn off 434 * display on active crtc 435 */ 436 return; 437 } 438 } 439 } 440 441 memset(&args, 0, sizeof(args)); 442 443 if (ASIC_IS_DCE5(rdev)) { 444 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); 445 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 446 switch (pll_id) { 447 case ATOM_PPLL1: 448 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; 449 break; 450 case ATOM_PPLL2: 451 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; 452 break; 453 case ATOM_DCPLL: 454 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; 455 break; 456 case ATOM_PPLL_INVALID: 457 return; 458 } 459 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 460 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); 461 args.v3.ucEnable = enable; 462 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE61(rdev)) 463 args.v3.ucEnable = ATOM_DISABLE; 464 } else if (ASIC_IS_DCE4(rdev)) { 465 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 466 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 467 switch (pll_id) { 468 case ATOM_PPLL1: 469 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL; 470 break; 471 case ATOM_PPLL2: 472 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL; 473 break; 474 case ATOM_DCPLL: 475 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL; 476 break; 477 case ATOM_PPLL_INVALID: 478 return; 479 } 480 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 481 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); 482 args.v2.ucEnable = enable; 483 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev)) 484 args.v2.ucEnable = ATOM_DISABLE; 485 } else if (ASIC_IS_DCE3(rdev)) { 486 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 487 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 488 args.v1.ucSpreadSpectrumStep = ss->step; 489 args.v1.ucSpreadSpectrumDelay = ss->delay; 490 args.v1.ucSpreadSpectrumRange = ss->range; 491 args.v1.ucPpll = pll_id; 492 args.v1.ucEnable = enable; 493 } else if (ASIC_IS_AVIVO(rdev)) { 494 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || 495 (ss->type & ATOM_EXTERNAL_SS_MASK)) { 496 atombios_disable_ss(rdev, pll_id); 497 return; 498 } 499 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 500 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 501 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; 502 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; 503 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; 504 args.lvds_ss_2.ucEnable = enable; 505 } else { 506 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || 507 (ss->type & ATOM_EXTERNAL_SS_MASK)) { 508 atombios_disable_ss(rdev, pll_id); 509 return; 510 } 511 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 512 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 513 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; 514 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; 515 args.lvds_ss.ucEnable = enable; 516 } 517 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 518 } 519 520 union adjust_pixel_clock { 521 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; 522 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; 523 }; 524 525 static u32 atombios_adjust_pll(struct drm_crtc *crtc, 526 struct drm_display_mode *mode) 527 { 528 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 529 struct drm_device *dev = crtc->dev; 530 struct radeon_device *rdev = dev->dev_private; 531 struct drm_encoder *encoder = radeon_crtc->encoder; 532 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 533 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 534 u32 adjusted_clock = mode->clock; 535 int encoder_mode = atombios_get_encoder_mode(encoder); 536 u32 dp_clock = mode->clock; 537 int bpc = radeon_get_monitor_bpc(connector); 538 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); 539 540 /* reset the pll flags */ 541 radeon_crtc->pll_flags = 0; 542 543 if (ASIC_IS_AVIVO(rdev)) { 544 if ((rdev->family == CHIP_RS600) || 545 (rdev->family == CHIP_RS690) || 546 (rdev->family == CHIP_RS740)) 547 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ 548 RADEON_PLL_PREFER_CLOSEST_LOWER); 549 550 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ 551 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 552 else 553 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 554 555 if (rdev->family < CHIP_RV770) 556 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; 557 /* use frac fb div on APUs */ 558 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev)) 559 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 560 /* use frac fb div on RS780/RS880 */ 561 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) 562 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 563 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000) 564 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 565 } else { 566 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY; 567 568 if (mode->clock > 200000) /* range limits??? */ 569 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 570 else 571 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 572 } 573 574 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || 575 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { 576 if (connector) { 577 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 578 struct radeon_connector_atom_dig *dig_connector = 579 radeon_connector->con_priv; 580 581 dp_clock = dig_connector->dp_clock; 582 } 583 } 584 585 /* use recommended ref_div for ss */ 586 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 587 if (radeon_crtc->ss_enabled) { 588 if (radeon_crtc->ss.refdiv) { 589 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 590 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; 591 if (ASIC_IS_AVIVO(rdev)) 592 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 593 } 594 } 595 } 596 597 if (ASIC_IS_AVIVO(rdev)) { 598 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ 599 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) 600 adjusted_clock = mode->clock * 2; 601 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 602 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; 603 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 604 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD; 605 } else { 606 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 607 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; 608 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) 609 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 610 } 611 612 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock 613 * accordingly based on the encoder/transmitter to work around 614 * special hw requirements. 615 */ 616 if (ASIC_IS_DCE3(rdev)) { 617 union adjust_pixel_clock args; 618 u8 frev, crev; 619 int index; 620 621 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); 622 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 623 &crev)) 624 return adjusted_clock; 625 626 memset(&args, 0, sizeof(args)); 627 628 switch (frev) { 629 case 1: 630 switch (crev) { 631 case 1: 632 case 2: 633 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); 634 args.v1.ucTransmitterID = radeon_encoder->encoder_id; 635 args.v1.ucEncodeMode = encoder_mode; 636 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) 637 args.v1.ucConfig |= 638 ADJUST_DISPLAY_CONFIG_SS_ENABLE; 639 640 atom_execute_table(rdev->mode_info.atom_context, 641 index, (uint32_t *)&args); 642 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; 643 break; 644 case 3: 645 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10); 646 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; 647 args.v3.sInput.ucEncodeMode = encoder_mode; 648 args.v3.sInput.ucDispPllConfig = 0; 649 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) 650 args.v3.sInput.ucDispPllConfig |= 651 DISPPLL_CONFIG_SS_ENABLE; 652 if (ENCODER_MODE_IS_DP(encoder_mode)) { 653 args.v3.sInput.ucDispPllConfig |= 654 DISPPLL_CONFIG_COHERENT_MODE; 655 /* 16200 or 27000 */ 656 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); 657 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 658 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 659 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) 660 /* deep color support */ 661 args.v3.sInput.usPixelClock = 662 cpu_to_le16((mode->clock * bpc / 8) / 10); 663 if (dig->coherent_mode) 664 args.v3.sInput.ucDispPllConfig |= 665 DISPPLL_CONFIG_COHERENT_MODE; 666 if (is_duallink) 667 args.v3.sInput.ucDispPllConfig |= 668 DISPPLL_CONFIG_DUAL_LINK; 669 } 670 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 671 ENCODER_OBJECT_ID_NONE) 672 args.v3.sInput.ucExtTransmitterID = 673 radeon_encoder_get_dp_bridge_encoder_id(encoder); 674 else 675 args.v3.sInput.ucExtTransmitterID = 0; 676 677 atom_execute_table(rdev->mode_info.atom_context, 678 index, (uint32_t *)&args); 679 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; 680 if (args.v3.sOutput.ucRefDiv) { 681 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 682 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 683 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; 684 } 685 if (args.v3.sOutput.ucPostDiv) { 686 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 687 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV; 688 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; 689 } 690 break; 691 default: 692 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 693 return adjusted_clock; 694 } 695 break; 696 default: 697 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 698 return adjusted_clock; 699 } 700 } 701 return adjusted_clock; 702 } 703 704 union set_pixel_clock { 705 SET_PIXEL_CLOCK_PS_ALLOCATION base; 706 PIXEL_CLOCK_PARAMETERS v1; 707 PIXEL_CLOCK_PARAMETERS_V2 v2; 708 PIXEL_CLOCK_PARAMETERS_V3 v3; 709 PIXEL_CLOCK_PARAMETERS_V5 v5; 710 PIXEL_CLOCK_PARAMETERS_V6 v6; 711 }; 712 713 /* on DCE5, make sure the voltage is high enough to support the 714 * required disp clk. 715 */ 716 static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev, 717 u32 dispclk) 718 { 719 u8 frev, crev; 720 int index; 721 union set_pixel_clock args; 722 723 memset(&args, 0, sizeof(args)); 724 725 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 726 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 727 &crev)) 728 return; 729 730 switch (frev) { 731 case 1: 732 switch (crev) { 733 case 5: 734 /* if the default dcpll clock is specified, 735 * SetPixelClock provides the dividers 736 */ 737 args.v5.ucCRTC = ATOM_CRTC_INVALID; 738 args.v5.usPixelClock = cpu_to_le16(dispclk); 739 args.v5.ucPpll = ATOM_DCPLL; 740 break; 741 case 6: 742 /* if the default dcpll clock is specified, 743 * SetPixelClock provides the dividers 744 */ 745 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); 746 if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev)) 747 args.v6.ucPpll = ATOM_EXT_PLL1; 748 else if (ASIC_IS_DCE6(rdev)) 749 args.v6.ucPpll = ATOM_PPLL0; 750 else 751 args.v6.ucPpll = ATOM_DCPLL; 752 break; 753 default: 754 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 755 return; 756 } 757 break; 758 default: 759 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 760 return; 761 } 762 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 763 } 764 765 static void atombios_crtc_program_pll(struct drm_crtc *crtc, 766 u32 crtc_id, 767 int pll_id, 768 u32 encoder_mode, 769 u32 encoder_id, 770 u32 clock, 771 u32 ref_div, 772 u32 fb_div, 773 u32 frac_fb_div, 774 u32 post_div, 775 int bpc, 776 bool ss_enabled, 777 struct radeon_atom_ss *ss) 778 { 779 struct drm_device *dev = crtc->dev; 780 struct radeon_device *rdev = dev->dev_private; 781 u8 frev, crev; 782 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 783 union set_pixel_clock args; 784 785 memset(&args, 0, sizeof(args)); 786 787 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 788 &crev)) 789 return; 790 791 switch (frev) { 792 case 1: 793 switch (crev) { 794 case 1: 795 if (clock == ATOM_DISABLE) 796 return; 797 args.v1.usPixelClock = cpu_to_le16(clock / 10); 798 args.v1.usRefDiv = cpu_to_le16(ref_div); 799 args.v1.usFbDiv = cpu_to_le16(fb_div); 800 args.v1.ucFracFbDiv = frac_fb_div; 801 args.v1.ucPostDiv = post_div; 802 args.v1.ucPpll = pll_id; 803 args.v1.ucCRTC = crtc_id; 804 args.v1.ucRefDivSrc = 1; 805 break; 806 case 2: 807 args.v2.usPixelClock = cpu_to_le16(clock / 10); 808 args.v2.usRefDiv = cpu_to_le16(ref_div); 809 args.v2.usFbDiv = cpu_to_le16(fb_div); 810 args.v2.ucFracFbDiv = frac_fb_div; 811 args.v2.ucPostDiv = post_div; 812 args.v2.ucPpll = pll_id; 813 args.v2.ucCRTC = crtc_id; 814 args.v2.ucRefDivSrc = 1; 815 break; 816 case 3: 817 args.v3.usPixelClock = cpu_to_le16(clock / 10); 818 args.v3.usRefDiv = cpu_to_le16(ref_div); 819 args.v3.usFbDiv = cpu_to_le16(fb_div); 820 args.v3.ucFracFbDiv = frac_fb_div; 821 args.v3.ucPostDiv = post_div; 822 args.v3.ucPpll = pll_id; 823 if (crtc_id == ATOM_CRTC2) 824 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2; 825 else 826 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1; 827 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 828 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; 829 args.v3.ucTransmitterId = encoder_id; 830 args.v3.ucEncoderMode = encoder_mode; 831 break; 832 case 5: 833 args.v5.ucCRTC = crtc_id; 834 args.v5.usPixelClock = cpu_to_le16(clock / 10); 835 args.v5.ucRefDiv = ref_div; 836 args.v5.usFbDiv = cpu_to_le16(fb_div); 837 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 838 args.v5.ucPostDiv = post_div; 839 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ 840 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 841 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; 842 switch (bpc) { 843 case 8: 844 default: 845 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; 846 break; 847 case 10: 848 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; 849 break; 850 } 851 args.v5.ucTransmitterID = encoder_id; 852 args.v5.ucEncoderMode = encoder_mode; 853 args.v5.ucPpll = pll_id; 854 break; 855 case 6: 856 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10); 857 args.v6.ucRefDiv = ref_div; 858 args.v6.usFbDiv = cpu_to_le16(fb_div); 859 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 860 args.v6.ucPostDiv = post_div; 861 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ 862 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 863 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; 864 switch (bpc) { 865 case 8: 866 default: 867 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; 868 break; 869 case 10: 870 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP; 871 break; 872 case 12: 873 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP; 874 break; 875 case 16: 876 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; 877 break; 878 } 879 args.v6.ucTransmitterID = encoder_id; 880 args.v6.ucEncoderMode = encoder_mode; 881 args.v6.ucPpll = pll_id; 882 break; 883 default: 884 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 885 return; 886 } 887 break; 888 default: 889 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 890 return; 891 } 892 893 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 894 } 895 896 static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 897 { 898 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 899 struct drm_device *dev = crtc->dev; 900 struct radeon_device *rdev = dev->dev_private; 901 struct radeon_encoder *radeon_encoder = 902 to_radeon_encoder(radeon_crtc->encoder); 903 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); 904 905 radeon_crtc->bpc = 8; 906 radeon_crtc->ss_enabled = false; 907 908 if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || 909 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { 910 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 911 struct drm_connector *connector = 912 radeon_get_connector_for_encoder(radeon_crtc->encoder); 913 struct radeon_connector *radeon_connector = 914 to_radeon_connector(connector); 915 struct radeon_connector_atom_dig *dig_connector = 916 radeon_connector->con_priv; 917 int dp_clock; 918 radeon_crtc->bpc = radeon_get_monitor_bpc(connector); 919 920 switch (encoder_mode) { 921 case ATOM_ENCODER_MODE_DP_MST: 922 case ATOM_ENCODER_MODE_DP: 923 /* DP/eDP */ 924 dp_clock = dig_connector->dp_clock / 10; 925 if (ASIC_IS_DCE4(rdev)) 926 radeon_crtc->ss_enabled = 927 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, 928 ASIC_INTERNAL_SS_ON_DP, 929 dp_clock); 930 else { 931 if (dp_clock == 16200) { 932 radeon_crtc->ss_enabled = 933 radeon_atombios_get_ppll_ss_info(rdev, 934 &radeon_crtc->ss, 935 ATOM_DP_SS_ID2); 936 if (!radeon_crtc->ss_enabled) 937 radeon_crtc->ss_enabled = 938 radeon_atombios_get_ppll_ss_info(rdev, 939 &radeon_crtc->ss, 940 ATOM_DP_SS_ID1); 941 } else 942 radeon_crtc->ss_enabled = 943 radeon_atombios_get_ppll_ss_info(rdev, 944 &radeon_crtc->ss, 945 ATOM_DP_SS_ID1); 946 } 947 break; 948 case ATOM_ENCODER_MODE_LVDS: 949 if (ASIC_IS_DCE4(rdev)) 950 radeon_crtc->ss_enabled = 951 radeon_atombios_get_asic_ss_info(rdev, 952 &radeon_crtc->ss, 953 dig->lcd_ss_id, 954 mode->clock / 10); 955 else 956 radeon_crtc->ss_enabled = 957 radeon_atombios_get_ppll_ss_info(rdev, 958 &radeon_crtc->ss, 959 dig->lcd_ss_id); 960 break; 961 case ATOM_ENCODER_MODE_DVI: 962 if (ASIC_IS_DCE4(rdev)) 963 radeon_crtc->ss_enabled = 964 radeon_atombios_get_asic_ss_info(rdev, 965 &radeon_crtc->ss, 966 ASIC_INTERNAL_SS_ON_TMDS, 967 mode->clock / 10); 968 break; 969 case ATOM_ENCODER_MODE_HDMI: 970 if (ASIC_IS_DCE4(rdev)) 971 radeon_crtc->ss_enabled = 972 radeon_atombios_get_asic_ss_info(rdev, 973 &radeon_crtc->ss, 974 ASIC_INTERNAL_SS_ON_HDMI, 975 mode->clock / 10); 976 break; 977 default: 978 break; 979 } 980 } 981 982 /* adjust pixel clock as needed */ 983 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode); 984 985 return true; 986 } 987 988 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 989 { 990 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 991 struct drm_device *dev = crtc->dev; 992 struct radeon_device *rdev = dev->dev_private; 993 struct radeon_encoder *radeon_encoder = 994 to_radeon_encoder(radeon_crtc->encoder); 995 u32 pll_clock = mode->clock; 996 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; 997 struct radeon_pll *pll; 998 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); 999 1000 switch (radeon_crtc->pll_id) { 1001 case ATOM_PPLL1: 1002 pll = &rdev->clock.p1pll; 1003 break; 1004 case ATOM_PPLL2: 1005 pll = &rdev->clock.p2pll; 1006 break; 1007 case ATOM_DCPLL: 1008 case ATOM_PPLL_INVALID: 1009 default: 1010 pll = &rdev->clock.dcpll; 1011 break; 1012 } 1013 1014 /* update pll params */ 1015 pll->flags = radeon_crtc->pll_flags; 1016 pll->reference_div = radeon_crtc->pll_reference_div; 1017 pll->post_div = radeon_crtc->pll_post_div; 1018 1019 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1020 /* TV seems to prefer the legacy algo on some boards */ 1021 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, 1022 &fb_div, &frac_fb_div, &ref_div, &post_div); 1023 else if (ASIC_IS_AVIVO(rdev)) 1024 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, 1025 &fb_div, &frac_fb_div, &ref_div, &post_div); 1026 else 1027 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, 1028 &fb_div, &frac_fb_div, &ref_div, &post_div); 1029 1030 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, 1031 radeon_crtc->crtc_id, &radeon_crtc->ss); 1032 1033 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 1034 encoder_mode, radeon_encoder->encoder_id, mode->clock, 1035 ref_div, fb_div, frac_fb_div, post_div, 1036 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss); 1037 1038 if (radeon_crtc->ss_enabled) { 1039 /* calculate ss amount and step size */ 1040 if (ASIC_IS_DCE4(rdev)) { 1041 u32 step_size; 1042 u32 amount = (((fb_div * 10) + frac_fb_div) * radeon_crtc->ss.percentage) / 10000; 1043 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; 1044 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & 1045 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK; 1046 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) 1047 step_size = (4 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) / 1048 (125 * 25 * pll->reference_freq / 100); 1049 else 1050 step_size = (2 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) / 1051 (125 * 25 * pll->reference_freq / 100); 1052 radeon_crtc->ss.step = step_size; 1053 } 1054 1055 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, 1056 radeon_crtc->crtc_id, &radeon_crtc->ss); 1057 } 1058 } 1059 1060 static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 1061 struct drm_framebuffer *fb, 1062 int x, int y, int atomic) 1063 { 1064 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1065 struct drm_device *dev = crtc->dev; 1066 struct radeon_device *rdev = dev->dev_private; 1067 struct radeon_framebuffer *radeon_fb; 1068 struct drm_framebuffer *target_fb; 1069 struct drm_gem_object *obj; 1070 struct radeon_bo *rbo; 1071 uint64_t fb_location; 1072 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1073 unsigned bankw, bankh, mtaspect, tile_split; 1074 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); 1075 u32 tmp, viewport_w, viewport_h; 1076 int r; 1077 1078 /* no fb bound */ 1079 if (!atomic && !crtc->fb) { 1080 DRM_DEBUG_KMS("No FB bound\n"); 1081 return 0; 1082 } 1083 1084 if (atomic) { 1085 radeon_fb = to_radeon_framebuffer(fb); 1086 target_fb = fb; 1087 } 1088 else { 1089 radeon_fb = to_radeon_framebuffer(crtc->fb); 1090 target_fb = crtc->fb; 1091 } 1092 1093 /* If atomic, assume fb object is pinned & idle & fenced and 1094 * just update base pointers 1095 */ 1096 obj = radeon_fb->obj; 1097 rbo = gem_to_radeon_bo(obj); 1098 r = radeon_bo_reserve(rbo, false); 1099 if (unlikely(r != 0)) 1100 return r; 1101 1102 if (atomic) 1103 fb_location = radeon_bo_gpu_offset(rbo); 1104 else { 1105 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); 1106 if (unlikely(r != 0)) { 1107 radeon_bo_unreserve(rbo); 1108 return -EINVAL; 1109 } 1110 } 1111 1112 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1113 radeon_bo_unreserve(rbo); 1114 1115 switch (target_fb->bits_per_pixel) { 1116 case 8: 1117 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | 1118 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); 1119 break; 1120 case 15: 1121 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1122 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); 1123 break; 1124 case 16: 1125 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1126 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); 1127 #ifdef __BIG_ENDIAN 1128 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1129 #endif 1130 break; 1131 case 24: 1132 case 32: 1133 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1134 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); 1135 #ifdef __BIG_ENDIAN 1136 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1137 #endif 1138 break; 1139 default: 1140 DRM_ERROR("Unsupported screen depth %d\n", 1141 target_fb->bits_per_pixel); 1142 return -EINVAL; 1143 } 1144 1145 if (tiling_flags & RADEON_TILING_MACRO) { 1146 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); 1147 1148 /* Set NUM_BANKS. */ 1149 if (rdev->family >= CHIP_BONAIRE) { 1150 unsigned tileb, index, num_banks, tile_split_bytes; 1151 1152 /* Calculate the macrotile mode index. */ 1153 tile_split_bytes = 64 << tile_split; 1154 tileb = 8 * 8 * target_fb->bits_per_pixel / 8; 1155 tileb = min(tile_split_bytes, tileb); 1156 1157 for (index = 0; tileb > 64; index++) { 1158 tileb >>= 1; 1159 } 1160 1161 if (index >= 16) { 1162 DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n", 1163 target_fb->bits_per_pixel, tile_split); 1164 return -EINVAL; 1165 } 1166 1167 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; 1168 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks); 1169 } else { 1170 /* SI and older. */ 1171 if (rdev->family >= CHIP_TAHITI) 1172 tmp = rdev->config.si.tile_config; 1173 else if (rdev->family >= CHIP_CAYMAN) 1174 tmp = rdev->config.cayman.tile_config; 1175 else 1176 tmp = rdev->config.evergreen.tile_config; 1177 1178 switch ((tmp & 0xf0) >> 4) { 1179 case 0: /* 4 banks */ 1180 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK); 1181 break; 1182 case 1: /* 8 banks */ 1183 default: 1184 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK); 1185 break; 1186 case 2: /* 16 banks */ 1187 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK); 1188 break; 1189 } 1190 } 1191 1192 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); 1193 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split); 1194 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); 1195 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh); 1196 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); 1197 if (rdev->family >= CHIP_BONAIRE) { 1198 /* XXX need to know more about the surface tiling mode */ 1199 fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING); 1200 } 1201 } else if (tiling_flags & RADEON_TILING_MICRO) 1202 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); 1203 1204 if (rdev->family >= CHIP_BONAIRE) { 1205 /* Read the pipe config from the 2D TILED SCANOUT mode. 1206 * It should be the same for the other modes too, but not all 1207 * modes set the pipe config field. */ 1208 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f; 1209 1210 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config); 1211 } else if ((rdev->family == CHIP_TAHITI) || 1212 (rdev->family == CHIP_PITCAIRN)) 1213 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16); 1214 else if ((rdev->family == CHIP_VERDE) || 1215 (rdev->family == CHIP_OLAND) || 1216 (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */ 1217 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16); 1218 1219 switch (radeon_crtc->crtc_id) { 1220 case 0: 1221 WREG32(AVIVO_D1VGA_CONTROL, 0); 1222 break; 1223 case 1: 1224 WREG32(AVIVO_D2VGA_CONTROL, 0); 1225 break; 1226 case 2: 1227 WREG32(EVERGREEN_D3VGA_CONTROL, 0); 1228 break; 1229 case 3: 1230 WREG32(EVERGREEN_D4VGA_CONTROL, 0); 1231 break; 1232 case 4: 1233 WREG32(EVERGREEN_D5VGA_CONTROL, 0); 1234 break; 1235 case 5: 1236 WREG32(EVERGREEN_D6VGA_CONTROL, 0); 1237 break; 1238 default: 1239 break; 1240 } 1241 1242 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 1243 upper_32_bits(fb_location)); 1244 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 1245 upper_32_bits(fb_location)); 1246 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1247 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1248 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1249 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1250 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1251 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1252 1253 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1254 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1255 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); 1256 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); 1257 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); 1258 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); 1259 1260 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 1261 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 1262 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1263 1264 if (rdev->family >= CHIP_BONAIRE) 1265 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1266 target_fb->height); 1267 else 1268 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1269 target_fb->height); 1270 x &= ~3; 1271 y &= ~1; 1272 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, 1273 (x << 16) | y); 1274 viewport_w = crtc->mode.hdisplay; 1275 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1276 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1277 (viewport_w << 16) | viewport_h); 1278 1279 /* pageflip setup */ 1280 /* make sure flip is at vb rather than hb */ 1281 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); 1282 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN; 1283 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); 1284 1285 /* set pageflip to happen anywhere in vblank interval */ 1286 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); 1287 1288 if (!atomic && fb && fb != crtc->fb) { 1289 radeon_fb = to_radeon_framebuffer(fb); 1290 rbo = gem_to_radeon_bo(radeon_fb->obj); 1291 r = radeon_bo_reserve(rbo, false); 1292 if (unlikely(r != 0)) 1293 return r; 1294 radeon_bo_unpin(rbo); 1295 radeon_bo_unreserve(rbo); 1296 } 1297 1298 /* Bytes per pixel may have changed */ 1299 radeon_bandwidth_update(rdev); 1300 1301 return 0; 1302 } 1303 1304 static int avivo_crtc_do_set_base(struct drm_crtc *crtc, 1305 struct drm_framebuffer *fb, 1306 int x, int y, int atomic) 1307 { 1308 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1309 struct drm_device *dev = crtc->dev; 1310 struct radeon_device *rdev = dev->dev_private; 1311 struct radeon_framebuffer *radeon_fb; 1312 struct drm_gem_object *obj; 1313 struct radeon_bo *rbo; 1314 struct drm_framebuffer *target_fb; 1315 uint64_t fb_location; 1316 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1317 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; 1318 u32 tmp, viewport_w, viewport_h; 1319 int r; 1320 1321 /* no fb bound */ 1322 if (!atomic && !crtc->fb) { 1323 DRM_DEBUG_KMS("No FB bound\n"); 1324 return 0; 1325 } 1326 1327 if (atomic) { 1328 radeon_fb = to_radeon_framebuffer(fb); 1329 target_fb = fb; 1330 } 1331 else { 1332 radeon_fb = to_radeon_framebuffer(crtc->fb); 1333 target_fb = crtc->fb; 1334 } 1335 1336 obj = radeon_fb->obj; 1337 rbo = gem_to_radeon_bo(obj); 1338 r = radeon_bo_reserve(rbo, false); 1339 if (unlikely(r != 0)) 1340 return r; 1341 1342 /* If atomic, assume fb object is pinned & idle & fenced and 1343 * just update base pointers 1344 */ 1345 if (atomic) 1346 fb_location = radeon_bo_gpu_offset(rbo); 1347 else { 1348 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); 1349 if (unlikely(r != 0)) { 1350 radeon_bo_unreserve(rbo); 1351 return -EINVAL; 1352 } 1353 } 1354 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1355 radeon_bo_unreserve(rbo); 1356 1357 switch (target_fb->bits_per_pixel) { 1358 case 8: 1359 fb_format = 1360 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | 1361 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; 1362 break; 1363 case 15: 1364 fb_format = 1365 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1366 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; 1367 break; 1368 case 16: 1369 fb_format = 1370 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1371 AVIVO_D1GRPH_CONTROL_16BPP_RGB565; 1372 #ifdef __BIG_ENDIAN 1373 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 1374 #endif 1375 break; 1376 case 24: 1377 case 32: 1378 fb_format = 1379 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | 1380 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; 1381 #ifdef __BIG_ENDIAN 1382 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; 1383 #endif 1384 break; 1385 default: 1386 DRM_ERROR("Unsupported screen depth %d\n", 1387 target_fb->bits_per_pixel); 1388 return -EINVAL; 1389 } 1390 1391 if (rdev->family >= CHIP_R600) { 1392 if (tiling_flags & RADEON_TILING_MACRO) 1393 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1; 1394 else if (tiling_flags & RADEON_TILING_MICRO) 1395 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1; 1396 } else { 1397 if (tiling_flags & RADEON_TILING_MACRO) 1398 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; 1399 1400 if (tiling_flags & RADEON_TILING_MICRO) 1401 fb_format |= AVIVO_D1GRPH_TILED; 1402 } 1403 1404 if (radeon_crtc->crtc_id == 0) 1405 WREG32(AVIVO_D1VGA_CONTROL, 0); 1406 else 1407 WREG32(AVIVO_D2VGA_CONTROL, 0); 1408 1409 if (rdev->family >= CHIP_RV770) { 1410 if (radeon_crtc->crtc_id) { 1411 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1412 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1413 } else { 1414 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1415 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1416 } 1417 } 1418 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1419 (u32) fb_location); 1420 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + 1421 radeon_crtc->crtc_offset, (u32) fb_location); 1422 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1423 if (rdev->family >= CHIP_R600) 1424 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1425 1426 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1427 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1428 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); 1429 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); 1430 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); 1431 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); 1432 1433 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 1434 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 1435 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1436 1437 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1438 target_fb->height); 1439 x &= ~3; 1440 y &= ~1; 1441 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, 1442 (x << 16) | y); 1443 viewport_w = crtc->mode.hdisplay; 1444 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1445 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1446 (viewport_w << 16) | viewport_h); 1447 1448 /* pageflip setup */ 1449 /* make sure flip is at vb rather than hb */ 1450 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); 1451 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN; 1452 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); 1453 1454 /* set pageflip to happen anywhere in vblank interval */ 1455 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); 1456 1457 if (!atomic && fb && fb != crtc->fb) { 1458 radeon_fb = to_radeon_framebuffer(fb); 1459 rbo = gem_to_radeon_bo(radeon_fb->obj); 1460 r = radeon_bo_reserve(rbo, false); 1461 if (unlikely(r != 0)) 1462 return r; 1463 radeon_bo_unpin(rbo); 1464 radeon_bo_unreserve(rbo); 1465 } 1466 1467 /* Bytes per pixel may have changed */ 1468 radeon_bandwidth_update(rdev); 1469 1470 return 0; 1471 } 1472 1473 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 1474 struct drm_framebuffer *old_fb) 1475 { 1476 struct drm_device *dev = crtc->dev; 1477 struct radeon_device *rdev = dev->dev_private; 1478 1479 if (ASIC_IS_DCE4(rdev)) 1480 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0); 1481 else if (ASIC_IS_AVIVO(rdev)) 1482 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0); 1483 else 1484 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); 1485 } 1486 1487 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 1488 struct drm_framebuffer *fb, 1489 int x, int y, enum mode_set_atomic state) 1490 { 1491 struct drm_device *dev = crtc->dev; 1492 struct radeon_device *rdev = dev->dev_private; 1493 1494 if (ASIC_IS_DCE4(rdev)) 1495 return dce4_crtc_do_set_base(crtc, fb, x, y, 1); 1496 else if (ASIC_IS_AVIVO(rdev)) 1497 return avivo_crtc_do_set_base(crtc, fb, x, y, 1); 1498 else 1499 return radeon_crtc_do_set_base(crtc, fb, x, y, 1); 1500 } 1501 1502 /* properly set additional regs when using atombios */ 1503 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) 1504 { 1505 struct drm_device *dev = crtc->dev; 1506 struct radeon_device *rdev = dev->dev_private; 1507 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1508 u32 disp_merge_cntl; 1509 1510 switch (radeon_crtc->crtc_id) { 1511 case 0: 1512 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); 1513 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 1514 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); 1515 break; 1516 case 1: 1517 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 1518 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 1519 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); 1520 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); 1521 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); 1522 break; 1523 } 1524 } 1525 1526 /** 1527 * radeon_get_pll_use_mask - look up a mask of which pplls are in use 1528 * 1529 * @crtc: drm crtc 1530 * 1531 * Returns the mask of which PPLLs (Pixel PLLs) are in use. 1532 */ 1533 static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc) 1534 { 1535 struct drm_device *dev = crtc->dev; 1536 struct drm_crtc *test_crtc; 1537 struct radeon_crtc *test_radeon_crtc; 1538 u32 pll_in_use = 0; 1539 1540 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1541 if (crtc == test_crtc) 1542 continue; 1543 1544 test_radeon_crtc = to_radeon_crtc(test_crtc); 1545 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 1546 pll_in_use |= (1 << test_radeon_crtc->pll_id); 1547 } 1548 return pll_in_use; 1549 } 1550 1551 /** 1552 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP 1553 * 1554 * @crtc: drm crtc 1555 * 1556 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is 1557 * also in DP mode. For DP, a single PPLL can be used for all DP 1558 * crtcs/encoders. 1559 */ 1560 static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) 1561 { 1562 struct drm_device *dev = crtc->dev; 1563 struct drm_crtc *test_crtc; 1564 struct radeon_crtc *test_radeon_crtc; 1565 1566 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1567 if (crtc == test_crtc) 1568 continue; 1569 test_radeon_crtc = to_radeon_crtc(test_crtc); 1570 if (test_radeon_crtc->encoder && 1571 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { 1572 /* for DP use the same PLL for all */ 1573 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 1574 return test_radeon_crtc->pll_id; 1575 } 1576 } 1577 return ATOM_PPLL_INVALID; 1578 } 1579 1580 /** 1581 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc 1582 * 1583 * @crtc: drm crtc 1584 * @encoder: drm encoder 1585 * 1586 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can 1587 * be shared (i.e., same clock). 1588 */ 1589 static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc) 1590 { 1591 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1592 struct drm_device *dev = crtc->dev; 1593 struct drm_crtc *test_crtc; 1594 struct radeon_crtc *test_radeon_crtc; 1595 u32 adjusted_clock, test_adjusted_clock; 1596 1597 adjusted_clock = radeon_crtc->adjusted_clock; 1598 1599 if (adjusted_clock == 0) 1600 return ATOM_PPLL_INVALID; 1601 1602 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1603 if (crtc == test_crtc) 1604 continue; 1605 test_radeon_crtc = to_radeon_crtc(test_crtc); 1606 if (test_radeon_crtc->encoder && 1607 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { 1608 /* check if we are already driving this connector with another crtc */ 1609 if (test_radeon_crtc->connector == radeon_crtc->connector) { 1610 /* if we are, return that pll */ 1611 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 1612 return test_radeon_crtc->pll_id; 1613 } 1614 /* for non-DP check the clock */ 1615 test_adjusted_clock = test_radeon_crtc->adjusted_clock; 1616 if ((crtc->mode.clock == test_crtc->mode.clock) && 1617 (adjusted_clock == test_adjusted_clock) && 1618 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) && 1619 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)) 1620 return test_radeon_crtc->pll_id; 1621 } 1622 } 1623 return ATOM_PPLL_INVALID; 1624 } 1625 1626 /** 1627 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc. 1628 * 1629 * @crtc: drm crtc 1630 * 1631 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 1632 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 1633 * monitors a dedicated PPLL must be used. If a particular board has 1634 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 1635 * as there is no need to program the PLL itself. If we are not able to 1636 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 1637 * avoid messing up an existing monitor. 1638 * 1639 * Asic specific PLL information 1640 * 1641 * DCE 8.x 1642 * KB/KV 1643 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 1644 * CI 1645 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1646 * 1647 * DCE 6.1 1648 * - PPLL2 is only available to UNIPHYA (both DP and non-DP) 1649 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP) 1650 * 1651 * DCE 6.0 1652 * - PPLL0 is available to all UNIPHY (DP only) 1653 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1654 * 1655 * DCE 5.0 1656 * - DCPLL is available to all UNIPHY (DP only) 1657 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1658 * 1659 * DCE 3.0/4.0/4.1 1660 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1661 * 1662 */ 1663 static int radeon_atom_pick_pll(struct drm_crtc *crtc) 1664 { 1665 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1666 struct drm_device *dev = crtc->dev; 1667 struct radeon_device *rdev = dev->dev_private; 1668 struct radeon_encoder *radeon_encoder = 1669 to_radeon_encoder(radeon_crtc->encoder); 1670 u32 pll_in_use; 1671 int pll; 1672 1673 if (ASIC_IS_DCE8(rdev)) { 1674 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1675 if (rdev->clock.dp_extclk) 1676 /* skip PPLL programming if using ext clock */ 1677 return ATOM_PPLL_INVALID; 1678 else { 1679 /* use the same PPLL for all DP monitors */ 1680 pll = radeon_get_shared_dp_ppll(crtc); 1681 if (pll != ATOM_PPLL_INVALID) 1682 return pll; 1683 } 1684 } else { 1685 /* use the same PPLL for all monitors with the same clock */ 1686 pll = radeon_get_shared_nondp_ppll(crtc); 1687 if (pll != ATOM_PPLL_INVALID) 1688 return pll; 1689 } 1690 /* otherwise, pick one of the plls */ 1691 if ((rdev->family == CHIP_KAVERI) || 1692 (rdev->family == CHIP_KABINI)) { 1693 /* KB/KV has PPLL1 and PPLL2 */ 1694 pll_in_use = radeon_get_pll_use_mask(crtc); 1695 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1696 return ATOM_PPLL2; 1697 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1698 return ATOM_PPLL1; 1699 DRM_ERROR("unable to allocate a PPLL\n"); 1700 return ATOM_PPLL_INVALID; 1701 } else { 1702 /* CI has PPLL0, PPLL1, and PPLL2 */ 1703 pll_in_use = radeon_get_pll_use_mask(crtc); 1704 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1705 return ATOM_PPLL2; 1706 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1707 return ATOM_PPLL1; 1708 if (!(pll_in_use & (1 << ATOM_PPLL0))) 1709 return ATOM_PPLL0; 1710 DRM_ERROR("unable to allocate a PPLL\n"); 1711 return ATOM_PPLL_INVALID; 1712 } 1713 } else if (ASIC_IS_DCE61(rdev)) { 1714 struct radeon_encoder_atom_dig *dig = 1715 radeon_encoder->enc_priv; 1716 1717 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) && 1718 (dig->linkb == false)) 1719 /* UNIPHY A uses PPLL2 */ 1720 return ATOM_PPLL2; 1721 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1722 /* UNIPHY B/C/D/E/F */ 1723 if (rdev->clock.dp_extclk) 1724 /* skip PPLL programming if using ext clock */ 1725 return ATOM_PPLL_INVALID; 1726 else { 1727 /* use the same PPLL for all DP monitors */ 1728 pll = radeon_get_shared_dp_ppll(crtc); 1729 if (pll != ATOM_PPLL_INVALID) 1730 return pll; 1731 } 1732 } else { 1733 /* use the same PPLL for all monitors with the same clock */ 1734 pll = radeon_get_shared_nondp_ppll(crtc); 1735 if (pll != ATOM_PPLL_INVALID) 1736 return pll; 1737 } 1738 /* UNIPHY B/C/D/E/F */ 1739 pll_in_use = radeon_get_pll_use_mask(crtc); 1740 if (!(pll_in_use & (1 << ATOM_PPLL0))) 1741 return ATOM_PPLL0; 1742 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1743 return ATOM_PPLL1; 1744 DRM_ERROR("unable to allocate a PPLL\n"); 1745 return ATOM_PPLL_INVALID; 1746 } else if (ASIC_IS_DCE4(rdev)) { 1747 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, 1748 * depending on the asic: 1749 * DCE4: PPLL or ext clock 1750 * DCE5: PPLL, DCPLL, or ext clock 1751 * DCE6: PPLL, PPLL0, or ext clock 1752 * 1753 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip 1754 * PPLL/DCPLL programming and only program the DP DTO for the 1755 * crtc virtual pixel clock. 1756 */ 1757 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1758 if (rdev->clock.dp_extclk) 1759 /* skip PPLL programming if using ext clock */ 1760 return ATOM_PPLL_INVALID; 1761 else if (ASIC_IS_DCE6(rdev)) 1762 /* use PPLL0 for all DP */ 1763 return ATOM_PPLL0; 1764 else if (ASIC_IS_DCE5(rdev)) 1765 /* use DCPLL for all DP */ 1766 return ATOM_DCPLL; 1767 else { 1768 /* use the same PPLL for all DP monitors */ 1769 pll = radeon_get_shared_dp_ppll(crtc); 1770 if (pll != ATOM_PPLL_INVALID) 1771 return pll; 1772 } 1773 } else if (!ASIC_IS_DCE41(rdev)) { /* Don't share PLLs on DCE4.1 chips */ 1774 /* use the same PPLL for all monitors with the same clock */ 1775 pll = radeon_get_shared_nondp_ppll(crtc); 1776 if (pll != ATOM_PPLL_INVALID) 1777 return pll; 1778 } 1779 /* all other cases */ 1780 pll_in_use = radeon_get_pll_use_mask(crtc); 1781 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1782 return ATOM_PPLL1; 1783 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1784 return ATOM_PPLL2; 1785 DRM_ERROR("unable to allocate a PPLL\n"); 1786 return ATOM_PPLL_INVALID; 1787 } else { 1788 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ 1789 /* some atombios (observed in some DCE2/DCE3) code have a bug, 1790 * the matching btw pll and crtc is done through 1791 * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the 1792 * pll (1 or 2) to select which register to write. ie if using 1793 * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2 1794 * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to 1795 * choose which value to write. Which is reverse order from 1796 * register logic. So only case that works is when pllid is 1797 * same as crtcid or when both pll and crtc are enabled and 1798 * both use same clock. 1799 * 1800 * So just return crtc id as if crtc and pll were hard linked 1801 * together even if they aren't 1802 */ 1803 return radeon_crtc->crtc_id; 1804 } 1805 } 1806 1807 void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev) 1808 { 1809 /* always set DCPLL */ 1810 if (ASIC_IS_DCE6(rdev)) 1811 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); 1812 else if (ASIC_IS_DCE4(rdev)) { 1813 struct radeon_atom_ss ss; 1814 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, 1815 ASIC_INTERNAL_SS_ON_DCPLL, 1816 rdev->clock.default_dispclk); 1817 if (ss_enabled) 1818 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss); 1819 /* XXX: DCE5, make sure voltage, dispclk is high enough */ 1820 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); 1821 if (ss_enabled) 1822 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss); 1823 } 1824 1825 } 1826 1827 int atombios_crtc_mode_set(struct drm_crtc *crtc, 1828 struct drm_display_mode *mode, 1829 struct drm_display_mode *adjusted_mode, 1830 int x, int y, struct drm_framebuffer *old_fb) 1831 { 1832 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1833 struct drm_device *dev = crtc->dev; 1834 struct radeon_device *rdev = dev->dev_private; 1835 struct radeon_encoder *radeon_encoder = 1836 to_radeon_encoder(radeon_crtc->encoder); 1837 bool is_tvcv = false; 1838 1839 if (radeon_encoder->active_device & 1840 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 1841 is_tvcv = true; 1842 1843 atombios_crtc_set_pll(crtc, adjusted_mode); 1844 1845 if (ASIC_IS_DCE4(rdev)) 1846 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1847 else if (ASIC_IS_AVIVO(rdev)) { 1848 if (is_tvcv) 1849 atombios_crtc_set_timing(crtc, adjusted_mode); 1850 else 1851 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1852 } else { 1853 atombios_crtc_set_timing(crtc, adjusted_mode); 1854 if (radeon_crtc->crtc_id == 0) 1855 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1856 radeon_legacy_atom_fixup(crtc); 1857 } 1858 atombios_crtc_set_base(crtc, x, y, old_fb); 1859 atombios_overscan_setup(crtc, mode, adjusted_mode); 1860 atombios_scaler_setup(crtc); 1861 /* update the hw version fpr dpm */ 1862 radeon_crtc->hw_mode = *adjusted_mode; 1863 1864 return 0; 1865 } 1866 1867 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, 1868 const struct drm_display_mode *mode, 1869 struct drm_display_mode *adjusted_mode) 1870 { 1871 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1872 struct drm_device *dev = crtc->dev; 1873 struct drm_encoder *encoder; 1874 1875 /* assign the encoder to the radeon crtc to avoid repeated lookups later */ 1876 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1877 if (encoder->crtc == crtc) { 1878 radeon_crtc->encoder = encoder; 1879 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder); 1880 break; 1881 } 1882 } 1883 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) { 1884 radeon_crtc->encoder = NULL; 1885 radeon_crtc->connector = NULL; 1886 return false; 1887 } 1888 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 1889 return false; 1890 if (!atombios_crtc_prepare_pll(crtc, adjusted_mode)) 1891 return false; 1892 /* pick pll */ 1893 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); 1894 /* if we can't get a PPLL for a non-DP encoder, fail */ 1895 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) && 1896 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) 1897 return false; 1898 1899 return true; 1900 } 1901 1902 static void atombios_crtc_prepare(struct drm_crtc *crtc) 1903 { 1904 struct drm_device *dev = crtc->dev; 1905 struct radeon_device *rdev = dev->dev_private; 1906 1907 /* disable crtc pair power gating before programming */ 1908 if (ASIC_IS_DCE6(rdev)) 1909 atombios_powergate_crtc(crtc, ATOM_DISABLE); 1910 1911 atombios_lock_crtc(crtc, ATOM_ENABLE); 1912 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1913 } 1914 1915 static void atombios_crtc_commit(struct drm_crtc *crtc) 1916 { 1917 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 1918 atombios_lock_crtc(crtc, ATOM_DISABLE); 1919 } 1920 1921 static void atombios_crtc_disable(struct drm_crtc *crtc) 1922 { 1923 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1924 struct drm_device *dev = crtc->dev; 1925 struct radeon_device *rdev = dev->dev_private; 1926 struct radeon_atom_ss ss; 1927 int i; 1928 1929 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1930 if (crtc->fb) { 1931 int r; 1932 struct radeon_framebuffer *radeon_fb; 1933 struct radeon_bo *rbo; 1934 1935 radeon_fb = to_radeon_framebuffer(crtc->fb); 1936 rbo = gem_to_radeon_bo(radeon_fb->obj); 1937 r = radeon_bo_reserve(rbo, false); 1938 if (unlikely(r)) 1939 DRM_ERROR("failed to reserve rbo before unpin\n"); 1940 else { 1941 radeon_bo_unpin(rbo); 1942 radeon_bo_unreserve(rbo); 1943 } 1944 } 1945 /* disable the GRPH */ 1946 if (ASIC_IS_DCE4(rdev)) 1947 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0); 1948 else if (ASIC_IS_AVIVO(rdev)) 1949 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0); 1950 1951 if (ASIC_IS_DCE6(rdev)) 1952 atombios_powergate_crtc(crtc, ATOM_ENABLE); 1953 1954 for (i = 0; i < rdev->num_crtc; i++) { 1955 if (rdev->mode_info.crtcs[i] && 1956 rdev->mode_info.crtcs[i]->enabled && 1957 i != radeon_crtc->crtc_id && 1958 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) { 1959 /* one other crtc is using this pll don't turn 1960 * off the pll 1961 */ 1962 goto done; 1963 } 1964 } 1965 1966 switch (radeon_crtc->pll_id) { 1967 case ATOM_PPLL1: 1968 case ATOM_PPLL2: 1969 /* disable the ppll */ 1970 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 1971 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 1972 break; 1973 case ATOM_PPLL0: 1974 /* disable the ppll */ 1975 if ((rdev->family == CHIP_ARUBA) || 1976 (rdev->family == CHIP_BONAIRE) || 1977 (rdev->family == CHIP_HAWAII)) 1978 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 1979 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 1980 break; 1981 default: 1982 break; 1983 } 1984 done: 1985 radeon_crtc->pll_id = ATOM_PPLL_INVALID; 1986 radeon_crtc->adjusted_clock = 0; 1987 radeon_crtc->encoder = NULL; 1988 radeon_crtc->connector = NULL; 1989 } 1990 1991 static const struct drm_crtc_helper_funcs atombios_helper_funcs = { 1992 .dpms = atombios_crtc_dpms, 1993 .mode_fixup = atombios_crtc_mode_fixup, 1994 .mode_set = atombios_crtc_mode_set, 1995 .mode_set_base = atombios_crtc_set_base, 1996 .mode_set_base_atomic = atombios_crtc_set_base_atomic, 1997 .prepare = atombios_crtc_prepare, 1998 .commit = atombios_crtc_commit, 1999 .load_lut = radeon_crtc_load_lut, 2000 .disable = atombios_crtc_disable, 2001 }; 2002 2003 void radeon_atombios_init_crtc(struct drm_device *dev, 2004 struct radeon_crtc *radeon_crtc) 2005 { 2006 struct radeon_device *rdev = dev->dev_private; 2007 2008 if (ASIC_IS_DCE4(rdev)) { 2009 switch (radeon_crtc->crtc_id) { 2010 case 0: 2011 default: 2012 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; 2013 break; 2014 case 1: 2015 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; 2016 break; 2017 case 2: 2018 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; 2019 break; 2020 case 3: 2021 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; 2022 break; 2023 case 4: 2024 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; 2025 break; 2026 case 5: 2027 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; 2028 break; 2029 } 2030 } else { 2031 if (radeon_crtc->crtc_id == 1) 2032 radeon_crtc->crtc_offset = 2033 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; 2034 else 2035 radeon_crtc->crtc_offset = 0; 2036 } 2037 radeon_crtc->pll_id = ATOM_PPLL_INVALID; 2038 radeon_crtc->adjusted_clock = 0; 2039 radeon_crtc->encoder = NULL; 2040 radeon_crtc->connector = NULL; 2041 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); 2042 } 2043