1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_crtc_helper.h> 28 #include <drm/radeon_drm.h> 29 #include <drm/drm_fixed.h> 30 #include "radeon.h" 31 #include "atom.h" 32 #include "atom-bits.h" 33 34 static void atombios_overscan_setup(struct drm_crtc *crtc, 35 struct drm_display_mode *mode, 36 struct drm_display_mode *adjusted_mode) 37 { 38 struct drm_device *dev = crtc->dev; 39 struct radeon_device *rdev = dev->dev_private; 40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 41 SET_CRTC_OVERSCAN_PS_ALLOCATION args; 42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); 43 int a1, a2; 44 45 memset(&args, 0, sizeof(args)); 46 47 args.ucCRTC = radeon_crtc->crtc_id; 48 49 switch (radeon_crtc->rmx_type) { 50 case RMX_CENTER: 51 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 52 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 53 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 54 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 55 break; 56 case RMX_ASPECT: 57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; 58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; 59 60 if (a1 > a2) { 61 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 62 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 63 } else if (a2 > a1) { 64 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 65 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 66 } 67 break; 68 case RMX_FULL: 69 default: 70 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); 71 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); 72 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); 73 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); 74 break; 75 } 76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 77 } 78 79 static void atombios_scaler_setup(struct drm_crtc *crtc) 80 { 81 struct drm_device *dev = crtc->dev; 82 struct radeon_device *rdev = dev->dev_private; 83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 84 ENABLE_SCALER_PS_ALLOCATION args; 85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); 86 87 /* fixme - fill in enc_priv for atom dac */ 88 enum radeon_tv_std tv_std = TV_STD_NTSC; 89 bool is_tv = false, is_cv = false; 90 struct drm_encoder *encoder; 91 92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) 93 return; 94 95 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 96 /* find tv std */ 97 if (encoder->crtc == crtc) { 98 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 99 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 100 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 101 tv_std = tv_dac->tv_std; 102 is_tv = true; 103 } 104 } 105 } 106 107 memset(&args, 0, sizeof(args)); 108 109 args.ucScaler = radeon_crtc->crtc_id; 110 111 if (is_tv) { 112 switch (tv_std) { 113 case TV_STD_NTSC: 114 default: 115 args.ucTVStandard = ATOM_TV_NTSC; 116 break; 117 case TV_STD_PAL: 118 args.ucTVStandard = ATOM_TV_PAL; 119 break; 120 case TV_STD_PAL_M: 121 args.ucTVStandard = ATOM_TV_PALM; 122 break; 123 case TV_STD_PAL_60: 124 args.ucTVStandard = ATOM_TV_PAL60; 125 break; 126 case TV_STD_NTSC_J: 127 args.ucTVStandard = ATOM_TV_NTSCJ; 128 break; 129 case TV_STD_SCART_PAL: 130 args.ucTVStandard = ATOM_TV_PAL; /* ??? */ 131 break; 132 case TV_STD_SECAM: 133 args.ucTVStandard = ATOM_TV_SECAM; 134 break; 135 case TV_STD_PAL_CN: 136 args.ucTVStandard = ATOM_TV_PALCN; 137 break; 138 } 139 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 140 } else if (is_cv) { 141 args.ucTVStandard = ATOM_TV_CV; 142 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 143 } else { 144 switch (radeon_crtc->rmx_type) { 145 case RMX_FULL: 146 args.ucEnable = ATOM_SCALER_EXPANSION; 147 break; 148 case RMX_CENTER: 149 args.ucEnable = ATOM_SCALER_CENTER; 150 break; 151 case RMX_ASPECT: 152 args.ucEnable = ATOM_SCALER_EXPANSION; 153 break; 154 default: 155 if (ASIC_IS_AVIVO(rdev)) 156 args.ucEnable = ATOM_SCALER_DISABLE; 157 else 158 args.ucEnable = ATOM_SCALER_CENTER; 159 break; 160 } 161 } 162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 163 if ((is_tv || is_cv) 164 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { 165 atom_rv515_force_tv_scaler(rdev, radeon_crtc); 166 } 167 } 168 169 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) 170 { 171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 172 struct drm_device *dev = crtc->dev; 173 struct radeon_device *rdev = dev->dev_private; 174 int index = 175 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); 176 ENABLE_CRTC_PS_ALLOCATION args; 177 178 memset(&args, 0, sizeof(args)); 179 180 args.ucCRTC = radeon_crtc->crtc_id; 181 args.ucEnable = lock; 182 183 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 184 } 185 186 static void atombios_enable_crtc(struct drm_crtc *crtc, int state) 187 { 188 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 189 struct drm_device *dev = crtc->dev; 190 struct radeon_device *rdev = dev->dev_private; 191 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); 192 ENABLE_CRTC_PS_ALLOCATION args; 193 194 memset(&args, 0, sizeof(args)); 195 196 args.ucCRTC = radeon_crtc->crtc_id; 197 args.ucEnable = state; 198 199 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 200 } 201 202 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) 203 { 204 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 205 struct drm_device *dev = crtc->dev; 206 struct radeon_device *rdev = dev->dev_private; 207 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); 208 ENABLE_CRTC_PS_ALLOCATION args; 209 210 memset(&args, 0, sizeof(args)); 211 212 args.ucCRTC = radeon_crtc->crtc_id; 213 args.ucEnable = state; 214 215 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 216 } 217 218 static void atombios_blank_crtc(struct drm_crtc *crtc, int state) 219 { 220 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 221 struct drm_device *dev = crtc->dev; 222 struct radeon_device *rdev = dev->dev_private; 223 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); 224 BLANK_CRTC_PS_ALLOCATION args; 225 226 memset(&args, 0, sizeof(args)); 227 228 args.ucCRTC = radeon_crtc->crtc_id; 229 args.ucBlanking = state; 230 231 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 232 } 233 234 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) 235 { 236 struct drm_device *dev = crtc->dev; 237 struct radeon_device *rdev = dev->dev_private; 238 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 239 240 switch (mode) { 241 case DRM_MODE_DPMS_ON: 242 radeon_crtc->enabled = true; 243 /* adjust pm to dpms changes BEFORE enabling crtcs */ 244 radeon_pm_compute_clocks(rdev); 245 atombios_enable_crtc(crtc, ATOM_ENABLE); 246 if (ASIC_IS_DCE3(rdev)) 247 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); 248 atombios_blank_crtc(crtc, ATOM_DISABLE); 249 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); 250 radeon_crtc_load_lut(crtc); 251 break; 252 case DRM_MODE_DPMS_STANDBY: 253 case DRM_MODE_DPMS_SUSPEND: 254 case DRM_MODE_DPMS_OFF: 255 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); 256 if (radeon_crtc->enabled) 257 atombios_blank_crtc(crtc, ATOM_ENABLE); 258 if (ASIC_IS_DCE3(rdev)) 259 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); 260 atombios_enable_crtc(crtc, ATOM_DISABLE); 261 radeon_crtc->enabled = false; 262 /* adjust pm to dpms changes AFTER disabling crtcs */ 263 radeon_pm_compute_clocks(rdev); 264 break; 265 } 266 } 267 268 static void 269 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, 270 struct drm_display_mode *mode) 271 { 272 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 273 struct drm_device *dev = crtc->dev; 274 struct radeon_device *rdev = dev->dev_private; 275 SET_CRTC_USING_DTD_TIMING_PARAMETERS args; 276 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); 277 u16 misc = 0; 278 279 memset(&args, 0, sizeof(args)); 280 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); 281 args.usH_Blanking_Time = 282 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); 283 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); 284 args.usV_Blanking_Time = 285 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); 286 args.usH_SyncOffset = 287 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); 288 args.usH_SyncWidth = 289 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 290 args.usV_SyncOffset = 291 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); 292 args.usV_SyncWidth = 293 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 294 args.ucH_Border = radeon_crtc->h_border; 295 args.ucV_Border = radeon_crtc->v_border; 296 297 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 298 misc |= ATOM_VSYNC_POLARITY; 299 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 300 misc |= ATOM_HSYNC_POLARITY; 301 if (mode->flags & DRM_MODE_FLAG_CSYNC) 302 misc |= ATOM_COMPOSITESYNC; 303 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 304 misc |= ATOM_INTERLACE; 305 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 306 misc |= ATOM_DOUBLE_CLOCK_MODE; 307 308 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 309 args.ucCRTC = radeon_crtc->crtc_id; 310 311 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 312 } 313 314 static void atombios_crtc_set_timing(struct drm_crtc *crtc, 315 struct drm_display_mode *mode) 316 { 317 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 318 struct drm_device *dev = crtc->dev; 319 struct radeon_device *rdev = dev->dev_private; 320 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; 321 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); 322 u16 misc = 0; 323 324 memset(&args, 0, sizeof(args)); 325 args.usH_Total = cpu_to_le16(mode->crtc_htotal); 326 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); 327 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); 328 args.usH_SyncWidth = 329 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 330 args.usV_Total = cpu_to_le16(mode->crtc_vtotal); 331 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); 332 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); 333 args.usV_SyncWidth = 334 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 335 336 args.ucOverscanRight = radeon_crtc->h_border; 337 args.ucOverscanLeft = radeon_crtc->h_border; 338 args.ucOverscanBottom = radeon_crtc->v_border; 339 args.ucOverscanTop = radeon_crtc->v_border; 340 341 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 342 misc |= ATOM_VSYNC_POLARITY; 343 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 344 misc |= ATOM_HSYNC_POLARITY; 345 if (mode->flags & DRM_MODE_FLAG_CSYNC) 346 misc |= ATOM_COMPOSITESYNC; 347 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 348 misc |= ATOM_INTERLACE; 349 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 350 misc |= ATOM_DOUBLE_CLOCK_MODE; 351 352 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 353 args.ucCRTC = radeon_crtc->crtc_id; 354 355 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 356 } 357 358 static void atombios_disable_ss(struct drm_crtc *crtc) 359 { 360 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 361 struct drm_device *dev = crtc->dev; 362 struct radeon_device *rdev = dev->dev_private; 363 u32 ss_cntl; 364 365 if (ASIC_IS_DCE4(rdev)) { 366 switch (radeon_crtc->pll_id) { 367 case ATOM_PPLL1: 368 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); 369 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 370 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl); 371 break; 372 case ATOM_PPLL2: 373 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL); 374 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 375 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl); 376 break; 377 case ATOM_DCPLL: 378 case ATOM_PPLL_INVALID: 379 return; 380 } 381 } else if (ASIC_IS_AVIVO(rdev)) { 382 switch (radeon_crtc->pll_id) { 383 case ATOM_PPLL1: 384 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); 385 ss_cntl &= ~1; 386 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl); 387 break; 388 case ATOM_PPLL2: 389 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); 390 ss_cntl &= ~1; 391 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl); 392 break; 393 case ATOM_DCPLL: 394 case ATOM_PPLL_INVALID: 395 return; 396 } 397 } 398 } 399 400 401 union atom_enable_ss { 402 ENABLE_LVDS_SS_PARAMETERS lvds_ss; 403 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2; 404 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; 405 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2; 406 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; 407 }; 408 409 static void atombios_crtc_program_ss(struct drm_crtc *crtc, 410 int enable, 411 int pll_id, 412 struct radeon_atom_ss *ss) 413 { 414 struct drm_device *dev = crtc->dev; 415 struct radeon_device *rdev = dev->dev_private; 416 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); 417 union atom_enable_ss args; 418 419 memset(&args, 0, sizeof(args)); 420 421 if (ASIC_IS_DCE5(rdev)) { 422 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); 423 args.v3.ucSpreadSpectrumType = ss->type; 424 switch (pll_id) { 425 case ATOM_PPLL1: 426 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; 427 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 428 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); 429 break; 430 case ATOM_PPLL2: 431 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; 432 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 433 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); 434 break; 435 case ATOM_DCPLL: 436 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; 437 args.v3.usSpreadSpectrumAmount = cpu_to_le16(0); 438 args.v3.usSpreadSpectrumStep = cpu_to_le16(0); 439 break; 440 case ATOM_PPLL_INVALID: 441 return; 442 } 443 args.v2.ucEnable = enable; 444 } else if (ASIC_IS_DCE4(rdev)) { 445 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 446 args.v2.ucSpreadSpectrumType = ss->type; 447 switch (pll_id) { 448 case ATOM_PPLL1: 449 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL; 450 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 451 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); 452 break; 453 case ATOM_PPLL2: 454 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL; 455 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 456 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); 457 break; 458 case ATOM_DCPLL: 459 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL; 460 args.v2.usSpreadSpectrumAmount = cpu_to_le16(0); 461 args.v2.usSpreadSpectrumStep = cpu_to_le16(0); 462 break; 463 case ATOM_PPLL_INVALID: 464 return; 465 } 466 args.v2.ucEnable = enable; 467 } else if (ASIC_IS_DCE3(rdev)) { 468 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 469 args.v1.ucSpreadSpectrumType = ss->type; 470 args.v1.ucSpreadSpectrumStep = ss->step; 471 args.v1.ucSpreadSpectrumDelay = ss->delay; 472 args.v1.ucSpreadSpectrumRange = ss->range; 473 args.v1.ucPpll = pll_id; 474 args.v1.ucEnable = enable; 475 } else if (ASIC_IS_AVIVO(rdev)) { 476 if (enable == ATOM_DISABLE) { 477 atombios_disable_ss(crtc); 478 return; 479 } 480 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 481 args.lvds_ss_2.ucSpreadSpectrumType = ss->type; 482 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; 483 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; 484 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; 485 args.lvds_ss_2.ucEnable = enable; 486 } else { 487 if (enable == ATOM_DISABLE) { 488 atombios_disable_ss(crtc); 489 return; 490 } 491 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 492 args.lvds_ss.ucSpreadSpectrumType = ss->type; 493 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; 494 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; 495 args.lvds_ss.ucEnable = enable; 496 } 497 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 498 } 499 500 union adjust_pixel_clock { 501 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; 502 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; 503 }; 504 505 static u32 atombios_adjust_pll(struct drm_crtc *crtc, 506 struct drm_display_mode *mode, 507 struct radeon_pll *pll, 508 bool ss_enabled, 509 struct radeon_atom_ss *ss) 510 { 511 struct drm_device *dev = crtc->dev; 512 struct radeon_device *rdev = dev->dev_private; 513 struct drm_encoder *encoder = NULL; 514 struct radeon_encoder *radeon_encoder = NULL; 515 u32 adjusted_clock = mode->clock; 516 int encoder_mode = 0; 517 u32 dp_clock = mode->clock; 518 int bpc = 8; 519 520 /* reset the pll flags */ 521 pll->flags = 0; 522 523 if (ASIC_IS_AVIVO(rdev)) { 524 if ((rdev->family == CHIP_RS600) || 525 (rdev->family == CHIP_RS690) || 526 (rdev->family == CHIP_RS740)) 527 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ 528 RADEON_PLL_PREFER_CLOSEST_LOWER); 529 530 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ 531 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 532 else 533 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 534 } else { 535 pll->flags |= RADEON_PLL_LEGACY; 536 537 if (mode->clock > 200000) /* range limits??? */ 538 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 539 else 540 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 541 } 542 543 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 544 if (encoder->crtc == crtc) { 545 radeon_encoder = to_radeon_encoder(encoder); 546 encoder_mode = atombios_get_encoder_mode(encoder); 547 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) { 548 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 549 if (connector) { 550 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 551 struct radeon_connector_atom_dig *dig_connector = 552 radeon_connector->con_priv; 553 554 dp_clock = dig_connector->dp_clock; 555 } 556 } 557 558 /* use recommended ref_div for ss */ 559 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 560 if (ss_enabled) { 561 if (ss->refdiv) { 562 pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; 563 pll->flags |= RADEON_PLL_USE_REF_DIV; 564 pll->reference_div = ss->refdiv; 565 if (ASIC_IS_AVIVO(rdev)) 566 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; 567 } 568 } 569 } 570 571 if (ASIC_IS_AVIVO(rdev)) { 572 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ 573 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) 574 adjusted_clock = mode->clock * 2; 575 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 576 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; 577 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 578 pll->flags |= RADEON_PLL_IS_LCD; 579 } else { 580 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 581 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; 582 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) 583 pll->flags |= RADEON_PLL_USE_REF_DIV; 584 } 585 break; 586 } 587 } 588 589 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock 590 * accordingly based on the encoder/transmitter to work around 591 * special hw requirements. 592 */ 593 if (ASIC_IS_DCE3(rdev)) { 594 union adjust_pixel_clock args; 595 u8 frev, crev; 596 int index; 597 598 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); 599 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 600 &crev)) 601 return adjusted_clock; 602 603 memset(&args, 0, sizeof(args)); 604 605 switch (frev) { 606 case 1: 607 switch (crev) { 608 case 1: 609 case 2: 610 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); 611 args.v1.ucTransmitterID = radeon_encoder->encoder_id; 612 args.v1.ucEncodeMode = encoder_mode; 613 if (ss_enabled) 614 args.v1.ucConfig |= 615 ADJUST_DISPLAY_CONFIG_SS_ENABLE; 616 617 atom_execute_table(rdev->mode_info.atom_context, 618 index, (uint32_t *)&args); 619 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; 620 break; 621 case 3: 622 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10); 623 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; 624 args.v3.sInput.ucEncodeMode = encoder_mode; 625 args.v3.sInput.ucDispPllConfig = 0; 626 if (ss_enabled) 627 args.v3.sInput.ucDispPllConfig |= 628 DISPPLL_CONFIG_SS_ENABLE; 629 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 630 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 631 if (encoder_mode == ATOM_ENCODER_MODE_DP) { 632 args.v3.sInput.ucDispPllConfig |= 633 DISPPLL_CONFIG_COHERENT_MODE; 634 /* 16200 or 27000 */ 635 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); 636 } else { 637 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { 638 /* deep color support */ 639 args.v3.sInput.usPixelClock = 640 cpu_to_le16((mode->clock * bpc / 8) / 10); 641 } 642 if (dig->coherent_mode) 643 args.v3.sInput.ucDispPllConfig |= 644 DISPPLL_CONFIG_COHERENT_MODE; 645 if (mode->clock > 165000) 646 args.v3.sInput.ucDispPllConfig |= 647 DISPPLL_CONFIG_DUAL_LINK; 648 } 649 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 650 if (encoder_mode == ATOM_ENCODER_MODE_DP) { 651 args.v3.sInput.ucDispPllConfig |= 652 DISPPLL_CONFIG_COHERENT_MODE; 653 /* 16200 or 27000 */ 654 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); 655 } else if (encoder_mode != ATOM_ENCODER_MODE_LVDS) { 656 if (mode->clock > 165000) 657 args.v3.sInput.ucDispPllConfig |= 658 DISPPLL_CONFIG_DUAL_LINK; 659 } 660 } 661 atom_execute_table(rdev->mode_info.atom_context, 662 index, (uint32_t *)&args); 663 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; 664 if (args.v3.sOutput.ucRefDiv) { 665 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; 666 pll->flags |= RADEON_PLL_USE_REF_DIV; 667 pll->reference_div = args.v3.sOutput.ucRefDiv; 668 } 669 if (args.v3.sOutput.ucPostDiv) { 670 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; 671 pll->flags |= RADEON_PLL_USE_POST_DIV; 672 pll->post_div = args.v3.sOutput.ucPostDiv; 673 } 674 break; 675 default: 676 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 677 return adjusted_clock; 678 } 679 break; 680 default: 681 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 682 return adjusted_clock; 683 } 684 } 685 return adjusted_clock; 686 } 687 688 union set_pixel_clock { 689 SET_PIXEL_CLOCK_PS_ALLOCATION base; 690 PIXEL_CLOCK_PARAMETERS v1; 691 PIXEL_CLOCK_PARAMETERS_V2 v2; 692 PIXEL_CLOCK_PARAMETERS_V3 v3; 693 PIXEL_CLOCK_PARAMETERS_V5 v5; 694 PIXEL_CLOCK_PARAMETERS_V6 v6; 695 }; 696 697 /* on DCE5, make sure the voltage is high enough to support the 698 * required disp clk. 699 */ 700 static void atombios_crtc_set_dcpll(struct drm_crtc *crtc, 701 u32 dispclk) 702 { 703 struct drm_device *dev = crtc->dev; 704 struct radeon_device *rdev = dev->dev_private; 705 u8 frev, crev; 706 int index; 707 union set_pixel_clock args; 708 709 memset(&args, 0, sizeof(args)); 710 711 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 712 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 713 &crev)) 714 return; 715 716 switch (frev) { 717 case 1: 718 switch (crev) { 719 case 5: 720 /* if the default dcpll clock is specified, 721 * SetPixelClock provides the dividers 722 */ 723 args.v5.ucCRTC = ATOM_CRTC_INVALID; 724 args.v5.usPixelClock = cpu_to_le16(dispclk); 725 args.v5.ucPpll = ATOM_DCPLL; 726 break; 727 case 6: 728 /* if the default dcpll clock is specified, 729 * SetPixelClock provides the dividers 730 */ 731 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); 732 args.v6.ucPpll = ATOM_DCPLL; 733 break; 734 default: 735 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 736 return; 737 } 738 break; 739 default: 740 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 741 return; 742 } 743 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 744 } 745 746 static void atombios_crtc_program_pll(struct drm_crtc *crtc, 747 int crtc_id, 748 int pll_id, 749 u32 encoder_mode, 750 u32 encoder_id, 751 u32 clock, 752 u32 ref_div, 753 u32 fb_div, 754 u32 frac_fb_div, 755 u32 post_div) 756 { 757 struct drm_device *dev = crtc->dev; 758 struct radeon_device *rdev = dev->dev_private; 759 u8 frev, crev; 760 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 761 union set_pixel_clock args; 762 763 memset(&args, 0, sizeof(args)); 764 765 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 766 &crev)) 767 return; 768 769 switch (frev) { 770 case 1: 771 switch (crev) { 772 case 1: 773 if (clock == ATOM_DISABLE) 774 return; 775 args.v1.usPixelClock = cpu_to_le16(clock / 10); 776 args.v1.usRefDiv = cpu_to_le16(ref_div); 777 args.v1.usFbDiv = cpu_to_le16(fb_div); 778 args.v1.ucFracFbDiv = frac_fb_div; 779 args.v1.ucPostDiv = post_div; 780 args.v1.ucPpll = pll_id; 781 args.v1.ucCRTC = crtc_id; 782 args.v1.ucRefDivSrc = 1; 783 break; 784 case 2: 785 args.v2.usPixelClock = cpu_to_le16(clock / 10); 786 args.v2.usRefDiv = cpu_to_le16(ref_div); 787 args.v2.usFbDiv = cpu_to_le16(fb_div); 788 args.v2.ucFracFbDiv = frac_fb_div; 789 args.v2.ucPostDiv = post_div; 790 args.v2.ucPpll = pll_id; 791 args.v2.ucCRTC = crtc_id; 792 args.v2.ucRefDivSrc = 1; 793 break; 794 case 3: 795 args.v3.usPixelClock = cpu_to_le16(clock / 10); 796 args.v3.usRefDiv = cpu_to_le16(ref_div); 797 args.v3.usFbDiv = cpu_to_le16(fb_div); 798 args.v3.ucFracFbDiv = frac_fb_div; 799 args.v3.ucPostDiv = post_div; 800 args.v3.ucPpll = pll_id; 801 args.v3.ucMiscInfo = (pll_id << 2); 802 args.v3.ucTransmitterId = encoder_id; 803 args.v3.ucEncoderMode = encoder_mode; 804 break; 805 case 5: 806 args.v5.ucCRTC = crtc_id; 807 args.v5.usPixelClock = cpu_to_le16(clock / 10); 808 args.v5.ucRefDiv = ref_div; 809 args.v5.usFbDiv = cpu_to_le16(fb_div); 810 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 811 args.v5.ucPostDiv = post_div; 812 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ 813 args.v5.ucTransmitterID = encoder_id; 814 args.v5.ucEncoderMode = encoder_mode; 815 args.v5.ucPpll = pll_id; 816 break; 817 case 6: 818 args.v6.ulCrtcPclkFreq.ucCRTC = crtc_id; 819 args.v6.ulCrtcPclkFreq.ulPixelClock = cpu_to_le32(clock / 10); 820 args.v6.ucRefDiv = ref_div; 821 args.v6.usFbDiv = cpu_to_le16(fb_div); 822 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 823 args.v6.ucPostDiv = post_div; 824 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ 825 args.v6.ucTransmitterID = encoder_id; 826 args.v6.ucEncoderMode = encoder_mode; 827 args.v6.ucPpll = pll_id; 828 break; 829 default: 830 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 831 return; 832 } 833 break; 834 default: 835 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 836 return; 837 } 838 839 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 840 } 841 842 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 843 { 844 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 845 struct drm_device *dev = crtc->dev; 846 struct radeon_device *rdev = dev->dev_private; 847 struct drm_encoder *encoder = NULL; 848 struct radeon_encoder *radeon_encoder = NULL; 849 u32 pll_clock = mode->clock; 850 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; 851 struct radeon_pll *pll; 852 u32 adjusted_clock; 853 int encoder_mode = 0; 854 struct radeon_atom_ss ss; 855 bool ss_enabled = false; 856 857 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 858 if (encoder->crtc == crtc) { 859 radeon_encoder = to_radeon_encoder(encoder); 860 encoder_mode = atombios_get_encoder_mode(encoder); 861 break; 862 } 863 } 864 865 if (!radeon_encoder) 866 return; 867 868 switch (radeon_crtc->pll_id) { 869 case ATOM_PPLL1: 870 pll = &rdev->clock.p1pll; 871 break; 872 case ATOM_PPLL2: 873 pll = &rdev->clock.p2pll; 874 break; 875 case ATOM_DCPLL: 876 case ATOM_PPLL_INVALID: 877 default: 878 pll = &rdev->clock.dcpll; 879 break; 880 } 881 882 if (radeon_encoder->active_device & 883 (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) { 884 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 885 struct drm_connector *connector = 886 radeon_get_connector_for_encoder(encoder); 887 struct radeon_connector *radeon_connector = 888 to_radeon_connector(connector); 889 struct radeon_connector_atom_dig *dig_connector = 890 radeon_connector->con_priv; 891 int dp_clock; 892 893 switch (encoder_mode) { 894 case ATOM_ENCODER_MODE_DP: 895 /* DP/eDP */ 896 dp_clock = dig_connector->dp_clock / 10; 897 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { 898 if (ASIC_IS_DCE4(rdev)) 899 ss_enabled = 900 radeon_atombios_get_asic_ss_info(rdev, &ss, 901 dig->lcd_ss_id, 902 dp_clock); 903 else 904 ss_enabled = 905 radeon_atombios_get_ppll_ss_info(rdev, &ss, 906 dig->lcd_ss_id); 907 } else { 908 if (ASIC_IS_DCE4(rdev)) 909 ss_enabled = 910 radeon_atombios_get_asic_ss_info(rdev, &ss, 911 ASIC_INTERNAL_SS_ON_DP, 912 dp_clock); 913 else { 914 if (dp_clock == 16200) { 915 ss_enabled = 916 radeon_atombios_get_ppll_ss_info(rdev, &ss, 917 ATOM_DP_SS_ID2); 918 if (!ss_enabled) 919 ss_enabled = 920 radeon_atombios_get_ppll_ss_info(rdev, &ss, 921 ATOM_DP_SS_ID1); 922 } else 923 ss_enabled = 924 radeon_atombios_get_ppll_ss_info(rdev, &ss, 925 ATOM_DP_SS_ID1); 926 } 927 } 928 break; 929 case ATOM_ENCODER_MODE_LVDS: 930 if (ASIC_IS_DCE4(rdev)) 931 ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, 932 dig->lcd_ss_id, 933 mode->clock / 10); 934 else 935 ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss, 936 dig->lcd_ss_id); 937 break; 938 case ATOM_ENCODER_MODE_DVI: 939 if (ASIC_IS_DCE4(rdev)) 940 ss_enabled = 941 radeon_atombios_get_asic_ss_info(rdev, &ss, 942 ASIC_INTERNAL_SS_ON_TMDS, 943 mode->clock / 10); 944 break; 945 case ATOM_ENCODER_MODE_HDMI: 946 if (ASIC_IS_DCE4(rdev)) 947 ss_enabled = 948 radeon_atombios_get_asic_ss_info(rdev, &ss, 949 ASIC_INTERNAL_SS_ON_HDMI, 950 mode->clock / 10); 951 break; 952 default: 953 break; 954 } 955 } 956 957 /* adjust pixel clock as needed */ 958 adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss); 959 960 if (ASIC_IS_AVIVO(rdev)) 961 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, 962 &ref_div, &post_div); 963 else 964 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, 965 &ref_div, &post_div); 966 967 atombios_crtc_program_ss(crtc, ATOM_DISABLE, radeon_crtc->pll_id, &ss); 968 969 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 970 encoder_mode, radeon_encoder->encoder_id, mode->clock, 971 ref_div, fb_div, frac_fb_div, post_div); 972 973 if (ss_enabled) { 974 /* calculate ss amount and step size */ 975 if (ASIC_IS_DCE4(rdev)) { 976 u32 step_size; 977 u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000; 978 ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; 979 ss.amount |= ((amount - (ss.amount * 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & 980 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK; 981 if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) 982 step_size = (4 * amount * ref_div * (ss.rate * 2048)) / 983 (125 * 25 * pll->reference_freq / 100); 984 else 985 step_size = (2 * amount * ref_div * (ss.rate * 2048)) / 986 (125 * 25 * pll->reference_freq / 100); 987 ss.step = step_size; 988 } 989 990 atombios_crtc_program_ss(crtc, ATOM_ENABLE, radeon_crtc->pll_id, &ss); 991 } 992 } 993 994 static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 995 struct drm_framebuffer *fb, 996 int x, int y, int atomic) 997 { 998 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 999 struct drm_device *dev = crtc->dev; 1000 struct radeon_device *rdev = dev->dev_private; 1001 struct radeon_framebuffer *radeon_fb; 1002 struct drm_framebuffer *target_fb; 1003 struct drm_gem_object *obj; 1004 struct radeon_bo *rbo; 1005 uint64_t fb_location; 1006 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1007 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); 1008 int r; 1009 1010 /* no fb bound */ 1011 if (!atomic && !crtc->fb) { 1012 DRM_DEBUG_KMS("No FB bound\n"); 1013 return 0; 1014 } 1015 1016 if (atomic) { 1017 radeon_fb = to_radeon_framebuffer(fb); 1018 target_fb = fb; 1019 } 1020 else { 1021 radeon_fb = to_radeon_framebuffer(crtc->fb); 1022 target_fb = crtc->fb; 1023 } 1024 1025 /* If atomic, assume fb object is pinned & idle & fenced and 1026 * just update base pointers 1027 */ 1028 obj = radeon_fb->obj; 1029 rbo = obj->driver_private; 1030 r = radeon_bo_reserve(rbo, false); 1031 if (unlikely(r != 0)) 1032 return r; 1033 1034 if (atomic) 1035 fb_location = radeon_bo_gpu_offset(rbo); 1036 else { 1037 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); 1038 if (unlikely(r != 0)) { 1039 radeon_bo_unreserve(rbo); 1040 return -EINVAL; 1041 } 1042 } 1043 1044 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1045 radeon_bo_unreserve(rbo); 1046 1047 switch (target_fb->bits_per_pixel) { 1048 case 8: 1049 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | 1050 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); 1051 break; 1052 case 15: 1053 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1054 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); 1055 break; 1056 case 16: 1057 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1058 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); 1059 #ifdef __BIG_ENDIAN 1060 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1061 #endif 1062 break; 1063 case 24: 1064 case 32: 1065 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1066 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); 1067 #ifdef __BIG_ENDIAN 1068 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1069 #endif 1070 break; 1071 default: 1072 DRM_ERROR("Unsupported screen depth %d\n", 1073 target_fb->bits_per_pixel); 1074 return -EINVAL; 1075 } 1076 1077 if (tiling_flags & RADEON_TILING_MACRO) 1078 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); 1079 else if (tiling_flags & RADEON_TILING_MICRO) 1080 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); 1081 1082 switch (radeon_crtc->crtc_id) { 1083 case 0: 1084 WREG32(AVIVO_D1VGA_CONTROL, 0); 1085 break; 1086 case 1: 1087 WREG32(AVIVO_D2VGA_CONTROL, 0); 1088 break; 1089 case 2: 1090 WREG32(EVERGREEN_D3VGA_CONTROL, 0); 1091 break; 1092 case 3: 1093 WREG32(EVERGREEN_D4VGA_CONTROL, 0); 1094 break; 1095 case 4: 1096 WREG32(EVERGREEN_D5VGA_CONTROL, 0); 1097 break; 1098 case 5: 1099 WREG32(EVERGREEN_D6VGA_CONTROL, 0); 1100 break; 1101 default: 1102 break; 1103 } 1104 1105 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 1106 upper_32_bits(fb_location)); 1107 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 1108 upper_32_bits(fb_location)); 1109 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1110 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1111 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1112 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1113 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1114 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1115 1116 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1117 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1118 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); 1119 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); 1120 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); 1121 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); 1122 1123 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8); 1124 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 1125 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1126 1127 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1128 crtc->mode.vdisplay); 1129 x &= ~3; 1130 y &= ~1; 1131 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, 1132 (x << 16) | y); 1133 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1134 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); 1135 1136 if (!atomic && fb && fb != crtc->fb) { 1137 radeon_fb = to_radeon_framebuffer(fb); 1138 rbo = radeon_fb->obj->driver_private; 1139 r = radeon_bo_reserve(rbo, false); 1140 if (unlikely(r != 0)) 1141 return r; 1142 radeon_bo_unpin(rbo); 1143 radeon_bo_unreserve(rbo); 1144 } 1145 1146 /* Bytes per pixel may have changed */ 1147 radeon_bandwidth_update(rdev); 1148 1149 return 0; 1150 } 1151 1152 static int avivo_crtc_do_set_base(struct drm_crtc *crtc, 1153 struct drm_framebuffer *fb, 1154 int x, int y, int atomic) 1155 { 1156 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1157 struct drm_device *dev = crtc->dev; 1158 struct radeon_device *rdev = dev->dev_private; 1159 struct radeon_framebuffer *radeon_fb; 1160 struct drm_gem_object *obj; 1161 struct radeon_bo *rbo; 1162 struct drm_framebuffer *target_fb; 1163 uint64_t fb_location; 1164 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1165 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; 1166 int r; 1167 1168 /* no fb bound */ 1169 if (!atomic && !crtc->fb) { 1170 DRM_DEBUG_KMS("No FB bound\n"); 1171 return 0; 1172 } 1173 1174 if (atomic) { 1175 radeon_fb = to_radeon_framebuffer(fb); 1176 target_fb = fb; 1177 } 1178 else { 1179 radeon_fb = to_radeon_framebuffer(crtc->fb); 1180 target_fb = crtc->fb; 1181 } 1182 1183 obj = radeon_fb->obj; 1184 rbo = obj->driver_private; 1185 r = radeon_bo_reserve(rbo, false); 1186 if (unlikely(r != 0)) 1187 return r; 1188 1189 /* If atomic, assume fb object is pinned & idle & fenced and 1190 * just update base pointers 1191 */ 1192 if (atomic) 1193 fb_location = radeon_bo_gpu_offset(rbo); 1194 else { 1195 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); 1196 if (unlikely(r != 0)) { 1197 radeon_bo_unreserve(rbo); 1198 return -EINVAL; 1199 } 1200 } 1201 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1202 radeon_bo_unreserve(rbo); 1203 1204 switch (target_fb->bits_per_pixel) { 1205 case 8: 1206 fb_format = 1207 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | 1208 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; 1209 break; 1210 case 15: 1211 fb_format = 1212 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1213 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; 1214 break; 1215 case 16: 1216 fb_format = 1217 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1218 AVIVO_D1GRPH_CONTROL_16BPP_RGB565; 1219 #ifdef __BIG_ENDIAN 1220 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 1221 #endif 1222 break; 1223 case 24: 1224 case 32: 1225 fb_format = 1226 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | 1227 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; 1228 #ifdef __BIG_ENDIAN 1229 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; 1230 #endif 1231 break; 1232 default: 1233 DRM_ERROR("Unsupported screen depth %d\n", 1234 target_fb->bits_per_pixel); 1235 return -EINVAL; 1236 } 1237 1238 if (rdev->family >= CHIP_R600) { 1239 if (tiling_flags & RADEON_TILING_MACRO) 1240 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1; 1241 else if (tiling_flags & RADEON_TILING_MICRO) 1242 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1; 1243 } else { 1244 if (tiling_flags & RADEON_TILING_MACRO) 1245 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; 1246 1247 if (tiling_flags & RADEON_TILING_MICRO) 1248 fb_format |= AVIVO_D1GRPH_TILED; 1249 } 1250 1251 if (radeon_crtc->crtc_id == 0) 1252 WREG32(AVIVO_D1VGA_CONTROL, 0); 1253 else 1254 WREG32(AVIVO_D2VGA_CONTROL, 0); 1255 1256 if (rdev->family >= CHIP_RV770) { 1257 if (radeon_crtc->crtc_id) { 1258 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1259 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1260 } else { 1261 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1262 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1263 } 1264 } 1265 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1266 (u32) fb_location); 1267 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + 1268 radeon_crtc->crtc_offset, (u32) fb_location); 1269 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1270 if (rdev->family >= CHIP_R600) 1271 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1272 1273 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1274 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1275 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); 1276 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); 1277 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); 1278 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); 1279 1280 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8); 1281 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 1282 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1283 1284 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1285 crtc->mode.vdisplay); 1286 x &= ~3; 1287 y &= ~1; 1288 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, 1289 (x << 16) | y); 1290 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1291 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); 1292 1293 if (!atomic && fb && fb != crtc->fb) { 1294 radeon_fb = to_radeon_framebuffer(fb); 1295 rbo = radeon_fb->obj->driver_private; 1296 r = radeon_bo_reserve(rbo, false); 1297 if (unlikely(r != 0)) 1298 return r; 1299 radeon_bo_unpin(rbo); 1300 radeon_bo_unreserve(rbo); 1301 } 1302 1303 /* Bytes per pixel may have changed */ 1304 radeon_bandwidth_update(rdev); 1305 1306 return 0; 1307 } 1308 1309 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 1310 struct drm_framebuffer *old_fb) 1311 { 1312 struct drm_device *dev = crtc->dev; 1313 struct radeon_device *rdev = dev->dev_private; 1314 1315 if (ASIC_IS_DCE4(rdev)) 1316 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0); 1317 else if (ASIC_IS_AVIVO(rdev)) 1318 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0); 1319 else 1320 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); 1321 } 1322 1323 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 1324 struct drm_framebuffer *fb, 1325 int x, int y, enum mode_set_atomic state) 1326 { 1327 struct drm_device *dev = crtc->dev; 1328 struct radeon_device *rdev = dev->dev_private; 1329 1330 if (ASIC_IS_DCE4(rdev)) 1331 return dce4_crtc_do_set_base(crtc, fb, x, y, 1); 1332 else if (ASIC_IS_AVIVO(rdev)) 1333 return avivo_crtc_do_set_base(crtc, fb, x, y, 1); 1334 else 1335 return radeon_crtc_do_set_base(crtc, fb, x, y, 1); 1336 } 1337 1338 /* properly set additional regs when using atombios */ 1339 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) 1340 { 1341 struct drm_device *dev = crtc->dev; 1342 struct radeon_device *rdev = dev->dev_private; 1343 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1344 u32 disp_merge_cntl; 1345 1346 switch (radeon_crtc->crtc_id) { 1347 case 0: 1348 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); 1349 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 1350 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); 1351 break; 1352 case 1: 1353 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 1354 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 1355 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); 1356 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); 1357 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); 1358 break; 1359 } 1360 } 1361 1362 static int radeon_atom_pick_pll(struct drm_crtc *crtc) 1363 { 1364 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1365 struct drm_device *dev = crtc->dev; 1366 struct radeon_device *rdev = dev->dev_private; 1367 struct drm_encoder *test_encoder; 1368 struct drm_crtc *test_crtc; 1369 uint32_t pll_in_use = 0; 1370 1371 if (ASIC_IS_DCE4(rdev)) { 1372 /* if crtc is driving DP and we have an ext clock, use that */ 1373 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 1374 if (test_encoder->crtc && (test_encoder->crtc == crtc)) { 1375 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) { 1376 if (rdev->clock.dp_extclk) 1377 return ATOM_PPLL_INVALID; 1378 } 1379 } 1380 } 1381 1382 /* otherwise, pick one of the plls */ 1383 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1384 struct radeon_crtc *radeon_test_crtc; 1385 1386 if (crtc == test_crtc) 1387 continue; 1388 1389 radeon_test_crtc = to_radeon_crtc(test_crtc); 1390 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) && 1391 (radeon_test_crtc->pll_id <= ATOM_PPLL2)) 1392 pll_in_use |= (1 << radeon_test_crtc->pll_id); 1393 } 1394 if (!(pll_in_use & 1)) 1395 return ATOM_PPLL1; 1396 return ATOM_PPLL2; 1397 } else 1398 return radeon_crtc->crtc_id; 1399 1400 } 1401 1402 int atombios_crtc_mode_set(struct drm_crtc *crtc, 1403 struct drm_display_mode *mode, 1404 struct drm_display_mode *adjusted_mode, 1405 int x, int y, struct drm_framebuffer *old_fb) 1406 { 1407 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1408 struct drm_device *dev = crtc->dev; 1409 struct radeon_device *rdev = dev->dev_private; 1410 struct drm_encoder *encoder; 1411 bool is_tvcv = false; 1412 1413 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1414 /* find tv std */ 1415 if (encoder->crtc == crtc) { 1416 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1417 if (radeon_encoder->active_device & 1418 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 1419 is_tvcv = true; 1420 } 1421 } 1422 1423 /* always set DCPLL */ 1424 if (ASIC_IS_DCE4(rdev)) { 1425 struct radeon_atom_ss ss; 1426 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, 1427 ASIC_INTERNAL_SS_ON_DCPLL, 1428 rdev->clock.default_dispclk); 1429 if (ss_enabled) 1430 atombios_crtc_program_ss(crtc, ATOM_DISABLE, ATOM_DCPLL, &ss); 1431 /* XXX: DCE5, make sure voltage, dispclk is high enough */ 1432 atombios_crtc_set_dcpll(crtc, rdev->clock.default_dispclk); 1433 if (ss_enabled) 1434 atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL, &ss); 1435 } 1436 atombios_crtc_set_pll(crtc, adjusted_mode); 1437 1438 if (ASIC_IS_DCE4(rdev)) 1439 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1440 else if (ASIC_IS_AVIVO(rdev)) { 1441 if (is_tvcv) 1442 atombios_crtc_set_timing(crtc, adjusted_mode); 1443 else 1444 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1445 } else { 1446 atombios_crtc_set_timing(crtc, adjusted_mode); 1447 if (radeon_crtc->crtc_id == 0) 1448 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1449 radeon_legacy_atom_fixup(crtc); 1450 } 1451 atombios_crtc_set_base(crtc, x, y, old_fb); 1452 atombios_overscan_setup(crtc, mode, adjusted_mode); 1453 atombios_scaler_setup(crtc); 1454 return 0; 1455 } 1456 1457 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, 1458 struct drm_display_mode *mode, 1459 struct drm_display_mode *adjusted_mode) 1460 { 1461 struct drm_device *dev = crtc->dev; 1462 struct radeon_device *rdev = dev->dev_private; 1463 1464 /* adjust pm to upcoming mode change */ 1465 radeon_pm_compute_clocks(rdev); 1466 1467 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 1468 return false; 1469 return true; 1470 } 1471 1472 static void atombios_crtc_prepare(struct drm_crtc *crtc) 1473 { 1474 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1475 1476 /* pick pll */ 1477 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); 1478 1479 atombios_lock_crtc(crtc, ATOM_ENABLE); 1480 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1481 } 1482 1483 static void atombios_crtc_commit(struct drm_crtc *crtc) 1484 { 1485 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 1486 atombios_lock_crtc(crtc, ATOM_DISABLE); 1487 } 1488 1489 static void atombios_crtc_disable(struct drm_crtc *crtc) 1490 { 1491 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1492 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1493 1494 switch (radeon_crtc->pll_id) { 1495 case ATOM_PPLL1: 1496 case ATOM_PPLL2: 1497 /* disable the ppll */ 1498 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 1499 0, 0, ATOM_DISABLE, 0, 0, 0, 0); 1500 break; 1501 default: 1502 break; 1503 } 1504 radeon_crtc->pll_id = -1; 1505 } 1506 1507 static const struct drm_crtc_helper_funcs atombios_helper_funcs = { 1508 .dpms = atombios_crtc_dpms, 1509 .mode_fixup = atombios_crtc_mode_fixup, 1510 .mode_set = atombios_crtc_mode_set, 1511 .mode_set_base = atombios_crtc_set_base, 1512 .mode_set_base_atomic = atombios_crtc_set_base_atomic, 1513 .prepare = atombios_crtc_prepare, 1514 .commit = atombios_crtc_commit, 1515 .load_lut = radeon_crtc_load_lut, 1516 .disable = atombios_crtc_disable, 1517 }; 1518 1519 void radeon_atombios_init_crtc(struct drm_device *dev, 1520 struct radeon_crtc *radeon_crtc) 1521 { 1522 struct radeon_device *rdev = dev->dev_private; 1523 1524 if (ASIC_IS_DCE4(rdev)) { 1525 switch (radeon_crtc->crtc_id) { 1526 case 0: 1527 default: 1528 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; 1529 break; 1530 case 1: 1531 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; 1532 break; 1533 case 2: 1534 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; 1535 break; 1536 case 3: 1537 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; 1538 break; 1539 case 4: 1540 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; 1541 break; 1542 case 5: 1543 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; 1544 break; 1545 } 1546 } else { 1547 if (radeon_crtc->crtc_id == 1) 1548 radeon_crtc->crtc_offset = 1549 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; 1550 else 1551 radeon_crtc->crtc_offset = 0; 1552 } 1553 radeon_crtc->pll_id = -1; 1554 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); 1555 } 1556