1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_crtc_helper.h> 28 #include <drm/radeon_drm.h> 29 #include "radeon_fixed.h" 30 #include "radeon.h" 31 #include "atom.h" 32 #include "atom-bits.h" 33 34 static void atombios_overscan_setup(struct drm_crtc *crtc, 35 struct drm_display_mode *mode, 36 struct drm_display_mode *adjusted_mode) 37 { 38 struct drm_device *dev = crtc->dev; 39 struct radeon_device *rdev = dev->dev_private; 40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 41 SET_CRTC_OVERSCAN_PS_ALLOCATION args; 42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); 43 int a1, a2; 44 45 memset(&args, 0, sizeof(args)); 46 47 args.usOverscanRight = 0; 48 args.usOverscanLeft = 0; 49 args.usOverscanBottom = 0; 50 args.usOverscanTop = 0; 51 args.ucCRTC = radeon_crtc->crtc_id; 52 53 switch (radeon_crtc->rmx_type) { 54 case RMX_CENTER: 55 args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; 56 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; 57 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; 58 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; 59 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 60 break; 61 case RMX_ASPECT: 62 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; 63 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; 64 65 if (a1 > a2) { 66 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; 67 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; 68 } else if (a2 > a1) { 69 args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; 70 args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; 71 } 72 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 73 break; 74 case RMX_FULL: 75 default: 76 args.usOverscanRight = 0; 77 args.usOverscanLeft = 0; 78 args.usOverscanBottom = 0; 79 args.usOverscanTop = 0; 80 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 81 break; 82 } 83 } 84 85 static void atombios_scaler_setup(struct drm_crtc *crtc) 86 { 87 struct drm_device *dev = crtc->dev; 88 struct radeon_device *rdev = dev->dev_private; 89 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 90 ENABLE_SCALER_PS_ALLOCATION args; 91 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); 92 93 /* fixme - fill in enc_priv for atom dac */ 94 enum radeon_tv_std tv_std = TV_STD_NTSC; 95 bool is_tv = false, is_cv = false; 96 struct drm_encoder *encoder; 97 98 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) 99 return; 100 101 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 102 /* find tv std */ 103 if (encoder->crtc == crtc) { 104 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 105 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 106 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 107 tv_std = tv_dac->tv_std; 108 is_tv = true; 109 } 110 } 111 } 112 113 memset(&args, 0, sizeof(args)); 114 115 args.ucScaler = radeon_crtc->crtc_id; 116 117 if (is_tv) { 118 switch (tv_std) { 119 case TV_STD_NTSC: 120 default: 121 args.ucTVStandard = ATOM_TV_NTSC; 122 break; 123 case TV_STD_PAL: 124 args.ucTVStandard = ATOM_TV_PAL; 125 break; 126 case TV_STD_PAL_M: 127 args.ucTVStandard = ATOM_TV_PALM; 128 break; 129 case TV_STD_PAL_60: 130 args.ucTVStandard = ATOM_TV_PAL60; 131 break; 132 case TV_STD_NTSC_J: 133 args.ucTVStandard = ATOM_TV_NTSCJ; 134 break; 135 case TV_STD_SCART_PAL: 136 args.ucTVStandard = ATOM_TV_PAL; /* ??? */ 137 break; 138 case TV_STD_SECAM: 139 args.ucTVStandard = ATOM_TV_SECAM; 140 break; 141 case TV_STD_PAL_CN: 142 args.ucTVStandard = ATOM_TV_PALCN; 143 break; 144 } 145 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 146 } else if (is_cv) { 147 args.ucTVStandard = ATOM_TV_CV; 148 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 149 } else { 150 switch (radeon_crtc->rmx_type) { 151 case RMX_FULL: 152 args.ucEnable = ATOM_SCALER_EXPANSION; 153 break; 154 case RMX_CENTER: 155 args.ucEnable = ATOM_SCALER_CENTER; 156 break; 157 case RMX_ASPECT: 158 args.ucEnable = ATOM_SCALER_EXPANSION; 159 break; 160 default: 161 if (ASIC_IS_AVIVO(rdev)) 162 args.ucEnable = ATOM_SCALER_DISABLE; 163 else 164 args.ucEnable = ATOM_SCALER_CENTER; 165 break; 166 } 167 } 168 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 169 if ((is_tv || is_cv) 170 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { 171 atom_rv515_force_tv_scaler(rdev, radeon_crtc); 172 } 173 } 174 175 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) 176 { 177 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 178 struct drm_device *dev = crtc->dev; 179 struct radeon_device *rdev = dev->dev_private; 180 int index = 181 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); 182 ENABLE_CRTC_PS_ALLOCATION args; 183 184 memset(&args, 0, sizeof(args)); 185 186 args.ucCRTC = radeon_crtc->crtc_id; 187 args.ucEnable = lock; 188 189 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 190 } 191 192 static void atombios_enable_crtc(struct drm_crtc *crtc, int state) 193 { 194 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 195 struct drm_device *dev = crtc->dev; 196 struct radeon_device *rdev = dev->dev_private; 197 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); 198 ENABLE_CRTC_PS_ALLOCATION args; 199 200 memset(&args, 0, sizeof(args)); 201 202 args.ucCRTC = radeon_crtc->crtc_id; 203 args.ucEnable = state; 204 205 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 206 } 207 208 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) 209 { 210 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 211 struct drm_device *dev = crtc->dev; 212 struct radeon_device *rdev = dev->dev_private; 213 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); 214 ENABLE_CRTC_PS_ALLOCATION args; 215 216 memset(&args, 0, sizeof(args)); 217 218 args.ucCRTC = radeon_crtc->crtc_id; 219 args.ucEnable = state; 220 221 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 222 } 223 224 static void atombios_blank_crtc(struct drm_crtc *crtc, int state) 225 { 226 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 227 struct drm_device *dev = crtc->dev; 228 struct radeon_device *rdev = dev->dev_private; 229 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); 230 BLANK_CRTC_PS_ALLOCATION args; 231 232 memset(&args, 0, sizeof(args)); 233 234 args.ucCRTC = radeon_crtc->crtc_id; 235 args.ucBlanking = state; 236 237 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 238 } 239 240 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) 241 { 242 struct drm_device *dev = crtc->dev; 243 struct radeon_device *rdev = dev->dev_private; 244 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 245 246 switch (mode) { 247 case DRM_MODE_DPMS_ON: 248 atombios_enable_crtc(crtc, 1); 249 if (ASIC_IS_DCE3(rdev)) 250 atombios_enable_crtc_memreq(crtc, 1); 251 atombios_blank_crtc(crtc, 0); 252 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); 253 radeon_crtc_load_lut(crtc); 254 break; 255 case DRM_MODE_DPMS_STANDBY: 256 case DRM_MODE_DPMS_SUSPEND: 257 case DRM_MODE_DPMS_OFF: 258 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); 259 atombios_blank_crtc(crtc, 1); 260 if (ASIC_IS_DCE3(rdev)) 261 atombios_enable_crtc_memreq(crtc, 0); 262 atombios_enable_crtc(crtc, 0); 263 break; 264 } 265 } 266 267 static void 268 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, 269 struct drm_display_mode *mode) 270 { 271 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 272 struct drm_device *dev = crtc->dev; 273 struct radeon_device *rdev = dev->dev_private; 274 SET_CRTC_USING_DTD_TIMING_PARAMETERS args; 275 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); 276 u16 misc = 0; 277 278 memset(&args, 0, sizeof(args)); 279 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay); 280 args.usH_Blanking_Time = 281 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay); 282 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay); 283 args.usV_Blanking_Time = 284 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay); 285 args.usH_SyncOffset = 286 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay); 287 args.usH_SyncWidth = 288 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 289 args.usV_SyncOffset = 290 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay); 291 args.usV_SyncWidth = 292 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 293 /*args.ucH_Border = mode->hborder;*/ 294 /*args.ucV_Border = mode->vborder;*/ 295 296 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 297 misc |= ATOM_VSYNC_POLARITY; 298 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 299 misc |= ATOM_HSYNC_POLARITY; 300 if (mode->flags & DRM_MODE_FLAG_CSYNC) 301 misc |= ATOM_COMPOSITESYNC; 302 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 303 misc |= ATOM_INTERLACE; 304 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 305 misc |= ATOM_DOUBLE_CLOCK_MODE; 306 307 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 308 args.ucCRTC = radeon_crtc->crtc_id; 309 310 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 311 } 312 313 static void atombios_crtc_set_timing(struct drm_crtc *crtc, 314 struct drm_display_mode *mode) 315 { 316 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 317 struct drm_device *dev = crtc->dev; 318 struct radeon_device *rdev = dev->dev_private; 319 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; 320 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); 321 u16 misc = 0; 322 323 memset(&args, 0, sizeof(args)); 324 args.usH_Total = cpu_to_le16(mode->crtc_htotal); 325 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); 326 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); 327 args.usH_SyncWidth = 328 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 329 args.usV_Total = cpu_to_le16(mode->crtc_vtotal); 330 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); 331 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); 332 args.usV_SyncWidth = 333 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 334 335 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 336 misc |= ATOM_VSYNC_POLARITY; 337 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 338 misc |= ATOM_HSYNC_POLARITY; 339 if (mode->flags & DRM_MODE_FLAG_CSYNC) 340 misc |= ATOM_COMPOSITESYNC; 341 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 342 misc |= ATOM_INTERLACE; 343 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 344 misc |= ATOM_DOUBLE_CLOCK_MODE; 345 346 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 347 args.ucCRTC = radeon_crtc->crtc_id; 348 349 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 350 } 351 352 static void atombios_set_ss(struct drm_crtc *crtc, int enable) 353 { 354 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 355 struct drm_device *dev = crtc->dev; 356 struct radeon_device *rdev = dev->dev_private; 357 struct drm_encoder *encoder = NULL; 358 struct radeon_encoder *radeon_encoder = NULL; 359 struct radeon_encoder_atom_dig *dig = NULL; 360 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); 361 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION args; 362 ENABLE_LVDS_SS_PARAMETERS legacy_args; 363 uint16_t percentage = 0; 364 uint8_t type = 0, step = 0, delay = 0, range = 0; 365 366 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 367 if (encoder->crtc == crtc) { 368 radeon_encoder = to_radeon_encoder(encoder); 369 /* only enable spread spectrum on LVDS */ 370 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 371 dig = radeon_encoder->enc_priv; 372 if (dig && dig->ss) { 373 percentage = dig->ss->percentage; 374 type = dig->ss->type; 375 step = dig->ss->step; 376 delay = dig->ss->delay; 377 range = dig->ss->range; 378 } else if (enable) 379 return; 380 } else if (enable) 381 return; 382 break; 383 } 384 } 385 386 if (!radeon_encoder) 387 return; 388 389 if (ASIC_IS_AVIVO(rdev)) { 390 memset(&args, 0, sizeof(args)); 391 args.usSpreadSpectrumPercentage = cpu_to_le16(percentage); 392 args.ucSpreadSpectrumType = type; 393 args.ucSpreadSpectrumStep = step; 394 args.ucSpreadSpectrumDelay = delay; 395 args.ucSpreadSpectrumRange = range; 396 args.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; 397 args.ucEnable = enable; 398 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 399 } else { 400 memset(&legacy_args, 0, sizeof(legacy_args)); 401 legacy_args.usSpreadSpectrumPercentage = cpu_to_le16(percentage); 402 legacy_args.ucSpreadSpectrumType = type; 403 legacy_args.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2; 404 legacy_args.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4; 405 legacy_args.ucEnable = enable; 406 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&legacy_args); 407 } 408 } 409 410 union adjust_pixel_clock { 411 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; 412 }; 413 414 static u32 atombios_adjust_pll(struct drm_crtc *crtc, 415 struct drm_display_mode *mode, 416 struct radeon_pll *pll) 417 { 418 struct drm_device *dev = crtc->dev; 419 struct radeon_device *rdev = dev->dev_private; 420 struct drm_encoder *encoder = NULL; 421 struct radeon_encoder *radeon_encoder = NULL; 422 u32 adjusted_clock = mode->clock; 423 424 /* reset the pll flags */ 425 pll->flags = 0; 426 427 if (ASIC_IS_AVIVO(rdev)) { 428 if ((rdev->family == CHIP_RS600) || 429 (rdev->family == CHIP_RS690) || 430 (rdev->family == CHIP_RS740)) 431 pll->flags |= (RADEON_PLL_USE_FRAC_FB_DIV | 432 RADEON_PLL_PREFER_CLOSEST_LOWER); 433 434 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ 435 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 436 else 437 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 438 } else { 439 pll->flags |= RADEON_PLL_LEGACY; 440 441 if (mode->clock > 200000) /* range limits??? */ 442 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 443 else 444 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 445 446 } 447 448 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 449 if (encoder->crtc == crtc) { 450 radeon_encoder = to_radeon_encoder(encoder); 451 if (ASIC_IS_AVIVO(rdev)) { 452 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ 453 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) 454 adjusted_clock = mode->clock * 2; 455 } else { 456 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 457 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; 458 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) 459 pll->flags |= RADEON_PLL_USE_REF_DIV; 460 } 461 break; 462 } 463 } 464 465 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock 466 * accordingly based on the encoder/transmitter to work around 467 * special hw requirements. 468 */ 469 if (ASIC_IS_DCE3(rdev)) { 470 union adjust_pixel_clock args; 471 struct radeon_encoder_atom_dig *dig; 472 u8 frev, crev; 473 int index; 474 475 if (!radeon_encoder->enc_priv) 476 return adjusted_clock; 477 dig = radeon_encoder->enc_priv; 478 479 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); 480 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 481 &crev); 482 483 memset(&args, 0, sizeof(args)); 484 485 switch (frev) { 486 case 1: 487 switch (crev) { 488 case 1: 489 case 2: 490 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); 491 args.v1.ucTransmitterID = radeon_encoder->encoder_id; 492 args.v1.ucEncodeMode = atombios_get_encoder_mode(encoder); 493 494 atom_execute_table(rdev->mode_info.atom_context, 495 index, (uint32_t *)&args); 496 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; 497 break; 498 default: 499 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 500 return adjusted_clock; 501 } 502 break; 503 default: 504 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 505 return adjusted_clock; 506 } 507 } 508 return adjusted_clock; 509 } 510 511 union set_pixel_clock { 512 SET_PIXEL_CLOCK_PS_ALLOCATION base; 513 PIXEL_CLOCK_PARAMETERS v1; 514 PIXEL_CLOCK_PARAMETERS_V2 v2; 515 PIXEL_CLOCK_PARAMETERS_V3 v3; 516 }; 517 518 void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 519 { 520 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 521 struct drm_device *dev = crtc->dev; 522 struct radeon_device *rdev = dev->dev_private; 523 struct drm_encoder *encoder = NULL; 524 struct radeon_encoder *radeon_encoder = NULL; 525 u8 frev, crev; 526 int index; 527 union set_pixel_clock args; 528 u32 pll_clock = mode->clock; 529 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; 530 struct radeon_pll *pll; 531 u32 adjusted_clock; 532 533 memset(&args, 0, sizeof(args)); 534 535 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 536 if (encoder->crtc == crtc) { 537 radeon_encoder = to_radeon_encoder(encoder); 538 break; 539 } 540 } 541 542 if (!radeon_encoder) 543 return; 544 545 if (radeon_crtc->crtc_id == 0) 546 pll = &rdev->clock.p1pll; 547 else 548 pll = &rdev->clock.p2pll; 549 550 /* adjust pixel clock as needed */ 551 adjusted_clock = atombios_adjust_pll(crtc, mode, pll); 552 553 if (ASIC_IS_AVIVO(rdev)) { 554 if (radeon_new_pll) 555 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, 556 &fb_div, &frac_fb_div, 557 &ref_div, &post_div); 558 else 559 radeon_compute_pll(pll, adjusted_clock, &pll_clock, 560 &fb_div, &frac_fb_div, 561 &ref_div, &post_div); 562 } else 563 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, 564 &ref_div, &post_div); 565 566 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 567 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 568 &crev); 569 570 switch (frev) { 571 case 1: 572 switch (crev) { 573 case 1: 574 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); 575 args.v1.usRefDiv = cpu_to_le16(ref_div); 576 args.v1.usFbDiv = cpu_to_le16(fb_div); 577 args.v1.ucFracFbDiv = frac_fb_div; 578 args.v1.ucPostDiv = post_div; 579 args.v1.ucPpll = 580 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; 581 args.v1.ucCRTC = radeon_crtc->crtc_id; 582 args.v1.ucRefDivSrc = 1; 583 break; 584 case 2: 585 args.v2.usPixelClock = cpu_to_le16(mode->clock / 10); 586 args.v2.usRefDiv = cpu_to_le16(ref_div); 587 args.v2.usFbDiv = cpu_to_le16(fb_div); 588 args.v2.ucFracFbDiv = frac_fb_div; 589 args.v2.ucPostDiv = post_div; 590 args.v2.ucPpll = 591 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; 592 args.v2.ucCRTC = radeon_crtc->crtc_id; 593 args.v2.ucRefDivSrc = 1; 594 break; 595 case 3: 596 args.v3.usPixelClock = cpu_to_le16(mode->clock / 10); 597 args.v3.usRefDiv = cpu_to_le16(ref_div); 598 args.v3.usFbDiv = cpu_to_le16(fb_div); 599 args.v3.ucFracFbDiv = frac_fb_div; 600 args.v3.ucPostDiv = post_div; 601 args.v3.ucPpll = 602 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; 603 args.v3.ucMiscInfo = (radeon_crtc->crtc_id << 2); 604 args.v3.ucTransmitterId = radeon_encoder->encoder_id; 605 args.v3.ucEncoderMode = 606 atombios_get_encoder_mode(encoder); 607 break; 608 default: 609 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 610 return; 611 } 612 break; 613 default: 614 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 615 return; 616 } 617 618 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 619 } 620 621 static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y, 622 struct drm_framebuffer *old_fb) 623 { 624 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 625 struct drm_device *dev = crtc->dev; 626 struct radeon_device *rdev = dev->dev_private; 627 struct radeon_framebuffer *radeon_fb; 628 struct drm_gem_object *obj; 629 struct radeon_bo *rbo; 630 uint64_t fb_location; 631 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 632 int r; 633 634 /* no fb bound */ 635 if (!crtc->fb) { 636 DRM_DEBUG("No FB bound\n"); 637 return 0; 638 } 639 640 radeon_fb = to_radeon_framebuffer(crtc->fb); 641 642 /* Pin framebuffer & get tilling informations */ 643 obj = radeon_fb->obj; 644 rbo = obj->driver_private; 645 r = radeon_bo_reserve(rbo, false); 646 if (unlikely(r != 0)) 647 return r; 648 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); 649 if (unlikely(r != 0)) { 650 radeon_bo_unreserve(rbo); 651 return -EINVAL; 652 } 653 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 654 radeon_bo_unreserve(rbo); 655 656 switch (crtc->fb->bits_per_pixel) { 657 case 8: 658 fb_format = 659 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | 660 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; 661 break; 662 case 15: 663 fb_format = 664 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 665 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; 666 break; 667 case 16: 668 fb_format = 669 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 670 AVIVO_D1GRPH_CONTROL_16BPP_RGB565; 671 break; 672 case 24: 673 case 32: 674 fb_format = 675 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | 676 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; 677 break; 678 default: 679 DRM_ERROR("Unsupported screen depth %d\n", 680 crtc->fb->bits_per_pixel); 681 return -EINVAL; 682 } 683 684 if (tiling_flags & RADEON_TILING_MACRO) 685 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; 686 687 if (tiling_flags & RADEON_TILING_MICRO) 688 fb_format |= AVIVO_D1GRPH_TILED; 689 690 if (radeon_crtc->crtc_id == 0) 691 WREG32(AVIVO_D1VGA_CONTROL, 0); 692 else 693 WREG32(AVIVO_D2VGA_CONTROL, 0); 694 695 if (rdev->family >= CHIP_RV770) { 696 if (radeon_crtc->crtc_id) { 697 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0); 698 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0); 699 } else { 700 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0); 701 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0); 702 } 703 } 704 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 705 (u32) fb_location); 706 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + 707 radeon_crtc->crtc_offset, (u32) fb_location); 708 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 709 710 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 711 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 712 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); 713 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); 714 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width); 715 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height); 716 717 fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8); 718 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 719 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 720 721 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 722 crtc->mode.vdisplay); 723 x &= ~3; 724 y &= ~1; 725 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, 726 (x << 16) | y); 727 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 728 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); 729 730 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) 731 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 732 AVIVO_D1MODE_INTERLEAVE_EN); 733 else 734 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 735 736 if (old_fb && old_fb != crtc->fb) { 737 radeon_fb = to_radeon_framebuffer(old_fb); 738 rbo = radeon_fb->obj->driver_private; 739 r = radeon_bo_reserve(rbo, false); 740 if (unlikely(r != 0)) 741 return r; 742 radeon_bo_unpin(rbo); 743 radeon_bo_unreserve(rbo); 744 } 745 746 /* Bytes per pixel may have changed */ 747 radeon_bandwidth_update(rdev); 748 749 return 0; 750 } 751 752 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 753 struct drm_framebuffer *old_fb) 754 { 755 struct drm_device *dev = crtc->dev; 756 struct radeon_device *rdev = dev->dev_private; 757 758 if (ASIC_IS_AVIVO(rdev)) 759 return avivo_crtc_set_base(crtc, x, y, old_fb); 760 else 761 return radeon_crtc_set_base(crtc, x, y, old_fb); 762 } 763 764 /* properly set additional regs when using atombios */ 765 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) 766 { 767 struct drm_device *dev = crtc->dev; 768 struct radeon_device *rdev = dev->dev_private; 769 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 770 u32 disp_merge_cntl; 771 772 switch (radeon_crtc->crtc_id) { 773 case 0: 774 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); 775 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 776 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); 777 break; 778 case 1: 779 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 780 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 781 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); 782 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); 783 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); 784 break; 785 } 786 } 787 788 int atombios_crtc_mode_set(struct drm_crtc *crtc, 789 struct drm_display_mode *mode, 790 struct drm_display_mode *adjusted_mode, 791 int x, int y, struct drm_framebuffer *old_fb) 792 { 793 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 794 struct drm_device *dev = crtc->dev; 795 struct radeon_device *rdev = dev->dev_private; 796 797 /* TODO color tiling */ 798 799 atombios_set_ss(crtc, 0); 800 atombios_crtc_set_pll(crtc, adjusted_mode); 801 atombios_set_ss(crtc, 1); 802 atombios_crtc_set_timing(crtc, adjusted_mode); 803 804 if (ASIC_IS_AVIVO(rdev)) 805 atombios_crtc_set_base(crtc, x, y, old_fb); 806 else { 807 if (radeon_crtc->crtc_id == 0) 808 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 809 atombios_crtc_set_base(crtc, x, y, old_fb); 810 radeon_legacy_atom_fixup(crtc); 811 } 812 atombios_overscan_setup(crtc, mode, adjusted_mode); 813 atombios_scaler_setup(crtc); 814 return 0; 815 } 816 817 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, 818 struct drm_display_mode *mode, 819 struct drm_display_mode *adjusted_mode) 820 { 821 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 822 return false; 823 return true; 824 } 825 826 static void atombios_crtc_prepare(struct drm_crtc *crtc) 827 { 828 atombios_lock_crtc(crtc, 1); 829 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 830 } 831 832 static void atombios_crtc_commit(struct drm_crtc *crtc) 833 { 834 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 835 atombios_lock_crtc(crtc, 0); 836 } 837 838 static const struct drm_crtc_helper_funcs atombios_helper_funcs = { 839 .dpms = atombios_crtc_dpms, 840 .mode_fixup = atombios_crtc_mode_fixup, 841 .mode_set = atombios_crtc_mode_set, 842 .mode_set_base = atombios_crtc_set_base, 843 .prepare = atombios_crtc_prepare, 844 .commit = atombios_crtc_commit, 845 .load_lut = radeon_crtc_load_lut, 846 }; 847 848 void radeon_atombios_init_crtc(struct drm_device *dev, 849 struct radeon_crtc *radeon_crtc) 850 { 851 if (radeon_crtc->crtc_id == 1) 852 radeon_crtc->crtc_offset = 853 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; 854 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); 855 } 856