1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_crtc_helper.h> 28 #include <drm/drm_fb_helper.h> 29 #include <drm/radeon_drm.h> 30 #include <drm/drm_fixed.h> 31 #include "radeon.h" 32 #include "atom.h" 33 #include "atom-bits.h" 34 35 static void atombios_overscan_setup(struct drm_crtc *crtc, 36 struct drm_display_mode *mode, 37 struct drm_display_mode *adjusted_mode) 38 { 39 struct drm_device *dev = crtc->dev; 40 struct radeon_device *rdev = dev->dev_private; 41 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 42 SET_CRTC_OVERSCAN_PS_ALLOCATION args; 43 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); 44 int a1, a2; 45 46 memset(&args, 0, sizeof(args)); 47 48 args.ucCRTC = radeon_crtc->crtc_id; 49 50 switch (radeon_crtc->rmx_type) { 51 case RMX_CENTER: 52 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 53 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 54 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 55 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 56 break; 57 case RMX_ASPECT: 58 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; 59 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; 60 61 if (a1 > a2) { 62 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 63 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 64 } else if (a2 > a1) { 65 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 66 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 67 } 68 break; 69 case RMX_FULL: 70 default: 71 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); 72 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); 73 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); 74 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); 75 break; 76 } 77 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 78 } 79 80 static void atombios_scaler_setup(struct drm_crtc *crtc) 81 { 82 struct drm_device *dev = crtc->dev; 83 struct radeon_device *rdev = dev->dev_private; 84 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 85 ENABLE_SCALER_PS_ALLOCATION args; 86 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); 87 struct radeon_encoder *radeon_encoder = 88 to_radeon_encoder(radeon_crtc->encoder); 89 /* fixme - fill in enc_priv for atom dac */ 90 enum radeon_tv_std tv_std = TV_STD_NTSC; 91 bool is_tv = false, is_cv = false; 92 93 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) 94 return; 95 96 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 97 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 98 tv_std = tv_dac->tv_std; 99 is_tv = true; 100 } 101 102 memset(&args, 0, sizeof(args)); 103 104 args.ucScaler = radeon_crtc->crtc_id; 105 106 if (is_tv) { 107 switch (tv_std) { 108 case TV_STD_NTSC: 109 default: 110 args.ucTVStandard = ATOM_TV_NTSC; 111 break; 112 case TV_STD_PAL: 113 args.ucTVStandard = ATOM_TV_PAL; 114 break; 115 case TV_STD_PAL_M: 116 args.ucTVStandard = ATOM_TV_PALM; 117 break; 118 case TV_STD_PAL_60: 119 args.ucTVStandard = ATOM_TV_PAL60; 120 break; 121 case TV_STD_NTSC_J: 122 args.ucTVStandard = ATOM_TV_NTSCJ; 123 break; 124 case TV_STD_SCART_PAL: 125 args.ucTVStandard = ATOM_TV_PAL; /* ??? */ 126 break; 127 case TV_STD_SECAM: 128 args.ucTVStandard = ATOM_TV_SECAM; 129 break; 130 case TV_STD_PAL_CN: 131 args.ucTVStandard = ATOM_TV_PALCN; 132 break; 133 } 134 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 135 } else if (is_cv) { 136 args.ucTVStandard = ATOM_TV_CV; 137 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 138 } else { 139 switch (radeon_crtc->rmx_type) { 140 case RMX_FULL: 141 args.ucEnable = ATOM_SCALER_EXPANSION; 142 break; 143 case RMX_CENTER: 144 args.ucEnable = ATOM_SCALER_CENTER; 145 break; 146 case RMX_ASPECT: 147 args.ucEnable = ATOM_SCALER_EXPANSION; 148 break; 149 default: 150 if (ASIC_IS_AVIVO(rdev)) 151 args.ucEnable = ATOM_SCALER_DISABLE; 152 else 153 args.ucEnable = ATOM_SCALER_CENTER; 154 break; 155 } 156 } 157 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 158 if ((is_tv || is_cv) 159 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { 160 atom_rv515_force_tv_scaler(rdev, radeon_crtc); 161 } 162 } 163 164 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) 165 { 166 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 167 struct drm_device *dev = crtc->dev; 168 struct radeon_device *rdev = dev->dev_private; 169 int index = 170 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); 171 ENABLE_CRTC_PS_ALLOCATION args; 172 173 memset(&args, 0, sizeof(args)); 174 175 args.ucCRTC = radeon_crtc->crtc_id; 176 args.ucEnable = lock; 177 178 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 179 } 180 181 static void atombios_enable_crtc(struct drm_crtc *crtc, int state) 182 { 183 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 184 struct drm_device *dev = crtc->dev; 185 struct radeon_device *rdev = dev->dev_private; 186 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); 187 ENABLE_CRTC_PS_ALLOCATION args; 188 189 memset(&args, 0, sizeof(args)); 190 191 args.ucCRTC = radeon_crtc->crtc_id; 192 args.ucEnable = state; 193 194 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 195 } 196 197 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) 198 { 199 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 200 struct drm_device *dev = crtc->dev; 201 struct radeon_device *rdev = dev->dev_private; 202 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); 203 ENABLE_CRTC_PS_ALLOCATION args; 204 205 memset(&args, 0, sizeof(args)); 206 207 args.ucCRTC = radeon_crtc->crtc_id; 208 args.ucEnable = state; 209 210 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 211 } 212 213 static const u32 vga_control_regs[6] = 214 { 215 AVIVO_D1VGA_CONTROL, 216 AVIVO_D2VGA_CONTROL, 217 EVERGREEN_D3VGA_CONTROL, 218 EVERGREEN_D4VGA_CONTROL, 219 EVERGREEN_D5VGA_CONTROL, 220 EVERGREEN_D6VGA_CONTROL, 221 }; 222 223 static void atombios_blank_crtc(struct drm_crtc *crtc, int state) 224 { 225 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 226 struct drm_device *dev = crtc->dev; 227 struct radeon_device *rdev = dev->dev_private; 228 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); 229 BLANK_CRTC_PS_ALLOCATION args; 230 u32 vga_control = 0; 231 232 memset(&args, 0, sizeof(args)); 233 234 if (ASIC_IS_DCE8(rdev)) { 235 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]); 236 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1); 237 } 238 239 args.ucCRTC = radeon_crtc->crtc_id; 240 args.ucBlanking = state; 241 242 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 243 244 if (ASIC_IS_DCE8(rdev)) { 245 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control); 246 } 247 } 248 249 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state) 250 { 251 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 252 struct drm_device *dev = crtc->dev; 253 struct radeon_device *rdev = dev->dev_private; 254 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating); 255 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args; 256 257 memset(&args, 0, sizeof(args)); 258 259 args.ucDispPipeId = radeon_crtc->crtc_id; 260 args.ucEnable = state; 261 262 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 263 } 264 265 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) 266 { 267 struct drm_device *dev = crtc->dev; 268 struct radeon_device *rdev = dev->dev_private; 269 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 270 271 switch (mode) { 272 case DRM_MODE_DPMS_ON: 273 radeon_crtc->enabled = true; 274 atombios_enable_crtc(crtc, ATOM_ENABLE); 275 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) 276 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); 277 atombios_blank_crtc(crtc, ATOM_DISABLE); 278 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); 279 radeon_crtc_load_lut(crtc); 280 break; 281 case DRM_MODE_DPMS_STANDBY: 282 case DRM_MODE_DPMS_SUSPEND: 283 case DRM_MODE_DPMS_OFF: 284 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); 285 if (radeon_crtc->enabled) 286 atombios_blank_crtc(crtc, ATOM_ENABLE); 287 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) 288 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); 289 atombios_enable_crtc(crtc, ATOM_DISABLE); 290 radeon_crtc->enabled = false; 291 break; 292 } 293 /* adjust pm to dpms */ 294 radeon_pm_compute_clocks(rdev); 295 } 296 297 static void 298 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, 299 struct drm_display_mode *mode) 300 { 301 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 302 struct drm_device *dev = crtc->dev; 303 struct radeon_device *rdev = dev->dev_private; 304 SET_CRTC_USING_DTD_TIMING_PARAMETERS args; 305 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); 306 u16 misc = 0; 307 308 memset(&args, 0, sizeof(args)); 309 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); 310 args.usH_Blanking_Time = 311 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); 312 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); 313 args.usV_Blanking_Time = 314 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); 315 args.usH_SyncOffset = 316 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); 317 args.usH_SyncWidth = 318 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 319 args.usV_SyncOffset = 320 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); 321 args.usV_SyncWidth = 322 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 323 args.ucH_Border = radeon_crtc->h_border; 324 args.ucV_Border = radeon_crtc->v_border; 325 326 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 327 misc |= ATOM_VSYNC_POLARITY; 328 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 329 misc |= ATOM_HSYNC_POLARITY; 330 if (mode->flags & DRM_MODE_FLAG_CSYNC) 331 misc |= ATOM_COMPOSITESYNC; 332 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 333 misc |= ATOM_INTERLACE; 334 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 335 misc |= ATOM_DOUBLE_CLOCK_MODE; 336 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 337 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2; 338 339 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 340 args.ucCRTC = radeon_crtc->crtc_id; 341 342 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 343 } 344 345 static void atombios_crtc_set_timing(struct drm_crtc *crtc, 346 struct drm_display_mode *mode) 347 { 348 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 349 struct drm_device *dev = crtc->dev; 350 struct radeon_device *rdev = dev->dev_private; 351 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; 352 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); 353 u16 misc = 0; 354 355 memset(&args, 0, sizeof(args)); 356 args.usH_Total = cpu_to_le16(mode->crtc_htotal); 357 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); 358 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); 359 args.usH_SyncWidth = 360 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 361 args.usV_Total = cpu_to_le16(mode->crtc_vtotal); 362 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); 363 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); 364 args.usV_SyncWidth = 365 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 366 367 args.ucOverscanRight = radeon_crtc->h_border; 368 args.ucOverscanLeft = radeon_crtc->h_border; 369 args.ucOverscanBottom = radeon_crtc->v_border; 370 args.ucOverscanTop = radeon_crtc->v_border; 371 372 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 373 misc |= ATOM_VSYNC_POLARITY; 374 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 375 misc |= ATOM_HSYNC_POLARITY; 376 if (mode->flags & DRM_MODE_FLAG_CSYNC) 377 misc |= ATOM_COMPOSITESYNC; 378 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 379 misc |= ATOM_INTERLACE; 380 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 381 misc |= ATOM_DOUBLE_CLOCK_MODE; 382 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 383 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2; 384 385 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 386 args.ucCRTC = radeon_crtc->crtc_id; 387 388 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 389 } 390 391 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id) 392 { 393 u32 ss_cntl; 394 395 if (ASIC_IS_DCE4(rdev)) { 396 switch (pll_id) { 397 case ATOM_PPLL1: 398 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); 399 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 400 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl); 401 break; 402 case ATOM_PPLL2: 403 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL); 404 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 405 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl); 406 break; 407 case ATOM_DCPLL: 408 case ATOM_PPLL_INVALID: 409 return; 410 } 411 } else if (ASIC_IS_AVIVO(rdev)) { 412 switch (pll_id) { 413 case ATOM_PPLL1: 414 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); 415 ss_cntl &= ~1; 416 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl); 417 break; 418 case ATOM_PPLL2: 419 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); 420 ss_cntl &= ~1; 421 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl); 422 break; 423 case ATOM_DCPLL: 424 case ATOM_PPLL_INVALID: 425 return; 426 } 427 } 428 } 429 430 431 union atom_enable_ss { 432 ENABLE_LVDS_SS_PARAMETERS lvds_ss; 433 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2; 434 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; 435 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2; 436 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; 437 }; 438 439 static void atombios_crtc_program_ss(struct radeon_device *rdev, 440 int enable, 441 int pll_id, 442 int crtc_id, 443 struct radeon_atom_ss *ss) 444 { 445 unsigned i; 446 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); 447 union atom_enable_ss args; 448 449 if (enable) { 450 /* Don't mess with SS if percentage is 0 or external ss. 451 * SS is already disabled previously, and disabling it 452 * again can cause display problems if the pll is already 453 * programmed. 454 */ 455 if (ss->percentage == 0) 456 return; 457 if (ss->type & ATOM_EXTERNAL_SS_MASK) 458 return; 459 } else { 460 for (i = 0; i < rdev->num_crtc; i++) { 461 if (rdev->mode_info.crtcs[i] && 462 rdev->mode_info.crtcs[i]->enabled && 463 i != crtc_id && 464 pll_id == rdev->mode_info.crtcs[i]->pll_id) { 465 /* one other crtc is using this pll don't turn 466 * off spread spectrum as it might turn off 467 * display on active crtc 468 */ 469 return; 470 } 471 } 472 } 473 474 memset(&args, 0, sizeof(args)); 475 476 if (ASIC_IS_DCE5(rdev)) { 477 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); 478 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 479 switch (pll_id) { 480 case ATOM_PPLL1: 481 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; 482 break; 483 case ATOM_PPLL2: 484 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; 485 break; 486 case ATOM_DCPLL: 487 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; 488 break; 489 case ATOM_PPLL_INVALID: 490 return; 491 } 492 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 493 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); 494 args.v3.ucEnable = enable; 495 } else if (ASIC_IS_DCE4(rdev)) { 496 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 497 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 498 switch (pll_id) { 499 case ATOM_PPLL1: 500 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL; 501 break; 502 case ATOM_PPLL2: 503 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL; 504 break; 505 case ATOM_DCPLL: 506 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL; 507 break; 508 case ATOM_PPLL_INVALID: 509 return; 510 } 511 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 512 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); 513 args.v2.ucEnable = enable; 514 } else if (ASIC_IS_DCE3(rdev)) { 515 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 516 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 517 args.v1.ucSpreadSpectrumStep = ss->step; 518 args.v1.ucSpreadSpectrumDelay = ss->delay; 519 args.v1.ucSpreadSpectrumRange = ss->range; 520 args.v1.ucPpll = pll_id; 521 args.v1.ucEnable = enable; 522 } else if (ASIC_IS_AVIVO(rdev)) { 523 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || 524 (ss->type & ATOM_EXTERNAL_SS_MASK)) { 525 atombios_disable_ss(rdev, pll_id); 526 return; 527 } 528 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 529 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 530 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; 531 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; 532 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; 533 args.lvds_ss_2.ucEnable = enable; 534 } else { 535 if (enable == ATOM_DISABLE) { 536 atombios_disable_ss(rdev, pll_id); 537 return; 538 } 539 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 540 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 541 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; 542 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; 543 args.lvds_ss.ucEnable = enable; 544 } 545 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 546 } 547 548 union adjust_pixel_clock { 549 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; 550 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; 551 }; 552 553 static u32 atombios_adjust_pll(struct drm_crtc *crtc, 554 struct drm_display_mode *mode) 555 { 556 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 557 struct drm_device *dev = crtc->dev; 558 struct radeon_device *rdev = dev->dev_private; 559 struct drm_encoder *encoder = radeon_crtc->encoder; 560 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 561 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 562 u32 adjusted_clock = mode->clock; 563 int encoder_mode = atombios_get_encoder_mode(encoder); 564 u32 dp_clock = mode->clock; 565 u32 clock = mode->clock; 566 int bpc = radeon_crtc->bpc; 567 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); 568 569 /* reset the pll flags */ 570 radeon_crtc->pll_flags = 0; 571 572 if (ASIC_IS_AVIVO(rdev)) { 573 if ((rdev->family == CHIP_RS600) || 574 (rdev->family == CHIP_RS690) || 575 (rdev->family == CHIP_RS740)) 576 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ 577 RADEON_PLL_PREFER_CLOSEST_LOWER); 578 579 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ 580 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 581 else 582 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 583 584 if (rdev->family < CHIP_RV770) 585 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; 586 /* use frac fb div on APUs */ 587 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev)) 588 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 589 /* use frac fb div on RS780/RS880 */ 590 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) 591 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 592 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000) 593 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 594 } else { 595 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY; 596 597 if (mode->clock > 200000) /* range limits??? */ 598 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 599 else 600 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 601 } 602 603 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || 604 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { 605 if (connector) { 606 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 607 struct radeon_connector_atom_dig *dig_connector = 608 radeon_connector->con_priv; 609 610 dp_clock = dig_connector->dp_clock; 611 } 612 } 613 614 if (radeon_encoder->is_mst_encoder) { 615 struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv; 616 struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv; 617 618 dp_clock = dig_connector->dp_clock; 619 } 620 621 /* use recommended ref_div for ss */ 622 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 623 if (radeon_crtc->ss_enabled) { 624 if (radeon_crtc->ss.refdiv) { 625 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 626 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; 627 if (ASIC_IS_AVIVO(rdev)) 628 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 629 } 630 } 631 } 632 633 if (ASIC_IS_AVIVO(rdev)) { 634 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ 635 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) 636 adjusted_clock = mode->clock * 2; 637 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 638 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; 639 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 640 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD; 641 } else { 642 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 643 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; 644 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) 645 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 646 } 647 648 /* adjust pll for deep color modes */ 649 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { 650 switch (bpc) { 651 case 8: 652 default: 653 break; 654 case 10: 655 clock = (clock * 5) / 4; 656 break; 657 case 12: 658 clock = (clock * 3) / 2; 659 break; 660 case 16: 661 clock = clock * 2; 662 break; 663 } 664 } 665 666 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock 667 * accordingly based on the encoder/transmitter to work around 668 * special hw requirements. 669 */ 670 if (ASIC_IS_DCE3(rdev)) { 671 union adjust_pixel_clock args; 672 u8 frev, crev; 673 int index; 674 675 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); 676 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 677 &crev)) 678 return adjusted_clock; 679 680 memset(&args, 0, sizeof(args)); 681 682 switch (frev) { 683 case 1: 684 switch (crev) { 685 case 1: 686 case 2: 687 args.v1.usPixelClock = cpu_to_le16(clock / 10); 688 args.v1.ucTransmitterID = radeon_encoder->encoder_id; 689 args.v1.ucEncodeMode = encoder_mode; 690 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) 691 args.v1.ucConfig |= 692 ADJUST_DISPLAY_CONFIG_SS_ENABLE; 693 694 atom_execute_table(rdev->mode_info.atom_context, 695 index, (uint32_t *)&args); 696 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; 697 break; 698 case 3: 699 args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10); 700 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; 701 args.v3.sInput.ucEncodeMode = encoder_mode; 702 args.v3.sInput.ucDispPllConfig = 0; 703 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) 704 args.v3.sInput.ucDispPllConfig |= 705 DISPPLL_CONFIG_SS_ENABLE; 706 if (ENCODER_MODE_IS_DP(encoder_mode)) { 707 args.v3.sInput.ucDispPllConfig |= 708 DISPPLL_CONFIG_COHERENT_MODE; 709 /* 16200 or 27000 */ 710 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); 711 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 712 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 713 if (dig->coherent_mode) 714 args.v3.sInput.ucDispPllConfig |= 715 DISPPLL_CONFIG_COHERENT_MODE; 716 if (is_duallink) 717 args.v3.sInput.ucDispPllConfig |= 718 DISPPLL_CONFIG_DUAL_LINK; 719 } 720 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 721 ENCODER_OBJECT_ID_NONE) 722 args.v3.sInput.ucExtTransmitterID = 723 radeon_encoder_get_dp_bridge_encoder_id(encoder); 724 else 725 args.v3.sInput.ucExtTransmitterID = 0; 726 727 atom_execute_table(rdev->mode_info.atom_context, 728 index, (uint32_t *)&args); 729 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; 730 if (args.v3.sOutput.ucRefDiv) { 731 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 732 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 733 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; 734 } 735 if (args.v3.sOutput.ucPostDiv) { 736 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 737 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV; 738 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; 739 } 740 break; 741 default: 742 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 743 return adjusted_clock; 744 } 745 break; 746 default: 747 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 748 return adjusted_clock; 749 } 750 } 751 return adjusted_clock; 752 } 753 754 union set_pixel_clock { 755 SET_PIXEL_CLOCK_PS_ALLOCATION base; 756 PIXEL_CLOCK_PARAMETERS v1; 757 PIXEL_CLOCK_PARAMETERS_V2 v2; 758 PIXEL_CLOCK_PARAMETERS_V3 v3; 759 PIXEL_CLOCK_PARAMETERS_V5 v5; 760 PIXEL_CLOCK_PARAMETERS_V6 v6; 761 }; 762 763 /* on DCE5, make sure the voltage is high enough to support the 764 * required disp clk. 765 */ 766 static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev, 767 u32 dispclk) 768 { 769 u8 frev, crev; 770 int index; 771 union set_pixel_clock args; 772 773 memset(&args, 0, sizeof(args)); 774 775 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 776 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 777 &crev)) 778 return; 779 780 switch (frev) { 781 case 1: 782 switch (crev) { 783 case 5: 784 /* if the default dcpll clock is specified, 785 * SetPixelClock provides the dividers 786 */ 787 args.v5.ucCRTC = ATOM_CRTC_INVALID; 788 args.v5.usPixelClock = cpu_to_le16(dispclk); 789 args.v5.ucPpll = ATOM_DCPLL; 790 break; 791 case 6: 792 /* if the default dcpll clock is specified, 793 * SetPixelClock provides the dividers 794 */ 795 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); 796 if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev)) 797 args.v6.ucPpll = ATOM_EXT_PLL1; 798 else if (ASIC_IS_DCE6(rdev)) 799 args.v6.ucPpll = ATOM_PPLL0; 800 else 801 args.v6.ucPpll = ATOM_DCPLL; 802 break; 803 default: 804 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 805 return; 806 } 807 break; 808 default: 809 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 810 return; 811 } 812 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 813 } 814 815 static void atombios_crtc_program_pll(struct drm_crtc *crtc, 816 u32 crtc_id, 817 int pll_id, 818 u32 encoder_mode, 819 u32 encoder_id, 820 u32 clock, 821 u32 ref_div, 822 u32 fb_div, 823 u32 frac_fb_div, 824 u32 post_div, 825 int bpc, 826 bool ss_enabled, 827 struct radeon_atom_ss *ss) 828 { 829 struct drm_device *dev = crtc->dev; 830 struct radeon_device *rdev = dev->dev_private; 831 u8 frev, crev; 832 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 833 union set_pixel_clock args; 834 835 memset(&args, 0, sizeof(args)); 836 837 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 838 &crev)) 839 return; 840 841 switch (frev) { 842 case 1: 843 switch (crev) { 844 case 1: 845 if (clock == ATOM_DISABLE) 846 return; 847 args.v1.usPixelClock = cpu_to_le16(clock / 10); 848 args.v1.usRefDiv = cpu_to_le16(ref_div); 849 args.v1.usFbDiv = cpu_to_le16(fb_div); 850 args.v1.ucFracFbDiv = frac_fb_div; 851 args.v1.ucPostDiv = post_div; 852 args.v1.ucPpll = pll_id; 853 args.v1.ucCRTC = crtc_id; 854 args.v1.ucRefDivSrc = 1; 855 break; 856 case 2: 857 args.v2.usPixelClock = cpu_to_le16(clock / 10); 858 args.v2.usRefDiv = cpu_to_le16(ref_div); 859 args.v2.usFbDiv = cpu_to_le16(fb_div); 860 args.v2.ucFracFbDiv = frac_fb_div; 861 args.v2.ucPostDiv = post_div; 862 args.v2.ucPpll = pll_id; 863 args.v2.ucCRTC = crtc_id; 864 args.v2.ucRefDivSrc = 1; 865 break; 866 case 3: 867 args.v3.usPixelClock = cpu_to_le16(clock / 10); 868 args.v3.usRefDiv = cpu_to_le16(ref_div); 869 args.v3.usFbDiv = cpu_to_le16(fb_div); 870 args.v3.ucFracFbDiv = frac_fb_div; 871 args.v3.ucPostDiv = post_div; 872 args.v3.ucPpll = pll_id; 873 if (crtc_id == ATOM_CRTC2) 874 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2; 875 else 876 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1; 877 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 878 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; 879 args.v3.ucTransmitterId = encoder_id; 880 args.v3.ucEncoderMode = encoder_mode; 881 break; 882 case 5: 883 args.v5.ucCRTC = crtc_id; 884 args.v5.usPixelClock = cpu_to_le16(clock / 10); 885 args.v5.ucRefDiv = ref_div; 886 args.v5.usFbDiv = cpu_to_le16(fb_div); 887 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 888 args.v5.ucPostDiv = post_div; 889 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ 890 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 891 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; 892 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { 893 switch (bpc) { 894 case 8: 895 default: 896 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; 897 break; 898 case 10: 899 /* yes this is correct, the atom define is wrong */ 900 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP; 901 break; 902 case 12: 903 /* yes this is correct, the atom define is wrong */ 904 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; 905 break; 906 } 907 } 908 args.v5.ucTransmitterID = encoder_id; 909 args.v5.ucEncoderMode = encoder_mode; 910 args.v5.ucPpll = pll_id; 911 break; 912 case 6: 913 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10); 914 args.v6.ucRefDiv = ref_div; 915 args.v6.usFbDiv = cpu_to_le16(fb_div); 916 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 917 args.v6.ucPostDiv = post_div; 918 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ 919 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 920 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; 921 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { 922 switch (bpc) { 923 case 8: 924 default: 925 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; 926 break; 927 case 10: 928 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6; 929 break; 930 case 12: 931 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6; 932 break; 933 case 16: 934 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; 935 break; 936 } 937 } 938 args.v6.ucTransmitterID = encoder_id; 939 args.v6.ucEncoderMode = encoder_mode; 940 args.v6.ucPpll = pll_id; 941 break; 942 default: 943 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 944 return; 945 } 946 break; 947 default: 948 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 949 return; 950 } 951 952 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 953 } 954 955 static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 956 { 957 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 958 struct drm_device *dev = crtc->dev; 959 struct radeon_device *rdev = dev->dev_private; 960 struct radeon_encoder *radeon_encoder = 961 to_radeon_encoder(radeon_crtc->encoder); 962 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); 963 964 radeon_crtc->bpc = 8; 965 radeon_crtc->ss_enabled = false; 966 967 if (radeon_encoder->is_mst_encoder) { 968 radeon_dp_mst_prepare_pll(crtc, mode); 969 } else if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || 970 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { 971 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 972 struct drm_connector *connector = 973 radeon_get_connector_for_encoder(radeon_crtc->encoder); 974 struct radeon_connector *radeon_connector = 975 to_radeon_connector(connector); 976 struct radeon_connector_atom_dig *dig_connector = 977 radeon_connector->con_priv; 978 int dp_clock; 979 980 /* Assign mode clock for hdmi deep color max clock limit check */ 981 radeon_connector->pixelclock_for_modeset = mode->clock; 982 radeon_crtc->bpc = radeon_get_monitor_bpc(connector); 983 984 switch (encoder_mode) { 985 case ATOM_ENCODER_MODE_DP_MST: 986 case ATOM_ENCODER_MODE_DP: 987 /* DP/eDP */ 988 dp_clock = dig_connector->dp_clock / 10; 989 if (ASIC_IS_DCE4(rdev)) 990 radeon_crtc->ss_enabled = 991 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, 992 ASIC_INTERNAL_SS_ON_DP, 993 dp_clock); 994 else { 995 if (dp_clock == 16200) { 996 radeon_crtc->ss_enabled = 997 radeon_atombios_get_ppll_ss_info(rdev, 998 &radeon_crtc->ss, 999 ATOM_DP_SS_ID2); 1000 if (!radeon_crtc->ss_enabled) 1001 radeon_crtc->ss_enabled = 1002 radeon_atombios_get_ppll_ss_info(rdev, 1003 &radeon_crtc->ss, 1004 ATOM_DP_SS_ID1); 1005 } else { 1006 radeon_crtc->ss_enabled = 1007 radeon_atombios_get_ppll_ss_info(rdev, 1008 &radeon_crtc->ss, 1009 ATOM_DP_SS_ID1); 1010 } 1011 /* disable spread spectrum on DCE3 DP */ 1012 radeon_crtc->ss_enabled = false; 1013 } 1014 break; 1015 case ATOM_ENCODER_MODE_LVDS: 1016 if (ASIC_IS_DCE4(rdev)) 1017 radeon_crtc->ss_enabled = 1018 radeon_atombios_get_asic_ss_info(rdev, 1019 &radeon_crtc->ss, 1020 dig->lcd_ss_id, 1021 mode->clock / 10); 1022 else 1023 radeon_crtc->ss_enabled = 1024 radeon_atombios_get_ppll_ss_info(rdev, 1025 &radeon_crtc->ss, 1026 dig->lcd_ss_id); 1027 break; 1028 case ATOM_ENCODER_MODE_DVI: 1029 if (ASIC_IS_DCE4(rdev)) 1030 radeon_crtc->ss_enabled = 1031 radeon_atombios_get_asic_ss_info(rdev, 1032 &radeon_crtc->ss, 1033 ASIC_INTERNAL_SS_ON_TMDS, 1034 mode->clock / 10); 1035 break; 1036 case ATOM_ENCODER_MODE_HDMI: 1037 if (ASIC_IS_DCE4(rdev)) 1038 radeon_crtc->ss_enabled = 1039 radeon_atombios_get_asic_ss_info(rdev, 1040 &radeon_crtc->ss, 1041 ASIC_INTERNAL_SS_ON_HDMI, 1042 mode->clock / 10); 1043 break; 1044 default: 1045 break; 1046 } 1047 } 1048 1049 /* adjust pixel clock as needed */ 1050 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode); 1051 1052 return true; 1053 } 1054 1055 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 1056 { 1057 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1058 struct drm_device *dev = crtc->dev; 1059 struct radeon_device *rdev = dev->dev_private; 1060 struct radeon_encoder *radeon_encoder = 1061 to_radeon_encoder(radeon_crtc->encoder); 1062 u32 pll_clock = mode->clock; 1063 u32 clock = mode->clock; 1064 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; 1065 struct radeon_pll *pll; 1066 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); 1067 1068 /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */ 1069 if (ASIC_IS_DCE5(rdev) && 1070 (encoder_mode == ATOM_ENCODER_MODE_HDMI) && 1071 (radeon_crtc->bpc > 8)) 1072 clock = radeon_crtc->adjusted_clock; 1073 1074 switch (radeon_crtc->pll_id) { 1075 case ATOM_PPLL1: 1076 pll = &rdev->clock.p1pll; 1077 break; 1078 case ATOM_PPLL2: 1079 pll = &rdev->clock.p2pll; 1080 break; 1081 case ATOM_DCPLL: 1082 case ATOM_PPLL_INVALID: 1083 default: 1084 pll = &rdev->clock.dcpll; 1085 break; 1086 } 1087 1088 /* update pll params */ 1089 pll->flags = radeon_crtc->pll_flags; 1090 pll->reference_div = radeon_crtc->pll_reference_div; 1091 pll->post_div = radeon_crtc->pll_post_div; 1092 1093 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1094 /* TV seems to prefer the legacy algo on some boards */ 1095 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, 1096 &fb_div, &frac_fb_div, &ref_div, &post_div); 1097 else if (ASIC_IS_AVIVO(rdev)) 1098 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, 1099 &fb_div, &frac_fb_div, &ref_div, &post_div); 1100 else 1101 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, 1102 &fb_div, &frac_fb_div, &ref_div, &post_div); 1103 1104 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, 1105 radeon_crtc->crtc_id, &radeon_crtc->ss); 1106 1107 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 1108 encoder_mode, radeon_encoder->encoder_id, clock, 1109 ref_div, fb_div, frac_fb_div, post_div, 1110 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss); 1111 1112 if (radeon_crtc->ss_enabled) { 1113 /* calculate ss amount and step size */ 1114 if (ASIC_IS_DCE4(rdev)) { 1115 u32 step_size; 1116 u32 amount = (((fb_div * 10) + frac_fb_div) * 1117 (u32)radeon_crtc->ss.percentage) / 1118 (100 * (u32)radeon_crtc->ss.percentage_divider); 1119 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; 1120 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & 1121 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK; 1122 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) 1123 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / 1124 (125 * 25 * pll->reference_freq / 100); 1125 else 1126 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / 1127 (125 * 25 * pll->reference_freq / 100); 1128 radeon_crtc->ss.step = step_size; 1129 } 1130 1131 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, 1132 radeon_crtc->crtc_id, &radeon_crtc->ss); 1133 } 1134 } 1135 1136 static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 1137 struct drm_framebuffer *fb, 1138 int x, int y, int atomic) 1139 { 1140 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1141 struct drm_device *dev = crtc->dev; 1142 struct radeon_device *rdev = dev->dev_private; 1143 struct radeon_framebuffer *radeon_fb; 1144 struct drm_framebuffer *target_fb; 1145 struct drm_gem_object *obj; 1146 struct radeon_bo *rbo; 1147 uint64_t fb_location; 1148 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1149 unsigned bankw, bankh, mtaspect, tile_split; 1150 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); 1151 u32 tmp, viewport_w, viewport_h; 1152 int r; 1153 bool bypass_lut = false; 1154 1155 /* no fb bound */ 1156 if (!atomic && !crtc->primary->fb) { 1157 DRM_DEBUG_KMS("No FB bound\n"); 1158 return 0; 1159 } 1160 1161 if (atomic) { 1162 radeon_fb = to_radeon_framebuffer(fb); 1163 target_fb = fb; 1164 } 1165 else { 1166 radeon_fb = to_radeon_framebuffer(crtc->primary->fb); 1167 target_fb = crtc->primary->fb; 1168 } 1169 1170 /* If atomic, assume fb object is pinned & idle & fenced and 1171 * just update base pointers 1172 */ 1173 obj = radeon_fb->obj; 1174 rbo = gem_to_radeon_bo(obj); 1175 r = radeon_bo_reserve(rbo, false); 1176 if (unlikely(r != 0)) 1177 return r; 1178 1179 if (atomic) 1180 fb_location = radeon_bo_gpu_offset(rbo); 1181 else { 1182 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); 1183 if (unlikely(r != 0)) { 1184 radeon_bo_unreserve(rbo); 1185 return -EINVAL; 1186 } 1187 } 1188 1189 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1190 radeon_bo_unreserve(rbo); 1191 1192 switch (target_fb->pixel_format) { 1193 case DRM_FORMAT_C8: 1194 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | 1195 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); 1196 break; 1197 case DRM_FORMAT_XRGB4444: 1198 case DRM_FORMAT_ARGB4444: 1199 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1200 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444)); 1201 #ifdef __BIG_ENDIAN 1202 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1203 #endif 1204 break; 1205 case DRM_FORMAT_XRGB1555: 1206 case DRM_FORMAT_ARGB1555: 1207 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1208 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); 1209 #ifdef __BIG_ENDIAN 1210 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1211 #endif 1212 break; 1213 case DRM_FORMAT_BGRX5551: 1214 case DRM_FORMAT_BGRA5551: 1215 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1216 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551)); 1217 #ifdef __BIG_ENDIAN 1218 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1219 #endif 1220 break; 1221 case DRM_FORMAT_RGB565: 1222 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1223 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); 1224 #ifdef __BIG_ENDIAN 1225 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1226 #endif 1227 break; 1228 case DRM_FORMAT_XRGB8888: 1229 case DRM_FORMAT_ARGB8888: 1230 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1231 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); 1232 #ifdef __BIG_ENDIAN 1233 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1234 #endif 1235 break; 1236 case DRM_FORMAT_XRGB2101010: 1237 case DRM_FORMAT_ARGB2101010: 1238 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1239 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010)); 1240 #ifdef __BIG_ENDIAN 1241 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1242 #endif 1243 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1244 bypass_lut = true; 1245 break; 1246 case DRM_FORMAT_BGRX1010102: 1247 case DRM_FORMAT_BGRA1010102: 1248 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1249 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102)); 1250 #ifdef __BIG_ENDIAN 1251 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1252 #endif 1253 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1254 bypass_lut = true; 1255 break; 1256 default: 1257 DRM_ERROR("Unsupported screen format %s\n", 1258 drm_get_format_name(target_fb->pixel_format)); 1259 return -EINVAL; 1260 } 1261 1262 if (tiling_flags & RADEON_TILING_MACRO) { 1263 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); 1264 1265 /* Set NUM_BANKS. */ 1266 if (rdev->family >= CHIP_TAHITI) { 1267 unsigned index, num_banks; 1268 1269 if (rdev->family >= CHIP_BONAIRE) { 1270 unsigned tileb, tile_split_bytes; 1271 1272 /* Calculate the macrotile mode index. */ 1273 tile_split_bytes = 64 << tile_split; 1274 tileb = 8 * 8 * target_fb->bits_per_pixel / 8; 1275 tileb = min(tile_split_bytes, tileb); 1276 1277 for (index = 0; tileb > 64; index++) 1278 tileb >>= 1; 1279 1280 if (index >= 16) { 1281 DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n", 1282 target_fb->bits_per_pixel, tile_split); 1283 return -EINVAL; 1284 } 1285 1286 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; 1287 } else { 1288 switch (target_fb->bits_per_pixel) { 1289 case 8: 1290 index = 10; 1291 break; 1292 case 16: 1293 index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP; 1294 break; 1295 default: 1296 case 32: 1297 index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP; 1298 break; 1299 } 1300 1301 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3; 1302 } 1303 1304 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks); 1305 } else { 1306 /* NI and older. */ 1307 if (rdev->family >= CHIP_CAYMAN) 1308 tmp = rdev->config.cayman.tile_config; 1309 else 1310 tmp = rdev->config.evergreen.tile_config; 1311 1312 switch ((tmp & 0xf0) >> 4) { 1313 case 0: /* 4 banks */ 1314 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK); 1315 break; 1316 case 1: /* 8 banks */ 1317 default: 1318 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK); 1319 break; 1320 case 2: /* 16 banks */ 1321 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK); 1322 break; 1323 } 1324 } 1325 1326 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); 1327 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split); 1328 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); 1329 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh); 1330 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); 1331 if (rdev->family >= CHIP_BONAIRE) { 1332 /* XXX need to know more about the surface tiling mode */ 1333 fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING); 1334 } 1335 } else if (tiling_flags & RADEON_TILING_MICRO) 1336 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); 1337 1338 if (rdev->family >= CHIP_BONAIRE) { 1339 /* Read the pipe config from the 2D TILED SCANOUT mode. 1340 * It should be the same for the other modes too, but not all 1341 * modes set the pipe config field. */ 1342 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f; 1343 1344 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config); 1345 } else if ((rdev->family == CHIP_TAHITI) || 1346 (rdev->family == CHIP_PITCAIRN)) 1347 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16); 1348 else if ((rdev->family == CHIP_VERDE) || 1349 (rdev->family == CHIP_OLAND) || 1350 (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */ 1351 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16); 1352 1353 switch (radeon_crtc->crtc_id) { 1354 case 0: 1355 WREG32(AVIVO_D1VGA_CONTROL, 0); 1356 break; 1357 case 1: 1358 WREG32(AVIVO_D2VGA_CONTROL, 0); 1359 break; 1360 case 2: 1361 WREG32(EVERGREEN_D3VGA_CONTROL, 0); 1362 break; 1363 case 3: 1364 WREG32(EVERGREEN_D4VGA_CONTROL, 0); 1365 break; 1366 case 4: 1367 WREG32(EVERGREEN_D5VGA_CONTROL, 0); 1368 break; 1369 case 5: 1370 WREG32(EVERGREEN_D6VGA_CONTROL, 0); 1371 break; 1372 default: 1373 break; 1374 } 1375 1376 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 1377 upper_32_bits(fb_location)); 1378 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 1379 upper_32_bits(fb_location)); 1380 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1381 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1382 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1383 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1384 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1385 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1386 1387 /* 1388 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 1389 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 1390 * retain the full precision throughout the pipeline. 1391 */ 1392 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset, 1393 (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0), 1394 ~EVERGREEN_LUT_10BIT_BYPASS_EN); 1395 1396 if (bypass_lut) 1397 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 1398 1399 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1400 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1401 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); 1402 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); 1403 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); 1404 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); 1405 1406 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 1407 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 1408 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1409 1410 if (rdev->family >= CHIP_BONAIRE) 1411 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1412 target_fb->height); 1413 else 1414 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1415 target_fb->height); 1416 x &= ~3; 1417 y &= ~1; 1418 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, 1419 (x << 16) | y); 1420 viewport_w = crtc->mode.hdisplay; 1421 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1422 if ((rdev->family >= CHIP_BONAIRE) && 1423 (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)) 1424 viewport_h *= 2; 1425 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1426 (viewport_w << 16) | viewport_h); 1427 1428 /* pageflip setup */ 1429 /* make sure flip is at vb rather than hb */ 1430 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); 1431 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN; 1432 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); 1433 1434 /* set pageflip to happen only at start of vblank interval (front porch) */ 1435 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3); 1436 1437 if (!atomic && fb && fb != crtc->primary->fb) { 1438 radeon_fb = to_radeon_framebuffer(fb); 1439 rbo = gem_to_radeon_bo(radeon_fb->obj); 1440 r = radeon_bo_reserve(rbo, false); 1441 if (unlikely(r != 0)) 1442 return r; 1443 radeon_bo_unpin(rbo); 1444 radeon_bo_unreserve(rbo); 1445 } 1446 1447 /* Bytes per pixel may have changed */ 1448 radeon_bandwidth_update(rdev); 1449 1450 return 0; 1451 } 1452 1453 static int avivo_crtc_do_set_base(struct drm_crtc *crtc, 1454 struct drm_framebuffer *fb, 1455 int x, int y, int atomic) 1456 { 1457 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1458 struct drm_device *dev = crtc->dev; 1459 struct radeon_device *rdev = dev->dev_private; 1460 struct radeon_framebuffer *radeon_fb; 1461 struct drm_gem_object *obj; 1462 struct radeon_bo *rbo; 1463 struct drm_framebuffer *target_fb; 1464 uint64_t fb_location; 1465 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1466 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; 1467 u32 tmp, viewport_w, viewport_h; 1468 int r; 1469 bool bypass_lut = false; 1470 1471 /* no fb bound */ 1472 if (!atomic && !crtc->primary->fb) { 1473 DRM_DEBUG_KMS("No FB bound\n"); 1474 return 0; 1475 } 1476 1477 if (atomic) { 1478 radeon_fb = to_radeon_framebuffer(fb); 1479 target_fb = fb; 1480 } 1481 else { 1482 radeon_fb = to_radeon_framebuffer(crtc->primary->fb); 1483 target_fb = crtc->primary->fb; 1484 } 1485 1486 obj = radeon_fb->obj; 1487 rbo = gem_to_radeon_bo(obj); 1488 r = radeon_bo_reserve(rbo, false); 1489 if (unlikely(r != 0)) 1490 return r; 1491 1492 /* If atomic, assume fb object is pinned & idle & fenced and 1493 * just update base pointers 1494 */ 1495 if (atomic) 1496 fb_location = radeon_bo_gpu_offset(rbo); 1497 else { 1498 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); 1499 if (unlikely(r != 0)) { 1500 radeon_bo_unreserve(rbo); 1501 return -EINVAL; 1502 } 1503 } 1504 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1505 radeon_bo_unreserve(rbo); 1506 1507 switch (target_fb->pixel_format) { 1508 case DRM_FORMAT_C8: 1509 fb_format = 1510 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | 1511 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; 1512 break; 1513 case DRM_FORMAT_XRGB4444: 1514 case DRM_FORMAT_ARGB4444: 1515 fb_format = 1516 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1517 AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444; 1518 #ifdef __BIG_ENDIAN 1519 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 1520 #endif 1521 break; 1522 case DRM_FORMAT_XRGB1555: 1523 fb_format = 1524 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1525 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; 1526 #ifdef __BIG_ENDIAN 1527 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 1528 #endif 1529 break; 1530 case DRM_FORMAT_RGB565: 1531 fb_format = 1532 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1533 AVIVO_D1GRPH_CONTROL_16BPP_RGB565; 1534 #ifdef __BIG_ENDIAN 1535 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 1536 #endif 1537 break; 1538 case DRM_FORMAT_XRGB8888: 1539 case DRM_FORMAT_ARGB8888: 1540 fb_format = 1541 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | 1542 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; 1543 #ifdef __BIG_ENDIAN 1544 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; 1545 #endif 1546 break; 1547 case DRM_FORMAT_XRGB2101010: 1548 case DRM_FORMAT_ARGB2101010: 1549 fb_format = 1550 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | 1551 AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010; 1552 #ifdef __BIG_ENDIAN 1553 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; 1554 #endif 1555 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1556 bypass_lut = true; 1557 break; 1558 default: 1559 DRM_ERROR("Unsupported screen format %s\n", 1560 drm_get_format_name(target_fb->pixel_format)); 1561 return -EINVAL; 1562 } 1563 1564 if (rdev->family >= CHIP_R600) { 1565 if (tiling_flags & RADEON_TILING_MACRO) 1566 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1; 1567 else if (tiling_flags & RADEON_TILING_MICRO) 1568 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1; 1569 } else { 1570 if (tiling_flags & RADEON_TILING_MACRO) 1571 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; 1572 1573 if (tiling_flags & RADEON_TILING_MICRO) 1574 fb_format |= AVIVO_D1GRPH_TILED; 1575 } 1576 1577 if (radeon_crtc->crtc_id == 0) 1578 WREG32(AVIVO_D1VGA_CONTROL, 0); 1579 else 1580 WREG32(AVIVO_D2VGA_CONTROL, 0); 1581 1582 if (rdev->family >= CHIP_RV770) { 1583 if (radeon_crtc->crtc_id) { 1584 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1585 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1586 } else { 1587 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1588 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1589 } 1590 } 1591 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1592 (u32) fb_location); 1593 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + 1594 radeon_crtc->crtc_offset, (u32) fb_location); 1595 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1596 if (rdev->family >= CHIP_R600) 1597 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1598 1599 /* LUT only has 256 slots for 8 bpc fb. Bypass for > 8 bpc scanout for precision */ 1600 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, 1601 (bypass_lut ? AVIVO_LUT_10BIT_BYPASS_EN : 0), ~AVIVO_LUT_10BIT_BYPASS_EN); 1602 1603 if (bypass_lut) 1604 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 1605 1606 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1607 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1608 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); 1609 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); 1610 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); 1611 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); 1612 1613 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 1614 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 1615 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1616 1617 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1618 target_fb->height); 1619 x &= ~3; 1620 y &= ~1; 1621 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, 1622 (x << 16) | y); 1623 viewport_w = crtc->mode.hdisplay; 1624 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1625 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1626 (viewport_w << 16) | viewport_h); 1627 1628 /* pageflip setup */ 1629 /* make sure flip is at vb rather than hb */ 1630 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); 1631 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN; 1632 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); 1633 1634 /* set pageflip to happen only at start of vblank interval (front porch) */ 1635 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3); 1636 1637 if (!atomic && fb && fb != crtc->primary->fb) { 1638 radeon_fb = to_radeon_framebuffer(fb); 1639 rbo = gem_to_radeon_bo(radeon_fb->obj); 1640 r = radeon_bo_reserve(rbo, false); 1641 if (unlikely(r != 0)) 1642 return r; 1643 radeon_bo_unpin(rbo); 1644 radeon_bo_unreserve(rbo); 1645 } 1646 1647 /* Bytes per pixel may have changed */ 1648 radeon_bandwidth_update(rdev); 1649 1650 return 0; 1651 } 1652 1653 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 1654 struct drm_framebuffer *old_fb) 1655 { 1656 struct drm_device *dev = crtc->dev; 1657 struct radeon_device *rdev = dev->dev_private; 1658 1659 if (ASIC_IS_DCE4(rdev)) 1660 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0); 1661 else if (ASIC_IS_AVIVO(rdev)) 1662 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0); 1663 else 1664 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); 1665 } 1666 1667 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 1668 struct drm_framebuffer *fb, 1669 int x, int y, enum mode_set_atomic state) 1670 { 1671 struct drm_device *dev = crtc->dev; 1672 struct radeon_device *rdev = dev->dev_private; 1673 1674 if (ASIC_IS_DCE4(rdev)) 1675 return dce4_crtc_do_set_base(crtc, fb, x, y, 1); 1676 else if (ASIC_IS_AVIVO(rdev)) 1677 return avivo_crtc_do_set_base(crtc, fb, x, y, 1); 1678 else 1679 return radeon_crtc_do_set_base(crtc, fb, x, y, 1); 1680 } 1681 1682 /* properly set additional regs when using atombios */ 1683 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) 1684 { 1685 struct drm_device *dev = crtc->dev; 1686 struct radeon_device *rdev = dev->dev_private; 1687 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1688 u32 disp_merge_cntl; 1689 1690 switch (radeon_crtc->crtc_id) { 1691 case 0: 1692 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); 1693 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 1694 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); 1695 break; 1696 case 1: 1697 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 1698 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 1699 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); 1700 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); 1701 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); 1702 break; 1703 } 1704 } 1705 1706 /** 1707 * radeon_get_pll_use_mask - look up a mask of which pplls are in use 1708 * 1709 * @crtc: drm crtc 1710 * 1711 * Returns the mask of which PPLLs (Pixel PLLs) are in use. 1712 */ 1713 static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc) 1714 { 1715 struct drm_device *dev = crtc->dev; 1716 struct drm_crtc *test_crtc; 1717 struct radeon_crtc *test_radeon_crtc; 1718 u32 pll_in_use = 0; 1719 1720 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1721 if (crtc == test_crtc) 1722 continue; 1723 1724 test_radeon_crtc = to_radeon_crtc(test_crtc); 1725 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 1726 pll_in_use |= (1 << test_radeon_crtc->pll_id); 1727 } 1728 return pll_in_use; 1729 } 1730 1731 /** 1732 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP 1733 * 1734 * @crtc: drm crtc 1735 * 1736 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is 1737 * also in DP mode. For DP, a single PPLL can be used for all DP 1738 * crtcs/encoders. 1739 */ 1740 static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) 1741 { 1742 struct drm_device *dev = crtc->dev; 1743 struct drm_crtc *test_crtc; 1744 struct radeon_crtc *test_radeon_crtc; 1745 1746 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1747 if (crtc == test_crtc) 1748 continue; 1749 test_radeon_crtc = to_radeon_crtc(test_crtc); 1750 if (test_radeon_crtc->encoder && 1751 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { 1752 /* for DP use the same PLL for all */ 1753 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 1754 return test_radeon_crtc->pll_id; 1755 } 1756 } 1757 return ATOM_PPLL_INVALID; 1758 } 1759 1760 /** 1761 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc 1762 * 1763 * @crtc: drm crtc 1764 * @encoder: drm encoder 1765 * 1766 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can 1767 * be shared (i.e., same clock). 1768 */ 1769 static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc) 1770 { 1771 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1772 struct drm_device *dev = crtc->dev; 1773 struct drm_crtc *test_crtc; 1774 struct radeon_crtc *test_radeon_crtc; 1775 u32 adjusted_clock, test_adjusted_clock; 1776 1777 adjusted_clock = radeon_crtc->adjusted_clock; 1778 1779 if (adjusted_clock == 0) 1780 return ATOM_PPLL_INVALID; 1781 1782 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1783 if (crtc == test_crtc) 1784 continue; 1785 test_radeon_crtc = to_radeon_crtc(test_crtc); 1786 if (test_radeon_crtc->encoder && 1787 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { 1788 /* check if we are already driving this connector with another crtc */ 1789 if (test_radeon_crtc->connector == radeon_crtc->connector) { 1790 /* if we are, return that pll */ 1791 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 1792 return test_radeon_crtc->pll_id; 1793 } 1794 /* for non-DP check the clock */ 1795 test_adjusted_clock = test_radeon_crtc->adjusted_clock; 1796 if ((crtc->mode.clock == test_crtc->mode.clock) && 1797 (adjusted_clock == test_adjusted_clock) && 1798 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) && 1799 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)) 1800 return test_radeon_crtc->pll_id; 1801 } 1802 } 1803 return ATOM_PPLL_INVALID; 1804 } 1805 1806 /** 1807 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc. 1808 * 1809 * @crtc: drm crtc 1810 * 1811 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 1812 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 1813 * monitors a dedicated PPLL must be used. If a particular board has 1814 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 1815 * as there is no need to program the PLL itself. If we are not able to 1816 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 1817 * avoid messing up an existing monitor. 1818 * 1819 * Asic specific PLL information 1820 * 1821 * DCE 8.x 1822 * KB/KV 1823 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 1824 * CI 1825 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1826 * 1827 * DCE 6.1 1828 * - PPLL2 is only available to UNIPHYA (both DP and non-DP) 1829 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP) 1830 * 1831 * DCE 6.0 1832 * - PPLL0 is available to all UNIPHY (DP only) 1833 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1834 * 1835 * DCE 5.0 1836 * - DCPLL is available to all UNIPHY (DP only) 1837 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1838 * 1839 * DCE 3.0/4.0/4.1 1840 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1841 * 1842 */ 1843 static int radeon_atom_pick_pll(struct drm_crtc *crtc) 1844 { 1845 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1846 struct drm_device *dev = crtc->dev; 1847 struct radeon_device *rdev = dev->dev_private; 1848 struct radeon_encoder *radeon_encoder = 1849 to_radeon_encoder(radeon_crtc->encoder); 1850 u32 pll_in_use; 1851 int pll; 1852 1853 if (ASIC_IS_DCE8(rdev)) { 1854 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1855 if (rdev->clock.dp_extclk) 1856 /* skip PPLL programming if using ext clock */ 1857 return ATOM_PPLL_INVALID; 1858 else { 1859 /* use the same PPLL for all DP monitors */ 1860 pll = radeon_get_shared_dp_ppll(crtc); 1861 if (pll != ATOM_PPLL_INVALID) 1862 return pll; 1863 } 1864 } else { 1865 /* use the same PPLL for all monitors with the same clock */ 1866 pll = radeon_get_shared_nondp_ppll(crtc); 1867 if (pll != ATOM_PPLL_INVALID) 1868 return pll; 1869 } 1870 /* otherwise, pick one of the plls */ 1871 if ((rdev->family == CHIP_KABINI) || 1872 (rdev->family == CHIP_MULLINS)) { 1873 /* KB/ML has PPLL1 and PPLL2 */ 1874 pll_in_use = radeon_get_pll_use_mask(crtc); 1875 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1876 return ATOM_PPLL2; 1877 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1878 return ATOM_PPLL1; 1879 DRM_ERROR("unable to allocate a PPLL\n"); 1880 return ATOM_PPLL_INVALID; 1881 } else { 1882 /* CI/KV has PPLL0, PPLL1, and PPLL2 */ 1883 pll_in_use = radeon_get_pll_use_mask(crtc); 1884 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1885 return ATOM_PPLL2; 1886 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1887 return ATOM_PPLL1; 1888 if (!(pll_in_use & (1 << ATOM_PPLL0))) 1889 return ATOM_PPLL0; 1890 DRM_ERROR("unable to allocate a PPLL\n"); 1891 return ATOM_PPLL_INVALID; 1892 } 1893 } else if (ASIC_IS_DCE61(rdev)) { 1894 struct radeon_encoder_atom_dig *dig = 1895 radeon_encoder->enc_priv; 1896 1897 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) && 1898 (dig->linkb == false)) 1899 /* UNIPHY A uses PPLL2 */ 1900 return ATOM_PPLL2; 1901 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1902 /* UNIPHY B/C/D/E/F */ 1903 if (rdev->clock.dp_extclk) 1904 /* skip PPLL programming if using ext clock */ 1905 return ATOM_PPLL_INVALID; 1906 else { 1907 /* use the same PPLL for all DP monitors */ 1908 pll = radeon_get_shared_dp_ppll(crtc); 1909 if (pll != ATOM_PPLL_INVALID) 1910 return pll; 1911 } 1912 } else { 1913 /* use the same PPLL for all monitors with the same clock */ 1914 pll = radeon_get_shared_nondp_ppll(crtc); 1915 if (pll != ATOM_PPLL_INVALID) 1916 return pll; 1917 } 1918 /* UNIPHY B/C/D/E/F */ 1919 pll_in_use = radeon_get_pll_use_mask(crtc); 1920 if (!(pll_in_use & (1 << ATOM_PPLL0))) 1921 return ATOM_PPLL0; 1922 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1923 return ATOM_PPLL1; 1924 DRM_ERROR("unable to allocate a PPLL\n"); 1925 return ATOM_PPLL_INVALID; 1926 } else if (ASIC_IS_DCE41(rdev)) { 1927 /* Don't share PLLs on DCE4.1 chips */ 1928 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1929 if (rdev->clock.dp_extclk) 1930 /* skip PPLL programming if using ext clock */ 1931 return ATOM_PPLL_INVALID; 1932 } 1933 pll_in_use = radeon_get_pll_use_mask(crtc); 1934 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1935 return ATOM_PPLL1; 1936 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1937 return ATOM_PPLL2; 1938 DRM_ERROR("unable to allocate a PPLL\n"); 1939 return ATOM_PPLL_INVALID; 1940 } else if (ASIC_IS_DCE4(rdev)) { 1941 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, 1942 * depending on the asic: 1943 * DCE4: PPLL or ext clock 1944 * DCE5: PPLL, DCPLL, or ext clock 1945 * DCE6: PPLL, PPLL0, or ext clock 1946 * 1947 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip 1948 * PPLL/DCPLL programming and only program the DP DTO for the 1949 * crtc virtual pixel clock. 1950 */ 1951 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1952 if (rdev->clock.dp_extclk) 1953 /* skip PPLL programming if using ext clock */ 1954 return ATOM_PPLL_INVALID; 1955 else if (ASIC_IS_DCE6(rdev)) 1956 /* use PPLL0 for all DP */ 1957 return ATOM_PPLL0; 1958 else if (ASIC_IS_DCE5(rdev)) 1959 /* use DCPLL for all DP */ 1960 return ATOM_DCPLL; 1961 else { 1962 /* use the same PPLL for all DP monitors */ 1963 pll = radeon_get_shared_dp_ppll(crtc); 1964 if (pll != ATOM_PPLL_INVALID) 1965 return pll; 1966 } 1967 } else { 1968 /* use the same PPLL for all monitors with the same clock */ 1969 pll = radeon_get_shared_nondp_ppll(crtc); 1970 if (pll != ATOM_PPLL_INVALID) 1971 return pll; 1972 } 1973 /* all other cases */ 1974 pll_in_use = radeon_get_pll_use_mask(crtc); 1975 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1976 return ATOM_PPLL1; 1977 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1978 return ATOM_PPLL2; 1979 DRM_ERROR("unable to allocate a PPLL\n"); 1980 return ATOM_PPLL_INVALID; 1981 } else { 1982 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ 1983 /* some atombios (observed in some DCE2/DCE3) code have a bug, 1984 * the matching btw pll and crtc is done through 1985 * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the 1986 * pll (1 or 2) to select which register to write. ie if using 1987 * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2 1988 * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to 1989 * choose which value to write. Which is reverse order from 1990 * register logic. So only case that works is when pllid is 1991 * same as crtcid or when both pll and crtc are enabled and 1992 * both use same clock. 1993 * 1994 * So just return crtc id as if crtc and pll were hard linked 1995 * together even if they aren't 1996 */ 1997 return radeon_crtc->crtc_id; 1998 } 1999 } 2000 2001 void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev) 2002 { 2003 /* always set DCPLL */ 2004 if (ASIC_IS_DCE6(rdev)) 2005 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); 2006 else if (ASIC_IS_DCE4(rdev)) { 2007 struct radeon_atom_ss ss; 2008 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, 2009 ASIC_INTERNAL_SS_ON_DCPLL, 2010 rdev->clock.default_dispclk); 2011 if (ss_enabled) 2012 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss); 2013 /* XXX: DCE5, make sure voltage, dispclk is high enough */ 2014 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); 2015 if (ss_enabled) 2016 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss); 2017 } 2018 2019 } 2020 2021 int atombios_crtc_mode_set(struct drm_crtc *crtc, 2022 struct drm_display_mode *mode, 2023 struct drm_display_mode *adjusted_mode, 2024 int x, int y, struct drm_framebuffer *old_fb) 2025 { 2026 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 2027 struct drm_device *dev = crtc->dev; 2028 struct radeon_device *rdev = dev->dev_private; 2029 struct radeon_encoder *radeon_encoder = 2030 to_radeon_encoder(radeon_crtc->encoder); 2031 bool is_tvcv = false; 2032 2033 if (radeon_encoder->active_device & 2034 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2035 is_tvcv = true; 2036 2037 if (!radeon_crtc->adjusted_clock) 2038 return -EINVAL; 2039 2040 atombios_crtc_set_pll(crtc, adjusted_mode); 2041 2042 if (ASIC_IS_DCE4(rdev)) 2043 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 2044 else if (ASIC_IS_AVIVO(rdev)) { 2045 if (is_tvcv) 2046 atombios_crtc_set_timing(crtc, adjusted_mode); 2047 else 2048 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 2049 } else { 2050 atombios_crtc_set_timing(crtc, adjusted_mode); 2051 if (radeon_crtc->crtc_id == 0) 2052 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 2053 radeon_legacy_atom_fixup(crtc); 2054 } 2055 atombios_crtc_set_base(crtc, x, y, old_fb); 2056 atombios_overscan_setup(crtc, mode, adjusted_mode); 2057 atombios_scaler_setup(crtc); 2058 radeon_cursor_reset(crtc); 2059 /* update the hw version fpr dpm */ 2060 radeon_crtc->hw_mode = *adjusted_mode; 2061 2062 return 0; 2063 } 2064 2065 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, 2066 const struct drm_display_mode *mode, 2067 struct drm_display_mode *adjusted_mode) 2068 { 2069 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 2070 struct drm_device *dev = crtc->dev; 2071 struct drm_encoder *encoder; 2072 2073 /* assign the encoder to the radeon crtc to avoid repeated lookups later */ 2074 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2075 if (encoder->crtc == crtc) { 2076 radeon_crtc->encoder = encoder; 2077 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder); 2078 break; 2079 } 2080 } 2081 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) { 2082 radeon_crtc->encoder = NULL; 2083 radeon_crtc->connector = NULL; 2084 return false; 2085 } 2086 if (radeon_crtc->encoder) { 2087 struct radeon_encoder *radeon_encoder = 2088 to_radeon_encoder(radeon_crtc->encoder); 2089 2090 radeon_crtc->output_csc = radeon_encoder->output_csc; 2091 } 2092 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2093 return false; 2094 if (!atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2095 return false; 2096 /* pick pll */ 2097 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); 2098 /* if we can't get a PPLL for a non-DP encoder, fail */ 2099 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) && 2100 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) 2101 return false; 2102 2103 return true; 2104 } 2105 2106 static void atombios_crtc_prepare(struct drm_crtc *crtc) 2107 { 2108 struct drm_device *dev = crtc->dev; 2109 struct radeon_device *rdev = dev->dev_private; 2110 2111 /* disable crtc pair power gating before programming */ 2112 if (ASIC_IS_DCE6(rdev)) 2113 atombios_powergate_crtc(crtc, ATOM_DISABLE); 2114 2115 atombios_lock_crtc(crtc, ATOM_ENABLE); 2116 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2117 } 2118 2119 static void atombios_crtc_commit(struct drm_crtc *crtc) 2120 { 2121 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2122 atombios_lock_crtc(crtc, ATOM_DISABLE); 2123 } 2124 2125 static void atombios_crtc_disable(struct drm_crtc *crtc) 2126 { 2127 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 2128 struct drm_device *dev = crtc->dev; 2129 struct radeon_device *rdev = dev->dev_private; 2130 struct radeon_atom_ss ss; 2131 int i; 2132 2133 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2134 if (crtc->primary->fb) { 2135 int r; 2136 struct radeon_framebuffer *radeon_fb; 2137 struct radeon_bo *rbo; 2138 2139 radeon_fb = to_radeon_framebuffer(crtc->primary->fb); 2140 rbo = gem_to_radeon_bo(radeon_fb->obj); 2141 r = radeon_bo_reserve(rbo, false); 2142 if (unlikely(r)) 2143 DRM_ERROR("failed to reserve rbo before unpin\n"); 2144 else { 2145 radeon_bo_unpin(rbo); 2146 radeon_bo_unreserve(rbo); 2147 } 2148 } 2149 /* disable the GRPH */ 2150 if (ASIC_IS_DCE4(rdev)) 2151 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0); 2152 else if (ASIC_IS_AVIVO(rdev)) 2153 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0); 2154 2155 if (ASIC_IS_DCE6(rdev)) 2156 atombios_powergate_crtc(crtc, ATOM_ENABLE); 2157 2158 for (i = 0; i < rdev->num_crtc; i++) { 2159 if (rdev->mode_info.crtcs[i] && 2160 rdev->mode_info.crtcs[i]->enabled && 2161 i != radeon_crtc->crtc_id && 2162 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) { 2163 /* one other crtc is using this pll don't turn 2164 * off the pll 2165 */ 2166 goto done; 2167 } 2168 } 2169 2170 switch (radeon_crtc->pll_id) { 2171 case ATOM_PPLL1: 2172 case ATOM_PPLL2: 2173 /* disable the ppll */ 2174 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 2175 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2176 break; 2177 case ATOM_PPLL0: 2178 /* disable the ppll */ 2179 if ((rdev->family == CHIP_ARUBA) || 2180 (rdev->family == CHIP_KAVERI) || 2181 (rdev->family == CHIP_BONAIRE) || 2182 (rdev->family == CHIP_HAWAII)) 2183 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 2184 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2185 break; 2186 default: 2187 break; 2188 } 2189 done: 2190 radeon_crtc->pll_id = ATOM_PPLL_INVALID; 2191 radeon_crtc->adjusted_clock = 0; 2192 radeon_crtc->encoder = NULL; 2193 radeon_crtc->connector = NULL; 2194 } 2195 2196 static const struct drm_crtc_helper_funcs atombios_helper_funcs = { 2197 .dpms = atombios_crtc_dpms, 2198 .mode_fixup = atombios_crtc_mode_fixup, 2199 .mode_set = atombios_crtc_mode_set, 2200 .mode_set_base = atombios_crtc_set_base, 2201 .mode_set_base_atomic = atombios_crtc_set_base_atomic, 2202 .prepare = atombios_crtc_prepare, 2203 .commit = atombios_crtc_commit, 2204 .load_lut = radeon_crtc_load_lut, 2205 .disable = atombios_crtc_disable, 2206 }; 2207 2208 void radeon_atombios_init_crtc(struct drm_device *dev, 2209 struct radeon_crtc *radeon_crtc) 2210 { 2211 struct radeon_device *rdev = dev->dev_private; 2212 2213 if (ASIC_IS_DCE4(rdev)) { 2214 switch (radeon_crtc->crtc_id) { 2215 case 0: 2216 default: 2217 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; 2218 break; 2219 case 1: 2220 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; 2221 break; 2222 case 2: 2223 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; 2224 break; 2225 case 3: 2226 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; 2227 break; 2228 case 4: 2229 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; 2230 break; 2231 case 5: 2232 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; 2233 break; 2234 } 2235 } else { 2236 if (radeon_crtc->crtc_id == 1) 2237 radeon_crtc->crtc_offset = 2238 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; 2239 else 2240 radeon_crtc->crtc_offset = 0; 2241 } 2242 radeon_crtc->pll_id = ATOM_PPLL_INVALID; 2243 radeon_crtc->adjusted_clock = 0; 2244 radeon_crtc->encoder = NULL; 2245 radeon_crtc->connector = NULL; 2246 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); 2247 } 2248