1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_crtc_helper.h> 28 #include <drm/radeon_drm.h> 29 #include <drm/drm_fixed.h> 30 #include "radeon.h" 31 #include "atom.h" 32 #include "atom-bits.h" 33 34 static void atombios_overscan_setup(struct drm_crtc *crtc, 35 struct drm_display_mode *mode, 36 struct drm_display_mode *adjusted_mode) 37 { 38 struct drm_device *dev = crtc->dev; 39 struct radeon_device *rdev = dev->dev_private; 40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 41 SET_CRTC_OVERSCAN_PS_ALLOCATION args; 42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); 43 int a1, a2; 44 45 memset(&args, 0, sizeof(args)); 46 47 args.ucCRTC = radeon_crtc->crtc_id; 48 49 switch (radeon_crtc->rmx_type) { 50 case RMX_CENTER: 51 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 52 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 53 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 54 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 55 break; 56 case RMX_ASPECT: 57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; 58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; 59 60 if (a1 > a2) { 61 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 62 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 63 } else if (a2 > a1) { 64 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 65 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 66 } 67 break; 68 case RMX_FULL: 69 default: 70 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); 71 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); 72 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); 73 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); 74 break; 75 } 76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 77 } 78 79 static void atombios_scaler_setup(struct drm_crtc *crtc) 80 { 81 struct drm_device *dev = crtc->dev; 82 struct radeon_device *rdev = dev->dev_private; 83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 84 ENABLE_SCALER_PS_ALLOCATION args; 85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); 86 87 /* fixme - fill in enc_priv for atom dac */ 88 enum radeon_tv_std tv_std = TV_STD_NTSC; 89 bool is_tv = false, is_cv = false; 90 struct drm_encoder *encoder; 91 92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) 93 return; 94 95 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 96 /* find tv std */ 97 if (encoder->crtc == crtc) { 98 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 99 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 100 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 101 tv_std = tv_dac->tv_std; 102 is_tv = true; 103 } 104 } 105 } 106 107 memset(&args, 0, sizeof(args)); 108 109 args.ucScaler = radeon_crtc->crtc_id; 110 111 if (is_tv) { 112 switch (tv_std) { 113 case TV_STD_NTSC: 114 default: 115 args.ucTVStandard = ATOM_TV_NTSC; 116 break; 117 case TV_STD_PAL: 118 args.ucTVStandard = ATOM_TV_PAL; 119 break; 120 case TV_STD_PAL_M: 121 args.ucTVStandard = ATOM_TV_PALM; 122 break; 123 case TV_STD_PAL_60: 124 args.ucTVStandard = ATOM_TV_PAL60; 125 break; 126 case TV_STD_NTSC_J: 127 args.ucTVStandard = ATOM_TV_NTSCJ; 128 break; 129 case TV_STD_SCART_PAL: 130 args.ucTVStandard = ATOM_TV_PAL; /* ??? */ 131 break; 132 case TV_STD_SECAM: 133 args.ucTVStandard = ATOM_TV_SECAM; 134 break; 135 case TV_STD_PAL_CN: 136 args.ucTVStandard = ATOM_TV_PALCN; 137 break; 138 } 139 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 140 } else if (is_cv) { 141 args.ucTVStandard = ATOM_TV_CV; 142 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 143 } else { 144 switch (radeon_crtc->rmx_type) { 145 case RMX_FULL: 146 args.ucEnable = ATOM_SCALER_EXPANSION; 147 break; 148 case RMX_CENTER: 149 args.ucEnable = ATOM_SCALER_CENTER; 150 break; 151 case RMX_ASPECT: 152 args.ucEnable = ATOM_SCALER_EXPANSION; 153 break; 154 default: 155 if (ASIC_IS_AVIVO(rdev)) 156 args.ucEnable = ATOM_SCALER_DISABLE; 157 else 158 args.ucEnable = ATOM_SCALER_CENTER; 159 break; 160 } 161 } 162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 163 if ((is_tv || is_cv) 164 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { 165 atom_rv515_force_tv_scaler(rdev, radeon_crtc); 166 } 167 } 168 169 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) 170 { 171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 172 struct drm_device *dev = crtc->dev; 173 struct radeon_device *rdev = dev->dev_private; 174 int index = 175 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); 176 ENABLE_CRTC_PS_ALLOCATION args; 177 178 memset(&args, 0, sizeof(args)); 179 180 args.ucCRTC = radeon_crtc->crtc_id; 181 args.ucEnable = lock; 182 183 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 184 } 185 186 static void atombios_enable_crtc(struct drm_crtc *crtc, int state) 187 { 188 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 189 struct drm_device *dev = crtc->dev; 190 struct radeon_device *rdev = dev->dev_private; 191 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); 192 ENABLE_CRTC_PS_ALLOCATION args; 193 194 memset(&args, 0, sizeof(args)); 195 196 args.ucCRTC = radeon_crtc->crtc_id; 197 args.ucEnable = state; 198 199 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 200 } 201 202 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) 203 { 204 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 205 struct drm_device *dev = crtc->dev; 206 struct radeon_device *rdev = dev->dev_private; 207 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); 208 ENABLE_CRTC_PS_ALLOCATION args; 209 210 memset(&args, 0, sizeof(args)); 211 212 args.ucCRTC = radeon_crtc->crtc_id; 213 args.ucEnable = state; 214 215 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 216 } 217 218 static void atombios_blank_crtc(struct drm_crtc *crtc, int state) 219 { 220 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 221 struct drm_device *dev = crtc->dev; 222 struct radeon_device *rdev = dev->dev_private; 223 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); 224 BLANK_CRTC_PS_ALLOCATION args; 225 226 memset(&args, 0, sizeof(args)); 227 228 args.ucCRTC = radeon_crtc->crtc_id; 229 args.ucBlanking = state; 230 231 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 232 } 233 234 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) 235 { 236 struct drm_device *dev = crtc->dev; 237 struct radeon_device *rdev = dev->dev_private; 238 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 239 240 switch (mode) { 241 case DRM_MODE_DPMS_ON: 242 radeon_crtc->enabled = true; 243 /* adjust pm to dpms changes BEFORE enabling crtcs */ 244 radeon_pm_compute_clocks(rdev); 245 atombios_enable_crtc(crtc, ATOM_ENABLE); 246 if (ASIC_IS_DCE3(rdev)) 247 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); 248 atombios_blank_crtc(crtc, ATOM_DISABLE); 249 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); 250 radeon_crtc_load_lut(crtc); 251 break; 252 case DRM_MODE_DPMS_STANDBY: 253 case DRM_MODE_DPMS_SUSPEND: 254 case DRM_MODE_DPMS_OFF: 255 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); 256 if (radeon_crtc->enabled) 257 atombios_blank_crtc(crtc, ATOM_ENABLE); 258 if (ASIC_IS_DCE3(rdev)) 259 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); 260 atombios_enable_crtc(crtc, ATOM_DISABLE); 261 radeon_crtc->enabled = false; 262 /* adjust pm to dpms changes AFTER disabling crtcs */ 263 radeon_pm_compute_clocks(rdev); 264 break; 265 } 266 } 267 268 static void 269 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, 270 struct drm_display_mode *mode) 271 { 272 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 273 struct drm_device *dev = crtc->dev; 274 struct radeon_device *rdev = dev->dev_private; 275 SET_CRTC_USING_DTD_TIMING_PARAMETERS args; 276 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); 277 u16 misc = 0; 278 279 memset(&args, 0, sizeof(args)); 280 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); 281 args.usH_Blanking_Time = 282 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); 283 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); 284 args.usV_Blanking_Time = 285 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); 286 args.usH_SyncOffset = 287 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); 288 args.usH_SyncWidth = 289 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 290 args.usV_SyncOffset = 291 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); 292 args.usV_SyncWidth = 293 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 294 args.ucH_Border = radeon_crtc->h_border; 295 args.ucV_Border = radeon_crtc->v_border; 296 297 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 298 misc |= ATOM_VSYNC_POLARITY; 299 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 300 misc |= ATOM_HSYNC_POLARITY; 301 if (mode->flags & DRM_MODE_FLAG_CSYNC) 302 misc |= ATOM_COMPOSITESYNC; 303 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 304 misc |= ATOM_INTERLACE; 305 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 306 misc |= ATOM_DOUBLE_CLOCK_MODE; 307 308 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 309 args.ucCRTC = radeon_crtc->crtc_id; 310 311 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 312 } 313 314 static void atombios_crtc_set_timing(struct drm_crtc *crtc, 315 struct drm_display_mode *mode) 316 { 317 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 318 struct drm_device *dev = crtc->dev; 319 struct radeon_device *rdev = dev->dev_private; 320 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; 321 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); 322 u16 misc = 0; 323 324 memset(&args, 0, sizeof(args)); 325 args.usH_Total = cpu_to_le16(mode->crtc_htotal); 326 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); 327 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); 328 args.usH_SyncWidth = 329 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 330 args.usV_Total = cpu_to_le16(mode->crtc_vtotal); 331 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); 332 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); 333 args.usV_SyncWidth = 334 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 335 336 args.ucOverscanRight = radeon_crtc->h_border; 337 args.ucOverscanLeft = radeon_crtc->h_border; 338 args.ucOverscanBottom = radeon_crtc->v_border; 339 args.ucOverscanTop = radeon_crtc->v_border; 340 341 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 342 misc |= ATOM_VSYNC_POLARITY; 343 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 344 misc |= ATOM_HSYNC_POLARITY; 345 if (mode->flags & DRM_MODE_FLAG_CSYNC) 346 misc |= ATOM_COMPOSITESYNC; 347 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 348 misc |= ATOM_INTERLACE; 349 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 350 misc |= ATOM_DOUBLE_CLOCK_MODE; 351 352 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 353 args.ucCRTC = radeon_crtc->crtc_id; 354 355 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 356 } 357 358 static void atombios_disable_ss(struct drm_crtc *crtc) 359 { 360 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 361 struct drm_device *dev = crtc->dev; 362 struct radeon_device *rdev = dev->dev_private; 363 u32 ss_cntl; 364 365 if (ASIC_IS_DCE4(rdev)) { 366 switch (radeon_crtc->pll_id) { 367 case ATOM_PPLL1: 368 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); 369 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 370 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl); 371 break; 372 case ATOM_PPLL2: 373 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL); 374 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 375 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl); 376 break; 377 case ATOM_DCPLL: 378 case ATOM_PPLL_INVALID: 379 return; 380 } 381 } else if (ASIC_IS_AVIVO(rdev)) { 382 switch (radeon_crtc->pll_id) { 383 case ATOM_PPLL1: 384 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); 385 ss_cntl &= ~1; 386 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl); 387 break; 388 case ATOM_PPLL2: 389 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); 390 ss_cntl &= ~1; 391 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl); 392 break; 393 case ATOM_DCPLL: 394 case ATOM_PPLL_INVALID: 395 return; 396 } 397 } 398 } 399 400 401 union atom_enable_ss { 402 ENABLE_LVDS_SS_PARAMETERS lvds_ss; 403 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2; 404 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; 405 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2; 406 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; 407 }; 408 409 static void atombios_crtc_program_ss(struct drm_crtc *crtc, 410 int enable, 411 int pll_id, 412 struct radeon_atom_ss *ss) 413 { 414 struct drm_device *dev = crtc->dev; 415 struct radeon_device *rdev = dev->dev_private; 416 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); 417 union atom_enable_ss args; 418 419 memset(&args, 0, sizeof(args)); 420 421 if (ASIC_IS_DCE5(rdev)) { 422 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); 423 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 424 switch (pll_id) { 425 case ATOM_PPLL1: 426 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; 427 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 428 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); 429 break; 430 case ATOM_PPLL2: 431 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; 432 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 433 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); 434 break; 435 case ATOM_DCPLL: 436 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; 437 args.v3.usSpreadSpectrumAmount = cpu_to_le16(0); 438 args.v3.usSpreadSpectrumStep = cpu_to_le16(0); 439 break; 440 case ATOM_PPLL_INVALID: 441 return; 442 } 443 args.v3.ucEnable = enable; 444 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK)) 445 args.v3.ucEnable = ATOM_DISABLE; 446 } else if (ASIC_IS_DCE4(rdev)) { 447 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 448 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 449 switch (pll_id) { 450 case ATOM_PPLL1: 451 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL; 452 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 453 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); 454 break; 455 case ATOM_PPLL2: 456 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL; 457 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 458 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); 459 break; 460 case ATOM_DCPLL: 461 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL; 462 args.v2.usSpreadSpectrumAmount = cpu_to_le16(0); 463 args.v2.usSpreadSpectrumStep = cpu_to_le16(0); 464 break; 465 case ATOM_PPLL_INVALID: 466 return; 467 } 468 args.v2.ucEnable = enable; 469 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK)) 470 args.v2.ucEnable = ATOM_DISABLE; 471 } else if (ASIC_IS_DCE3(rdev)) { 472 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 473 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 474 args.v1.ucSpreadSpectrumStep = ss->step; 475 args.v1.ucSpreadSpectrumDelay = ss->delay; 476 args.v1.ucSpreadSpectrumRange = ss->range; 477 args.v1.ucPpll = pll_id; 478 args.v1.ucEnable = enable; 479 } else if (ASIC_IS_AVIVO(rdev)) { 480 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || 481 (ss->type & ATOM_EXTERNAL_SS_MASK)) { 482 atombios_disable_ss(crtc); 483 return; 484 } 485 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 486 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 487 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; 488 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; 489 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; 490 args.lvds_ss_2.ucEnable = enable; 491 } else { 492 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || 493 (ss->type & ATOM_EXTERNAL_SS_MASK)) { 494 atombios_disable_ss(crtc); 495 return; 496 } 497 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 498 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 499 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; 500 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; 501 args.lvds_ss.ucEnable = enable; 502 } 503 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 504 } 505 506 union adjust_pixel_clock { 507 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; 508 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; 509 }; 510 511 static u32 atombios_adjust_pll(struct drm_crtc *crtc, 512 struct drm_display_mode *mode, 513 struct radeon_pll *pll, 514 bool ss_enabled, 515 struct radeon_atom_ss *ss) 516 { 517 struct drm_device *dev = crtc->dev; 518 struct radeon_device *rdev = dev->dev_private; 519 struct drm_encoder *encoder = NULL; 520 struct radeon_encoder *radeon_encoder = NULL; 521 struct drm_connector *connector = NULL; 522 u32 adjusted_clock = mode->clock; 523 int encoder_mode = 0; 524 u32 dp_clock = mode->clock; 525 int bpc = 8; 526 527 /* reset the pll flags */ 528 pll->flags = 0; 529 530 if (ASIC_IS_AVIVO(rdev)) { 531 if ((rdev->family == CHIP_RS600) || 532 (rdev->family == CHIP_RS690) || 533 (rdev->family == CHIP_RS740)) 534 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ 535 RADEON_PLL_PREFER_CLOSEST_LOWER); 536 537 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ 538 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 539 else 540 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 541 542 if (rdev->family < CHIP_RV770) 543 pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; 544 } else { 545 pll->flags |= RADEON_PLL_LEGACY; 546 547 if (mode->clock > 200000) /* range limits??? */ 548 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 549 else 550 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 551 } 552 553 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 554 if (encoder->crtc == crtc) { 555 radeon_encoder = to_radeon_encoder(encoder); 556 connector = radeon_get_connector_for_encoder(encoder); 557 if (connector) 558 bpc = connector->display_info.bpc; 559 encoder_mode = atombios_get_encoder_mode(encoder); 560 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || 561 radeon_encoder_is_dp_bridge(encoder)) { 562 if (connector) { 563 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 564 struct radeon_connector_atom_dig *dig_connector = 565 radeon_connector->con_priv; 566 567 dp_clock = dig_connector->dp_clock; 568 } 569 } 570 571 /* use recommended ref_div for ss */ 572 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 573 if (ss_enabled) { 574 if (ss->refdiv) { 575 pll->flags |= RADEON_PLL_USE_REF_DIV; 576 pll->reference_div = ss->refdiv; 577 if (ASIC_IS_AVIVO(rdev)) 578 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; 579 } 580 } 581 } 582 583 if (ASIC_IS_AVIVO(rdev)) { 584 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ 585 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) 586 adjusted_clock = mode->clock * 2; 587 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 588 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; 589 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 590 pll->flags |= RADEON_PLL_IS_LCD; 591 } else { 592 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 593 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; 594 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) 595 pll->flags |= RADEON_PLL_USE_REF_DIV; 596 } 597 break; 598 } 599 } 600 601 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock 602 * accordingly based on the encoder/transmitter to work around 603 * special hw requirements. 604 */ 605 if (ASIC_IS_DCE3(rdev)) { 606 union adjust_pixel_clock args; 607 u8 frev, crev; 608 int index; 609 610 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); 611 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 612 &crev)) 613 return adjusted_clock; 614 615 memset(&args, 0, sizeof(args)); 616 617 switch (frev) { 618 case 1: 619 switch (crev) { 620 case 1: 621 case 2: 622 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); 623 args.v1.ucTransmitterID = radeon_encoder->encoder_id; 624 args.v1.ucEncodeMode = encoder_mode; 625 if (ss_enabled && ss->percentage) 626 args.v1.ucConfig |= 627 ADJUST_DISPLAY_CONFIG_SS_ENABLE; 628 629 atom_execute_table(rdev->mode_info.atom_context, 630 index, (uint32_t *)&args); 631 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; 632 break; 633 case 3: 634 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10); 635 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; 636 args.v3.sInput.ucEncodeMode = encoder_mode; 637 args.v3.sInput.ucDispPllConfig = 0; 638 if (ss_enabled && ss->percentage) 639 args.v3.sInput.ucDispPllConfig |= 640 DISPPLL_CONFIG_SS_ENABLE; 641 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT) || 642 radeon_encoder_is_dp_bridge(encoder)) { 643 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 644 if (encoder_mode == ATOM_ENCODER_MODE_DP) { 645 args.v3.sInput.ucDispPllConfig |= 646 DISPPLL_CONFIG_COHERENT_MODE; 647 /* 16200 or 27000 */ 648 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); 649 } else { 650 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { 651 /* deep color support */ 652 args.v3.sInput.usPixelClock = 653 cpu_to_le16((mode->clock * bpc / 8) / 10); 654 } 655 if (dig->coherent_mode) 656 args.v3.sInput.ucDispPllConfig |= 657 DISPPLL_CONFIG_COHERENT_MODE; 658 if (mode->clock > 165000) 659 args.v3.sInput.ucDispPllConfig |= 660 DISPPLL_CONFIG_DUAL_LINK; 661 } 662 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 663 if (encoder_mode == ATOM_ENCODER_MODE_DP) { 664 args.v3.sInput.ucDispPllConfig |= 665 DISPPLL_CONFIG_COHERENT_MODE; 666 /* 16200 or 27000 */ 667 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); 668 } else if (encoder_mode != ATOM_ENCODER_MODE_LVDS) { 669 if (mode->clock > 165000) 670 args.v3.sInput.ucDispPllConfig |= 671 DISPPLL_CONFIG_DUAL_LINK; 672 } 673 } 674 if (radeon_encoder_is_dp_bridge(encoder)) { 675 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder); 676 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); 677 args.v3.sInput.ucExtTransmitterID = ext_radeon_encoder->encoder_id; 678 } else 679 args.v3.sInput.ucExtTransmitterID = 0; 680 681 atom_execute_table(rdev->mode_info.atom_context, 682 index, (uint32_t *)&args); 683 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; 684 if (args.v3.sOutput.ucRefDiv) { 685 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; 686 pll->flags |= RADEON_PLL_USE_REF_DIV; 687 pll->reference_div = args.v3.sOutput.ucRefDiv; 688 } 689 if (args.v3.sOutput.ucPostDiv) { 690 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; 691 pll->flags |= RADEON_PLL_USE_POST_DIV; 692 pll->post_div = args.v3.sOutput.ucPostDiv; 693 } 694 break; 695 default: 696 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 697 return adjusted_clock; 698 } 699 break; 700 default: 701 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 702 return adjusted_clock; 703 } 704 } 705 return adjusted_clock; 706 } 707 708 union set_pixel_clock { 709 SET_PIXEL_CLOCK_PS_ALLOCATION base; 710 PIXEL_CLOCK_PARAMETERS v1; 711 PIXEL_CLOCK_PARAMETERS_V2 v2; 712 PIXEL_CLOCK_PARAMETERS_V3 v3; 713 PIXEL_CLOCK_PARAMETERS_V5 v5; 714 PIXEL_CLOCK_PARAMETERS_V6 v6; 715 }; 716 717 /* on DCE5, make sure the voltage is high enough to support the 718 * required disp clk. 719 */ 720 static void atombios_crtc_set_dcpll(struct drm_crtc *crtc, 721 u32 dispclk) 722 { 723 struct drm_device *dev = crtc->dev; 724 struct radeon_device *rdev = dev->dev_private; 725 u8 frev, crev; 726 int index; 727 union set_pixel_clock args; 728 729 memset(&args, 0, sizeof(args)); 730 731 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 732 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 733 &crev)) 734 return; 735 736 switch (frev) { 737 case 1: 738 switch (crev) { 739 case 5: 740 /* if the default dcpll clock is specified, 741 * SetPixelClock provides the dividers 742 */ 743 args.v5.ucCRTC = ATOM_CRTC_INVALID; 744 args.v5.usPixelClock = cpu_to_le16(dispclk); 745 args.v5.ucPpll = ATOM_DCPLL; 746 break; 747 case 6: 748 /* if the default dcpll clock is specified, 749 * SetPixelClock provides the dividers 750 */ 751 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); 752 args.v6.ucPpll = ATOM_DCPLL; 753 break; 754 default: 755 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 756 return; 757 } 758 break; 759 default: 760 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 761 return; 762 } 763 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 764 } 765 766 static void atombios_crtc_program_pll(struct drm_crtc *crtc, 767 u32 crtc_id, 768 int pll_id, 769 u32 encoder_mode, 770 u32 encoder_id, 771 u32 clock, 772 u32 ref_div, 773 u32 fb_div, 774 u32 frac_fb_div, 775 u32 post_div, 776 int bpc, 777 bool ss_enabled, 778 struct radeon_atom_ss *ss) 779 { 780 struct drm_device *dev = crtc->dev; 781 struct radeon_device *rdev = dev->dev_private; 782 u8 frev, crev; 783 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 784 union set_pixel_clock args; 785 786 memset(&args, 0, sizeof(args)); 787 788 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 789 &crev)) 790 return; 791 792 switch (frev) { 793 case 1: 794 switch (crev) { 795 case 1: 796 if (clock == ATOM_DISABLE) 797 return; 798 args.v1.usPixelClock = cpu_to_le16(clock / 10); 799 args.v1.usRefDiv = cpu_to_le16(ref_div); 800 args.v1.usFbDiv = cpu_to_le16(fb_div); 801 args.v1.ucFracFbDiv = frac_fb_div; 802 args.v1.ucPostDiv = post_div; 803 args.v1.ucPpll = pll_id; 804 args.v1.ucCRTC = crtc_id; 805 args.v1.ucRefDivSrc = 1; 806 break; 807 case 2: 808 args.v2.usPixelClock = cpu_to_le16(clock / 10); 809 args.v2.usRefDiv = cpu_to_le16(ref_div); 810 args.v2.usFbDiv = cpu_to_le16(fb_div); 811 args.v2.ucFracFbDiv = frac_fb_div; 812 args.v2.ucPostDiv = post_div; 813 args.v2.ucPpll = pll_id; 814 args.v2.ucCRTC = crtc_id; 815 args.v2.ucRefDivSrc = 1; 816 break; 817 case 3: 818 args.v3.usPixelClock = cpu_to_le16(clock / 10); 819 args.v3.usRefDiv = cpu_to_le16(ref_div); 820 args.v3.usFbDiv = cpu_to_le16(fb_div); 821 args.v3.ucFracFbDiv = frac_fb_div; 822 args.v3.ucPostDiv = post_div; 823 args.v3.ucPpll = pll_id; 824 args.v3.ucMiscInfo = (pll_id << 2); 825 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 826 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; 827 args.v3.ucTransmitterId = encoder_id; 828 args.v3.ucEncoderMode = encoder_mode; 829 break; 830 case 5: 831 args.v5.ucCRTC = crtc_id; 832 args.v5.usPixelClock = cpu_to_le16(clock / 10); 833 args.v5.ucRefDiv = ref_div; 834 args.v5.usFbDiv = cpu_to_le16(fb_div); 835 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 836 args.v5.ucPostDiv = post_div; 837 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ 838 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 839 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; 840 switch (bpc) { 841 case 8: 842 default: 843 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; 844 break; 845 case 10: 846 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; 847 break; 848 } 849 args.v5.ucTransmitterID = encoder_id; 850 args.v5.ucEncoderMode = encoder_mode; 851 args.v5.ucPpll = pll_id; 852 break; 853 case 6: 854 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10); 855 args.v6.ucRefDiv = ref_div; 856 args.v6.usFbDiv = cpu_to_le16(fb_div); 857 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 858 args.v6.ucPostDiv = post_div; 859 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ 860 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 861 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; 862 switch (bpc) { 863 case 8: 864 default: 865 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; 866 break; 867 case 10: 868 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP; 869 break; 870 case 12: 871 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP; 872 break; 873 case 16: 874 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; 875 break; 876 } 877 args.v6.ucTransmitterID = encoder_id; 878 args.v6.ucEncoderMode = encoder_mode; 879 args.v6.ucPpll = pll_id; 880 break; 881 default: 882 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 883 return; 884 } 885 break; 886 default: 887 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 888 return; 889 } 890 891 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 892 } 893 894 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 895 { 896 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 897 struct drm_device *dev = crtc->dev; 898 struct radeon_device *rdev = dev->dev_private; 899 struct drm_encoder *encoder = NULL; 900 struct radeon_encoder *radeon_encoder = NULL; 901 u32 pll_clock = mode->clock; 902 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; 903 struct radeon_pll *pll; 904 u32 adjusted_clock; 905 int encoder_mode = 0; 906 struct radeon_atom_ss ss; 907 bool ss_enabled = false; 908 int bpc = 8; 909 910 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 911 if (encoder->crtc == crtc) { 912 radeon_encoder = to_radeon_encoder(encoder); 913 encoder_mode = atombios_get_encoder_mode(encoder); 914 break; 915 } 916 } 917 918 if (!radeon_encoder) 919 return; 920 921 switch (radeon_crtc->pll_id) { 922 case ATOM_PPLL1: 923 pll = &rdev->clock.p1pll; 924 break; 925 case ATOM_PPLL2: 926 pll = &rdev->clock.p2pll; 927 break; 928 case ATOM_DCPLL: 929 case ATOM_PPLL_INVALID: 930 default: 931 pll = &rdev->clock.dcpll; 932 break; 933 } 934 935 if (radeon_encoder->active_device & 936 (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) { 937 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 938 struct drm_connector *connector = 939 radeon_get_connector_for_encoder(encoder); 940 struct radeon_connector *radeon_connector = 941 to_radeon_connector(connector); 942 struct radeon_connector_atom_dig *dig_connector = 943 radeon_connector->con_priv; 944 int dp_clock; 945 bpc = connector->display_info.bpc; 946 947 switch (encoder_mode) { 948 case ATOM_ENCODER_MODE_DP: 949 /* DP/eDP */ 950 dp_clock = dig_connector->dp_clock / 10; 951 if (ASIC_IS_DCE4(rdev)) 952 ss_enabled = 953 radeon_atombios_get_asic_ss_info(rdev, &ss, 954 ASIC_INTERNAL_SS_ON_DP, 955 dp_clock); 956 else { 957 if (dp_clock == 16200) { 958 ss_enabled = 959 radeon_atombios_get_ppll_ss_info(rdev, &ss, 960 ATOM_DP_SS_ID2); 961 if (!ss_enabled) 962 ss_enabled = 963 radeon_atombios_get_ppll_ss_info(rdev, &ss, 964 ATOM_DP_SS_ID1); 965 } else 966 ss_enabled = 967 radeon_atombios_get_ppll_ss_info(rdev, &ss, 968 ATOM_DP_SS_ID1); 969 } 970 break; 971 case ATOM_ENCODER_MODE_LVDS: 972 if (ASIC_IS_DCE4(rdev)) 973 ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, 974 dig->lcd_ss_id, 975 mode->clock / 10); 976 else 977 ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss, 978 dig->lcd_ss_id); 979 break; 980 case ATOM_ENCODER_MODE_DVI: 981 if (ASIC_IS_DCE4(rdev)) 982 ss_enabled = 983 radeon_atombios_get_asic_ss_info(rdev, &ss, 984 ASIC_INTERNAL_SS_ON_TMDS, 985 mode->clock / 10); 986 break; 987 case ATOM_ENCODER_MODE_HDMI: 988 if (ASIC_IS_DCE4(rdev)) 989 ss_enabled = 990 radeon_atombios_get_asic_ss_info(rdev, &ss, 991 ASIC_INTERNAL_SS_ON_HDMI, 992 mode->clock / 10); 993 break; 994 default: 995 break; 996 } 997 } 998 999 /* adjust pixel clock as needed */ 1000 adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss); 1001 1002 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1003 /* TV seems to prefer the legacy algo on some boards */ 1004 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, 1005 &ref_div, &post_div); 1006 else if (ASIC_IS_AVIVO(rdev)) 1007 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, 1008 &ref_div, &post_div); 1009 else 1010 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, 1011 &ref_div, &post_div); 1012 1013 atombios_crtc_program_ss(crtc, ATOM_DISABLE, radeon_crtc->pll_id, &ss); 1014 1015 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 1016 encoder_mode, radeon_encoder->encoder_id, mode->clock, 1017 ref_div, fb_div, frac_fb_div, post_div, bpc, ss_enabled, &ss); 1018 1019 if (ss_enabled) { 1020 /* calculate ss amount and step size */ 1021 if (ASIC_IS_DCE4(rdev)) { 1022 u32 step_size; 1023 u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000; 1024 ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; 1025 ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & 1026 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK; 1027 if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) 1028 step_size = (4 * amount * ref_div * (ss.rate * 2048)) / 1029 (125 * 25 * pll->reference_freq / 100); 1030 else 1031 step_size = (2 * amount * ref_div * (ss.rate * 2048)) / 1032 (125 * 25 * pll->reference_freq / 100); 1033 ss.step = step_size; 1034 } 1035 1036 atombios_crtc_program_ss(crtc, ATOM_ENABLE, radeon_crtc->pll_id, &ss); 1037 } 1038 } 1039 1040 static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 1041 struct drm_framebuffer *fb, 1042 int x, int y, int atomic) 1043 { 1044 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1045 struct drm_device *dev = crtc->dev; 1046 struct radeon_device *rdev = dev->dev_private; 1047 struct radeon_framebuffer *radeon_fb; 1048 struct drm_framebuffer *target_fb; 1049 struct drm_gem_object *obj; 1050 struct radeon_bo *rbo; 1051 uint64_t fb_location; 1052 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1053 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); 1054 u32 tmp, viewport_w, viewport_h; 1055 int r; 1056 1057 /* no fb bound */ 1058 if (!atomic && !crtc->fb) { 1059 DRM_DEBUG_KMS("No FB bound\n"); 1060 return 0; 1061 } 1062 1063 if (atomic) { 1064 radeon_fb = to_radeon_framebuffer(fb); 1065 target_fb = fb; 1066 } 1067 else { 1068 radeon_fb = to_radeon_framebuffer(crtc->fb); 1069 target_fb = crtc->fb; 1070 } 1071 1072 /* If atomic, assume fb object is pinned & idle & fenced and 1073 * just update base pointers 1074 */ 1075 obj = radeon_fb->obj; 1076 rbo = gem_to_radeon_bo(obj); 1077 r = radeon_bo_reserve(rbo, false); 1078 if (unlikely(r != 0)) 1079 return r; 1080 1081 if (atomic) 1082 fb_location = radeon_bo_gpu_offset(rbo); 1083 else { 1084 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); 1085 if (unlikely(r != 0)) { 1086 radeon_bo_unreserve(rbo); 1087 return -EINVAL; 1088 } 1089 } 1090 1091 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1092 radeon_bo_unreserve(rbo); 1093 1094 switch (target_fb->bits_per_pixel) { 1095 case 8: 1096 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | 1097 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); 1098 break; 1099 case 15: 1100 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1101 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); 1102 break; 1103 case 16: 1104 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1105 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); 1106 #ifdef __BIG_ENDIAN 1107 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1108 #endif 1109 break; 1110 case 24: 1111 case 32: 1112 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1113 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); 1114 #ifdef __BIG_ENDIAN 1115 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1116 #endif 1117 break; 1118 default: 1119 DRM_ERROR("Unsupported screen depth %d\n", 1120 target_fb->bits_per_pixel); 1121 return -EINVAL; 1122 } 1123 1124 if (tiling_flags & RADEON_TILING_MACRO) 1125 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); 1126 else if (tiling_flags & RADEON_TILING_MICRO) 1127 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); 1128 1129 switch (radeon_crtc->crtc_id) { 1130 case 0: 1131 WREG32(AVIVO_D1VGA_CONTROL, 0); 1132 break; 1133 case 1: 1134 WREG32(AVIVO_D2VGA_CONTROL, 0); 1135 break; 1136 case 2: 1137 WREG32(EVERGREEN_D3VGA_CONTROL, 0); 1138 break; 1139 case 3: 1140 WREG32(EVERGREEN_D4VGA_CONTROL, 0); 1141 break; 1142 case 4: 1143 WREG32(EVERGREEN_D5VGA_CONTROL, 0); 1144 break; 1145 case 5: 1146 WREG32(EVERGREEN_D6VGA_CONTROL, 0); 1147 break; 1148 default: 1149 break; 1150 } 1151 1152 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 1153 upper_32_bits(fb_location)); 1154 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 1155 upper_32_bits(fb_location)); 1156 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1157 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1158 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1159 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1160 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1161 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1162 1163 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1164 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1165 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); 1166 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); 1167 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); 1168 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); 1169 1170 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8); 1171 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 1172 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1173 1174 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1175 crtc->mode.vdisplay); 1176 x &= ~3; 1177 y &= ~1; 1178 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, 1179 (x << 16) | y); 1180 viewport_w = crtc->mode.hdisplay; 1181 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1182 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1183 (viewport_w << 16) | viewport_h); 1184 1185 /* pageflip setup */ 1186 /* make sure flip is at vb rather than hb */ 1187 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); 1188 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN; 1189 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); 1190 1191 /* set pageflip to happen anywhere in vblank interval */ 1192 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); 1193 1194 if (!atomic && fb && fb != crtc->fb) { 1195 radeon_fb = to_radeon_framebuffer(fb); 1196 rbo = gem_to_radeon_bo(radeon_fb->obj); 1197 r = radeon_bo_reserve(rbo, false); 1198 if (unlikely(r != 0)) 1199 return r; 1200 radeon_bo_unpin(rbo); 1201 radeon_bo_unreserve(rbo); 1202 } 1203 1204 /* Bytes per pixel may have changed */ 1205 radeon_bandwidth_update(rdev); 1206 1207 return 0; 1208 } 1209 1210 static int avivo_crtc_do_set_base(struct drm_crtc *crtc, 1211 struct drm_framebuffer *fb, 1212 int x, int y, int atomic) 1213 { 1214 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1215 struct drm_device *dev = crtc->dev; 1216 struct radeon_device *rdev = dev->dev_private; 1217 struct radeon_framebuffer *radeon_fb; 1218 struct drm_gem_object *obj; 1219 struct radeon_bo *rbo; 1220 struct drm_framebuffer *target_fb; 1221 uint64_t fb_location; 1222 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1223 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; 1224 u32 tmp, viewport_w, viewport_h; 1225 int r; 1226 1227 /* no fb bound */ 1228 if (!atomic && !crtc->fb) { 1229 DRM_DEBUG_KMS("No FB bound\n"); 1230 return 0; 1231 } 1232 1233 if (atomic) { 1234 radeon_fb = to_radeon_framebuffer(fb); 1235 target_fb = fb; 1236 } 1237 else { 1238 radeon_fb = to_radeon_framebuffer(crtc->fb); 1239 target_fb = crtc->fb; 1240 } 1241 1242 obj = radeon_fb->obj; 1243 rbo = gem_to_radeon_bo(obj); 1244 r = radeon_bo_reserve(rbo, false); 1245 if (unlikely(r != 0)) 1246 return r; 1247 1248 /* If atomic, assume fb object is pinned & idle & fenced and 1249 * just update base pointers 1250 */ 1251 if (atomic) 1252 fb_location = radeon_bo_gpu_offset(rbo); 1253 else { 1254 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); 1255 if (unlikely(r != 0)) { 1256 radeon_bo_unreserve(rbo); 1257 return -EINVAL; 1258 } 1259 } 1260 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1261 radeon_bo_unreserve(rbo); 1262 1263 switch (target_fb->bits_per_pixel) { 1264 case 8: 1265 fb_format = 1266 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | 1267 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; 1268 break; 1269 case 15: 1270 fb_format = 1271 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1272 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; 1273 break; 1274 case 16: 1275 fb_format = 1276 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1277 AVIVO_D1GRPH_CONTROL_16BPP_RGB565; 1278 #ifdef __BIG_ENDIAN 1279 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 1280 #endif 1281 break; 1282 case 24: 1283 case 32: 1284 fb_format = 1285 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | 1286 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; 1287 #ifdef __BIG_ENDIAN 1288 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; 1289 #endif 1290 break; 1291 default: 1292 DRM_ERROR("Unsupported screen depth %d\n", 1293 target_fb->bits_per_pixel); 1294 return -EINVAL; 1295 } 1296 1297 if (rdev->family >= CHIP_R600) { 1298 if (tiling_flags & RADEON_TILING_MACRO) 1299 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1; 1300 else if (tiling_flags & RADEON_TILING_MICRO) 1301 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1; 1302 } else { 1303 if (tiling_flags & RADEON_TILING_MACRO) 1304 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; 1305 1306 if (tiling_flags & RADEON_TILING_MICRO) 1307 fb_format |= AVIVO_D1GRPH_TILED; 1308 } 1309 1310 if (radeon_crtc->crtc_id == 0) 1311 WREG32(AVIVO_D1VGA_CONTROL, 0); 1312 else 1313 WREG32(AVIVO_D2VGA_CONTROL, 0); 1314 1315 if (rdev->family >= CHIP_RV770) { 1316 if (radeon_crtc->crtc_id) { 1317 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1318 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1319 } else { 1320 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1321 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1322 } 1323 } 1324 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1325 (u32) fb_location); 1326 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + 1327 radeon_crtc->crtc_offset, (u32) fb_location); 1328 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1329 if (rdev->family >= CHIP_R600) 1330 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1331 1332 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1333 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1334 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); 1335 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); 1336 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); 1337 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); 1338 1339 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8); 1340 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 1341 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1342 1343 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1344 crtc->mode.vdisplay); 1345 x &= ~3; 1346 y &= ~1; 1347 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, 1348 (x << 16) | y); 1349 viewport_w = crtc->mode.hdisplay; 1350 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1351 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1352 (viewport_w << 16) | viewport_h); 1353 1354 /* pageflip setup */ 1355 /* make sure flip is at vb rather than hb */ 1356 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); 1357 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN; 1358 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); 1359 1360 /* set pageflip to happen anywhere in vblank interval */ 1361 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); 1362 1363 if (!atomic && fb && fb != crtc->fb) { 1364 radeon_fb = to_radeon_framebuffer(fb); 1365 rbo = gem_to_radeon_bo(radeon_fb->obj); 1366 r = radeon_bo_reserve(rbo, false); 1367 if (unlikely(r != 0)) 1368 return r; 1369 radeon_bo_unpin(rbo); 1370 radeon_bo_unreserve(rbo); 1371 } 1372 1373 /* Bytes per pixel may have changed */ 1374 radeon_bandwidth_update(rdev); 1375 1376 return 0; 1377 } 1378 1379 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 1380 struct drm_framebuffer *old_fb) 1381 { 1382 struct drm_device *dev = crtc->dev; 1383 struct radeon_device *rdev = dev->dev_private; 1384 1385 if (ASIC_IS_DCE4(rdev)) 1386 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0); 1387 else if (ASIC_IS_AVIVO(rdev)) 1388 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0); 1389 else 1390 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); 1391 } 1392 1393 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 1394 struct drm_framebuffer *fb, 1395 int x, int y, enum mode_set_atomic state) 1396 { 1397 struct drm_device *dev = crtc->dev; 1398 struct radeon_device *rdev = dev->dev_private; 1399 1400 if (ASIC_IS_DCE4(rdev)) 1401 return dce4_crtc_do_set_base(crtc, fb, x, y, 1); 1402 else if (ASIC_IS_AVIVO(rdev)) 1403 return avivo_crtc_do_set_base(crtc, fb, x, y, 1); 1404 else 1405 return radeon_crtc_do_set_base(crtc, fb, x, y, 1); 1406 } 1407 1408 /* properly set additional regs when using atombios */ 1409 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) 1410 { 1411 struct drm_device *dev = crtc->dev; 1412 struct radeon_device *rdev = dev->dev_private; 1413 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1414 u32 disp_merge_cntl; 1415 1416 switch (radeon_crtc->crtc_id) { 1417 case 0: 1418 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); 1419 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 1420 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); 1421 break; 1422 case 1: 1423 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 1424 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 1425 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); 1426 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); 1427 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); 1428 break; 1429 } 1430 } 1431 1432 static int radeon_atom_pick_pll(struct drm_crtc *crtc) 1433 { 1434 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1435 struct drm_device *dev = crtc->dev; 1436 struct radeon_device *rdev = dev->dev_private; 1437 struct drm_encoder *test_encoder; 1438 struct drm_crtc *test_crtc; 1439 uint32_t pll_in_use = 0; 1440 1441 if (ASIC_IS_DCE4(rdev)) { 1442 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 1443 if (test_encoder->crtc && (test_encoder->crtc == crtc)) { 1444 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, 1445 * depending on the asic: 1446 * DCE4: PPLL or ext clock 1447 * DCE5: DCPLL or ext clock 1448 * 1449 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip 1450 * PPLL/DCPLL programming and only program the DP DTO for the 1451 * crtc virtual pixel clock. 1452 */ 1453 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) { 1454 if (ASIC_IS_DCE5(rdev) || rdev->clock.dp_extclk) 1455 return ATOM_PPLL_INVALID; 1456 } 1457 } 1458 } 1459 1460 /* otherwise, pick one of the plls */ 1461 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1462 struct radeon_crtc *radeon_test_crtc; 1463 1464 if (crtc == test_crtc) 1465 continue; 1466 1467 radeon_test_crtc = to_radeon_crtc(test_crtc); 1468 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) && 1469 (radeon_test_crtc->pll_id <= ATOM_PPLL2)) 1470 pll_in_use |= (1 << radeon_test_crtc->pll_id); 1471 } 1472 if (!(pll_in_use & 1)) 1473 return ATOM_PPLL1; 1474 return ATOM_PPLL2; 1475 } else 1476 return radeon_crtc->crtc_id; 1477 1478 } 1479 1480 int atombios_crtc_mode_set(struct drm_crtc *crtc, 1481 struct drm_display_mode *mode, 1482 struct drm_display_mode *adjusted_mode, 1483 int x, int y, struct drm_framebuffer *old_fb) 1484 { 1485 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1486 struct drm_device *dev = crtc->dev; 1487 struct radeon_device *rdev = dev->dev_private; 1488 struct drm_encoder *encoder; 1489 bool is_tvcv = false; 1490 1491 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1492 /* find tv std */ 1493 if (encoder->crtc == crtc) { 1494 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1495 if (radeon_encoder->active_device & 1496 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 1497 is_tvcv = true; 1498 } 1499 } 1500 1501 /* always set DCPLL */ 1502 if (ASIC_IS_DCE4(rdev)) { 1503 struct radeon_atom_ss ss; 1504 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, 1505 ASIC_INTERNAL_SS_ON_DCPLL, 1506 rdev->clock.default_dispclk); 1507 if (ss_enabled) 1508 atombios_crtc_program_ss(crtc, ATOM_DISABLE, ATOM_DCPLL, &ss); 1509 /* XXX: DCE5, make sure voltage, dispclk is high enough */ 1510 atombios_crtc_set_dcpll(crtc, rdev->clock.default_dispclk); 1511 if (ss_enabled) 1512 atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL, &ss); 1513 } 1514 atombios_crtc_set_pll(crtc, adjusted_mode); 1515 1516 if (ASIC_IS_DCE4(rdev)) 1517 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1518 else if (ASIC_IS_AVIVO(rdev)) { 1519 if (is_tvcv) 1520 atombios_crtc_set_timing(crtc, adjusted_mode); 1521 else 1522 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1523 } else { 1524 atombios_crtc_set_timing(crtc, adjusted_mode); 1525 if (radeon_crtc->crtc_id == 0) 1526 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1527 radeon_legacy_atom_fixup(crtc); 1528 } 1529 atombios_crtc_set_base(crtc, x, y, old_fb); 1530 atombios_overscan_setup(crtc, mode, adjusted_mode); 1531 atombios_scaler_setup(crtc); 1532 return 0; 1533 } 1534 1535 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, 1536 struct drm_display_mode *mode, 1537 struct drm_display_mode *adjusted_mode) 1538 { 1539 struct drm_device *dev = crtc->dev; 1540 struct radeon_device *rdev = dev->dev_private; 1541 1542 /* adjust pm to upcoming mode change */ 1543 radeon_pm_compute_clocks(rdev); 1544 1545 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 1546 return false; 1547 return true; 1548 } 1549 1550 static void atombios_crtc_prepare(struct drm_crtc *crtc) 1551 { 1552 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1553 1554 /* pick pll */ 1555 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); 1556 1557 atombios_lock_crtc(crtc, ATOM_ENABLE); 1558 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1559 } 1560 1561 static void atombios_crtc_commit(struct drm_crtc *crtc) 1562 { 1563 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 1564 atombios_lock_crtc(crtc, ATOM_DISABLE); 1565 } 1566 1567 static void atombios_crtc_disable(struct drm_crtc *crtc) 1568 { 1569 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1570 struct radeon_atom_ss ss; 1571 1572 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1573 1574 switch (radeon_crtc->pll_id) { 1575 case ATOM_PPLL1: 1576 case ATOM_PPLL2: 1577 /* disable the ppll */ 1578 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 1579 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 1580 break; 1581 default: 1582 break; 1583 } 1584 radeon_crtc->pll_id = -1; 1585 } 1586 1587 static const struct drm_crtc_helper_funcs atombios_helper_funcs = { 1588 .dpms = atombios_crtc_dpms, 1589 .mode_fixup = atombios_crtc_mode_fixup, 1590 .mode_set = atombios_crtc_mode_set, 1591 .mode_set_base = atombios_crtc_set_base, 1592 .mode_set_base_atomic = atombios_crtc_set_base_atomic, 1593 .prepare = atombios_crtc_prepare, 1594 .commit = atombios_crtc_commit, 1595 .load_lut = radeon_crtc_load_lut, 1596 .disable = atombios_crtc_disable, 1597 }; 1598 1599 void radeon_atombios_init_crtc(struct drm_device *dev, 1600 struct radeon_crtc *radeon_crtc) 1601 { 1602 struct radeon_device *rdev = dev->dev_private; 1603 1604 if (ASIC_IS_DCE4(rdev)) { 1605 switch (radeon_crtc->crtc_id) { 1606 case 0: 1607 default: 1608 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; 1609 break; 1610 case 1: 1611 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; 1612 break; 1613 case 2: 1614 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; 1615 break; 1616 case 3: 1617 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; 1618 break; 1619 case 4: 1620 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; 1621 break; 1622 case 5: 1623 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; 1624 break; 1625 } 1626 } else { 1627 if (radeon_crtc->crtc_id == 1) 1628 radeon_crtc->crtc_offset = 1629 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; 1630 else 1631 radeon_crtc->crtc_offset = 0; 1632 } 1633 radeon_crtc->pll_id = -1; 1634 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); 1635 } 1636