1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2007-8 Advanced Micro Devices, Inc. 3771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 4771fe6b9SJerome Glisse * 5771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 6771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 7771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 8771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 10771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 11771fe6b9SJerome Glisse * 12771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 13771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 14771fe6b9SJerome Glisse * 15771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 22771fe6b9SJerome Glisse * 23771fe6b9SJerome Glisse * Authors: Dave Airlie 24771fe6b9SJerome Glisse * Alex Deucher 25771fe6b9SJerome Glisse */ 26771fe6b9SJerome Glisse #include <drm/drmP.h> 27771fe6b9SJerome Glisse #include <drm/drm_crtc_helper.h> 28771fe6b9SJerome Glisse #include <drm/radeon_drm.h> 2968adac5eSBen Skeggs #include <drm/drm_fixed.h> 30771fe6b9SJerome Glisse #include "radeon.h" 31771fe6b9SJerome Glisse #include "atom.h" 32771fe6b9SJerome Glisse #include "atom-bits.h" 33771fe6b9SJerome Glisse 34c93bb85bSJerome Glisse static void atombios_overscan_setup(struct drm_crtc *crtc, 35c93bb85bSJerome Glisse struct drm_display_mode *mode, 36c93bb85bSJerome Glisse struct drm_display_mode *adjusted_mode) 37c93bb85bSJerome Glisse { 38c93bb85bSJerome Glisse struct drm_device *dev = crtc->dev; 39c93bb85bSJerome Glisse struct radeon_device *rdev = dev->dev_private; 40c93bb85bSJerome Glisse struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 41c93bb85bSJerome Glisse SET_CRTC_OVERSCAN_PS_ALLOCATION args; 42c93bb85bSJerome Glisse int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); 43c93bb85bSJerome Glisse int a1, a2; 44c93bb85bSJerome Glisse 45c93bb85bSJerome Glisse memset(&args, 0, sizeof(args)); 46c93bb85bSJerome Glisse 47c93bb85bSJerome Glisse args.ucCRTC = radeon_crtc->crtc_id; 48c93bb85bSJerome Glisse 49c93bb85bSJerome Glisse switch (radeon_crtc->rmx_type) { 50c93bb85bSJerome Glisse case RMX_CENTER: 514589433cSCédric Cano args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 524589433cSCédric Cano args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 534589433cSCédric Cano args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 544589433cSCédric Cano args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 55c93bb85bSJerome Glisse break; 56c93bb85bSJerome Glisse case RMX_ASPECT: 57c93bb85bSJerome Glisse a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; 58c93bb85bSJerome Glisse a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; 59c93bb85bSJerome Glisse 60c93bb85bSJerome Glisse if (a1 > a2) { 614589433cSCédric Cano args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 624589433cSCédric Cano args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 63c93bb85bSJerome Glisse } else if (a2 > a1) { 64942b0e95SAlex Deucher args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 65942b0e95SAlex Deucher args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 66c93bb85bSJerome Glisse } 67c93bb85bSJerome Glisse break; 68c93bb85bSJerome Glisse case RMX_FULL: 69c93bb85bSJerome Glisse default: 704589433cSCédric Cano args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); 714589433cSCédric Cano args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); 724589433cSCédric Cano args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); 734589433cSCédric Cano args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); 74c93bb85bSJerome Glisse break; 75c93bb85bSJerome Glisse } 765b1714d3SAlex Deucher atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 77c93bb85bSJerome Glisse } 78c93bb85bSJerome Glisse 79c93bb85bSJerome Glisse static void atombios_scaler_setup(struct drm_crtc *crtc) 80c93bb85bSJerome Glisse { 81c93bb85bSJerome Glisse struct drm_device *dev = crtc->dev; 82c93bb85bSJerome Glisse struct radeon_device *rdev = dev->dev_private; 83c93bb85bSJerome Glisse struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 84c93bb85bSJerome Glisse ENABLE_SCALER_PS_ALLOCATION args; 85c93bb85bSJerome Glisse int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); 865df3196bSAlex Deucher struct radeon_encoder *radeon_encoder = 875df3196bSAlex Deucher to_radeon_encoder(radeon_crtc->encoder); 88c93bb85bSJerome Glisse /* fixme - fill in enc_priv for atom dac */ 89c93bb85bSJerome Glisse enum radeon_tv_std tv_std = TV_STD_NTSC; 904ce001abSDave Airlie bool is_tv = false, is_cv = false; 91c93bb85bSJerome Glisse 92c93bb85bSJerome Glisse if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) 93c93bb85bSJerome Glisse return; 94c93bb85bSJerome Glisse 954ce001abSDave Airlie if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 964ce001abSDave Airlie struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 974ce001abSDave Airlie tv_std = tv_dac->tv_std; 984ce001abSDave Airlie is_tv = true; 994ce001abSDave Airlie } 1004ce001abSDave Airlie 101c93bb85bSJerome Glisse memset(&args, 0, sizeof(args)); 102c93bb85bSJerome Glisse 103c93bb85bSJerome Glisse args.ucScaler = radeon_crtc->crtc_id; 104c93bb85bSJerome Glisse 1054ce001abSDave Airlie if (is_tv) { 106c93bb85bSJerome Glisse switch (tv_std) { 107c93bb85bSJerome Glisse case TV_STD_NTSC: 108c93bb85bSJerome Glisse default: 109c93bb85bSJerome Glisse args.ucTVStandard = ATOM_TV_NTSC; 110c93bb85bSJerome Glisse break; 111c93bb85bSJerome Glisse case TV_STD_PAL: 112c93bb85bSJerome Glisse args.ucTVStandard = ATOM_TV_PAL; 113c93bb85bSJerome Glisse break; 114c93bb85bSJerome Glisse case TV_STD_PAL_M: 115c93bb85bSJerome Glisse args.ucTVStandard = ATOM_TV_PALM; 116c93bb85bSJerome Glisse break; 117c93bb85bSJerome Glisse case TV_STD_PAL_60: 118c93bb85bSJerome Glisse args.ucTVStandard = ATOM_TV_PAL60; 119c93bb85bSJerome Glisse break; 120c93bb85bSJerome Glisse case TV_STD_NTSC_J: 121c93bb85bSJerome Glisse args.ucTVStandard = ATOM_TV_NTSCJ; 122c93bb85bSJerome Glisse break; 123c93bb85bSJerome Glisse case TV_STD_SCART_PAL: 124c93bb85bSJerome Glisse args.ucTVStandard = ATOM_TV_PAL; /* ??? */ 125c93bb85bSJerome Glisse break; 126c93bb85bSJerome Glisse case TV_STD_SECAM: 127c93bb85bSJerome Glisse args.ucTVStandard = ATOM_TV_SECAM; 128c93bb85bSJerome Glisse break; 129c93bb85bSJerome Glisse case TV_STD_PAL_CN: 130c93bb85bSJerome Glisse args.ucTVStandard = ATOM_TV_PALCN; 131c93bb85bSJerome Glisse break; 132c93bb85bSJerome Glisse } 133c93bb85bSJerome Glisse args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 1344ce001abSDave Airlie } else if (is_cv) { 135c93bb85bSJerome Glisse args.ucTVStandard = ATOM_TV_CV; 136c93bb85bSJerome Glisse args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 137c93bb85bSJerome Glisse } else { 138c93bb85bSJerome Glisse switch (radeon_crtc->rmx_type) { 139c93bb85bSJerome Glisse case RMX_FULL: 140c93bb85bSJerome Glisse args.ucEnable = ATOM_SCALER_EXPANSION; 141c93bb85bSJerome Glisse break; 142c93bb85bSJerome Glisse case RMX_CENTER: 143c93bb85bSJerome Glisse args.ucEnable = ATOM_SCALER_CENTER; 144c93bb85bSJerome Glisse break; 145c93bb85bSJerome Glisse case RMX_ASPECT: 146c93bb85bSJerome Glisse args.ucEnable = ATOM_SCALER_EXPANSION; 147c93bb85bSJerome Glisse break; 148c93bb85bSJerome Glisse default: 149c93bb85bSJerome Glisse if (ASIC_IS_AVIVO(rdev)) 150c93bb85bSJerome Glisse args.ucEnable = ATOM_SCALER_DISABLE; 151c93bb85bSJerome Glisse else 152c93bb85bSJerome Glisse args.ucEnable = ATOM_SCALER_CENTER; 153c93bb85bSJerome Glisse break; 154c93bb85bSJerome Glisse } 155c93bb85bSJerome Glisse } 156c93bb85bSJerome Glisse atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1574ce001abSDave Airlie if ((is_tv || is_cv) 1584ce001abSDave Airlie && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { 1594ce001abSDave Airlie atom_rv515_force_tv_scaler(rdev, radeon_crtc); 160c93bb85bSJerome Glisse } 161c93bb85bSJerome Glisse } 162c93bb85bSJerome Glisse 163771fe6b9SJerome Glisse static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) 164771fe6b9SJerome Glisse { 165771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 166771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 167771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 168771fe6b9SJerome Glisse int index = 169771fe6b9SJerome Glisse GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); 170771fe6b9SJerome Glisse ENABLE_CRTC_PS_ALLOCATION args; 171771fe6b9SJerome Glisse 172771fe6b9SJerome Glisse memset(&args, 0, sizeof(args)); 173771fe6b9SJerome Glisse 174771fe6b9SJerome Glisse args.ucCRTC = radeon_crtc->crtc_id; 175771fe6b9SJerome Glisse args.ucEnable = lock; 176771fe6b9SJerome Glisse 177771fe6b9SJerome Glisse atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 178771fe6b9SJerome Glisse } 179771fe6b9SJerome Glisse 180771fe6b9SJerome Glisse static void atombios_enable_crtc(struct drm_crtc *crtc, int state) 181771fe6b9SJerome Glisse { 182771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 183771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 184771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 185771fe6b9SJerome Glisse int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); 186771fe6b9SJerome Glisse ENABLE_CRTC_PS_ALLOCATION args; 187771fe6b9SJerome Glisse 188771fe6b9SJerome Glisse memset(&args, 0, sizeof(args)); 189771fe6b9SJerome Glisse 190771fe6b9SJerome Glisse args.ucCRTC = radeon_crtc->crtc_id; 191771fe6b9SJerome Glisse args.ucEnable = state; 192771fe6b9SJerome Glisse 193771fe6b9SJerome Glisse atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 194771fe6b9SJerome Glisse } 195771fe6b9SJerome Glisse 196771fe6b9SJerome Glisse static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) 197771fe6b9SJerome Glisse { 198771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 199771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 200771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 201771fe6b9SJerome Glisse int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); 202771fe6b9SJerome Glisse ENABLE_CRTC_PS_ALLOCATION args; 203771fe6b9SJerome Glisse 204771fe6b9SJerome Glisse memset(&args, 0, sizeof(args)); 205771fe6b9SJerome Glisse 206771fe6b9SJerome Glisse args.ucCRTC = radeon_crtc->crtc_id; 207771fe6b9SJerome Glisse args.ucEnable = state; 208771fe6b9SJerome Glisse 209771fe6b9SJerome Glisse atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 210771fe6b9SJerome Glisse } 211771fe6b9SJerome Glisse 212771fe6b9SJerome Glisse static void atombios_blank_crtc(struct drm_crtc *crtc, int state) 213771fe6b9SJerome Glisse { 214771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 215771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 216771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 217771fe6b9SJerome Glisse int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); 218771fe6b9SJerome Glisse BLANK_CRTC_PS_ALLOCATION args; 219771fe6b9SJerome Glisse 220771fe6b9SJerome Glisse memset(&args, 0, sizeof(args)); 221771fe6b9SJerome Glisse 222771fe6b9SJerome Glisse args.ucCRTC = radeon_crtc->crtc_id; 223771fe6b9SJerome Glisse args.ucBlanking = state; 224771fe6b9SJerome Glisse 225771fe6b9SJerome Glisse atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 226771fe6b9SJerome Glisse } 227771fe6b9SJerome Glisse 228fef9f91fSAlex Deucher static void atombios_powergate_crtc(struct drm_crtc *crtc, int state) 229fef9f91fSAlex Deucher { 230fef9f91fSAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 231fef9f91fSAlex Deucher struct drm_device *dev = crtc->dev; 232fef9f91fSAlex Deucher struct radeon_device *rdev = dev->dev_private; 233fef9f91fSAlex Deucher int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating); 234fef9f91fSAlex Deucher ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args; 235fef9f91fSAlex Deucher 236fef9f91fSAlex Deucher memset(&args, 0, sizeof(args)); 237fef9f91fSAlex Deucher 238fef9f91fSAlex Deucher args.ucDispPipeId = radeon_crtc->crtc_id; 239fef9f91fSAlex Deucher args.ucEnable = state; 240fef9f91fSAlex Deucher 241fef9f91fSAlex Deucher atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 242fef9f91fSAlex Deucher } 243fef9f91fSAlex Deucher 244771fe6b9SJerome Glisse void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) 245771fe6b9SJerome Glisse { 246771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 247771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 248500b7587SAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 249771fe6b9SJerome Glisse 250771fe6b9SJerome Glisse switch (mode) { 251771fe6b9SJerome Glisse case DRM_MODE_DPMS_ON: 252d7311171SAlex Deucher radeon_crtc->enabled = true; 253d7311171SAlex Deucher /* adjust pm to dpms changes BEFORE enabling crtcs */ 254d7311171SAlex Deucher radeon_pm_compute_clocks(rdev); 2556c0ae2abSAlex Deucher if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set) 256fef9f91fSAlex Deucher atombios_powergate_crtc(crtc, ATOM_DISABLE); 25737b4390eSAlex Deucher atombios_enable_crtc(crtc, ATOM_ENABLE); 25879f17c64SAlex Deucher if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) 25937b4390eSAlex Deucher atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); 26037b4390eSAlex Deucher atombios_blank_crtc(crtc, ATOM_DISABLE); 261500b7587SAlex Deucher drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); 262500b7587SAlex Deucher radeon_crtc_load_lut(crtc); 263771fe6b9SJerome Glisse break; 264771fe6b9SJerome Glisse case DRM_MODE_DPMS_STANDBY: 265771fe6b9SJerome Glisse case DRM_MODE_DPMS_SUSPEND: 266771fe6b9SJerome Glisse case DRM_MODE_DPMS_OFF: 267500b7587SAlex Deucher drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); 268a93f344dSAlex Deucher if (radeon_crtc->enabled) 26937b4390eSAlex Deucher atombios_blank_crtc(crtc, ATOM_ENABLE); 27079f17c64SAlex Deucher if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) 27137b4390eSAlex Deucher atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); 27237b4390eSAlex Deucher atombios_enable_crtc(crtc, ATOM_DISABLE); 273a48b9b4eSAlex Deucher radeon_crtc->enabled = false; 274c205b232SAlex Deucher if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set) 275fef9f91fSAlex Deucher atombios_powergate_crtc(crtc, ATOM_ENABLE); 276d7311171SAlex Deucher /* adjust pm to dpms changes AFTER disabling crtcs */ 277d7311171SAlex Deucher radeon_pm_compute_clocks(rdev); 278771fe6b9SJerome Glisse break; 279771fe6b9SJerome Glisse } 280771fe6b9SJerome Glisse } 281771fe6b9SJerome Glisse 282771fe6b9SJerome Glisse static void 283771fe6b9SJerome Glisse atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, 2845a9bcaccSAlex Deucher struct drm_display_mode *mode) 285771fe6b9SJerome Glisse { 2865a9bcaccSAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 287771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 288771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 2895a9bcaccSAlex Deucher SET_CRTC_USING_DTD_TIMING_PARAMETERS args; 290771fe6b9SJerome Glisse int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); 2915a9bcaccSAlex Deucher u16 misc = 0; 292771fe6b9SJerome Glisse 2935a9bcaccSAlex Deucher memset(&args, 0, sizeof(args)); 2945b1714d3SAlex Deucher args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); 2955a9bcaccSAlex Deucher args.usH_Blanking_Time = 2965b1714d3SAlex Deucher cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); 2975b1714d3SAlex Deucher args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); 2985a9bcaccSAlex Deucher args.usV_Blanking_Time = 2995b1714d3SAlex Deucher cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); 3005a9bcaccSAlex Deucher args.usH_SyncOffset = 3015b1714d3SAlex Deucher cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); 3025a9bcaccSAlex Deucher args.usH_SyncWidth = 3035a9bcaccSAlex Deucher cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 3045a9bcaccSAlex Deucher args.usV_SyncOffset = 3055b1714d3SAlex Deucher cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); 3065a9bcaccSAlex Deucher args.usV_SyncWidth = 3075a9bcaccSAlex Deucher cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 3085b1714d3SAlex Deucher args.ucH_Border = radeon_crtc->h_border; 3095b1714d3SAlex Deucher args.ucV_Border = radeon_crtc->v_border; 3105a9bcaccSAlex Deucher 3115a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_NVSYNC) 3125a9bcaccSAlex Deucher misc |= ATOM_VSYNC_POLARITY; 3135a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_NHSYNC) 3145a9bcaccSAlex Deucher misc |= ATOM_HSYNC_POLARITY; 3155a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_CSYNC) 3165a9bcaccSAlex Deucher misc |= ATOM_COMPOSITESYNC; 3175a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_INTERLACE) 3185a9bcaccSAlex Deucher misc |= ATOM_INTERLACE; 3195a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 3205a9bcaccSAlex Deucher misc |= ATOM_DOUBLE_CLOCK_MODE; 3215a9bcaccSAlex Deucher 3225a9bcaccSAlex Deucher args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 3235a9bcaccSAlex Deucher args.ucCRTC = radeon_crtc->crtc_id; 324771fe6b9SJerome Glisse 3255a9bcaccSAlex Deucher atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 326771fe6b9SJerome Glisse } 327771fe6b9SJerome Glisse 3285a9bcaccSAlex Deucher static void atombios_crtc_set_timing(struct drm_crtc *crtc, 3295a9bcaccSAlex Deucher struct drm_display_mode *mode) 330771fe6b9SJerome Glisse { 3315a9bcaccSAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 332771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 333771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 3345a9bcaccSAlex Deucher SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; 335771fe6b9SJerome Glisse int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); 3365a9bcaccSAlex Deucher u16 misc = 0; 337771fe6b9SJerome Glisse 3385a9bcaccSAlex Deucher memset(&args, 0, sizeof(args)); 3395a9bcaccSAlex Deucher args.usH_Total = cpu_to_le16(mode->crtc_htotal); 3405a9bcaccSAlex Deucher args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); 3415a9bcaccSAlex Deucher args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); 3425a9bcaccSAlex Deucher args.usH_SyncWidth = 3435a9bcaccSAlex Deucher cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 3445a9bcaccSAlex Deucher args.usV_Total = cpu_to_le16(mode->crtc_vtotal); 3455a9bcaccSAlex Deucher args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); 3465a9bcaccSAlex Deucher args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); 3475a9bcaccSAlex Deucher args.usV_SyncWidth = 3485a9bcaccSAlex Deucher cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 3495a9bcaccSAlex Deucher 35054bfe496SAlex Deucher args.ucOverscanRight = radeon_crtc->h_border; 35154bfe496SAlex Deucher args.ucOverscanLeft = radeon_crtc->h_border; 35254bfe496SAlex Deucher args.ucOverscanBottom = radeon_crtc->v_border; 35354bfe496SAlex Deucher args.ucOverscanTop = radeon_crtc->v_border; 35454bfe496SAlex Deucher 3555a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_NVSYNC) 3565a9bcaccSAlex Deucher misc |= ATOM_VSYNC_POLARITY; 3575a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_NHSYNC) 3585a9bcaccSAlex Deucher misc |= ATOM_HSYNC_POLARITY; 3595a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_CSYNC) 3605a9bcaccSAlex Deucher misc |= ATOM_COMPOSITESYNC; 3615a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_INTERLACE) 3625a9bcaccSAlex Deucher misc |= ATOM_INTERLACE; 3635a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 3645a9bcaccSAlex Deucher misc |= ATOM_DOUBLE_CLOCK_MODE; 3655a9bcaccSAlex Deucher 3665a9bcaccSAlex Deucher args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 3675a9bcaccSAlex Deucher args.ucCRTC = radeon_crtc->crtc_id; 368771fe6b9SJerome Glisse 3695a9bcaccSAlex Deucher atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 370771fe6b9SJerome Glisse } 371771fe6b9SJerome Glisse 3723fa47d9eSAlex Deucher static void atombios_disable_ss(struct radeon_device *rdev, int pll_id) 373b792210eSAlex Deucher { 374b792210eSAlex Deucher u32 ss_cntl; 375b792210eSAlex Deucher 376b792210eSAlex Deucher if (ASIC_IS_DCE4(rdev)) { 3773fa47d9eSAlex Deucher switch (pll_id) { 378b792210eSAlex Deucher case ATOM_PPLL1: 379b792210eSAlex Deucher ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); 380b792210eSAlex Deucher ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 381b792210eSAlex Deucher WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl); 382b792210eSAlex Deucher break; 383b792210eSAlex Deucher case ATOM_PPLL2: 384b792210eSAlex Deucher ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL); 385b792210eSAlex Deucher ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 386b792210eSAlex Deucher WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl); 387b792210eSAlex Deucher break; 388b792210eSAlex Deucher case ATOM_DCPLL: 389b792210eSAlex Deucher case ATOM_PPLL_INVALID: 390b792210eSAlex Deucher return; 391b792210eSAlex Deucher } 392b792210eSAlex Deucher } else if (ASIC_IS_AVIVO(rdev)) { 3933fa47d9eSAlex Deucher switch (pll_id) { 394b792210eSAlex Deucher case ATOM_PPLL1: 395b792210eSAlex Deucher ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); 396b792210eSAlex Deucher ss_cntl &= ~1; 397b792210eSAlex Deucher WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl); 398b792210eSAlex Deucher break; 399b792210eSAlex Deucher case ATOM_PPLL2: 400b792210eSAlex Deucher ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); 401b792210eSAlex Deucher ss_cntl &= ~1; 402b792210eSAlex Deucher WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl); 403b792210eSAlex Deucher break; 404b792210eSAlex Deucher case ATOM_DCPLL: 405b792210eSAlex Deucher case ATOM_PPLL_INVALID: 406b792210eSAlex Deucher return; 407b792210eSAlex Deucher } 408b792210eSAlex Deucher } 409b792210eSAlex Deucher } 410b792210eSAlex Deucher 411b792210eSAlex Deucher 41226b9fc3aSAlex Deucher union atom_enable_ss { 413ba032a58SAlex Deucher ENABLE_LVDS_SS_PARAMETERS lvds_ss; 414ba032a58SAlex Deucher ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2; 41526b9fc3aSAlex Deucher ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; 416ba032a58SAlex Deucher ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2; 417a572eaa3SAlex Deucher ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; 41826b9fc3aSAlex Deucher }; 41926b9fc3aSAlex Deucher 4203fa47d9eSAlex Deucher static void atombios_crtc_program_ss(struct radeon_device *rdev, 421ba032a58SAlex Deucher int enable, 422ba032a58SAlex Deucher int pll_id, 4235efcc76cSJerome Glisse int crtc_id, 424ba032a58SAlex Deucher struct radeon_atom_ss *ss) 425ebbe1cb9SAlex Deucher { 4265efcc76cSJerome Glisse unsigned i; 427ebbe1cb9SAlex Deucher int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); 42826b9fc3aSAlex Deucher union atom_enable_ss args; 429ebbe1cb9SAlex Deucher 4305efcc76cSJerome Glisse if (!enable) { 43153176706SAlex Deucher for (i = 0; i < rdev->num_crtc; i++) { 4325efcc76cSJerome Glisse if (rdev->mode_info.crtcs[i] && 4335efcc76cSJerome Glisse rdev->mode_info.crtcs[i]->enabled && 4345efcc76cSJerome Glisse i != crtc_id && 4355efcc76cSJerome Glisse pll_id == rdev->mode_info.crtcs[i]->pll_id) { 4365efcc76cSJerome Glisse /* one other crtc is using this pll don't turn 4375efcc76cSJerome Glisse * off spread spectrum as it might turn off 4385efcc76cSJerome Glisse * display on active crtc 4395efcc76cSJerome Glisse */ 4405efcc76cSJerome Glisse return; 4415efcc76cSJerome Glisse } 4425efcc76cSJerome Glisse } 4435efcc76cSJerome Glisse } 4445efcc76cSJerome Glisse 445ebbe1cb9SAlex Deucher memset(&args, 0, sizeof(args)); 446ba032a58SAlex Deucher 447a572eaa3SAlex Deucher if (ASIC_IS_DCE5(rdev)) { 4484589433cSCédric Cano args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); 4498e8e523dSAlex Deucher args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 450a572eaa3SAlex Deucher switch (pll_id) { 451a572eaa3SAlex Deucher case ATOM_PPLL1: 452a572eaa3SAlex Deucher args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; 453a572eaa3SAlex Deucher break; 454a572eaa3SAlex Deucher case ATOM_PPLL2: 455a572eaa3SAlex Deucher args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; 456a572eaa3SAlex Deucher break; 457a572eaa3SAlex Deucher case ATOM_DCPLL: 458a572eaa3SAlex Deucher args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; 459a572eaa3SAlex Deucher break; 460a572eaa3SAlex Deucher case ATOM_PPLL_INVALID: 461a572eaa3SAlex Deucher return; 462a572eaa3SAlex Deucher } 463f312f093SAlex Deucher args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 464f312f093SAlex Deucher args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); 465d0ae3e89SAlex Deucher args.v3.ucEnable = enable; 4660671bdd7SAlex Deucher if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE61(rdev)) 4678e8e523dSAlex Deucher args.v3.ucEnable = ATOM_DISABLE; 468a572eaa3SAlex Deucher } else if (ASIC_IS_DCE4(rdev)) { 469ba032a58SAlex Deucher args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 4708e8e523dSAlex Deucher args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 471ba032a58SAlex Deucher switch (pll_id) { 472ba032a58SAlex Deucher case ATOM_PPLL1: 473ba032a58SAlex Deucher args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL; 474ba032a58SAlex Deucher break; 475ba032a58SAlex Deucher case ATOM_PPLL2: 476ba032a58SAlex Deucher args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL; 477ba032a58SAlex Deucher break; 478ba032a58SAlex Deucher case ATOM_DCPLL: 479ba032a58SAlex Deucher args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL; 480ba032a58SAlex Deucher break; 481ba032a58SAlex Deucher case ATOM_PPLL_INVALID: 482ba032a58SAlex Deucher return; 483ba032a58SAlex Deucher } 484f312f093SAlex Deucher args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 485f312f093SAlex Deucher args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); 486ba032a58SAlex Deucher args.v2.ucEnable = enable; 48709cc6506SAlex Deucher if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev)) 4888e8e523dSAlex Deucher args.v2.ucEnable = ATOM_DISABLE; 489ba032a58SAlex Deucher } else if (ASIC_IS_DCE3(rdev)) { 490ba032a58SAlex Deucher args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 4918e8e523dSAlex Deucher args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 492ba032a58SAlex Deucher args.v1.ucSpreadSpectrumStep = ss->step; 493ba032a58SAlex Deucher args.v1.ucSpreadSpectrumDelay = ss->delay; 494ba032a58SAlex Deucher args.v1.ucSpreadSpectrumRange = ss->range; 495ba032a58SAlex Deucher args.v1.ucPpll = pll_id; 496ba032a58SAlex Deucher args.v1.ucEnable = enable; 497ba032a58SAlex Deucher } else if (ASIC_IS_AVIVO(rdev)) { 4988e8e523dSAlex Deucher if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || 4998e8e523dSAlex Deucher (ss->type & ATOM_EXTERNAL_SS_MASK)) { 5003fa47d9eSAlex Deucher atombios_disable_ss(rdev, pll_id); 501ba032a58SAlex Deucher return; 502ba032a58SAlex Deucher } 503ba032a58SAlex Deucher args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 5048e8e523dSAlex Deucher args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 505ba032a58SAlex Deucher args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; 506ba032a58SAlex Deucher args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; 507ba032a58SAlex Deucher args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; 508ba032a58SAlex Deucher args.lvds_ss_2.ucEnable = enable; 509ebbe1cb9SAlex Deucher } else { 5108e8e523dSAlex Deucher if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || 5118e8e523dSAlex Deucher (ss->type & ATOM_EXTERNAL_SS_MASK)) { 5123fa47d9eSAlex Deucher atombios_disable_ss(rdev, pll_id); 513ba032a58SAlex Deucher return; 514ba032a58SAlex Deucher } 515ba032a58SAlex Deucher args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 5168e8e523dSAlex Deucher args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 517ba032a58SAlex Deucher args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; 518ba032a58SAlex Deucher args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; 519ba032a58SAlex Deucher args.lvds_ss.ucEnable = enable; 520ebbe1cb9SAlex Deucher } 52126b9fc3aSAlex Deucher atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 522ebbe1cb9SAlex Deucher } 523ebbe1cb9SAlex Deucher 5244eaeca33SAlex Deucher union adjust_pixel_clock { 5254eaeca33SAlex Deucher ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; 526bcc1c2a1SAlex Deucher ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; 5274eaeca33SAlex Deucher }; 5284eaeca33SAlex Deucher 5294eaeca33SAlex Deucher static u32 atombios_adjust_pll(struct drm_crtc *crtc, 53019eca43eSAlex Deucher struct drm_display_mode *mode) 531771fe6b9SJerome Glisse { 53219eca43eSAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 533771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 534771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 5355df3196bSAlex Deucher struct drm_encoder *encoder = radeon_crtc->encoder; 5365df3196bSAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 5375df3196bSAlex Deucher struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 5384eaeca33SAlex Deucher u32 adjusted_clock = mode->clock; 5395df3196bSAlex Deucher int encoder_mode = atombios_get_encoder_mode(encoder); 540fbee67a6SAlex Deucher u32 dp_clock = mode->clock; 5415df3196bSAlex Deucher int bpc = radeon_get_monitor_bpc(connector); 5425df3196bSAlex Deucher bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); 543fc10332bSAlex Deucher 5444eaeca33SAlex Deucher /* reset the pll flags */ 54519eca43eSAlex Deucher radeon_crtc->pll_flags = 0; 546771fe6b9SJerome Glisse 547771fe6b9SJerome Glisse if (ASIC_IS_AVIVO(rdev)) { 548eb1300bcSAlex Deucher if ((rdev->family == CHIP_RS600) || 549eb1300bcSAlex Deucher (rdev->family == CHIP_RS690) || 550eb1300bcSAlex Deucher (rdev->family == CHIP_RS740)) 55119eca43eSAlex Deucher radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ 552eb1300bcSAlex Deucher RADEON_PLL_PREFER_CLOSEST_LOWER); 5535480f727SDave Airlie 5545480f727SDave Airlie if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ 55519eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 5565480f727SDave Airlie else 55719eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 5589bb09fa1SAlex Deucher 5595785e53fSAlex Deucher if (rdev->family < CHIP_RV770) 56019eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; 56137d4174dSAlex Deucher /* use frac fb div on APUs */ 56237d4174dSAlex Deucher if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) 56319eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 5645480f727SDave Airlie } else { 56519eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_LEGACY; 566771fe6b9SJerome Glisse 5675480f727SDave Airlie if (mode->clock > 200000) /* range limits??? */ 56819eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 5695480f727SDave Airlie else 57019eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 5715480f727SDave Airlie } 5725480f727SDave Airlie 573eac4dff6SAlex Deucher if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || 5741d33e1fcSAlex Deucher (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { 575fbee67a6SAlex Deucher if (connector) { 576fbee67a6SAlex Deucher struct radeon_connector *radeon_connector = to_radeon_connector(connector); 577fbee67a6SAlex Deucher struct radeon_connector_atom_dig *dig_connector = 578fbee67a6SAlex Deucher radeon_connector->con_priv; 579fbee67a6SAlex Deucher 580fbee67a6SAlex Deucher dp_clock = dig_connector->dp_clock; 581fbee67a6SAlex Deucher } 582fbee67a6SAlex Deucher } 5835b40ddf8SAlex Deucher 584ba032a58SAlex Deucher /* use recommended ref_div for ss */ 585ba032a58SAlex Deucher if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 58619eca43eSAlex Deucher if (radeon_crtc->ss_enabled) { 58719eca43eSAlex Deucher if (radeon_crtc->ss.refdiv) { 58819eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 58919eca43eSAlex Deucher radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; 5905b40ddf8SAlex Deucher if (ASIC_IS_AVIVO(rdev)) 59119eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 592ba032a58SAlex Deucher } 593ba032a58SAlex Deucher } 594ba032a58SAlex Deucher } 5955b40ddf8SAlex Deucher 5964eaeca33SAlex Deucher if (ASIC_IS_AVIVO(rdev)) { 5974eaeca33SAlex Deucher /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ 5984eaeca33SAlex Deucher if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) 5994eaeca33SAlex Deucher adjusted_clock = mode->clock * 2; 60048dfaaebSAlex Deucher if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 60119eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; 602619efb10SAlex Deucher if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 60319eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD; 6044eaeca33SAlex Deucher } else { 6054eaeca33SAlex Deucher if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 60619eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; 6074eaeca33SAlex Deucher if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) 60819eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 609771fe6b9SJerome Glisse } 610771fe6b9SJerome Glisse 6112606c886SAlex Deucher /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock 6122606c886SAlex Deucher * accordingly based on the encoder/transmitter to work around 6132606c886SAlex Deucher * special hw requirements. 6142606c886SAlex Deucher */ 6152606c886SAlex Deucher if (ASIC_IS_DCE3(rdev)) { 6164eaeca33SAlex Deucher union adjust_pixel_clock args; 6174eaeca33SAlex Deucher u8 frev, crev; 6184eaeca33SAlex Deucher int index; 6192606c886SAlex Deucher 6202606c886SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); 621a084e6eeSAlex Deucher if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 622a084e6eeSAlex Deucher &crev)) 623a084e6eeSAlex Deucher return adjusted_clock; 6244eaeca33SAlex Deucher 6254eaeca33SAlex Deucher memset(&args, 0, sizeof(args)); 6264eaeca33SAlex Deucher 6274eaeca33SAlex Deucher switch (frev) { 6284eaeca33SAlex Deucher case 1: 6294eaeca33SAlex Deucher switch (crev) { 6304eaeca33SAlex Deucher case 1: 6314eaeca33SAlex Deucher case 2: 6324eaeca33SAlex Deucher args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); 6334eaeca33SAlex Deucher args.v1.ucTransmitterID = radeon_encoder->encoder_id; 634bcc1c2a1SAlex Deucher args.v1.ucEncodeMode = encoder_mode; 63519eca43eSAlex Deucher if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) 636ba032a58SAlex Deucher args.v1.ucConfig |= 637ba032a58SAlex Deucher ADJUST_DISPLAY_CONFIG_SS_ENABLE; 6384eaeca33SAlex Deucher 6392606c886SAlex Deucher atom_execute_table(rdev->mode_info.atom_context, 6404eaeca33SAlex Deucher index, (uint32_t *)&args); 6414eaeca33SAlex Deucher adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; 6424eaeca33SAlex Deucher break; 643bcc1c2a1SAlex Deucher case 3: 644bcc1c2a1SAlex Deucher args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10); 645bcc1c2a1SAlex Deucher args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; 646bcc1c2a1SAlex Deucher args.v3.sInput.ucEncodeMode = encoder_mode; 647bcc1c2a1SAlex Deucher args.v3.sInput.ucDispPllConfig = 0; 64819eca43eSAlex Deucher if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) 649ba032a58SAlex Deucher args.v3.sInput.ucDispPllConfig |= 650ba032a58SAlex Deucher DISPPLL_CONFIG_SS_ENABLE; 651996d5c59SAlex Deucher if (ENCODER_MODE_IS_DP(encoder_mode)) { 652bcc1c2a1SAlex Deucher args.v3.sInput.ucDispPllConfig |= 653bcc1c2a1SAlex Deucher DISPPLL_CONFIG_COHERENT_MODE; 654fbee67a6SAlex Deucher /* 16200 or 27000 */ 655fbee67a6SAlex Deucher args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); 656b4f15f80SAlex Deucher } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 657b4f15f80SAlex Deucher struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 658b4f15f80SAlex Deucher if (encoder_mode == ATOM_ENCODER_MODE_HDMI) 659fbee67a6SAlex Deucher /* deep color support */ 660fbee67a6SAlex Deucher args.v3.sInput.usPixelClock = 661fbee67a6SAlex Deucher cpu_to_le16((mode->clock * bpc / 8) / 10); 662bcc1c2a1SAlex Deucher if (dig->coherent_mode) 663bcc1c2a1SAlex Deucher args.v3.sInput.ucDispPllConfig |= 664bcc1c2a1SAlex Deucher DISPPLL_CONFIG_COHERENT_MODE; 6659aa59993SAlex Deucher if (is_duallink) 666bcc1c2a1SAlex Deucher args.v3.sInput.ucDispPllConfig |= 667bcc1c2a1SAlex Deucher DISPPLL_CONFIG_DUAL_LINK; 668bcc1c2a1SAlex Deucher } 6691d33e1fcSAlex Deucher if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 6701d33e1fcSAlex Deucher ENCODER_OBJECT_ID_NONE) 6711d33e1fcSAlex Deucher args.v3.sInput.ucExtTransmitterID = 6721d33e1fcSAlex Deucher radeon_encoder_get_dp_bridge_encoder_id(encoder); 6731d33e1fcSAlex Deucher else 674cc9f67a0SAlex Deucher args.v3.sInput.ucExtTransmitterID = 0; 675cc9f67a0SAlex Deucher 676bcc1c2a1SAlex Deucher atom_execute_table(rdev->mode_info.atom_context, 677bcc1c2a1SAlex Deucher index, (uint32_t *)&args); 678bcc1c2a1SAlex Deucher adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; 679bcc1c2a1SAlex Deucher if (args.v3.sOutput.ucRefDiv) { 68019eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 68119eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 68219eca43eSAlex Deucher radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; 683bcc1c2a1SAlex Deucher } 684bcc1c2a1SAlex Deucher if (args.v3.sOutput.ucPostDiv) { 68519eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 68619eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV; 68719eca43eSAlex Deucher radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; 688bcc1c2a1SAlex Deucher } 689bcc1c2a1SAlex Deucher break; 6904eaeca33SAlex Deucher default: 6914eaeca33SAlex Deucher DRM_ERROR("Unknown table version %d %d\n", frev, crev); 6924eaeca33SAlex Deucher return adjusted_clock; 693d56ef9c8SAlex Deucher } 6944eaeca33SAlex Deucher break; 6954eaeca33SAlex Deucher default: 6964eaeca33SAlex Deucher DRM_ERROR("Unknown table version %d %d\n", frev, crev); 6974eaeca33SAlex Deucher return adjusted_clock; 6984eaeca33SAlex Deucher } 6994eaeca33SAlex Deucher } 7004eaeca33SAlex Deucher return adjusted_clock; 7014eaeca33SAlex Deucher } 7024eaeca33SAlex Deucher 7034eaeca33SAlex Deucher union set_pixel_clock { 7044eaeca33SAlex Deucher SET_PIXEL_CLOCK_PS_ALLOCATION base; 7054eaeca33SAlex Deucher PIXEL_CLOCK_PARAMETERS v1; 7064eaeca33SAlex Deucher PIXEL_CLOCK_PARAMETERS_V2 v2; 7074eaeca33SAlex Deucher PIXEL_CLOCK_PARAMETERS_V3 v3; 708bcc1c2a1SAlex Deucher PIXEL_CLOCK_PARAMETERS_V5 v5; 709f82b3ddcSAlex Deucher PIXEL_CLOCK_PARAMETERS_V6 v6; 7104eaeca33SAlex Deucher }; 7114eaeca33SAlex Deucher 712f82b3ddcSAlex Deucher /* on DCE5, make sure the voltage is high enough to support the 713f82b3ddcSAlex Deucher * required disp clk. 714f82b3ddcSAlex Deucher */ 715f3f1f03eSAlex Deucher static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev, 716f82b3ddcSAlex Deucher u32 dispclk) 717bcc1c2a1SAlex Deucher { 718bcc1c2a1SAlex Deucher u8 frev, crev; 719bcc1c2a1SAlex Deucher int index; 720bcc1c2a1SAlex Deucher union set_pixel_clock args; 721bcc1c2a1SAlex Deucher 722bcc1c2a1SAlex Deucher memset(&args, 0, sizeof(args)); 723bcc1c2a1SAlex Deucher 724bcc1c2a1SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 725a084e6eeSAlex Deucher if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 726a084e6eeSAlex Deucher &crev)) 727a084e6eeSAlex Deucher return; 728bcc1c2a1SAlex Deucher 729bcc1c2a1SAlex Deucher switch (frev) { 730bcc1c2a1SAlex Deucher case 1: 731bcc1c2a1SAlex Deucher switch (crev) { 732bcc1c2a1SAlex Deucher case 5: 733bcc1c2a1SAlex Deucher /* if the default dcpll clock is specified, 734bcc1c2a1SAlex Deucher * SetPixelClock provides the dividers 735bcc1c2a1SAlex Deucher */ 736bcc1c2a1SAlex Deucher args.v5.ucCRTC = ATOM_CRTC_INVALID; 7374589433cSCédric Cano args.v5.usPixelClock = cpu_to_le16(dispclk); 738bcc1c2a1SAlex Deucher args.v5.ucPpll = ATOM_DCPLL; 739bcc1c2a1SAlex Deucher break; 740f82b3ddcSAlex Deucher case 6: 741f82b3ddcSAlex Deucher /* if the default dcpll clock is specified, 742f82b3ddcSAlex Deucher * SetPixelClock provides the dividers 743f82b3ddcSAlex Deucher */ 744265aa6c8SAlex Deucher args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); 745729b95efSAlex Deucher if (ASIC_IS_DCE61(rdev)) 746729b95efSAlex Deucher args.v6.ucPpll = ATOM_EXT_PLL1; 747729b95efSAlex Deucher else if (ASIC_IS_DCE6(rdev)) 748f3f1f03eSAlex Deucher args.v6.ucPpll = ATOM_PPLL0; 749f3f1f03eSAlex Deucher else 750f82b3ddcSAlex Deucher args.v6.ucPpll = ATOM_DCPLL; 751f82b3ddcSAlex Deucher break; 752bcc1c2a1SAlex Deucher default: 753bcc1c2a1SAlex Deucher DRM_ERROR("Unknown table version %d %d\n", frev, crev); 754bcc1c2a1SAlex Deucher return; 755bcc1c2a1SAlex Deucher } 756bcc1c2a1SAlex Deucher break; 757bcc1c2a1SAlex Deucher default: 758bcc1c2a1SAlex Deucher DRM_ERROR("Unknown table version %d %d\n", frev, crev); 759bcc1c2a1SAlex Deucher return; 760bcc1c2a1SAlex Deucher } 761bcc1c2a1SAlex Deucher atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 762bcc1c2a1SAlex Deucher } 763bcc1c2a1SAlex Deucher 76437f9003bSAlex Deucher static void atombios_crtc_program_pll(struct drm_crtc *crtc, 765f1bece7fSBenjamin Herrenschmidt u32 crtc_id, 76637f9003bSAlex Deucher int pll_id, 76737f9003bSAlex Deucher u32 encoder_mode, 76837f9003bSAlex Deucher u32 encoder_id, 76937f9003bSAlex Deucher u32 clock, 77037f9003bSAlex Deucher u32 ref_div, 77137f9003bSAlex Deucher u32 fb_div, 77237f9003bSAlex Deucher u32 frac_fb_div, 773df271becSAlex Deucher u32 post_div, 7748e8e523dSAlex Deucher int bpc, 7758e8e523dSAlex Deucher bool ss_enabled, 7768e8e523dSAlex Deucher struct radeon_atom_ss *ss) 77737f9003bSAlex Deucher { 77837f9003bSAlex Deucher struct drm_device *dev = crtc->dev; 77937f9003bSAlex Deucher struct radeon_device *rdev = dev->dev_private; 78037f9003bSAlex Deucher u8 frev, crev; 78137f9003bSAlex Deucher int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 78237f9003bSAlex Deucher union set_pixel_clock args; 78337f9003bSAlex Deucher 78437f9003bSAlex Deucher memset(&args, 0, sizeof(args)); 78537f9003bSAlex Deucher 78637f9003bSAlex Deucher if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 78737f9003bSAlex Deucher &crev)) 78837f9003bSAlex Deucher return; 78937f9003bSAlex Deucher 79037f9003bSAlex Deucher switch (frev) { 79137f9003bSAlex Deucher case 1: 79237f9003bSAlex Deucher switch (crev) { 79337f9003bSAlex Deucher case 1: 79437f9003bSAlex Deucher if (clock == ATOM_DISABLE) 79537f9003bSAlex Deucher return; 79637f9003bSAlex Deucher args.v1.usPixelClock = cpu_to_le16(clock / 10); 79737f9003bSAlex Deucher args.v1.usRefDiv = cpu_to_le16(ref_div); 79837f9003bSAlex Deucher args.v1.usFbDiv = cpu_to_le16(fb_div); 79937f9003bSAlex Deucher args.v1.ucFracFbDiv = frac_fb_div; 80037f9003bSAlex Deucher args.v1.ucPostDiv = post_div; 80137f9003bSAlex Deucher args.v1.ucPpll = pll_id; 80237f9003bSAlex Deucher args.v1.ucCRTC = crtc_id; 80337f9003bSAlex Deucher args.v1.ucRefDivSrc = 1; 80437f9003bSAlex Deucher break; 80537f9003bSAlex Deucher case 2: 80637f9003bSAlex Deucher args.v2.usPixelClock = cpu_to_le16(clock / 10); 80737f9003bSAlex Deucher args.v2.usRefDiv = cpu_to_le16(ref_div); 80837f9003bSAlex Deucher args.v2.usFbDiv = cpu_to_le16(fb_div); 80937f9003bSAlex Deucher args.v2.ucFracFbDiv = frac_fb_div; 81037f9003bSAlex Deucher args.v2.ucPostDiv = post_div; 81137f9003bSAlex Deucher args.v2.ucPpll = pll_id; 81237f9003bSAlex Deucher args.v2.ucCRTC = crtc_id; 81337f9003bSAlex Deucher args.v2.ucRefDivSrc = 1; 81437f9003bSAlex Deucher break; 81537f9003bSAlex Deucher case 3: 81637f9003bSAlex Deucher args.v3.usPixelClock = cpu_to_le16(clock / 10); 81737f9003bSAlex Deucher args.v3.usRefDiv = cpu_to_le16(ref_div); 81837f9003bSAlex Deucher args.v3.usFbDiv = cpu_to_le16(fb_div); 81937f9003bSAlex Deucher args.v3.ucFracFbDiv = frac_fb_div; 82037f9003bSAlex Deucher args.v3.ucPostDiv = post_div; 82137f9003bSAlex Deucher args.v3.ucPpll = pll_id; 822e729586eSAlex Deucher if (crtc_id == ATOM_CRTC2) 823e729586eSAlex Deucher args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2; 824e729586eSAlex Deucher else 825e729586eSAlex Deucher args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1; 8266f15c506SAlex Deucher if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 8276f15c506SAlex Deucher args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; 82837f9003bSAlex Deucher args.v3.ucTransmitterId = encoder_id; 82937f9003bSAlex Deucher args.v3.ucEncoderMode = encoder_mode; 83037f9003bSAlex Deucher break; 83137f9003bSAlex Deucher case 5: 83237f9003bSAlex Deucher args.v5.ucCRTC = crtc_id; 83337f9003bSAlex Deucher args.v5.usPixelClock = cpu_to_le16(clock / 10); 83437f9003bSAlex Deucher args.v5.ucRefDiv = ref_div; 83537f9003bSAlex Deucher args.v5.usFbDiv = cpu_to_le16(fb_div); 83637f9003bSAlex Deucher args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 83737f9003bSAlex Deucher args.v5.ucPostDiv = post_div; 83837f9003bSAlex Deucher args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ 8398e8e523dSAlex Deucher if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 8408e8e523dSAlex Deucher args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; 841df271becSAlex Deucher switch (bpc) { 842df271becSAlex Deucher case 8: 843df271becSAlex Deucher default: 844df271becSAlex Deucher args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; 845df271becSAlex Deucher break; 846df271becSAlex Deucher case 10: 847df271becSAlex Deucher args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; 848df271becSAlex Deucher break; 849df271becSAlex Deucher } 85037f9003bSAlex Deucher args.v5.ucTransmitterID = encoder_id; 85137f9003bSAlex Deucher args.v5.ucEncoderMode = encoder_mode; 85237f9003bSAlex Deucher args.v5.ucPpll = pll_id; 85337f9003bSAlex Deucher break; 854f82b3ddcSAlex Deucher case 6: 855f1bece7fSBenjamin Herrenschmidt args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10); 856f82b3ddcSAlex Deucher args.v6.ucRefDiv = ref_div; 857f82b3ddcSAlex Deucher args.v6.usFbDiv = cpu_to_le16(fb_div); 858f82b3ddcSAlex Deucher args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 859f82b3ddcSAlex Deucher args.v6.ucPostDiv = post_div; 860f82b3ddcSAlex Deucher args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ 8618e8e523dSAlex Deucher if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 8628e8e523dSAlex Deucher args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; 863df271becSAlex Deucher switch (bpc) { 864df271becSAlex Deucher case 8: 865df271becSAlex Deucher default: 866df271becSAlex Deucher args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; 867df271becSAlex Deucher break; 868df271becSAlex Deucher case 10: 869df271becSAlex Deucher args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP; 870df271becSAlex Deucher break; 871df271becSAlex Deucher case 12: 872df271becSAlex Deucher args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP; 873df271becSAlex Deucher break; 874df271becSAlex Deucher case 16: 875df271becSAlex Deucher args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; 876df271becSAlex Deucher break; 877df271becSAlex Deucher } 878f82b3ddcSAlex Deucher args.v6.ucTransmitterID = encoder_id; 879f82b3ddcSAlex Deucher args.v6.ucEncoderMode = encoder_mode; 880f82b3ddcSAlex Deucher args.v6.ucPpll = pll_id; 881f82b3ddcSAlex Deucher break; 88237f9003bSAlex Deucher default: 88337f9003bSAlex Deucher DRM_ERROR("Unknown table version %d %d\n", frev, crev); 88437f9003bSAlex Deucher return; 88537f9003bSAlex Deucher } 88637f9003bSAlex Deucher break; 88737f9003bSAlex Deucher default: 88837f9003bSAlex Deucher DRM_ERROR("Unknown table version %d %d\n", frev, crev); 88937f9003bSAlex Deucher return; 89037f9003bSAlex Deucher } 89137f9003bSAlex Deucher 89237f9003bSAlex Deucher atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 89337f9003bSAlex Deucher } 89437f9003bSAlex Deucher 89519eca43eSAlex Deucher static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 89619eca43eSAlex Deucher { 89719eca43eSAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 89819eca43eSAlex Deucher struct drm_device *dev = crtc->dev; 89919eca43eSAlex Deucher struct radeon_device *rdev = dev->dev_private; 9005df3196bSAlex Deucher struct radeon_encoder *radeon_encoder = 9015df3196bSAlex Deucher to_radeon_encoder(radeon_crtc->encoder); 9025df3196bSAlex Deucher int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); 90319eca43eSAlex Deucher 90419eca43eSAlex Deucher radeon_crtc->bpc = 8; 90519eca43eSAlex Deucher radeon_crtc->ss_enabled = false; 90619eca43eSAlex Deucher 90719eca43eSAlex Deucher if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || 9085df3196bSAlex Deucher (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { 90919eca43eSAlex Deucher struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 91019eca43eSAlex Deucher struct drm_connector *connector = 9115df3196bSAlex Deucher radeon_get_connector_for_encoder(radeon_crtc->encoder); 91219eca43eSAlex Deucher struct radeon_connector *radeon_connector = 91319eca43eSAlex Deucher to_radeon_connector(connector); 91419eca43eSAlex Deucher struct radeon_connector_atom_dig *dig_connector = 91519eca43eSAlex Deucher radeon_connector->con_priv; 91619eca43eSAlex Deucher int dp_clock; 91719eca43eSAlex Deucher radeon_crtc->bpc = radeon_get_monitor_bpc(connector); 91819eca43eSAlex Deucher 91919eca43eSAlex Deucher switch (encoder_mode) { 92019eca43eSAlex Deucher case ATOM_ENCODER_MODE_DP_MST: 92119eca43eSAlex Deucher case ATOM_ENCODER_MODE_DP: 92219eca43eSAlex Deucher /* DP/eDP */ 92319eca43eSAlex Deucher dp_clock = dig_connector->dp_clock / 10; 92419eca43eSAlex Deucher if (ASIC_IS_DCE4(rdev)) 92519eca43eSAlex Deucher radeon_crtc->ss_enabled = 92619eca43eSAlex Deucher radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, 92719eca43eSAlex Deucher ASIC_INTERNAL_SS_ON_DP, 92819eca43eSAlex Deucher dp_clock); 92919eca43eSAlex Deucher else { 93019eca43eSAlex Deucher if (dp_clock == 16200) { 93119eca43eSAlex Deucher radeon_crtc->ss_enabled = 93219eca43eSAlex Deucher radeon_atombios_get_ppll_ss_info(rdev, 93319eca43eSAlex Deucher &radeon_crtc->ss, 93419eca43eSAlex Deucher ATOM_DP_SS_ID2); 93519eca43eSAlex Deucher if (!radeon_crtc->ss_enabled) 93619eca43eSAlex Deucher radeon_crtc->ss_enabled = 93719eca43eSAlex Deucher radeon_atombios_get_ppll_ss_info(rdev, 93819eca43eSAlex Deucher &radeon_crtc->ss, 93919eca43eSAlex Deucher ATOM_DP_SS_ID1); 94019eca43eSAlex Deucher } else 94119eca43eSAlex Deucher radeon_crtc->ss_enabled = 94219eca43eSAlex Deucher radeon_atombios_get_ppll_ss_info(rdev, 94319eca43eSAlex Deucher &radeon_crtc->ss, 94419eca43eSAlex Deucher ATOM_DP_SS_ID1); 94519eca43eSAlex Deucher } 94619eca43eSAlex Deucher break; 94719eca43eSAlex Deucher case ATOM_ENCODER_MODE_LVDS: 94819eca43eSAlex Deucher if (ASIC_IS_DCE4(rdev)) 94919eca43eSAlex Deucher radeon_crtc->ss_enabled = 95019eca43eSAlex Deucher radeon_atombios_get_asic_ss_info(rdev, 95119eca43eSAlex Deucher &radeon_crtc->ss, 95219eca43eSAlex Deucher dig->lcd_ss_id, 95319eca43eSAlex Deucher mode->clock / 10); 95419eca43eSAlex Deucher else 95519eca43eSAlex Deucher radeon_crtc->ss_enabled = 95619eca43eSAlex Deucher radeon_atombios_get_ppll_ss_info(rdev, 95719eca43eSAlex Deucher &radeon_crtc->ss, 95819eca43eSAlex Deucher dig->lcd_ss_id); 95919eca43eSAlex Deucher break; 96019eca43eSAlex Deucher case ATOM_ENCODER_MODE_DVI: 96119eca43eSAlex Deucher if (ASIC_IS_DCE4(rdev)) 96219eca43eSAlex Deucher radeon_crtc->ss_enabled = 96319eca43eSAlex Deucher radeon_atombios_get_asic_ss_info(rdev, 96419eca43eSAlex Deucher &radeon_crtc->ss, 96519eca43eSAlex Deucher ASIC_INTERNAL_SS_ON_TMDS, 96619eca43eSAlex Deucher mode->clock / 10); 96719eca43eSAlex Deucher break; 96819eca43eSAlex Deucher case ATOM_ENCODER_MODE_HDMI: 96919eca43eSAlex Deucher if (ASIC_IS_DCE4(rdev)) 97019eca43eSAlex Deucher radeon_crtc->ss_enabled = 97119eca43eSAlex Deucher radeon_atombios_get_asic_ss_info(rdev, 97219eca43eSAlex Deucher &radeon_crtc->ss, 97319eca43eSAlex Deucher ASIC_INTERNAL_SS_ON_HDMI, 97419eca43eSAlex Deucher mode->clock / 10); 97519eca43eSAlex Deucher break; 97619eca43eSAlex Deucher default: 97719eca43eSAlex Deucher break; 97819eca43eSAlex Deucher } 97919eca43eSAlex Deucher } 98019eca43eSAlex Deucher 98119eca43eSAlex Deucher /* adjust pixel clock as needed */ 98219eca43eSAlex Deucher radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode); 98319eca43eSAlex Deucher 98419eca43eSAlex Deucher return true; 98519eca43eSAlex Deucher } 98619eca43eSAlex Deucher 987bcc1c2a1SAlex Deucher static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 9884eaeca33SAlex Deucher { 9894eaeca33SAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 9904eaeca33SAlex Deucher struct drm_device *dev = crtc->dev; 9914eaeca33SAlex Deucher struct radeon_device *rdev = dev->dev_private; 9925df3196bSAlex Deucher struct radeon_encoder *radeon_encoder = 9935df3196bSAlex Deucher to_radeon_encoder(radeon_crtc->encoder); 9944eaeca33SAlex Deucher u32 pll_clock = mode->clock; 9954eaeca33SAlex Deucher u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; 9964eaeca33SAlex Deucher struct radeon_pll *pll; 9975df3196bSAlex Deucher int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); 9984eaeca33SAlex Deucher 999bcc1c2a1SAlex Deucher switch (radeon_crtc->pll_id) { 1000bcc1c2a1SAlex Deucher case ATOM_PPLL1: 10014eaeca33SAlex Deucher pll = &rdev->clock.p1pll; 1002bcc1c2a1SAlex Deucher break; 1003bcc1c2a1SAlex Deucher case ATOM_PPLL2: 10044eaeca33SAlex Deucher pll = &rdev->clock.p2pll; 1005bcc1c2a1SAlex Deucher break; 1006bcc1c2a1SAlex Deucher case ATOM_DCPLL: 1007bcc1c2a1SAlex Deucher case ATOM_PPLL_INVALID: 1008921d98b5SStefan Richter default: 1009bcc1c2a1SAlex Deucher pll = &rdev->clock.dcpll; 1010bcc1c2a1SAlex Deucher break; 1011bcc1c2a1SAlex Deucher } 10124eaeca33SAlex Deucher 101319eca43eSAlex Deucher /* update pll params */ 101419eca43eSAlex Deucher pll->flags = radeon_crtc->pll_flags; 101519eca43eSAlex Deucher pll->reference_div = radeon_crtc->pll_reference_div; 101619eca43eSAlex Deucher pll->post_div = radeon_crtc->pll_post_div; 10172606c886SAlex Deucher 101864146f8bSAlex Deucher if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 101964146f8bSAlex Deucher /* TV seems to prefer the legacy algo on some boards */ 102019eca43eSAlex Deucher radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, 102119eca43eSAlex Deucher &fb_div, &frac_fb_div, &ref_div, &post_div); 102264146f8bSAlex Deucher else if (ASIC_IS_AVIVO(rdev)) 102319eca43eSAlex Deucher radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, 102419eca43eSAlex Deucher &fb_div, &frac_fb_div, &ref_div, &post_div); 1025619efb10SAlex Deucher else 102619eca43eSAlex Deucher radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, 102719eca43eSAlex Deucher &fb_div, &frac_fb_div, &ref_div, &post_div); 1028771fe6b9SJerome Glisse 102919eca43eSAlex Deucher atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, 103019eca43eSAlex Deucher radeon_crtc->crtc_id, &radeon_crtc->ss); 1031ba032a58SAlex Deucher 103237f9003bSAlex Deucher atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 103337f9003bSAlex Deucher encoder_mode, radeon_encoder->encoder_id, mode->clock, 103419eca43eSAlex Deucher ref_div, fb_div, frac_fb_div, post_div, 103519eca43eSAlex Deucher radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss); 1036771fe6b9SJerome Glisse 103719eca43eSAlex Deucher if (radeon_crtc->ss_enabled) { 1038ba032a58SAlex Deucher /* calculate ss amount and step size */ 1039ba032a58SAlex Deucher if (ASIC_IS_DCE4(rdev)) { 1040ba032a58SAlex Deucher u32 step_size; 104119eca43eSAlex Deucher u32 amount = (((fb_div * 10) + frac_fb_div) * radeon_crtc->ss.percentage) / 10000; 104219eca43eSAlex Deucher radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; 104319eca43eSAlex Deucher radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & 1044ba032a58SAlex Deucher ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK; 104519eca43eSAlex Deucher if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) 104619eca43eSAlex Deucher step_size = (4 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) / 1047ba032a58SAlex Deucher (125 * 25 * pll->reference_freq / 100); 1048ba032a58SAlex Deucher else 104919eca43eSAlex Deucher step_size = (2 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) / 1050ba032a58SAlex Deucher (125 * 25 * pll->reference_freq / 100); 105119eca43eSAlex Deucher radeon_crtc->ss.step = step_size; 1052ba032a58SAlex Deucher } 1053ba032a58SAlex Deucher 105419eca43eSAlex Deucher atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, 105519eca43eSAlex Deucher radeon_crtc->crtc_id, &radeon_crtc->ss); 1056ba032a58SAlex Deucher } 1057771fe6b9SJerome Glisse } 1058771fe6b9SJerome Glisse 1059c9417bddSAlex Deucher static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 10604dd19b0dSChris Ball struct drm_framebuffer *fb, 10614dd19b0dSChris Ball int x, int y, int atomic) 1062bcc1c2a1SAlex Deucher { 1063bcc1c2a1SAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1064bcc1c2a1SAlex Deucher struct drm_device *dev = crtc->dev; 1065bcc1c2a1SAlex Deucher struct radeon_device *rdev = dev->dev_private; 1066bcc1c2a1SAlex Deucher struct radeon_framebuffer *radeon_fb; 10674dd19b0dSChris Ball struct drm_framebuffer *target_fb; 1068bcc1c2a1SAlex Deucher struct drm_gem_object *obj; 1069bcc1c2a1SAlex Deucher struct radeon_bo *rbo; 1070bcc1c2a1SAlex Deucher uint64_t fb_location; 1071bcc1c2a1SAlex Deucher uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1072285484e2SJerome Glisse unsigned bankw, bankh, mtaspect, tile_split; 1073fa6bee46SAlex Deucher u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); 1074adcfde51SAlex Deucher u32 tmp, viewport_w, viewport_h; 1075bcc1c2a1SAlex Deucher int r; 1076bcc1c2a1SAlex Deucher 1077bcc1c2a1SAlex Deucher /* no fb bound */ 10784dd19b0dSChris Ball if (!atomic && !crtc->fb) { 1079d9fdaafbSDave Airlie DRM_DEBUG_KMS("No FB bound\n"); 1080bcc1c2a1SAlex Deucher return 0; 1081bcc1c2a1SAlex Deucher } 1082bcc1c2a1SAlex Deucher 10834dd19b0dSChris Ball if (atomic) { 10844dd19b0dSChris Ball radeon_fb = to_radeon_framebuffer(fb); 10854dd19b0dSChris Ball target_fb = fb; 10864dd19b0dSChris Ball } 10874dd19b0dSChris Ball else { 1088bcc1c2a1SAlex Deucher radeon_fb = to_radeon_framebuffer(crtc->fb); 10894dd19b0dSChris Ball target_fb = crtc->fb; 10904dd19b0dSChris Ball } 1091bcc1c2a1SAlex Deucher 10924dd19b0dSChris Ball /* If atomic, assume fb object is pinned & idle & fenced and 10934dd19b0dSChris Ball * just update base pointers 10944dd19b0dSChris Ball */ 1095bcc1c2a1SAlex Deucher obj = radeon_fb->obj; 10967e4d15d9SDaniel Vetter rbo = gem_to_radeon_bo(obj); 1097bcc1c2a1SAlex Deucher r = radeon_bo_reserve(rbo, false); 1098bcc1c2a1SAlex Deucher if (unlikely(r != 0)) 1099bcc1c2a1SAlex Deucher return r; 11004dd19b0dSChris Ball 11014dd19b0dSChris Ball if (atomic) 11024dd19b0dSChris Ball fb_location = radeon_bo_gpu_offset(rbo); 11034dd19b0dSChris Ball else { 1104bcc1c2a1SAlex Deucher r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); 1105bcc1c2a1SAlex Deucher if (unlikely(r != 0)) { 1106bcc1c2a1SAlex Deucher radeon_bo_unreserve(rbo); 1107bcc1c2a1SAlex Deucher return -EINVAL; 1108bcc1c2a1SAlex Deucher } 11094dd19b0dSChris Ball } 11104dd19b0dSChris Ball 1111bcc1c2a1SAlex Deucher radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1112bcc1c2a1SAlex Deucher radeon_bo_unreserve(rbo); 1113bcc1c2a1SAlex Deucher 11144dd19b0dSChris Ball switch (target_fb->bits_per_pixel) { 1115bcc1c2a1SAlex Deucher case 8: 1116bcc1c2a1SAlex Deucher fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | 1117bcc1c2a1SAlex Deucher EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); 1118bcc1c2a1SAlex Deucher break; 1119bcc1c2a1SAlex Deucher case 15: 1120bcc1c2a1SAlex Deucher fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1121bcc1c2a1SAlex Deucher EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); 1122bcc1c2a1SAlex Deucher break; 1123bcc1c2a1SAlex Deucher case 16: 1124bcc1c2a1SAlex Deucher fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1125bcc1c2a1SAlex Deucher EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); 1126fa6bee46SAlex Deucher #ifdef __BIG_ENDIAN 1127fa6bee46SAlex Deucher fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1128fa6bee46SAlex Deucher #endif 1129bcc1c2a1SAlex Deucher break; 1130bcc1c2a1SAlex Deucher case 24: 1131bcc1c2a1SAlex Deucher case 32: 1132bcc1c2a1SAlex Deucher fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1133bcc1c2a1SAlex Deucher EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); 1134fa6bee46SAlex Deucher #ifdef __BIG_ENDIAN 1135fa6bee46SAlex Deucher fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1136fa6bee46SAlex Deucher #endif 1137bcc1c2a1SAlex Deucher break; 1138bcc1c2a1SAlex Deucher default: 1139bcc1c2a1SAlex Deucher DRM_ERROR("Unsupported screen depth %d\n", 11404dd19b0dSChris Ball target_fb->bits_per_pixel); 1141bcc1c2a1SAlex Deucher return -EINVAL; 1142bcc1c2a1SAlex Deucher } 1143bcc1c2a1SAlex Deucher 1144392e3722SAlex Deucher if (tiling_flags & RADEON_TILING_MACRO) { 1145b7019b2fSAlex Deucher if (rdev->family >= CHIP_TAHITI) 1146b7019b2fSAlex Deucher tmp = rdev->config.si.tile_config; 1147b7019b2fSAlex Deucher else if (rdev->family >= CHIP_CAYMAN) 1148392e3722SAlex Deucher tmp = rdev->config.cayman.tile_config; 1149392e3722SAlex Deucher else 1150392e3722SAlex Deucher tmp = rdev->config.evergreen.tile_config; 1151392e3722SAlex Deucher 1152392e3722SAlex Deucher switch ((tmp & 0xf0) >> 4) { 1153392e3722SAlex Deucher case 0: /* 4 banks */ 1154392e3722SAlex Deucher fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK); 1155392e3722SAlex Deucher break; 1156392e3722SAlex Deucher case 1: /* 8 banks */ 1157392e3722SAlex Deucher default: 1158392e3722SAlex Deucher fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK); 1159392e3722SAlex Deucher break; 1160392e3722SAlex Deucher case 2: /* 16 banks */ 1161392e3722SAlex Deucher fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK); 1162392e3722SAlex Deucher break; 1163392e3722SAlex Deucher } 1164392e3722SAlex Deucher 116597d66328SAlex Deucher fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); 1166285484e2SJerome Glisse 1167285484e2SJerome Glisse evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); 1168285484e2SJerome Glisse fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split); 1169285484e2SJerome Glisse fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); 1170285484e2SJerome Glisse fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh); 1171285484e2SJerome Glisse fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); 1172392e3722SAlex Deucher } else if (tiling_flags & RADEON_TILING_MICRO) 117397d66328SAlex Deucher fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); 117497d66328SAlex Deucher 1175b7019b2fSAlex Deucher if ((rdev->family == CHIP_TAHITI) || 1176b7019b2fSAlex Deucher (rdev->family == CHIP_PITCAIRN)) 1177b7019b2fSAlex Deucher fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16); 1178b7019b2fSAlex Deucher else if (rdev->family == CHIP_VERDE) 1179b7019b2fSAlex Deucher fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16); 1180b7019b2fSAlex Deucher 1181bcc1c2a1SAlex Deucher switch (radeon_crtc->crtc_id) { 1182bcc1c2a1SAlex Deucher case 0: 1183bcc1c2a1SAlex Deucher WREG32(AVIVO_D1VGA_CONTROL, 0); 1184bcc1c2a1SAlex Deucher break; 1185bcc1c2a1SAlex Deucher case 1: 1186bcc1c2a1SAlex Deucher WREG32(AVIVO_D2VGA_CONTROL, 0); 1187bcc1c2a1SAlex Deucher break; 1188bcc1c2a1SAlex Deucher case 2: 1189bcc1c2a1SAlex Deucher WREG32(EVERGREEN_D3VGA_CONTROL, 0); 1190bcc1c2a1SAlex Deucher break; 1191bcc1c2a1SAlex Deucher case 3: 1192bcc1c2a1SAlex Deucher WREG32(EVERGREEN_D4VGA_CONTROL, 0); 1193bcc1c2a1SAlex Deucher break; 1194bcc1c2a1SAlex Deucher case 4: 1195bcc1c2a1SAlex Deucher WREG32(EVERGREEN_D5VGA_CONTROL, 0); 1196bcc1c2a1SAlex Deucher break; 1197bcc1c2a1SAlex Deucher case 5: 1198bcc1c2a1SAlex Deucher WREG32(EVERGREEN_D6VGA_CONTROL, 0); 1199bcc1c2a1SAlex Deucher break; 1200bcc1c2a1SAlex Deucher default: 1201bcc1c2a1SAlex Deucher break; 1202bcc1c2a1SAlex Deucher } 1203bcc1c2a1SAlex Deucher 1204bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 1205bcc1c2a1SAlex Deucher upper_32_bits(fb_location)); 1206bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 1207bcc1c2a1SAlex Deucher upper_32_bits(fb_location)); 1208bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1209bcc1c2a1SAlex Deucher (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1210bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1211bcc1c2a1SAlex Deucher (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1212bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1213fa6bee46SAlex Deucher WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1214bcc1c2a1SAlex Deucher 1215bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1216bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1217bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); 1218bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); 12194dd19b0dSChris Ball WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); 12204dd19b0dSChris Ball WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); 1221bcc1c2a1SAlex Deucher 122201f2c773SVille Syrjälä fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 1223bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 1224bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1225bcc1c2a1SAlex Deucher 1226bcc1c2a1SAlex Deucher WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 12271b619250SMichel Dänzer target_fb->height); 1228bcc1c2a1SAlex Deucher x &= ~3; 1229bcc1c2a1SAlex Deucher y &= ~1; 1230bcc1c2a1SAlex Deucher WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, 1231bcc1c2a1SAlex Deucher (x << 16) | y); 1232adcfde51SAlex Deucher viewport_w = crtc->mode.hdisplay; 1233adcfde51SAlex Deucher viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1234bcc1c2a1SAlex Deucher WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1235adcfde51SAlex Deucher (viewport_w << 16) | viewport_h); 1236bcc1c2a1SAlex Deucher 1237fb9674bdSAlex Deucher /* pageflip setup */ 1238fb9674bdSAlex Deucher /* make sure flip is at vb rather than hb */ 1239fb9674bdSAlex Deucher tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); 1240fb9674bdSAlex Deucher tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN; 1241fb9674bdSAlex Deucher WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); 1242fb9674bdSAlex Deucher 1243fb9674bdSAlex Deucher /* set pageflip to happen anywhere in vblank interval */ 1244fb9674bdSAlex Deucher WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); 1245fb9674bdSAlex Deucher 12464dd19b0dSChris Ball if (!atomic && fb && fb != crtc->fb) { 12474dd19b0dSChris Ball radeon_fb = to_radeon_framebuffer(fb); 12487e4d15d9SDaniel Vetter rbo = gem_to_radeon_bo(radeon_fb->obj); 1249bcc1c2a1SAlex Deucher r = radeon_bo_reserve(rbo, false); 1250bcc1c2a1SAlex Deucher if (unlikely(r != 0)) 1251bcc1c2a1SAlex Deucher return r; 1252bcc1c2a1SAlex Deucher radeon_bo_unpin(rbo); 1253bcc1c2a1SAlex Deucher radeon_bo_unreserve(rbo); 1254bcc1c2a1SAlex Deucher } 1255bcc1c2a1SAlex Deucher 1256bcc1c2a1SAlex Deucher /* Bytes per pixel may have changed */ 1257bcc1c2a1SAlex Deucher radeon_bandwidth_update(rdev); 1258bcc1c2a1SAlex Deucher 1259bcc1c2a1SAlex Deucher return 0; 1260bcc1c2a1SAlex Deucher } 1261bcc1c2a1SAlex Deucher 12624dd19b0dSChris Ball static int avivo_crtc_do_set_base(struct drm_crtc *crtc, 12634dd19b0dSChris Ball struct drm_framebuffer *fb, 12644dd19b0dSChris Ball int x, int y, int atomic) 1265771fe6b9SJerome Glisse { 1266771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1267771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 1268771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 1269771fe6b9SJerome Glisse struct radeon_framebuffer *radeon_fb; 1270771fe6b9SJerome Glisse struct drm_gem_object *obj; 12714c788679SJerome Glisse struct radeon_bo *rbo; 12724dd19b0dSChris Ball struct drm_framebuffer *target_fb; 1273771fe6b9SJerome Glisse uint64_t fb_location; 1274e024e110SDave Airlie uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1275fa6bee46SAlex Deucher u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; 1276adcfde51SAlex Deucher u32 tmp, viewport_w, viewport_h; 12774c788679SJerome Glisse int r; 1278771fe6b9SJerome Glisse 12792de3b484SJerome Glisse /* no fb bound */ 12804dd19b0dSChris Ball if (!atomic && !crtc->fb) { 1281d9fdaafbSDave Airlie DRM_DEBUG_KMS("No FB bound\n"); 12822de3b484SJerome Glisse return 0; 12832de3b484SJerome Glisse } 1284771fe6b9SJerome Glisse 12854dd19b0dSChris Ball if (atomic) { 12864dd19b0dSChris Ball radeon_fb = to_radeon_framebuffer(fb); 12874dd19b0dSChris Ball target_fb = fb; 12884dd19b0dSChris Ball } 12894dd19b0dSChris Ball else { 1290771fe6b9SJerome Glisse radeon_fb = to_radeon_framebuffer(crtc->fb); 12914dd19b0dSChris Ball target_fb = crtc->fb; 12924dd19b0dSChris Ball } 1293771fe6b9SJerome Glisse 1294771fe6b9SJerome Glisse obj = radeon_fb->obj; 12957e4d15d9SDaniel Vetter rbo = gem_to_radeon_bo(obj); 12964c788679SJerome Glisse r = radeon_bo_reserve(rbo, false); 12974c788679SJerome Glisse if (unlikely(r != 0)) 12984c788679SJerome Glisse return r; 12994dd19b0dSChris Ball 13004dd19b0dSChris Ball /* If atomic, assume fb object is pinned & idle & fenced and 13014dd19b0dSChris Ball * just update base pointers 13024dd19b0dSChris Ball */ 13034dd19b0dSChris Ball if (atomic) 13044dd19b0dSChris Ball fb_location = radeon_bo_gpu_offset(rbo); 13054dd19b0dSChris Ball else { 13064c788679SJerome Glisse r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); 13074c788679SJerome Glisse if (unlikely(r != 0)) { 13084c788679SJerome Glisse radeon_bo_unreserve(rbo); 1309771fe6b9SJerome Glisse return -EINVAL; 1310771fe6b9SJerome Glisse } 13114dd19b0dSChris Ball } 13124c788679SJerome Glisse radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 13134c788679SJerome Glisse radeon_bo_unreserve(rbo); 1314771fe6b9SJerome Glisse 13154dd19b0dSChris Ball switch (target_fb->bits_per_pixel) { 131641456df2SDave Airlie case 8: 131741456df2SDave Airlie fb_format = 131841456df2SDave Airlie AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | 131941456df2SDave Airlie AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; 132041456df2SDave Airlie break; 1321771fe6b9SJerome Glisse case 15: 1322771fe6b9SJerome Glisse fb_format = 1323771fe6b9SJerome Glisse AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1324771fe6b9SJerome Glisse AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; 1325771fe6b9SJerome Glisse break; 1326771fe6b9SJerome Glisse case 16: 1327771fe6b9SJerome Glisse fb_format = 1328771fe6b9SJerome Glisse AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1329771fe6b9SJerome Glisse AVIVO_D1GRPH_CONTROL_16BPP_RGB565; 1330fa6bee46SAlex Deucher #ifdef __BIG_ENDIAN 1331fa6bee46SAlex Deucher fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 1332fa6bee46SAlex Deucher #endif 1333771fe6b9SJerome Glisse break; 1334771fe6b9SJerome Glisse case 24: 1335771fe6b9SJerome Glisse case 32: 1336771fe6b9SJerome Glisse fb_format = 1337771fe6b9SJerome Glisse AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | 1338771fe6b9SJerome Glisse AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; 1339fa6bee46SAlex Deucher #ifdef __BIG_ENDIAN 1340fa6bee46SAlex Deucher fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; 1341fa6bee46SAlex Deucher #endif 1342771fe6b9SJerome Glisse break; 1343771fe6b9SJerome Glisse default: 1344771fe6b9SJerome Glisse DRM_ERROR("Unsupported screen depth %d\n", 13454dd19b0dSChris Ball target_fb->bits_per_pixel); 1346771fe6b9SJerome Glisse return -EINVAL; 1347771fe6b9SJerome Glisse } 1348771fe6b9SJerome Glisse 134940c4ac1cSAlex Deucher if (rdev->family >= CHIP_R600) { 135040c4ac1cSAlex Deucher if (tiling_flags & RADEON_TILING_MACRO) 135140c4ac1cSAlex Deucher fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1; 135240c4ac1cSAlex Deucher else if (tiling_flags & RADEON_TILING_MICRO) 135340c4ac1cSAlex Deucher fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1; 135440c4ac1cSAlex Deucher } else { 1355cf2f05d3SDave Airlie if (tiling_flags & RADEON_TILING_MACRO) 1356cf2f05d3SDave Airlie fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; 1357cf2f05d3SDave Airlie 1358e024e110SDave Airlie if (tiling_flags & RADEON_TILING_MICRO) 1359e024e110SDave Airlie fb_format |= AVIVO_D1GRPH_TILED; 136040c4ac1cSAlex Deucher } 1361e024e110SDave Airlie 1362771fe6b9SJerome Glisse if (radeon_crtc->crtc_id == 0) 1363771fe6b9SJerome Glisse WREG32(AVIVO_D1VGA_CONTROL, 0); 1364771fe6b9SJerome Glisse else 1365771fe6b9SJerome Glisse WREG32(AVIVO_D2VGA_CONTROL, 0); 1366c290dadfSAlex Deucher 1367c290dadfSAlex Deucher if (rdev->family >= CHIP_RV770) { 1368c290dadfSAlex Deucher if (radeon_crtc->crtc_id) { 136995347871SAlex Deucher WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 137095347871SAlex Deucher WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1371c290dadfSAlex Deucher } else { 137295347871SAlex Deucher WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 137395347871SAlex Deucher WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1374c290dadfSAlex Deucher } 1375c290dadfSAlex Deucher } 1376771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1377771fe6b9SJerome Glisse (u32) fb_location); 1378771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + 1379771fe6b9SJerome Glisse radeon_crtc->crtc_offset, (u32) fb_location); 1380771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1381fa6bee46SAlex Deucher if (rdev->family >= CHIP_R600) 1382fa6bee46SAlex Deucher WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1383771fe6b9SJerome Glisse 1384771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1385771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1386771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); 1387771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); 13884dd19b0dSChris Ball WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); 13894dd19b0dSChris Ball WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); 1390771fe6b9SJerome Glisse 139101f2c773SVille Syrjälä fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 1392771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 1393771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1394771fe6b9SJerome Glisse 1395771fe6b9SJerome Glisse WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 13961b619250SMichel Dänzer target_fb->height); 1397771fe6b9SJerome Glisse x &= ~3; 1398771fe6b9SJerome Glisse y &= ~1; 1399771fe6b9SJerome Glisse WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, 1400771fe6b9SJerome Glisse (x << 16) | y); 1401adcfde51SAlex Deucher viewport_w = crtc->mode.hdisplay; 1402adcfde51SAlex Deucher viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1403771fe6b9SJerome Glisse WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1404adcfde51SAlex Deucher (viewport_w << 16) | viewport_h); 1405771fe6b9SJerome Glisse 1406fb9674bdSAlex Deucher /* pageflip setup */ 1407fb9674bdSAlex Deucher /* make sure flip is at vb rather than hb */ 1408fb9674bdSAlex Deucher tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); 1409fb9674bdSAlex Deucher tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN; 1410fb9674bdSAlex Deucher WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); 1411fb9674bdSAlex Deucher 1412fb9674bdSAlex Deucher /* set pageflip to happen anywhere in vblank interval */ 1413fb9674bdSAlex Deucher WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); 1414fb9674bdSAlex Deucher 14154dd19b0dSChris Ball if (!atomic && fb && fb != crtc->fb) { 14164dd19b0dSChris Ball radeon_fb = to_radeon_framebuffer(fb); 14177e4d15d9SDaniel Vetter rbo = gem_to_radeon_bo(radeon_fb->obj); 14184c788679SJerome Glisse r = radeon_bo_reserve(rbo, false); 14194c788679SJerome Glisse if (unlikely(r != 0)) 14204c788679SJerome Glisse return r; 14214c788679SJerome Glisse radeon_bo_unpin(rbo); 14224c788679SJerome Glisse radeon_bo_unreserve(rbo); 1423771fe6b9SJerome Glisse } 1424f30f37deSMichel Dänzer 1425f30f37deSMichel Dänzer /* Bytes per pixel may have changed */ 1426f30f37deSMichel Dänzer radeon_bandwidth_update(rdev); 1427f30f37deSMichel Dänzer 1428771fe6b9SJerome Glisse return 0; 1429771fe6b9SJerome Glisse } 1430771fe6b9SJerome Glisse 143154f088a9SAlex Deucher int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 143254f088a9SAlex Deucher struct drm_framebuffer *old_fb) 143354f088a9SAlex Deucher { 143454f088a9SAlex Deucher struct drm_device *dev = crtc->dev; 143554f088a9SAlex Deucher struct radeon_device *rdev = dev->dev_private; 143654f088a9SAlex Deucher 1437bcc1c2a1SAlex Deucher if (ASIC_IS_DCE4(rdev)) 1438c9417bddSAlex Deucher return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0); 1439bcc1c2a1SAlex Deucher else if (ASIC_IS_AVIVO(rdev)) 14404dd19b0dSChris Ball return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0); 144154f088a9SAlex Deucher else 14424dd19b0dSChris Ball return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); 14434dd19b0dSChris Ball } 14444dd19b0dSChris Ball 14454dd19b0dSChris Ball int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 14464dd19b0dSChris Ball struct drm_framebuffer *fb, 144721c74a8eSJason Wessel int x, int y, enum mode_set_atomic state) 14484dd19b0dSChris Ball { 14494dd19b0dSChris Ball struct drm_device *dev = crtc->dev; 14504dd19b0dSChris Ball struct radeon_device *rdev = dev->dev_private; 14514dd19b0dSChris Ball 14524dd19b0dSChris Ball if (ASIC_IS_DCE4(rdev)) 1453c9417bddSAlex Deucher return dce4_crtc_do_set_base(crtc, fb, x, y, 1); 14544dd19b0dSChris Ball else if (ASIC_IS_AVIVO(rdev)) 14554dd19b0dSChris Ball return avivo_crtc_do_set_base(crtc, fb, x, y, 1); 14564dd19b0dSChris Ball else 14574dd19b0dSChris Ball return radeon_crtc_do_set_base(crtc, fb, x, y, 1); 145854f088a9SAlex Deucher } 145954f088a9SAlex Deucher 1460615e0cb6SAlex Deucher /* properly set additional regs when using atombios */ 1461615e0cb6SAlex Deucher static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) 1462615e0cb6SAlex Deucher { 1463615e0cb6SAlex Deucher struct drm_device *dev = crtc->dev; 1464615e0cb6SAlex Deucher struct radeon_device *rdev = dev->dev_private; 1465615e0cb6SAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1466615e0cb6SAlex Deucher u32 disp_merge_cntl; 1467615e0cb6SAlex Deucher 1468615e0cb6SAlex Deucher switch (radeon_crtc->crtc_id) { 1469615e0cb6SAlex Deucher case 0: 1470615e0cb6SAlex Deucher disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); 1471615e0cb6SAlex Deucher disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 1472615e0cb6SAlex Deucher WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); 1473615e0cb6SAlex Deucher break; 1474615e0cb6SAlex Deucher case 1: 1475615e0cb6SAlex Deucher disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 1476615e0cb6SAlex Deucher disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 1477615e0cb6SAlex Deucher WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); 1478615e0cb6SAlex Deucher WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); 1479615e0cb6SAlex Deucher WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); 1480615e0cb6SAlex Deucher break; 1481615e0cb6SAlex Deucher } 1482615e0cb6SAlex Deucher } 1483615e0cb6SAlex Deucher 1484f3dd8508SAlex Deucher /** 1485f3dd8508SAlex Deucher * radeon_get_pll_use_mask - look up a mask of which pplls are in use 1486f3dd8508SAlex Deucher * 1487f3dd8508SAlex Deucher * @crtc: drm crtc 1488f3dd8508SAlex Deucher * 1489f3dd8508SAlex Deucher * Returns the mask of which PPLLs (Pixel PLLs) are in use. 1490f3dd8508SAlex Deucher */ 1491f3dd8508SAlex Deucher static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc) 1492f3dd8508SAlex Deucher { 1493f3dd8508SAlex Deucher struct drm_device *dev = crtc->dev; 1494f3dd8508SAlex Deucher struct drm_crtc *test_crtc; 149557b35e29SAlex Deucher struct radeon_crtc *test_radeon_crtc; 1496f3dd8508SAlex Deucher u32 pll_in_use = 0; 1497f3dd8508SAlex Deucher 1498f3dd8508SAlex Deucher list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1499f3dd8508SAlex Deucher if (crtc == test_crtc) 1500f3dd8508SAlex Deucher continue; 1501f3dd8508SAlex Deucher 150257b35e29SAlex Deucher test_radeon_crtc = to_radeon_crtc(test_crtc); 150357b35e29SAlex Deucher if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 150457b35e29SAlex Deucher pll_in_use |= (1 << test_radeon_crtc->pll_id); 1505f3dd8508SAlex Deucher } 1506f3dd8508SAlex Deucher return pll_in_use; 1507f3dd8508SAlex Deucher } 1508f3dd8508SAlex Deucher 1509f3dd8508SAlex Deucher /** 1510f3dd8508SAlex Deucher * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP 1511f3dd8508SAlex Deucher * 1512f3dd8508SAlex Deucher * @crtc: drm crtc 1513f3dd8508SAlex Deucher * 1514f3dd8508SAlex Deucher * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is 1515f3dd8508SAlex Deucher * also in DP mode. For DP, a single PPLL can be used for all DP 1516f3dd8508SAlex Deucher * crtcs/encoders. 1517f3dd8508SAlex Deucher */ 1518f3dd8508SAlex Deucher static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) 1519f3dd8508SAlex Deucher { 1520f3dd8508SAlex Deucher struct drm_device *dev = crtc->dev; 152157b35e29SAlex Deucher struct drm_crtc *test_crtc; 15225df3196bSAlex Deucher struct radeon_crtc *test_radeon_crtc; 1523f3dd8508SAlex Deucher 152457b35e29SAlex Deucher list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 152557b35e29SAlex Deucher if (crtc == test_crtc) 152657b35e29SAlex Deucher continue; 152757b35e29SAlex Deucher test_radeon_crtc = to_radeon_crtc(test_crtc); 152857b35e29SAlex Deucher if (test_radeon_crtc->encoder && 152957b35e29SAlex Deucher ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { 1530f3dd8508SAlex Deucher /* for DP use the same PLL for all */ 15315df3196bSAlex Deucher if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 15325df3196bSAlex Deucher return test_radeon_crtc->pll_id; 1533f3dd8508SAlex Deucher } 1534f3dd8508SAlex Deucher } 1535f3dd8508SAlex Deucher return ATOM_PPLL_INVALID; 1536f3dd8508SAlex Deucher } 1537f3dd8508SAlex Deucher 1538f3dd8508SAlex Deucher /** 15392f454cf1SAlex Deucher * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc 15402f454cf1SAlex Deucher * 15412f454cf1SAlex Deucher * @crtc: drm crtc 15422f454cf1SAlex Deucher * @encoder: drm encoder 15432f454cf1SAlex Deucher * 15442f454cf1SAlex Deucher * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can 15452f454cf1SAlex Deucher * be shared (i.e., same clock). 15462f454cf1SAlex Deucher */ 15475df3196bSAlex Deucher static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc) 15482f454cf1SAlex Deucher { 15495df3196bSAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 15502f454cf1SAlex Deucher struct drm_device *dev = crtc->dev; 15519642ac0eSAlex Deucher struct drm_crtc *test_crtc; 15525df3196bSAlex Deucher struct radeon_crtc *test_radeon_crtc; 15539642ac0eSAlex Deucher u32 adjusted_clock, test_adjusted_clock; 15542f454cf1SAlex Deucher 15559642ac0eSAlex Deucher adjusted_clock = radeon_crtc->adjusted_clock; 15569642ac0eSAlex Deucher 15579642ac0eSAlex Deucher if (adjusted_clock == 0) 15589642ac0eSAlex Deucher return ATOM_PPLL_INVALID; 15592f454cf1SAlex Deucher 156057b35e29SAlex Deucher list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 156157b35e29SAlex Deucher if (crtc == test_crtc) 156257b35e29SAlex Deucher continue; 15639642ac0eSAlex Deucher test_radeon_crtc = to_radeon_crtc(test_crtc); 156457b35e29SAlex Deucher if (test_radeon_crtc->encoder && 156557b35e29SAlex Deucher !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { 156657b35e29SAlex Deucher /* check if we are already driving this connector with another crtc */ 156757b35e29SAlex Deucher if (test_radeon_crtc->connector == radeon_crtc->connector) { 156857b35e29SAlex Deucher /* if we are, return that pll */ 156957b35e29SAlex Deucher if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 157057b35e29SAlex Deucher return test_radeon_crtc->pll_id; 157157b35e29SAlex Deucher } 15722f454cf1SAlex Deucher /* for non-DP check the clock */ 15739642ac0eSAlex Deucher test_adjusted_clock = test_radeon_crtc->adjusted_clock; 15749642ac0eSAlex Deucher if ((crtc->mode.clock == test_crtc->mode.clock) && 15759642ac0eSAlex Deucher (adjusted_clock == test_adjusted_clock) && 15769642ac0eSAlex Deucher (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) && 15775df3196bSAlex Deucher (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)) 15785df3196bSAlex Deucher return test_radeon_crtc->pll_id; 15792f454cf1SAlex Deucher } 15802f454cf1SAlex Deucher } 15812f454cf1SAlex Deucher return ATOM_PPLL_INVALID; 15822f454cf1SAlex Deucher } 15832f454cf1SAlex Deucher 15842f454cf1SAlex Deucher /** 1585f3dd8508SAlex Deucher * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc. 1586f3dd8508SAlex Deucher * 1587f3dd8508SAlex Deucher * @crtc: drm crtc 1588f3dd8508SAlex Deucher * 1589f3dd8508SAlex Deucher * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 1590f3dd8508SAlex Deucher * a single PPLL can be used for all DP crtcs/encoders. For non-DP 1591f3dd8508SAlex Deucher * monitors a dedicated PPLL must be used. If a particular board has 1592f3dd8508SAlex Deucher * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 1593f3dd8508SAlex Deucher * as there is no need to program the PLL itself. If we are not able to 1594f3dd8508SAlex Deucher * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 1595f3dd8508SAlex Deucher * avoid messing up an existing monitor. 1596f3dd8508SAlex Deucher * 1597f3dd8508SAlex Deucher * Asic specific PLL information 1598f3dd8508SAlex Deucher * 1599f3dd8508SAlex Deucher * DCE 6.1 1600f3dd8508SAlex Deucher * - PPLL2 is only available to UNIPHYA (both DP and non-DP) 1601f3dd8508SAlex Deucher * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP) 1602f3dd8508SAlex Deucher * 1603f3dd8508SAlex Deucher * DCE 6.0 1604f3dd8508SAlex Deucher * - PPLL0 is available to all UNIPHY (DP only) 1605f3dd8508SAlex Deucher * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1606f3dd8508SAlex Deucher * 1607f3dd8508SAlex Deucher * DCE 5.0 1608f3dd8508SAlex Deucher * - DCPLL is available to all UNIPHY (DP only) 1609f3dd8508SAlex Deucher * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1610f3dd8508SAlex Deucher * 1611f3dd8508SAlex Deucher * DCE 3.0/4.0/4.1 1612f3dd8508SAlex Deucher * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1613f3dd8508SAlex Deucher * 1614f3dd8508SAlex Deucher */ 1615bcc1c2a1SAlex Deucher static int radeon_atom_pick_pll(struct drm_crtc *crtc) 1616bcc1c2a1SAlex Deucher { 16175df3196bSAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1618bcc1c2a1SAlex Deucher struct drm_device *dev = crtc->dev; 1619bcc1c2a1SAlex Deucher struct radeon_device *rdev = dev->dev_private; 16205df3196bSAlex Deucher struct radeon_encoder *radeon_encoder = 16215df3196bSAlex Deucher to_radeon_encoder(radeon_crtc->encoder); 1622f3dd8508SAlex Deucher u32 pll_in_use; 1623f3dd8508SAlex Deucher int pll; 1624bcc1c2a1SAlex Deucher 162524e1f794SAlex Deucher if (ASIC_IS_DCE61(rdev)) { 162624e1f794SAlex Deucher struct radeon_encoder_atom_dig *dig = 16275df3196bSAlex Deucher radeon_encoder->enc_priv; 162824e1f794SAlex Deucher 16295df3196bSAlex Deucher if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) && 1630f3dd8508SAlex Deucher (dig->linkb == false)) 1631f3dd8508SAlex Deucher /* UNIPHY A uses PPLL2 */ 163224e1f794SAlex Deucher return ATOM_PPLL2; 16335df3196bSAlex Deucher else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1634f3dd8508SAlex Deucher /* UNIPHY B/C/D/E/F */ 1635f3dd8508SAlex Deucher if (rdev->clock.dp_extclk) 1636f3dd8508SAlex Deucher /* skip PPLL programming if using ext clock */ 1637f3dd8508SAlex Deucher return ATOM_PPLL_INVALID; 1638f3dd8508SAlex Deucher else { 1639f3dd8508SAlex Deucher /* use the same PPLL for all DP monitors */ 1640f3dd8508SAlex Deucher pll = radeon_get_shared_dp_ppll(crtc); 1641f3dd8508SAlex Deucher if (pll != ATOM_PPLL_INVALID) 1642f3dd8508SAlex Deucher return pll; 1643f3dd8508SAlex Deucher } 16442f454cf1SAlex Deucher } else { 16452f454cf1SAlex Deucher /* use the same PPLL for all monitors with the same clock */ 16465df3196bSAlex Deucher pll = radeon_get_shared_nondp_ppll(crtc); 16472f454cf1SAlex Deucher if (pll != ATOM_PPLL_INVALID) 16482f454cf1SAlex Deucher return pll; 1649f3dd8508SAlex Deucher } 165024e1f794SAlex Deucher /* UNIPHY B/C/D/E/F */ 1651f3dd8508SAlex Deucher pll_in_use = radeon_get_pll_use_mask(crtc); 1652f3dd8508SAlex Deucher if (!(pll_in_use & (1 << ATOM_PPLL0))) 165324e1f794SAlex Deucher return ATOM_PPLL0; 1654f3dd8508SAlex Deucher if (!(pll_in_use & (1 << ATOM_PPLL1))) 165524e1f794SAlex Deucher return ATOM_PPLL1; 1656f3dd8508SAlex Deucher DRM_ERROR("unable to allocate a PPLL\n"); 1657f3dd8508SAlex Deucher return ATOM_PPLL_INVALID; 165824e1f794SAlex Deucher } else if (ASIC_IS_DCE4(rdev)) { 165986a94defSAlex Deucher /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, 166086a94defSAlex Deucher * depending on the asic: 166186a94defSAlex Deucher * DCE4: PPLL or ext clock 1662f3dd8508SAlex Deucher * DCE5: PPLL, DCPLL, or ext clock 1663f3dd8508SAlex Deucher * DCE6: PPLL, PPLL0, or ext clock 166486a94defSAlex Deucher * 166586a94defSAlex Deucher * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip 166686a94defSAlex Deucher * PPLL/DCPLL programming and only program the DP DTO for the 166786a94defSAlex Deucher * crtc virtual pixel clock. 166886a94defSAlex Deucher */ 16695df3196bSAlex Deucher if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1670ecd67955SAlex Deucher if (rdev->clock.dp_extclk) 1671f3dd8508SAlex Deucher /* skip PPLL programming if using ext clock */ 1672ecd67955SAlex Deucher return ATOM_PPLL_INVALID; 167326fe45a0SAlex Deucher else if (ASIC_IS_DCE6(rdev)) 1674f3dd8508SAlex Deucher /* use PPLL0 for all DP */ 167526fe45a0SAlex Deucher return ATOM_PPLL0; 1676ecd67955SAlex Deucher else if (ASIC_IS_DCE5(rdev)) 1677f3dd8508SAlex Deucher /* use DCPLL for all DP */ 1678ecd67955SAlex Deucher return ATOM_DCPLL; 1679f3dd8508SAlex Deucher else { 1680f3dd8508SAlex Deucher /* use the same PPLL for all DP monitors */ 1681f3dd8508SAlex Deucher pll = radeon_get_shared_dp_ppll(crtc); 1682f3dd8508SAlex Deucher if (pll != ATOM_PPLL_INVALID) 1683f3dd8508SAlex Deucher return pll; 1684bcc1c2a1SAlex Deucher } 16852f454cf1SAlex Deucher } else { 16862f454cf1SAlex Deucher /* use the same PPLL for all monitors with the same clock */ 16875df3196bSAlex Deucher pll = radeon_get_shared_nondp_ppll(crtc); 16889dbbcfc6SAlex Deucher if (pll != ATOM_PPLL_INVALID) 16899dbbcfc6SAlex Deucher return pll; 16909dbbcfc6SAlex Deucher } 16915df3196bSAlex Deucher /* all other cases */ 16925df3196bSAlex Deucher pll_in_use = radeon_get_pll_use_mask(crtc); 16935df3196bSAlex Deucher if (!(pll_in_use & (1 << ATOM_PPLL2))) 16945df3196bSAlex Deucher return ATOM_PPLL2; 16955df3196bSAlex Deucher if (!(pll_in_use & (1 << ATOM_PPLL1))) 16965df3196bSAlex Deucher return ATOM_PPLL1; 16975df3196bSAlex Deucher DRM_ERROR("unable to allocate a PPLL\n"); 16985df3196bSAlex Deucher return ATOM_PPLL_INVALID; 16995df3196bSAlex Deucher } else { 17005df3196bSAlex Deucher if (ASIC_IS_AVIVO(rdev)) { 17015df3196bSAlex Deucher /* in DP mode, the DP ref clock can come from either PPLL 17025df3196bSAlex Deucher * depending on the asic: 17035df3196bSAlex Deucher * DCE3: PPLL1 or PPLL2 17045df3196bSAlex Deucher */ 17055df3196bSAlex Deucher if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 17065df3196bSAlex Deucher /* use the same PPLL for all DP monitors */ 17075df3196bSAlex Deucher pll = radeon_get_shared_dp_ppll(crtc); 17085df3196bSAlex Deucher if (pll != ATOM_PPLL_INVALID) 17095df3196bSAlex Deucher return pll; 17105df3196bSAlex Deucher } else { 17115df3196bSAlex Deucher /* use the same PPLL for all monitors with the same clock */ 17125df3196bSAlex Deucher pll = radeon_get_shared_nondp_ppll(crtc); 17135df3196bSAlex Deucher if (pll != ATOM_PPLL_INVALID) 17145df3196bSAlex Deucher return pll; 17159dbbcfc6SAlex Deucher } 17169dbbcfc6SAlex Deucher /* all other cases */ 17179dbbcfc6SAlex Deucher pll_in_use = radeon_get_pll_use_mask(crtc); 17189dbbcfc6SAlex Deucher if (!(pll_in_use & (1 << ATOM_PPLL2))) 17199dbbcfc6SAlex Deucher return ATOM_PPLL2; 17209dbbcfc6SAlex Deucher if (!(pll_in_use & (1 << ATOM_PPLL1))) 17219dbbcfc6SAlex Deucher return ATOM_PPLL1; 17229dbbcfc6SAlex Deucher DRM_ERROR("unable to allocate a PPLL\n"); 17239dbbcfc6SAlex Deucher return ATOM_PPLL_INVALID; 17242f454cf1SAlex Deucher } else { 17252f454cf1SAlex Deucher /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ 1726bcc1c2a1SAlex Deucher return radeon_crtc->crtc_id; 17272f454cf1SAlex Deucher } 17282f454cf1SAlex Deucher } 1729bcc1c2a1SAlex Deucher } 1730bcc1c2a1SAlex Deucher 1731f3f1f03eSAlex Deucher void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev) 17323fa47d9eSAlex Deucher { 17333fa47d9eSAlex Deucher /* always set DCPLL */ 1734f3f1f03eSAlex Deucher if (ASIC_IS_DCE6(rdev)) 1735f3f1f03eSAlex Deucher atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); 1736f3f1f03eSAlex Deucher else if (ASIC_IS_DCE4(rdev)) { 17373fa47d9eSAlex Deucher struct radeon_atom_ss ss; 17383fa47d9eSAlex Deucher bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, 17393fa47d9eSAlex Deucher ASIC_INTERNAL_SS_ON_DCPLL, 17403fa47d9eSAlex Deucher rdev->clock.default_dispclk); 17413fa47d9eSAlex Deucher if (ss_enabled) 17425efcc76cSJerome Glisse atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss); 17433fa47d9eSAlex Deucher /* XXX: DCE5, make sure voltage, dispclk is high enough */ 1744f3f1f03eSAlex Deucher atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); 17453fa47d9eSAlex Deucher if (ss_enabled) 17465efcc76cSJerome Glisse atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss); 17473fa47d9eSAlex Deucher } 17483fa47d9eSAlex Deucher 17493fa47d9eSAlex Deucher } 17503fa47d9eSAlex Deucher 1751771fe6b9SJerome Glisse int atombios_crtc_mode_set(struct drm_crtc *crtc, 1752771fe6b9SJerome Glisse struct drm_display_mode *mode, 1753771fe6b9SJerome Glisse struct drm_display_mode *adjusted_mode, 1754771fe6b9SJerome Glisse int x, int y, struct drm_framebuffer *old_fb) 1755771fe6b9SJerome Glisse { 1756771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1757771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 1758771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 17595df3196bSAlex Deucher struct radeon_encoder *radeon_encoder = 17605df3196bSAlex Deucher to_radeon_encoder(radeon_crtc->encoder); 176154bfe496SAlex Deucher bool is_tvcv = false; 1762771fe6b9SJerome Glisse 176354bfe496SAlex Deucher if (radeon_encoder->active_device & 176454bfe496SAlex Deucher (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 176554bfe496SAlex Deucher is_tvcv = true; 1766771fe6b9SJerome Glisse 1767771fe6b9SJerome Glisse atombios_crtc_set_pll(crtc, adjusted_mode); 1768771fe6b9SJerome Glisse 176954bfe496SAlex Deucher if (ASIC_IS_DCE4(rdev)) 1770bcc1c2a1SAlex Deucher atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 177154bfe496SAlex Deucher else if (ASIC_IS_AVIVO(rdev)) { 177254bfe496SAlex Deucher if (is_tvcv) 177354bfe496SAlex Deucher atombios_crtc_set_timing(crtc, adjusted_mode); 177454bfe496SAlex Deucher else 177554bfe496SAlex Deucher atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 177654bfe496SAlex Deucher } else { 1777bcc1c2a1SAlex Deucher atombios_crtc_set_timing(crtc, adjusted_mode); 17785a9bcaccSAlex Deucher if (radeon_crtc->crtc_id == 0) 17795a9bcaccSAlex Deucher atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1780615e0cb6SAlex Deucher radeon_legacy_atom_fixup(crtc); 1781771fe6b9SJerome Glisse } 1782bcc1c2a1SAlex Deucher atombios_crtc_set_base(crtc, x, y, old_fb); 1783c93bb85bSJerome Glisse atombios_overscan_setup(crtc, mode, adjusted_mode); 1784c93bb85bSJerome Glisse atombios_scaler_setup(crtc); 1785771fe6b9SJerome Glisse return 0; 1786771fe6b9SJerome Glisse } 1787771fe6b9SJerome Glisse 1788771fe6b9SJerome Glisse static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, 1789e811f5aeSLaurent Pinchart const struct drm_display_mode *mode, 1790771fe6b9SJerome Glisse struct drm_display_mode *adjusted_mode) 1791771fe6b9SJerome Glisse { 17925df3196bSAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 17935df3196bSAlex Deucher struct drm_device *dev = crtc->dev; 17945df3196bSAlex Deucher struct drm_encoder *encoder; 17955df3196bSAlex Deucher 17965df3196bSAlex Deucher /* assign the encoder to the radeon crtc to avoid repeated lookups later */ 17975df3196bSAlex Deucher list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 17985df3196bSAlex Deucher if (encoder->crtc == crtc) { 17995df3196bSAlex Deucher radeon_crtc->encoder = encoder; 180057b35e29SAlex Deucher radeon_crtc->connector = radeon_get_connector_for_encoder(encoder); 18015df3196bSAlex Deucher break; 18025df3196bSAlex Deucher } 18035df3196bSAlex Deucher } 180457b35e29SAlex Deucher if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) { 180557b35e29SAlex Deucher radeon_crtc->encoder = NULL; 180657b35e29SAlex Deucher radeon_crtc->connector = NULL; 18075df3196bSAlex Deucher return false; 180857b35e29SAlex Deucher } 1809c93bb85bSJerome Glisse if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 1810c93bb85bSJerome Glisse return false; 181119eca43eSAlex Deucher if (!atombios_crtc_prepare_pll(crtc, adjusted_mode)) 181219eca43eSAlex Deucher return false; 1813c0fd0834SAlex Deucher /* pick pll */ 1814c0fd0834SAlex Deucher radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); 1815c0fd0834SAlex Deucher /* if we can't get a PPLL for a non-DP encoder, fail */ 1816c0fd0834SAlex Deucher if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) && 1817c0fd0834SAlex Deucher !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) 1818c0fd0834SAlex Deucher return false; 1819c0fd0834SAlex Deucher 1820771fe6b9SJerome Glisse return true; 1821771fe6b9SJerome Glisse } 1822771fe6b9SJerome Glisse 1823771fe6b9SJerome Glisse static void atombios_crtc_prepare(struct drm_crtc *crtc) 1824771fe6b9SJerome Glisse { 1825267364acSAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 18266c0ae2abSAlex Deucher struct drm_device *dev = crtc->dev; 18276c0ae2abSAlex Deucher struct radeon_device *rdev = dev->dev_private; 1828267364acSAlex Deucher 18296c0ae2abSAlex Deucher radeon_crtc->in_mode_set = true; 1830267364acSAlex Deucher 18316c0ae2abSAlex Deucher /* disable crtc pair power gating before programming */ 18326c0ae2abSAlex Deucher if (ASIC_IS_DCE6(rdev)) 18336c0ae2abSAlex Deucher atombios_powergate_crtc(crtc, ATOM_DISABLE); 18346c0ae2abSAlex Deucher 183537b4390eSAlex Deucher atombios_lock_crtc(crtc, ATOM_ENABLE); 1836a348c84dSAlex Deucher atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1837771fe6b9SJerome Glisse } 1838771fe6b9SJerome Glisse 1839771fe6b9SJerome Glisse static void atombios_crtc_commit(struct drm_crtc *crtc) 1840771fe6b9SJerome Glisse { 18416c0ae2abSAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 18426c0ae2abSAlex Deucher 1843771fe6b9SJerome Glisse atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 184437b4390eSAlex Deucher atombios_lock_crtc(crtc, ATOM_DISABLE); 18456c0ae2abSAlex Deucher radeon_crtc->in_mode_set = false; 1846771fe6b9SJerome Glisse } 1847771fe6b9SJerome Glisse 184837f9003bSAlex Deucher static void atombios_crtc_disable(struct drm_crtc *crtc) 184937f9003bSAlex Deucher { 185037f9003bSAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 185164199870SAlex Deucher struct drm_device *dev = crtc->dev; 185264199870SAlex Deucher struct radeon_device *rdev = dev->dev_private; 18538e8e523dSAlex Deucher struct radeon_atom_ss ss; 18544e58591cSAlex Deucher int i; 18558e8e523dSAlex Deucher 185637f9003bSAlex Deucher atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 185737f9003bSAlex Deucher 18584e58591cSAlex Deucher for (i = 0; i < rdev->num_crtc; i++) { 18594e58591cSAlex Deucher if (rdev->mode_info.crtcs[i] && 18604e58591cSAlex Deucher rdev->mode_info.crtcs[i]->enabled && 18614e58591cSAlex Deucher i != radeon_crtc->crtc_id && 18624e58591cSAlex Deucher radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) { 18634e58591cSAlex Deucher /* one other crtc is using this pll don't turn 18644e58591cSAlex Deucher * off the pll 18654e58591cSAlex Deucher */ 18664e58591cSAlex Deucher goto done; 18674e58591cSAlex Deucher } 18684e58591cSAlex Deucher } 18694e58591cSAlex Deucher 187037f9003bSAlex Deucher switch (radeon_crtc->pll_id) { 187137f9003bSAlex Deucher case ATOM_PPLL1: 187237f9003bSAlex Deucher case ATOM_PPLL2: 187337f9003bSAlex Deucher /* disable the ppll */ 187437f9003bSAlex Deucher atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 18758e8e523dSAlex Deucher 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 187637f9003bSAlex Deucher break; 187764199870SAlex Deucher case ATOM_PPLL0: 187864199870SAlex Deucher /* disable the ppll */ 187964199870SAlex Deucher if (ASIC_IS_DCE61(rdev)) 188064199870SAlex Deucher atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 188164199870SAlex Deucher 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 188264199870SAlex Deucher break; 188337f9003bSAlex Deucher default: 188437f9003bSAlex Deucher break; 188537f9003bSAlex Deucher } 18864e58591cSAlex Deucher done: 1887f3dd8508SAlex Deucher radeon_crtc->pll_id = ATOM_PPLL_INVALID; 18889642ac0eSAlex Deucher radeon_crtc->adjusted_clock = 0; 18895df3196bSAlex Deucher radeon_crtc->encoder = NULL; 189057b35e29SAlex Deucher radeon_crtc->connector = NULL; 189137f9003bSAlex Deucher } 189237f9003bSAlex Deucher 1893771fe6b9SJerome Glisse static const struct drm_crtc_helper_funcs atombios_helper_funcs = { 1894771fe6b9SJerome Glisse .dpms = atombios_crtc_dpms, 1895771fe6b9SJerome Glisse .mode_fixup = atombios_crtc_mode_fixup, 1896771fe6b9SJerome Glisse .mode_set = atombios_crtc_mode_set, 1897771fe6b9SJerome Glisse .mode_set_base = atombios_crtc_set_base, 18984dd19b0dSChris Ball .mode_set_base_atomic = atombios_crtc_set_base_atomic, 1899771fe6b9SJerome Glisse .prepare = atombios_crtc_prepare, 1900771fe6b9SJerome Glisse .commit = atombios_crtc_commit, 1901068143d3SDave Airlie .load_lut = radeon_crtc_load_lut, 190237f9003bSAlex Deucher .disable = atombios_crtc_disable, 1903771fe6b9SJerome Glisse }; 1904771fe6b9SJerome Glisse 1905771fe6b9SJerome Glisse void radeon_atombios_init_crtc(struct drm_device *dev, 1906771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc) 1907771fe6b9SJerome Glisse { 1908bcc1c2a1SAlex Deucher struct radeon_device *rdev = dev->dev_private; 1909bcc1c2a1SAlex Deucher 1910bcc1c2a1SAlex Deucher if (ASIC_IS_DCE4(rdev)) { 1911bcc1c2a1SAlex Deucher switch (radeon_crtc->crtc_id) { 1912bcc1c2a1SAlex Deucher case 0: 1913bcc1c2a1SAlex Deucher default: 191412d7798fSAlex Deucher radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; 1915bcc1c2a1SAlex Deucher break; 1916bcc1c2a1SAlex Deucher case 1: 191712d7798fSAlex Deucher radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; 1918bcc1c2a1SAlex Deucher break; 1919bcc1c2a1SAlex Deucher case 2: 192012d7798fSAlex Deucher radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; 1921bcc1c2a1SAlex Deucher break; 1922bcc1c2a1SAlex Deucher case 3: 192312d7798fSAlex Deucher radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; 1924bcc1c2a1SAlex Deucher break; 1925bcc1c2a1SAlex Deucher case 4: 192612d7798fSAlex Deucher radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; 1927bcc1c2a1SAlex Deucher break; 1928bcc1c2a1SAlex Deucher case 5: 192912d7798fSAlex Deucher radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; 1930bcc1c2a1SAlex Deucher break; 1931bcc1c2a1SAlex Deucher } 1932bcc1c2a1SAlex Deucher } else { 1933771fe6b9SJerome Glisse if (radeon_crtc->crtc_id == 1) 1934771fe6b9SJerome Glisse radeon_crtc->crtc_offset = 1935771fe6b9SJerome Glisse AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; 1936bcc1c2a1SAlex Deucher else 1937bcc1c2a1SAlex Deucher radeon_crtc->crtc_offset = 0; 1938bcc1c2a1SAlex Deucher } 1939f3dd8508SAlex Deucher radeon_crtc->pll_id = ATOM_PPLL_INVALID; 19409642ac0eSAlex Deucher radeon_crtc->adjusted_clock = 0; 19415df3196bSAlex Deucher radeon_crtc->encoder = NULL; 194257b35e29SAlex Deucher radeon_crtc->connector = NULL; 1943771fe6b9SJerome Glisse drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); 1944771fe6b9SJerome Glisse } 1945