1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2007-8 Advanced Micro Devices, Inc. 3771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 4771fe6b9SJerome Glisse * 5771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 6771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 7771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 8771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 10771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 11771fe6b9SJerome Glisse * 12771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 13771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 14771fe6b9SJerome Glisse * 15771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 22771fe6b9SJerome Glisse * 23771fe6b9SJerome Glisse * Authors: Dave Airlie 24771fe6b9SJerome Glisse * Alex Deucher 25771fe6b9SJerome Glisse */ 26771fe6b9SJerome Glisse #include <drm/drmP.h> 27771fe6b9SJerome Glisse #include <drm/drm_crtc_helper.h> 28771fe6b9SJerome Glisse #include <drm/radeon_drm.h> 2968adac5eSBen Skeggs #include <drm/drm_fixed.h> 30771fe6b9SJerome Glisse #include "radeon.h" 31771fe6b9SJerome Glisse #include "atom.h" 32771fe6b9SJerome Glisse #include "atom-bits.h" 33771fe6b9SJerome Glisse 34c93bb85bSJerome Glisse static void atombios_overscan_setup(struct drm_crtc *crtc, 35c93bb85bSJerome Glisse struct drm_display_mode *mode, 36c93bb85bSJerome Glisse struct drm_display_mode *adjusted_mode) 37c93bb85bSJerome Glisse { 38c93bb85bSJerome Glisse struct drm_device *dev = crtc->dev; 39c93bb85bSJerome Glisse struct radeon_device *rdev = dev->dev_private; 40c93bb85bSJerome Glisse struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 41c93bb85bSJerome Glisse SET_CRTC_OVERSCAN_PS_ALLOCATION args; 42c93bb85bSJerome Glisse int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); 43c93bb85bSJerome Glisse int a1, a2; 44c93bb85bSJerome Glisse 45c93bb85bSJerome Glisse memset(&args, 0, sizeof(args)); 46c93bb85bSJerome Glisse 47c93bb85bSJerome Glisse args.ucCRTC = radeon_crtc->crtc_id; 48c93bb85bSJerome Glisse 49c93bb85bSJerome Glisse switch (radeon_crtc->rmx_type) { 50c93bb85bSJerome Glisse case RMX_CENTER: 514589433cSCédric Cano args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 524589433cSCédric Cano args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 534589433cSCédric Cano args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 544589433cSCédric Cano args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 55c93bb85bSJerome Glisse break; 56c93bb85bSJerome Glisse case RMX_ASPECT: 57c93bb85bSJerome Glisse a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; 58c93bb85bSJerome Glisse a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; 59c93bb85bSJerome Glisse 60c93bb85bSJerome Glisse if (a1 > a2) { 614589433cSCédric Cano args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 624589433cSCédric Cano args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 63c93bb85bSJerome Glisse } else if (a2 > a1) { 64942b0e95SAlex Deucher args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 65942b0e95SAlex Deucher args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 66c93bb85bSJerome Glisse } 67c93bb85bSJerome Glisse break; 68c93bb85bSJerome Glisse case RMX_FULL: 69c93bb85bSJerome Glisse default: 704589433cSCédric Cano args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); 714589433cSCédric Cano args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); 724589433cSCédric Cano args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); 734589433cSCédric Cano args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); 74c93bb85bSJerome Glisse break; 75c93bb85bSJerome Glisse } 765b1714d3SAlex Deucher atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 77c93bb85bSJerome Glisse } 78c93bb85bSJerome Glisse 79c93bb85bSJerome Glisse static void atombios_scaler_setup(struct drm_crtc *crtc) 80c93bb85bSJerome Glisse { 81c93bb85bSJerome Glisse struct drm_device *dev = crtc->dev; 82c93bb85bSJerome Glisse struct radeon_device *rdev = dev->dev_private; 83c93bb85bSJerome Glisse struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 84c93bb85bSJerome Glisse ENABLE_SCALER_PS_ALLOCATION args; 85c93bb85bSJerome Glisse int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); 865df3196bSAlex Deucher struct radeon_encoder *radeon_encoder = 875df3196bSAlex Deucher to_radeon_encoder(radeon_crtc->encoder); 88c93bb85bSJerome Glisse /* fixme - fill in enc_priv for atom dac */ 89c93bb85bSJerome Glisse enum radeon_tv_std tv_std = TV_STD_NTSC; 904ce001abSDave Airlie bool is_tv = false, is_cv = false; 91c93bb85bSJerome Glisse 92c93bb85bSJerome Glisse if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) 93c93bb85bSJerome Glisse return; 94c93bb85bSJerome Glisse 954ce001abSDave Airlie if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 964ce001abSDave Airlie struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 974ce001abSDave Airlie tv_std = tv_dac->tv_std; 984ce001abSDave Airlie is_tv = true; 994ce001abSDave Airlie } 1004ce001abSDave Airlie 101c93bb85bSJerome Glisse memset(&args, 0, sizeof(args)); 102c93bb85bSJerome Glisse 103c93bb85bSJerome Glisse args.ucScaler = radeon_crtc->crtc_id; 104c93bb85bSJerome Glisse 1054ce001abSDave Airlie if (is_tv) { 106c93bb85bSJerome Glisse switch (tv_std) { 107c93bb85bSJerome Glisse case TV_STD_NTSC: 108c93bb85bSJerome Glisse default: 109c93bb85bSJerome Glisse args.ucTVStandard = ATOM_TV_NTSC; 110c93bb85bSJerome Glisse break; 111c93bb85bSJerome Glisse case TV_STD_PAL: 112c93bb85bSJerome Glisse args.ucTVStandard = ATOM_TV_PAL; 113c93bb85bSJerome Glisse break; 114c93bb85bSJerome Glisse case TV_STD_PAL_M: 115c93bb85bSJerome Glisse args.ucTVStandard = ATOM_TV_PALM; 116c93bb85bSJerome Glisse break; 117c93bb85bSJerome Glisse case TV_STD_PAL_60: 118c93bb85bSJerome Glisse args.ucTVStandard = ATOM_TV_PAL60; 119c93bb85bSJerome Glisse break; 120c93bb85bSJerome Glisse case TV_STD_NTSC_J: 121c93bb85bSJerome Glisse args.ucTVStandard = ATOM_TV_NTSCJ; 122c93bb85bSJerome Glisse break; 123c93bb85bSJerome Glisse case TV_STD_SCART_PAL: 124c93bb85bSJerome Glisse args.ucTVStandard = ATOM_TV_PAL; /* ??? */ 125c93bb85bSJerome Glisse break; 126c93bb85bSJerome Glisse case TV_STD_SECAM: 127c93bb85bSJerome Glisse args.ucTVStandard = ATOM_TV_SECAM; 128c93bb85bSJerome Glisse break; 129c93bb85bSJerome Glisse case TV_STD_PAL_CN: 130c93bb85bSJerome Glisse args.ucTVStandard = ATOM_TV_PALCN; 131c93bb85bSJerome Glisse break; 132c93bb85bSJerome Glisse } 133c93bb85bSJerome Glisse args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 1344ce001abSDave Airlie } else if (is_cv) { 135c93bb85bSJerome Glisse args.ucTVStandard = ATOM_TV_CV; 136c93bb85bSJerome Glisse args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 137c93bb85bSJerome Glisse } else { 138c93bb85bSJerome Glisse switch (radeon_crtc->rmx_type) { 139c93bb85bSJerome Glisse case RMX_FULL: 140c93bb85bSJerome Glisse args.ucEnable = ATOM_SCALER_EXPANSION; 141c93bb85bSJerome Glisse break; 142c93bb85bSJerome Glisse case RMX_CENTER: 143c93bb85bSJerome Glisse args.ucEnable = ATOM_SCALER_CENTER; 144c93bb85bSJerome Glisse break; 145c93bb85bSJerome Glisse case RMX_ASPECT: 146c93bb85bSJerome Glisse args.ucEnable = ATOM_SCALER_EXPANSION; 147c93bb85bSJerome Glisse break; 148c93bb85bSJerome Glisse default: 149c93bb85bSJerome Glisse if (ASIC_IS_AVIVO(rdev)) 150c93bb85bSJerome Glisse args.ucEnable = ATOM_SCALER_DISABLE; 151c93bb85bSJerome Glisse else 152c93bb85bSJerome Glisse args.ucEnable = ATOM_SCALER_CENTER; 153c93bb85bSJerome Glisse break; 154c93bb85bSJerome Glisse } 155c93bb85bSJerome Glisse } 156c93bb85bSJerome Glisse atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1574ce001abSDave Airlie if ((is_tv || is_cv) 1584ce001abSDave Airlie && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { 1594ce001abSDave Airlie atom_rv515_force_tv_scaler(rdev, radeon_crtc); 160c93bb85bSJerome Glisse } 161c93bb85bSJerome Glisse } 162c93bb85bSJerome Glisse 163771fe6b9SJerome Glisse static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) 164771fe6b9SJerome Glisse { 165771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 166771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 167771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 168771fe6b9SJerome Glisse int index = 169771fe6b9SJerome Glisse GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); 170771fe6b9SJerome Glisse ENABLE_CRTC_PS_ALLOCATION args; 171771fe6b9SJerome Glisse 172771fe6b9SJerome Glisse memset(&args, 0, sizeof(args)); 173771fe6b9SJerome Glisse 174771fe6b9SJerome Glisse args.ucCRTC = radeon_crtc->crtc_id; 175771fe6b9SJerome Glisse args.ucEnable = lock; 176771fe6b9SJerome Glisse 177771fe6b9SJerome Glisse atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 178771fe6b9SJerome Glisse } 179771fe6b9SJerome Glisse 180771fe6b9SJerome Glisse static void atombios_enable_crtc(struct drm_crtc *crtc, int state) 181771fe6b9SJerome Glisse { 182771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 183771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 184771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 185771fe6b9SJerome Glisse int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); 186771fe6b9SJerome Glisse ENABLE_CRTC_PS_ALLOCATION args; 187771fe6b9SJerome Glisse 188771fe6b9SJerome Glisse memset(&args, 0, sizeof(args)); 189771fe6b9SJerome Glisse 190771fe6b9SJerome Glisse args.ucCRTC = radeon_crtc->crtc_id; 191771fe6b9SJerome Glisse args.ucEnable = state; 192771fe6b9SJerome Glisse 193771fe6b9SJerome Glisse atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 194771fe6b9SJerome Glisse } 195771fe6b9SJerome Glisse 196771fe6b9SJerome Glisse static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) 197771fe6b9SJerome Glisse { 198771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 199771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 200771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 201771fe6b9SJerome Glisse int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); 202771fe6b9SJerome Glisse ENABLE_CRTC_PS_ALLOCATION args; 203771fe6b9SJerome Glisse 204771fe6b9SJerome Glisse memset(&args, 0, sizeof(args)); 205771fe6b9SJerome Glisse 206771fe6b9SJerome Glisse args.ucCRTC = radeon_crtc->crtc_id; 207771fe6b9SJerome Glisse args.ucEnable = state; 208771fe6b9SJerome Glisse 209771fe6b9SJerome Glisse atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 210771fe6b9SJerome Glisse } 211771fe6b9SJerome Glisse 212771fe6b9SJerome Glisse static void atombios_blank_crtc(struct drm_crtc *crtc, int state) 213771fe6b9SJerome Glisse { 214771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 215771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 216771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 217771fe6b9SJerome Glisse int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); 218771fe6b9SJerome Glisse BLANK_CRTC_PS_ALLOCATION args; 219771fe6b9SJerome Glisse 220771fe6b9SJerome Glisse memset(&args, 0, sizeof(args)); 221771fe6b9SJerome Glisse 222771fe6b9SJerome Glisse args.ucCRTC = radeon_crtc->crtc_id; 223771fe6b9SJerome Glisse args.ucBlanking = state; 224771fe6b9SJerome Glisse 225771fe6b9SJerome Glisse atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 226771fe6b9SJerome Glisse } 227771fe6b9SJerome Glisse 228fef9f91fSAlex Deucher static void atombios_powergate_crtc(struct drm_crtc *crtc, int state) 229fef9f91fSAlex Deucher { 230fef9f91fSAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 231fef9f91fSAlex Deucher struct drm_device *dev = crtc->dev; 232fef9f91fSAlex Deucher struct radeon_device *rdev = dev->dev_private; 233fef9f91fSAlex Deucher int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating); 234fef9f91fSAlex Deucher ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args; 235fef9f91fSAlex Deucher 236fef9f91fSAlex Deucher memset(&args, 0, sizeof(args)); 237fef9f91fSAlex Deucher 238fef9f91fSAlex Deucher args.ucDispPipeId = radeon_crtc->crtc_id; 239fef9f91fSAlex Deucher args.ucEnable = state; 240fef9f91fSAlex Deucher 241fef9f91fSAlex Deucher atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 242fef9f91fSAlex Deucher } 243fef9f91fSAlex Deucher 244771fe6b9SJerome Glisse void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) 245771fe6b9SJerome Glisse { 246771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 247771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 248500b7587SAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 249771fe6b9SJerome Glisse 250771fe6b9SJerome Glisse switch (mode) { 251771fe6b9SJerome Glisse case DRM_MODE_DPMS_ON: 252d7311171SAlex Deucher radeon_crtc->enabled = true; 253d7311171SAlex Deucher /* adjust pm to dpms changes BEFORE enabling crtcs */ 254d7311171SAlex Deucher radeon_pm_compute_clocks(rdev); 25537b4390eSAlex Deucher atombios_enable_crtc(crtc, ATOM_ENABLE); 25679f17c64SAlex Deucher if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) 25737b4390eSAlex Deucher atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); 25837b4390eSAlex Deucher atombios_blank_crtc(crtc, ATOM_DISABLE); 259500b7587SAlex Deucher drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); 260500b7587SAlex Deucher radeon_crtc_load_lut(crtc); 261771fe6b9SJerome Glisse break; 262771fe6b9SJerome Glisse case DRM_MODE_DPMS_STANDBY: 263771fe6b9SJerome Glisse case DRM_MODE_DPMS_SUSPEND: 264771fe6b9SJerome Glisse case DRM_MODE_DPMS_OFF: 265500b7587SAlex Deucher drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); 266a93f344dSAlex Deucher if (radeon_crtc->enabled) 26737b4390eSAlex Deucher atombios_blank_crtc(crtc, ATOM_ENABLE); 26879f17c64SAlex Deucher if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) 26937b4390eSAlex Deucher atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); 27037b4390eSAlex Deucher atombios_enable_crtc(crtc, ATOM_DISABLE); 271a48b9b4eSAlex Deucher radeon_crtc->enabled = false; 272d7311171SAlex Deucher /* adjust pm to dpms changes AFTER disabling crtcs */ 273d7311171SAlex Deucher radeon_pm_compute_clocks(rdev); 274771fe6b9SJerome Glisse break; 275771fe6b9SJerome Glisse } 276771fe6b9SJerome Glisse } 277771fe6b9SJerome Glisse 278771fe6b9SJerome Glisse static void 279771fe6b9SJerome Glisse atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, 2805a9bcaccSAlex Deucher struct drm_display_mode *mode) 281771fe6b9SJerome Glisse { 2825a9bcaccSAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 283771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 284771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 2855a9bcaccSAlex Deucher SET_CRTC_USING_DTD_TIMING_PARAMETERS args; 286771fe6b9SJerome Glisse int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); 2875a9bcaccSAlex Deucher u16 misc = 0; 288771fe6b9SJerome Glisse 2895a9bcaccSAlex Deucher memset(&args, 0, sizeof(args)); 2905b1714d3SAlex Deucher args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); 2915a9bcaccSAlex Deucher args.usH_Blanking_Time = 2925b1714d3SAlex Deucher cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); 2935b1714d3SAlex Deucher args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); 2945a9bcaccSAlex Deucher args.usV_Blanking_Time = 2955b1714d3SAlex Deucher cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); 2965a9bcaccSAlex Deucher args.usH_SyncOffset = 2975b1714d3SAlex Deucher cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); 2985a9bcaccSAlex Deucher args.usH_SyncWidth = 2995a9bcaccSAlex Deucher cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 3005a9bcaccSAlex Deucher args.usV_SyncOffset = 3015b1714d3SAlex Deucher cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); 3025a9bcaccSAlex Deucher args.usV_SyncWidth = 3035a9bcaccSAlex Deucher cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 3045b1714d3SAlex Deucher args.ucH_Border = radeon_crtc->h_border; 3055b1714d3SAlex Deucher args.ucV_Border = radeon_crtc->v_border; 3065a9bcaccSAlex Deucher 3075a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_NVSYNC) 3085a9bcaccSAlex Deucher misc |= ATOM_VSYNC_POLARITY; 3095a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_NHSYNC) 3105a9bcaccSAlex Deucher misc |= ATOM_HSYNC_POLARITY; 3115a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_CSYNC) 3125a9bcaccSAlex Deucher misc |= ATOM_COMPOSITESYNC; 3135a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_INTERLACE) 3145a9bcaccSAlex Deucher misc |= ATOM_INTERLACE; 3155a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 3165a9bcaccSAlex Deucher misc |= ATOM_DOUBLE_CLOCK_MODE; 3175a9bcaccSAlex Deucher 3185a9bcaccSAlex Deucher args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 3195a9bcaccSAlex Deucher args.ucCRTC = radeon_crtc->crtc_id; 320771fe6b9SJerome Glisse 3215a9bcaccSAlex Deucher atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 322771fe6b9SJerome Glisse } 323771fe6b9SJerome Glisse 3245a9bcaccSAlex Deucher static void atombios_crtc_set_timing(struct drm_crtc *crtc, 3255a9bcaccSAlex Deucher struct drm_display_mode *mode) 326771fe6b9SJerome Glisse { 3275a9bcaccSAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 328771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 329771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 3305a9bcaccSAlex Deucher SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; 331771fe6b9SJerome Glisse int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); 3325a9bcaccSAlex Deucher u16 misc = 0; 333771fe6b9SJerome Glisse 3345a9bcaccSAlex Deucher memset(&args, 0, sizeof(args)); 3355a9bcaccSAlex Deucher args.usH_Total = cpu_to_le16(mode->crtc_htotal); 3365a9bcaccSAlex Deucher args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); 3375a9bcaccSAlex Deucher args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); 3385a9bcaccSAlex Deucher args.usH_SyncWidth = 3395a9bcaccSAlex Deucher cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 3405a9bcaccSAlex Deucher args.usV_Total = cpu_to_le16(mode->crtc_vtotal); 3415a9bcaccSAlex Deucher args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); 3425a9bcaccSAlex Deucher args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); 3435a9bcaccSAlex Deucher args.usV_SyncWidth = 3445a9bcaccSAlex Deucher cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 3455a9bcaccSAlex Deucher 34654bfe496SAlex Deucher args.ucOverscanRight = radeon_crtc->h_border; 34754bfe496SAlex Deucher args.ucOverscanLeft = radeon_crtc->h_border; 34854bfe496SAlex Deucher args.ucOverscanBottom = radeon_crtc->v_border; 34954bfe496SAlex Deucher args.ucOverscanTop = radeon_crtc->v_border; 35054bfe496SAlex Deucher 3515a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_NVSYNC) 3525a9bcaccSAlex Deucher misc |= ATOM_VSYNC_POLARITY; 3535a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_NHSYNC) 3545a9bcaccSAlex Deucher misc |= ATOM_HSYNC_POLARITY; 3555a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_CSYNC) 3565a9bcaccSAlex Deucher misc |= ATOM_COMPOSITESYNC; 3575a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_INTERLACE) 3585a9bcaccSAlex Deucher misc |= ATOM_INTERLACE; 3595a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 3605a9bcaccSAlex Deucher misc |= ATOM_DOUBLE_CLOCK_MODE; 3615a9bcaccSAlex Deucher 3625a9bcaccSAlex Deucher args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 3635a9bcaccSAlex Deucher args.ucCRTC = radeon_crtc->crtc_id; 364771fe6b9SJerome Glisse 3655a9bcaccSAlex Deucher atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 366771fe6b9SJerome Glisse } 367771fe6b9SJerome Glisse 3683fa47d9eSAlex Deucher static void atombios_disable_ss(struct radeon_device *rdev, int pll_id) 369b792210eSAlex Deucher { 370b792210eSAlex Deucher u32 ss_cntl; 371b792210eSAlex Deucher 372b792210eSAlex Deucher if (ASIC_IS_DCE4(rdev)) { 3733fa47d9eSAlex Deucher switch (pll_id) { 374b792210eSAlex Deucher case ATOM_PPLL1: 375b792210eSAlex Deucher ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); 376b792210eSAlex Deucher ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 377b792210eSAlex Deucher WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl); 378b792210eSAlex Deucher break; 379b792210eSAlex Deucher case ATOM_PPLL2: 380b792210eSAlex Deucher ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL); 381b792210eSAlex Deucher ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 382b792210eSAlex Deucher WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl); 383b792210eSAlex Deucher break; 384b792210eSAlex Deucher case ATOM_DCPLL: 385b792210eSAlex Deucher case ATOM_PPLL_INVALID: 386b792210eSAlex Deucher return; 387b792210eSAlex Deucher } 388b792210eSAlex Deucher } else if (ASIC_IS_AVIVO(rdev)) { 3893fa47d9eSAlex Deucher switch (pll_id) { 390b792210eSAlex Deucher case ATOM_PPLL1: 391b792210eSAlex Deucher ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); 392b792210eSAlex Deucher ss_cntl &= ~1; 393b792210eSAlex Deucher WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl); 394b792210eSAlex Deucher break; 395b792210eSAlex Deucher case ATOM_PPLL2: 396b792210eSAlex Deucher ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); 397b792210eSAlex Deucher ss_cntl &= ~1; 398b792210eSAlex Deucher WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl); 399b792210eSAlex Deucher break; 400b792210eSAlex Deucher case ATOM_DCPLL: 401b792210eSAlex Deucher case ATOM_PPLL_INVALID: 402b792210eSAlex Deucher return; 403b792210eSAlex Deucher } 404b792210eSAlex Deucher } 405b792210eSAlex Deucher } 406b792210eSAlex Deucher 407b792210eSAlex Deucher 40826b9fc3aSAlex Deucher union atom_enable_ss { 409ba032a58SAlex Deucher ENABLE_LVDS_SS_PARAMETERS lvds_ss; 410ba032a58SAlex Deucher ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2; 41126b9fc3aSAlex Deucher ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; 412ba032a58SAlex Deucher ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2; 413a572eaa3SAlex Deucher ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; 41426b9fc3aSAlex Deucher }; 41526b9fc3aSAlex Deucher 4163fa47d9eSAlex Deucher static void atombios_crtc_program_ss(struct radeon_device *rdev, 417ba032a58SAlex Deucher int enable, 418ba032a58SAlex Deucher int pll_id, 4195efcc76cSJerome Glisse int crtc_id, 420ba032a58SAlex Deucher struct radeon_atom_ss *ss) 421ebbe1cb9SAlex Deucher { 4225efcc76cSJerome Glisse unsigned i; 423ebbe1cb9SAlex Deucher int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); 42426b9fc3aSAlex Deucher union atom_enable_ss args; 425ebbe1cb9SAlex Deucher 4265efcc76cSJerome Glisse if (!enable) { 42753176706SAlex Deucher for (i = 0; i < rdev->num_crtc; i++) { 4285efcc76cSJerome Glisse if (rdev->mode_info.crtcs[i] && 4295efcc76cSJerome Glisse rdev->mode_info.crtcs[i]->enabled && 4305efcc76cSJerome Glisse i != crtc_id && 4315efcc76cSJerome Glisse pll_id == rdev->mode_info.crtcs[i]->pll_id) { 4325efcc76cSJerome Glisse /* one other crtc is using this pll don't turn 4335efcc76cSJerome Glisse * off spread spectrum as it might turn off 4345efcc76cSJerome Glisse * display on active crtc 4355efcc76cSJerome Glisse */ 4365efcc76cSJerome Glisse return; 4375efcc76cSJerome Glisse } 4385efcc76cSJerome Glisse } 4395efcc76cSJerome Glisse } 4405efcc76cSJerome Glisse 441ebbe1cb9SAlex Deucher memset(&args, 0, sizeof(args)); 442ba032a58SAlex Deucher 443a572eaa3SAlex Deucher if (ASIC_IS_DCE5(rdev)) { 4444589433cSCédric Cano args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); 4458e8e523dSAlex Deucher args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 446a572eaa3SAlex Deucher switch (pll_id) { 447a572eaa3SAlex Deucher case ATOM_PPLL1: 448a572eaa3SAlex Deucher args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; 449a572eaa3SAlex Deucher break; 450a572eaa3SAlex Deucher case ATOM_PPLL2: 451a572eaa3SAlex Deucher args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; 452a572eaa3SAlex Deucher break; 453a572eaa3SAlex Deucher case ATOM_DCPLL: 454a572eaa3SAlex Deucher args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; 455a572eaa3SAlex Deucher break; 456a572eaa3SAlex Deucher case ATOM_PPLL_INVALID: 457a572eaa3SAlex Deucher return; 458a572eaa3SAlex Deucher } 459f312f093SAlex Deucher args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 460f312f093SAlex Deucher args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); 461d0ae3e89SAlex Deucher args.v3.ucEnable = enable; 4620671bdd7SAlex Deucher if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE61(rdev)) 4638e8e523dSAlex Deucher args.v3.ucEnable = ATOM_DISABLE; 464a572eaa3SAlex Deucher } else if (ASIC_IS_DCE4(rdev)) { 465ba032a58SAlex Deucher args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 4668e8e523dSAlex Deucher args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 467ba032a58SAlex Deucher switch (pll_id) { 468ba032a58SAlex Deucher case ATOM_PPLL1: 469ba032a58SAlex Deucher args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL; 470ba032a58SAlex Deucher break; 471ba032a58SAlex Deucher case ATOM_PPLL2: 472ba032a58SAlex Deucher args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL; 473ba032a58SAlex Deucher break; 474ba032a58SAlex Deucher case ATOM_DCPLL: 475ba032a58SAlex Deucher args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL; 476ba032a58SAlex Deucher break; 477ba032a58SAlex Deucher case ATOM_PPLL_INVALID: 478ba032a58SAlex Deucher return; 479ba032a58SAlex Deucher } 480f312f093SAlex Deucher args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 481f312f093SAlex Deucher args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); 482ba032a58SAlex Deucher args.v2.ucEnable = enable; 48309cc6506SAlex Deucher if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev)) 4848e8e523dSAlex Deucher args.v2.ucEnable = ATOM_DISABLE; 485ba032a58SAlex Deucher } else if (ASIC_IS_DCE3(rdev)) { 486ba032a58SAlex Deucher args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 4878e8e523dSAlex Deucher args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 488ba032a58SAlex Deucher args.v1.ucSpreadSpectrumStep = ss->step; 489ba032a58SAlex Deucher args.v1.ucSpreadSpectrumDelay = ss->delay; 490ba032a58SAlex Deucher args.v1.ucSpreadSpectrumRange = ss->range; 491ba032a58SAlex Deucher args.v1.ucPpll = pll_id; 492ba032a58SAlex Deucher args.v1.ucEnable = enable; 493ba032a58SAlex Deucher } else if (ASIC_IS_AVIVO(rdev)) { 4948e8e523dSAlex Deucher if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || 4958e8e523dSAlex Deucher (ss->type & ATOM_EXTERNAL_SS_MASK)) { 4963fa47d9eSAlex Deucher atombios_disable_ss(rdev, pll_id); 497ba032a58SAlex Deucher return; 498ba032a58SAlex Deucher } 499ba032a58SAlex Deucher args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 5008e8e523dSAlex Deucher args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 501ba032a58SAlex Deucher args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; 502ba032a58SAlex Deucher args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; 503ba032a58SAlex Deucher args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; 504ba032a58SAlex Deucher args.lvds_ss_2.ucEnable = enable; 505ebbe1cb9SAlex Deucher } else { 5068e8e523dSAlex Deucher if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || 5078e8e523dSAlex Deucher (ss->type & ATOM_EXTERNAL_SS_MASK)) { 5083fa47d9eSAlex Deucher atombios_disable_ss(rdev, pll_id); 509ba032a58SAlex Deucher return; 510ba032a58SAlex Deucher } 511ba032a58SAlex Deucher args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 5128e8e523dSAlex Deucher args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 513ba032a58SAlex Deucher args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; 514ba032a58SAlex Deucher args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; 515ba032a58SAlex Deucher args.lvds_ss.ucEnable = enable; 516ebbe1cb9SAlex Deucher } 51726b9fc3aSAlex Deucher atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 518ebbe1cb9SAlex Deucher } 519ebbe1cb9SAlex Deucher 5204eaeca33SAlex Deucher union adjust_pixel_clock { 5214eaeca33SAlex Deucher ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; 522bcc1c2a1SAlex Deucher ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; 5234eaeca33SAlex Deucher }; 5244eaeca33SAlex Deucher 5254eaeca33SAlex Deucher static u32 atombios_adjust_pll(struct drm_crtc *crtc, 52619eca43eSAlex Deucher struct drm_display_mode *mode) 527771fe6b9SJerome Glisse { 52819eca43eSAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 529771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 530771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 5315df3196bSAlex Deucher struct drm_encoder *encoder = radeon_crtc->encoder; 5325df3196bSAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 5335df3196bSAlex Deucher struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 5344eaeca33SAlex Deucher u32 adjusted_clock = mode->clock; 5355df3196bSAlex Deucher int encoder_mode = atombios_get_encoder_mode(encoder); 536fbee67a6SAlex Deucher u32 dp_clock = mode->clock; 5375df3196bSAlex Deucher int bpc = radeon_get_monitor_bpc(connector); 5385df3196bSAlex Deucher bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); 539fc10332bSAlex Deucher 5404eaeca33SAlex Deucher /* reset the pll flags */ 54119eca43eSAlex Deucher radeon_crtc->pll_flags = 0; 542771fe6b9SJerome Glisse 543771fe6b9SJerome Glisse if (ASIC_IS_AVIVO(rdev)) { 544eb1300bcSAlex Deucher if ((rdev->family == CHIP_RS600) || 545eb1300bcSAlex Deucher (rdev->family == CHIP_RS690) || 546eb1300bcSAlex Deucher (rdev->family == CHIP_RS740)) 54719eca43eSAlex Deucher radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ 548eb1300bcSAlex Deucher RADEON_PLL_PREFER_CLOSEST_LOWER); 5495480f727SDave Airlie 5505480f727SDave Airlie if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ 55119eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 5525480f727SDave Airlie else 55319eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 5549bb09fa1SAlex Deucher 5555785e53fSAlex Deucher if (rdev->family < CHIP_RV770) 55619eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; 55737d4174dSAlex Deucher /* use frac fb div on APUs */ 558c7d2f227SAlex Deucher if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev)) 55919eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 56041167828SAlex Deucher /* use frac fb div on RS780/RS880 */ 56141167828SAlex Deucher if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) 56241167828SAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 563a02dc74bSAlex Deucher if (ASIC_IS_DCE32(rdev) && mode->clock > 165000) 564a02dc74bSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 5655480f727SDave Airlie } else { 56619eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_LEGACY; 567771fe6b9SJerome Glisse 5685480f727SDave Airlie if (mode->clock > 200000) /* range limits??? */ 56919eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 5705480f727SDave Airlie else 57119eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 5725480f727SDave Airlie } 5735480f727SDave Airlie 574eac4dff6SAlex Deucher if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || 5751d33e1fcSAlex Deucher (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { 576fbee67a6SAlex Deucher if (connector) { 577fbee67a6SAlex Deucher struct radeon_connector *radeon_connector = to_radeon_connector(connector); 578fbee67a6SAlex Deucher struct radeon_connector_atom_dig *dig_connector = 579fbee67a6SAlex Deucher radeon_connector->con_priv; 580fbee67a6SAlex Deucher 581fbee67a6SAlex Deucher dp_clock = dig_connector->dp_clock; 582fbee67a6SAlex Deucher } 583fbee67a6SAlex Deucher } 5845b40ddf8SAlex Deucher 585ba032a58SAlex Deucher /* use recommended ref_div for ss */ 586ba032a58SAlex Deucher if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 58719eca43eSAlex Deucher if (radeon_crtc->ss_enabled) { 58819eca43eSAlex Deucher if (radeon_crtc->ss.refdiv) { 58919eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 59019eca43eSAlex Deucher radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; 5915b40ddf8SAlex Deucher if (ASIC_IS_AVIVO(rdev)) 59219eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 593ba032a58SAlex Deucher } 594ba032a58SAlex Deucher } 595ba032a58SAlex Deucher } 5965b40ddf8SAlex Deucher 5974eaeca33SAlex Deucher if (ASIC_IS_AVIVO(rdev)) { 5984eaeca33SAlex Deucher /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ 5994eaeca33SAlex Deucher if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) 6004eaeca33SAlex Deucher adjusted_clock = mode->clock * 2; 60148dfaaebSAlex Deucher if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 60219eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; 603619efb10SAlex Deucher if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 60419eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD; 6054eaeca33SAlex Deucher } else { 6064eaeca33SAlex Deucher if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 60719eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; 6084eaeca33SAlex Deucher if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) 60919eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 610771fe6b9SJerome Glisse } 611771fe6b9SJerome Glisse 6122606c886SAlex Deucher /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock 6132606c886SAlex Deucher * accordingly based on the encoder/transmitter to work around 6142606c886SAlex Deucher * special hw requirements. 6152606c886SAlex Deucher */ 6162606c886SAlex Deucher if (ASIC_IS_DCE3(rdev)) { 6174eaeca33SAlex Deucher union adjust_pixel_clock args; 6184eaeca33SAlex Deucher u8 frev, crev; 6194eaeca33SAlex Deucher int index; 6202606c886SAlex Deucher 6212606c886SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); 622a084e6eeSAlex Deucher if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 623a084e6eeSAlex Deucher &crev)) 624a084e6eeSAlex Deucher return adjusted_clock; 6254eaeca33SAlex Deucher 6264eaeca33SAlex Deucher memset(&args, 0, sizeof(args)); 6274eaeca33SAlex Deucher 6284eaeca33SAlex Deucher switch (frev) { 6294eaeca33SAlex Deucher case 1: 6304eaeca33SAlex Deucher switch (crev) { 6314eaeca33SAlex Deucher case 1: 6324eaeca33SAlex Deucher case 2: 6334eaeca33SAlex Deucher args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); 6344eaeca33SAlex Deucher args.v1.ucTransmitterID = radeon_encoder->encoder_id; 635bcc1c2a1SAlex Deucher args.v1.ucEncodeMode = encoder_mode; 63619eca43eSAlex Deucher if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) 637ba032a58SAlex Deucher args.v1.ucConfig |= 638ba032a58SAlex Deucher ADJUST_DISPLAY_CONFIG_SS_ENABLE; 6394eaeca33SAlex Deucher 6402606c886SAlex Deucher atom_execute_table(rdev->mode_info.atom_context, 6414eaeca33SAlex Deucher index, (uint32_t *)&args); 6424eaeca33SAlex Deucher adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; 6434eaeca33SAlex Deucher break; 644bcc1c2a1SAlex Deucher case 3: 645bcc1c2a1SAlex Deucher args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10); 646bcc1c2a1SAlex Deucher args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; 647bcc1c2a1SAlex Deucher args.v3.sInput.ucEncodeMode = encoder_mode; 648bcc1c2a1SAlex Deucher args.v3.sInput.ucDispPllConfig = 0; 64919eca43eSAlex Deucher if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) 650ba032a58SAlex Deucher args.v3.sInput.ucDispPllConfig |= 651ba032a58SAlex Deucher DISPPLL_CONFIG_SS_ENABLE; 652996d5c59SAlex Deucher if (ENCODER_MODE_IS_DP(encoder_mode)) { 653bcc1c2a1SAlex Deucher args.v3.sInput.ucDispPllConfig |= 654bcc1c2a1SAlex Deucher DISPPLL_CONFIG_COHERENT_MODE; 655fbee67a6SAlex Deucher /* 16200 or 27000 */ 656fbee67a6SAlex Deucher args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); 657b4f15f80SAlex Deucher } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 658b4f15f80SAlex Deucher struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 659b4f15f80SAlex Deucher if (encoder_mode == ATOM_ENCODER_MODE_HDMI) 660fbee67a6SAlex Deucher /* deep color support */ 661fbee67a6SAlex Deucher args.v3.sInput.usPixelClock = 662fbee67a6SAlex Deucher cpu_to_le16((mode->clock * bpc / 8) / 10); 663bcc1c2a1SAlex Deucher if (dig->coherent_mode) 664bcc1c2a1SAlex Deucher args.v3.sInput.ucDispPllConfig |= 665bcc1c2a1SAlex Deucher DISPPLL_CONFIG_COHERENT_MODE; 6669aa59993SAlex Deucher if (is_duallink) 667bcc1c2a1SAlex Deucher args.v3.sInput.ucDispPllConfig |= 668bcc1c2a1SAlex Deucher DISPPLL_CONFIG_DUAL_LINK; 669bcc1c2a1SAlex Deucher } 6701d33e1fcSAlex Deucher if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 6711d33e1fcSAlex Deucher ENCODER_OBJECT_ID_NONE) 6721d33e1fcSAlex Deucher args.v3.sInput.ucExtTransmitterID = 6731d33e1fcSAlex Deucher radeon_encoder_get_dp_bridge_encoder_id(encoder); 6741d33e1fcSAlex Deucher else 675cc9f67a0SAlex Deucher args.v3.sInput.ucExtTransmitterID = 0; 676cc9f67a0SAlex Deucher 677bcc1c2a1SAlex Deucher atom_execute_table(rdev->mode_info.atom_context, 678bcc1c2a1SAlex Deucher index, (uint32_t *)&args); 679bcc1c2a1SAlex Deucher adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; 680bcc1c2a1SAlex Deucher if (args.v3.sOutput.ucRefDiv) { 68119eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 68219eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 68319eca43eSAlex Deucher radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; 684bcc1c2a1SAlex Deucher } 685bcc1c2a1SAlex Deucher if (args.v3.sOutput.ucPostDiv) { 68619eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 68719eca43eSAlex Deucher radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV; 68819eca43eSAlex Deucher radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; 689bcc1c2a1SAlex Deucher } 690bcc1c2a1SAlex Deucher break; 6914eaeca33SAlex Deucher default: 6924eaeca33SAlex Deucher DRM_ERROR("Unknown table version %d %d\n", frev, crev); 6934eaeca33SAlex Deucher return adjusted_clock; 694d56ef9c8SAlex Deucher } 6954eaeca33SAlex Deucher break; 6964eaeca33SAlex Deucher default: 6974eaeca33SAlex Deucher DRM_ERROR("Unknown table version %d %d\n", frev, crev); 6984eaeca33SAlex Deucher return adjusted_clock; 6994eaeca33SAlex Deucher } 7004eaeca33SAlex Deucher } 7014eaeca33SAlex Deucher return adjusted_clock; 7024eaeca33SAlex Deucher } 7034eaeca33SAlex Deucher 7044eaeca33SAlex Deucher union set_pixel_clock { 7054eaeca33SAlex Deucher SET_PIXEL_CLOCK_PS_ALLOCATION base; 7064eaeca33SAlex Deucher PIXEL_CLOCK_PARAMETERS v1; 7074eaeca33SAlex Deucher PIXEL_CLOCK_PARAMETERS_V2 v2; 7084eaeca33SAlex Deucher PIXEL_CLOCK_PARAMETERS_V3 v3; 709bcc1c2a1SAlex Deucher PIXEL_CLOCK_PARAMETERS_V5 v5; 710f82b3ddcSAlex Deucher PIXEL_CLOCK_PARAMETERS_V6 v6; 7114eaeca33SAlex Deucher }; 7124eaeca33SAlex Deucher 713f82b3ddcSAlex Deucher /* on DCE5, make sure the voltage is high enough to support the 714f82b3ddcSAlex Deucher * required disp clk. 715f82b3ddcSAlex Deucher */ 716f3f1f03eSAlex Deucher static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev, 717f82b3ddcSAlex Deucher u32 dispclk) 718bcc1c2a1SAlex Deucher { 719bcc1c2a1SAlex Deucher u8 frev, crev; 720bcc1c2a1SAlex Deucher int index; 721bcc1c2a1SAlex Deucher union set_pixel_clock args; 722bcc1c2a1SAlex Deucher 723bcc1c2a1SAlex Deucher memset(&args, 0, sizeof(args)); 724bcc1c2a1SAlex Deucher 725bcc1c2a1SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 726a084e6eeSAlex Deucher if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 727a084e6eeSAlex Deucher &crev)) 728a084e6eeSAlex Deucher return; 729bcc1c2a1SAlex Deucher 730bcc1c2a1SAlex Deucher switch (frev) { 731bcc1c2a1SAlex Deucher case 1: 732bcc1c2a1SAlex Deucher switch (crev) { 733bcc1c2a1SAlex Deucher case 5: 734bcc1c2a1SAlex Deucher /* if the default dcpll clock is specified, 735bcc1c2a1SAlex Deucher * SetPixelClock provides the dividers 736bcc1c2a1SAlex Deucher */ 737bcc1c2a1SAlex Deucher args.v5.ucCRTC = ATOM_CRTC_INVALID; 7384589433cSCédric Cano args.v5.usPixelClock = cpu_to_le16(dispclk); 739bcc1c2a1SAlex Deucher args.v5.ucPpll = ATOM_DCPLL; 740bcc1c2a1SAlex Deucher break; 741f82b3ddcSAlex Deucher case 6: 742f82b3ddcSAlex Deucher /* if the default dcpll clock is specified, 743f82b3ddcSAlex Deucher * SetPixelClock provides the dividers 744f82b3ddcSAlex Deucher */ 745265aa6c8SAlex Deucher args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); 7468542c12bSAlex Deucher if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev)) 747729b95efSAlex Deucher args.v6.ucPpll = ATOM_EXT_PLL1; 748729b95efSAlex Deucher else if (ASIC_IS_DCE6(rdev)) 749f3f1f03eSAlex Deucher args.v6.ucPpll = ATOM_PPLL0; 750f3f1f03eSAlex Deucher else 751f82b3ddcSAlex Deucher args.v6.ucPpll = ATOM_DCPLL; 752f82b3ddcSAlex Deucher break; 753bcc1c2a1SAlex Deucher default: 754bcc1c2a1SAlex Deucher DRM_ERROR("Unknown table version %d %d\n", frev, crev); 755bcc1c2a1SAlex Deucher return; 756bcc1c2a1SAlex Deucher } 757bcc1c2a1SAlex Deucher break; 758bcc1c2a1SAlex Deucher default: 759bcc1c2a1SAlex Deucher DRM_ERROR("Unknown table version %d %d\n", frev, crev); 760bcc1c2a1SAlex Deucher return; 761bcc1c2a1SAlex Deucher } 762bcc1c2a1SAlex Deucher atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 763bcc1c2a1SAlex Deucher } 764bcc1c2a1SAlex Deucher 76537f9003bSAlex Deucher static void atombios_crtc_program_pll(struct drm_crtc *crtc, 766f1bece7fSBenjamin Herrenschmidt u32 crtc_id, 76737f9003bSAlex Deucher int pll_id, 76837f9003bSAlex Deucher u32 encoder_mode, 76937f9003bSAlex Deucher u32 encoder_id, 77037f9003bSAlex Deucher u32 clock, 77137f9003bSAlex Deucher u32 ref_div, 77237f9003bSAlex Deucher u32 fb_div, 77337f9003bSAlex Deucher u32 frac_fb_div, 774df271becSAlex Deucher u32 post_div, 7758e8e523dSAlex Deucher int bpc, 7768e8e523dSAlex Deucher bool ss_enabled, 7778e8e523dSAlex Deucher struct radeon_atom_ss *ss) 77837f9003bSAlex Deucher { 77937f9003bSAlex Deucher struct drm_device *dev = crtc->dev; 78037f9003bSAlex Deucher struct radeon_device *rdev = dev->dev_private; 78137f9003bSAlex Deucher u8 frev, crev; 78237f9003bSAlex Deucher int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 78337f9003bSAlex Deucher union set_pixel_clock args; 78437f9003bSAlex Deucher 78537f9003bSAlex Deucher memset(&args, 0, sizeof(args)); 78637f9003bSAlex Deucher 78737f9003bSAlex Deucher if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 78837f9003bSAlex Deucher &crev)) 78937f9003bSAlex Deucher return; 79037f9003bSAlex Deucher 79137f9003bSAlex Deucher switch (frev) { 79237f9003bSAlex Deucher case 1: 79337f9003bSAlex Deucher switch (crev) { 79437f9003bSAlex Deucher case 1: 79537f9003bSAlex Deucher if (clock == ATOM_DISABLE) 79637f9003bSAlex Deucher return; 79737f9003bSAlex Deucher args.v1.usPixelClock = cpu_to_le16(clock / 10); 79837f9003bSAlex Deucher args.v1.usRefDiv = cpu_to_le16(ref_div); 79937f9003bSAlex Deucher args.v1.usFbDiv = cpu_to_le16(fb_div); 80037f9003bSAlex Deucher args.v1.ucFracFbDiv = frac_fb_div; 80137f9003bSAlex Deucher args.v1.ucPostDiv = post_div; 80237f9003bSAlex Deucher args.v1.ucPpll = pll_id; 80337f9003bSAlex Deucher args.v1.ucCRTC = crtc_id; 80437f9003bSAlex Deucher args.v1.ucRefDivSrc = 1; 80537f9003bSAlex Deucher break; 80637f9003bSAlex Deucher case 2: 80737f9003bSAlex Deucher args.v2.usPixelClock = cpu_to_le16(clock / 10); 80837f9003bSAlex Deucher args.v2.usRefDiv = cpu_to_le16(ref_div); 80937f9003bSAlex Deucher args.v2.usFbDiv = cpu_to_le16(fb_div); 81037f9003bSAlex Deucher args.v2.ucFracFbDiv = frac_fb_div; 81137f9003bSAlex Deucher args.v2.ucPostDiv = post_div; 81237f9003bSAlex Deucher args.v2.ucPpll = pll_id; 81337f9003bSAlex Deucher args.v2.ucCRTC = crtc_id; 81437f9003bSAlex Deucher args.v2.ucRefDivSrc = 1; 81537f9003bSAlex Deucher break; 81637f9003bSAlex Deucher case 3: 81737f9003bSAlex Deucher args.v3.usPixelClock = cpu_to_le16(clock / 10); 81837f9003bSAlex Deucher args.v3.usRefDiv = cpu_to_le16(ref_div); 81937f9003bSAlex Deucher args.v3.usFbDiv = cpu_to_le16(fb_div); 82037f9003bSAlex Deucher args.v3.ucFracFbDiv = frac_fb_div; 82137f9003bSAlex Deucher args.v3.ucPostDiv = post_div; 82237f9003bSAlex Deucher args.v3.ucPpll = pll_id; 823e729586eSAlex Deucher if (crtc_id == ATOM_CRTC2) 824e729586eSAlex Deucher args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2; 825e729586eSAlex Deucher else 826e729586eSAlex Deucher args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1; 8276f15c506SAlex Deucher if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 8286f15c506SAlex Deucher args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; 82937f9003bSAlex Deucher args.v3.ucTransmitterId = encoder_id; 83037f9003bSAlex Deucher args.v3.ucEncoderMode = encoder_mode; 83137f9003bSAlex Deucher break; 83237f9003bSAlex Deucher case 5: 83337f9003bSAlex Deucher args.v5.ucCRTC = crtc_id; 83437f9003bSAlex Deucher args.v5.usPixelClock = cpu_to_le16(clock / 10); 83537f9003bSAlex Deucher args.v5.ucRefDiv = ref_div; 83637f9003bSAlex Deucher args.v5.usFbDiv = cpu_to_le16(fb_div); 83737f9003bSAlex Deucher args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 83837f9003bSAlex Deucher args.v5.ucPostDiv = post_div; 83937f9003bSAlex Deucher args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ 8408e8e523dSAlex Deucher if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 8418e8e523dSAlex Deucher args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; 842df271becSAlex Deucher switch (bpc) { 843df271becSAlex Deucher case 8: 844df271becSAlex Deucher default: 845df271becSAlex Deucher args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; 846df271becSAlex Deucher break; 847df271becSAlex Deucher case 10: 848df271becSAlex Deucher args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; 849df271becSAlex Deucher break; 850df271becSAlex Deucher } 85137f9003bSAlex Deucher args.v5.ucTransmitterID = encoder_id; 85237f9003bSAlex Deucher args.v5.ucEncoderMode = encoder_mode; 85337f9003bSAlex Deucher args.v5.ucPpll = pll_id; 85437f9003bSAlex Deucher break; 855f82b3ddcSAlex Deucher case 6: 856f1bece7fSBenjamin Herrenschmidt args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10); 857f82b3ddcSAlex Deucher args.v6.ucRefDiv = ref_div; 858f82b3ddcSAlex Deucher args.v6.usFbDiv = cpu_to_le16(fb_div); 859f82b3ddcSAlex Deucher args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 860f82b3ddcSAlex Deucher args.v6.ucPostDiv = post_div; 861f82b3ddcSAlex Deucher args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ 8628e8e523dSAlex Deucher if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 8638e8e523dSAlex Deucher args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; 864df271becSAlex Deucher switch (bpc) { 865df271becSAlex Deucher case 8: 866df271becSAlex Deucher default: 867df271becSAlex Deucher args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; 868df271becSAlex Deucher break; 869df271becSAlex Deucher case 10: 870df271becSAlex Deucher args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP; 871df271becSAlex Deucher break; 872df271becSAlex Deucher case 12: 873df271becSAlex Deucher args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP; 874df271becSAlex Deucher break; 875df271becSAlex Deucher case 16: 876df271becSAlex Deucher args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; 877df271becSAlex Deucher break; 878df271becSAlex Deucher } 879f82b3ddcSAlex Deucher args.v6.ucTransmitterID = encoder_id; 880f82b3ddcSAlex Deucher args.v6.ucEncoderMode = encoder_mode; 881f82b3ddcSAlex Deucher args.v6.ucPpll = pll_id; 882f82b3ddcSAlex Deucher break; 88337f9003bSAlex Deucher default: 88437f9003bSAlex Deucher DRM_ERROR("Unknown table version %d %d\n", frev, crev); 88537f9003bSAlex Deucher return; 88637f9003bSAlex Deucher } 88737f9003bSAlex Deucher break; 88837f9003bSAlex Deucher default: 88937f9003bSAlex Deucher DRM_ERROR("Unknown table version %d %d\n", frev, crev); 89037f9003bSAlex Deucher return; 89137f9003bSAlex Deucher } 89237f9003bSAlex Deucher 89337f9003bSAlex Deucher atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 89437f9003bSAlex Deucher } 89537f9003bSAlex Deucher 89619eca43eSAlex Deucher static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 89719eca43eSAlex Deucher { 89819eca43eSAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 89919eca43eSAlex Deucher struct drm_device *dev = crtc->dev; 90019eca43eSAlex Deucher struct radeon_device *rdev = dev->dev_private; 9015df3196bSAlex Deucher struct radeon_encoder *radeon_encoder = 9025df3196bSAlex Deucher to_radeon_encoder(radeon_crtc->encoder); 9035df3196bSAlex Deucher int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); 90419eca43eSAlex Deucher 90519eca43eSAlex Deucher radeon_crtc->bpc = 8; 90619eca43eSAlex Deucher radeon_crtc->ss_enabled = false; 90719eca43eSAlex Deucher 90819eca43eSAlex Deucher if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || 9095df3196bSAlex Deucher (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { 91019eca43eSAlex Deucher struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 91119eca43eSAlex Deucher struct drm_connector *connector = 9125df3196bSAlex Deucher radeon_get_connector_for_encoder(radeon_crtc->encoder); 91319eca43eSAlex Deucher struct radeon_connector *radeon_connector = 91419eca43eSAlex Deucher to_radeon_connector(connector); 91519eca43eSAlex Deucher struct radeon_connector_atom_dig *dig_connector = 91619eca43eSAlex Deucher radeon_connector->con_priv; 91719eca43eSAlex Deucher int dp_clock; 91819eca43eSAlex Deucher radeon_crtc->bpc = radeon_get_monitor_bpc(connector); 91919eca43eSAlex Deucher 92019eca43eSAlex Deucher switch (encoder_mode) { 92119eca43eSAlex Deucher case ATOM_ENCODER_MODE_DP_MST: 92219eca43eSAlex Deucher case ATOM_ENCODER_MODE_DP: 92319eca43eSAlex Deucher /* DP/eDP */ 92419eca43eSAlex Deucher dp_clock = dig_connector->dp_clock / 10; 92519eca43eSAlex Deucher if (ASIC_IS_DCE4(rdev)) 92619eca43eSAlex Deucher radeon_crtc->ss_enabled = 92719eca43eSAlex Deucher radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, 92819eca43eSAlex Deucher ASIC_INTERNAL_SS_ON_DP, 92919eca43eSAlex Deucher dp_clock); 93019eca43eSAlex Deucher else { 93119eca43eSAlex Deucher if (dp_clock == 16200) { 93219eca43eSAlex Deucher radeon_crtc->ss_enabled = 93319eca43eSAlex Deucher radeon_atombios_get_ppll_ss_info(rdev, 93419eca43eSAlex Deucher &radeon_crtc->ss, 93519eca43eSAlex Deucher ATOM_DP_SS_ID2); 93619eca43eSAlex Deucher if (!radeon_crtc->ss_enabled) 93719eca43eSAlex Deucher radeon_crtc->ss_enabled = 93819eca43eSAlex Deucher radeon_atombios_get_ppll_ss_info(rdev, 93919eca43eSAlex Deucher &radeon_crtc->ss, 94019eca43eSAlex Deucher ATOM_DP_SS_ID1); 94119eca43eSAlex Deucher } else 94219eca43eSAlex Deucher radeon_crtc->ss_enabled = 94319eca43eSAlex Deucher radeon_atombios_get_ppll_ss_info(rdev, 94419eca43eSAlex Deucher &radeon_crtc->ss, 94519eca43eSAlex Deucher ATOM_DP_SS_ID1); 94619eca43eSAlex Deucher } 94719eca43eSAlex Deucher break; 94819eca43eSAlex Deucher case ATOM_ENCODER_MODE_LVDS: 94919eca43eSAlex Deucher if (ASIC_IS_DCE4(rdev)) 95019eca43eSAlex Deucher radeon_crtc->ss_enabled = 95119eca43eSAlex Deucher radeon_atombios_get_asic_ss_info(rdev, 95219eca43eSAlex Deucher &radeon_crtc->ss, 95319eca43eSAlex Deucher dig->lcd_ss_id, 95419eca43eSAlex Deucher mode->clock / 10); 95519eca43eSAlex Deucher else 95619eca43eSAlex Deucher radeon_crtc->ss_enabled = 95719eca43eSAlex Deucher radeon_atombios_get_ppll_ss_info(rdev, 95819eca43eSAlex Deucher &radeon_crtc->ss, 95919eca43eSAlex Deucher dig->lcd_ss_id); 96019eca43eSAlex Deucher break; 96119eca43eSAlex Deucher case ATOM_ENCODER_MODE_DVI: 96219eca43eSAlex Deucher if (ASIC_IS_DCE4(rdev)) 96319eca43eSAlex Deucher radeon_crtc->ss_enabled = 96419eca43eSAlex Deucher radeon_atombios_get_asic_ss_info(rdev, 96519eca43eSAlex Deucher &radeon_crtc->ss, 96619eca43eSAlex Deucher ASIC_INTERNAL_SS_ON_TMDS, 96719eca43eSAlex Deucher mode->clock / 10); 96819eca43eSAlex Deucher break; 96919eca43eSAlex Deucher case ATOM_ENCODER_MODE_HDMI: 97019eca43eSAlex Deucher if (ASIC_IS_DCE4(rdev)) 97119eca43eSAlex Deucher radeon_crtc->ss_enabled = 97219eca43eSAlex Deucher radeon_atombios_get_asic_ss_info(rdev, 97319eca43eSAlex Deucher &radeon_crtc->ss, 97419eca43eSAlex Deucher ASIC_INTERNAL_SS_ON_HDMI, 97519eca43eSAlex Deucher mode->clock / 10); 97619eca43eSAlex Deucher break; 97719eca43eSAlex Deucher default: 97819eca43eSAlex Deucher break; 97919eca43eSAlex Deucher } 98019eca43eSAlex Deucher } 98119eca43eSAlex Deucher 98219eca43eSAlex Deucher /* adjust pixel clock as needed */ 98319eca43eSAlex Deucher radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode); 98419eca43eSAlex Deucher 98519eca43eSAlex Deucher return true; 98619eca43eSAlex Deucher } 98719eca43eSAlex Deucher 988bcc1c2a1SAlex Deucher static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 9894eaeca33SAlex Deucher { 9904eaeca33SAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 9914eaeca33SAlex Deucher struct drm_device *dev = crtc->dev; 9924eaeca33SAlex Deucher struct radeon_device *rdev = dev->dev_private; 9935df3196bSAlex Deucher struct radeon_encoder *radeon_encoder = 9945df3196bSAlex Deucher to_radeon_encoder(radeon_crtc->encoder); 9954eaeca33SAlex Deucher u32 pll_clock = mode->clock; 9964eaeca33SAlex Deucher u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; 9974eaeca33SAlex Deucher struct radeon_pll *pll; 9985df3196bSAlex Deucher int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); 9994eaeca33SAlex Deucher 1000bcc1c2a1SAlex Deucher switch (radeon_crtc->pll_id) { 1001bcc1c2a1SAlex Deucher case ATOM_PPLL1: 10024eaeca33SAlex Deucher pll = &rdev->clock.p1pll; 1003bcc1c2a1SAlex Deucher break; 1004bcc1c2a1SAlex Deucher case ATOM_PPLL2: 10054eaeca33SAlex Deucher pll = &rdev->clock.p2pll; 1006bcc1c2a1SAlex Deucher break; 1007bcc1c2a1SAlex Deucher case ATOM_DCPLL: 1008bcc1c2a1SAlex Deucher case ATOM_PPLL_INVALID: 1009921d98b5SStefan Richter default: 1010bcc1c2a1SAlex Deucher pll = &rdev->clock.dcpll; 1011bcc1c2a1SAlex Deucher break; 1012bcc1c2a1SAlex Deucher } 10134eaeca33SAlex Deucher 101419eca43eSAlex Deucher /* update pll params */ 101519eca43eSAlex Deucher pll->flags = radeon_crtc->pll_flags; 101619eca43eSAlex Deucher pll->reference_div = radeon_crtc->pll_reference_div; 101719eca43eSAlex Deucher pll->post_div = radeon_crtc->pll_post_div; 10182606c886SAlex Deucher 101964146f8bSAlex Deucher if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 102064146f8bSAlex Deucher /* TV seems to prefer the legacy algo on some boards */ 102119eca43eSAlex Deucher radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, 102219eca43eSAlex Deucher &fb_div, &frac_fb_div, &ref_div, &post_div); 102364146f8bSAlex Deucher else if (ASIC_IS_AVIVO(rdev)) 102419eca43eSAlex Deucher radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, 102519eca43eSAlex Deucher &fb_div, &frac_fb_div, &ref_div, &post_div); 1026619efb10SAlex Deucher else 102719eca43eSAlex Deucher radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, 102819eca43eSAlex Deucher &fb_div, &frac_fb_div, &ref_div, &post_div); 1029771fe6b9SJerome Glisse 103019eca43eSAlex Deucher atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, 103119eca43eSAlex Deucher radeon_crtc->crtc_id, &radeon_crtc->ss); 1032ba032a58SAlex Deucher 103337f9003bSAlex Deucher atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 103437f9003bSAlex Deucher encoder_mode, radeon_encoder->encoder_id, mode->clock, 103519eca43eSAlex Deucher ref_div, fb_div, frac_fb_div, post_div, 103619eca43eSAlex Deucher radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss); 1037771fe6b9SJerome Glisse 103819eca43eSAlex Deucher if (radeon_crtc->ss_enabled) { 1039ba032a58SAlex Deucher /* calculate ss amount and step size */ 1040ba032a58SAlex Deucher if (ASIC_IS_DCE4(rdev)) { 1041ba032a58SAlex Deucher u32 step_size; 104219eca43eSAlex Deucher u32 amount = (((fb_div * 10) + frac_fb_div) * radeon_crtc->ss.percentage) / 10000; 104319eca43eSAlex Deucher radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; 104419eca43eSAlex Deucher radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & 1045ba032a58SAlex Deucher ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK; 104619eca43eSAlex Deucher if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) 104719eca43eSAlex Deucher step_size = (4 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) / 1048ba032a58SAlex Deucher (125 * 25 * pll->reference_freq / 100); 1049ba032a58SAlex Deucher else 105019eca43eSAlex Deucher step_size = (2 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) / 1051ba032a58SAlex Deucher (125 * 25 * pll->reference_freq / 100); 105219eca43eSAlex Deucher radeon_crtc->ss.step = step_size; 1053ba032a58SAlex Deucher } 1054ba032a58SAlex Deucher 105519eca43eSAlex Deucher atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, 105619eca43eSAlex Deucher radeon_crtc->crtc_id, &radeon_crtc->ss); 1057ba032a58SAlex Deucher } 1058771fe6b9SJerome Glisse } 1059771fe6b9SJerome Glisse 1060c9417bddSAlex Deucher static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 10614dd19b0dSChris Ball struct drm_framebuffer *fb, 10624dd19b0dSChris Ball int x, int y, int atomic) 1063bcc1c2a1SAlex Deucher { 1064bcc1c2a1SAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1065bcc1c2a1SAlex Deucher struct drm_device *dev = crtc->dev; 1066bcc1c2a1SAlex Deucher struct radeon_device *rdev = dev->dev_private; 1067bcc1c2a1SAlex Deucher struct radeon_framebuffer *radeon_fb; 10684dd19b0dSChris Ball struct drm_framebuffer *target_fb; 1069bcc1c2a1SAlex Deucher struct drm_gem_object *obj; 1070bcc1c2a1SAlex Deucher struct radeon_bo *rbo; 1071bcc1c2a1SAlex Deucher uint64_t fb_location; 1072bcc1c2a1SAlex Deucher uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1073285484e2SJerome Glisse unsigned bankw, bankh, mtaspect, tile_split; 1074fa6bee46SAlex Deucher u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); 1075adcfde51SAlex Deucher u32 tmp, viewport_w, viewport_h; 1076bcc1c2a1SAlex Deucher int r; 1077bcc1c2a1SAlex Deucher 1078bcc1c2a1SAlex Deucher /* no fb bound */ 10794dd19b0dSChris Ball if (!atomic && !crtc->fb) { 1080d9fdaafbSDave Airlie DRM_DEBUG_KMS("No FB bound\n"); 1081bcc1c2a1SAlex Deucher return 0; 1082bcc1c2a1SAlex Deucher } 1083bcc1c2a1SAlex Deucher 10844dd19b0dSChris Ball if (atomic) { 10854dd19b0dSChris Ball radeon_fb = to_radeon_framebuffer(fb); 10864dd19b0dSChris Ball target_fb = fb; 10874dd19b0dSChris Ball } 10884dd19b0dSChris Ball else { 1089bcc1c2a1SAlex Deucher radeon_fb = to_radeon_framebuffer(crtc->fb); 10904dd19b0dSChris Ball target_fb = crtc->fb; 10914dd19b0dSChris Ball } 1092bcc1c2a1SAlex Deucher 10934dd19b0dSChris Ball /* If atomic, assume fb object is pinned & idle & fenced and 10944dd19b0dSChris Ball * just update base pointers 10954dd19b0dSChris Ball */ 1096bcc1c2a1SAlex Deucher obj = radeon_fb->obj; 10977e4d15d9SDaniel Vetter rbo = gem_to_radeon_bo(obj); 1098bcc1c2a1SAlex Deucher r = radeon_bo_reserve(rbo, false); 1099bcc1c2a1SAlex Deucher if (unlikely(r != 0)) 1100bcc1c2a1SAlex Deucher return r; 11014dd19b0dSChris Ball 11024dd19b0dSChris Ball if (atomic) 11034dd19b0dSChris Ball fb_location = radeon_bo_gpu_offset(rbo); 11044dd19b0dSChris Ball else { 1105bcc1c2a1SAlex Deucher r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); 1106bcc1c2a1SAlex Deucher if (unlikely(r != 0)) { 1107bcc1c2a1SAlex Deucher radeon_bo_unreserve(rbo); 1108bcc1c2a1SAlex Deucher return -EINVAL; 1109bcc1c2a1SAlex Deucher } 11104dd19b0dSChris Ball } 11114dd19b0dSChris Ball 1112bcc1c2a1SAlex Deucher radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1113bcc1c2a1SAlex Deucher radeon_bo_unreserve(rbo); 1114bcc1c2a1SAlex Deucher 11154dd19b0dSChris Ball switch (target_fb->bits_per_pixel) { 1116bcc1c2a1SAlex Deucher case 8: 1117bcc1c2a1SAlex Deucher fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | 1118bcc1c2a1SAlex Deucher EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); 1119bcc1c2a1SAlex Deucher break; 1120bcc1c2a1SAlex Deucher case 15: 1121bcc1c2a1SAlex Deucher fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1122bcc1c2a1SAlex Deucher EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); 1123bcc1c2a1SAlex Deucher break; 1124bcc1c2a1SAlex Deucher case 16: 1125bcc1c2a1SAlex Deucher fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1126bcc1c2a1SAlex Deucher EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); 1127fa6bee46SAlex Deucher #ifdef __BIG_ENDIAN 1128fa6bee46SAlex Deucher fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1129fa6bee46SAlex Deucher #endif 1130bcc1c2a1SAlex Deucher break; 1131bcc1c2a1SAlex Deucher case 24: 1132bcc1c2a1SAlex Deucher case 32: 1133bcc1c2a1SAlex Deucher fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1134bcc1c2a1SAlex Deucher EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); 1135fa6bee46SAlex Deucher #ifdef __BIG_ENDIAN 1136fa6bee46SAlex Deucher fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1137fa6bee46SAlex Deucher #endif 1138bcc1c2a1SAlex Deucher break; 1139bcc1c2a1SAlex Deucher default: 1140bcc1c2a1SAlex Deucher DRM_ERROR("Unsupported screen depth %d\n", 11414dd19b0dSChris Ball target_fb->bits_per_pixel); 1142bcc1c2a1SAlex Deucher return -EINVAL; 1143bcc1c2a1SAlex Deucher } 1144bcc1c2a1SAlex Deucher 1145392e3722SAlex Deucher if (tiling_flags & RADEON_TILING_MACRO) { 11468da0e500SAlex Deucher if (rdev->family >= CHIP_BONAIRE) 11478da0e500SAlex Deucher tmp = rdev->config.cik.tile_config; 11488da0e500SAlex Deucher else if (rdev->family >= CHIP_TAHITI) 1149b7019b2fSAlex Deucher tmp = rdev->config.si.tile_config; 1150b7019b2fSAlex Deucher else if (rdev->family >= CHIP_CAYMAN) 1151392e3722SAlex Deucher tmp = rdev->config.cayman.tile_config; 1152392e3722SAlex Deucher else 1153392e3722SAlex Deucher tmp = rdev->config.evergreen.tile_config; 1154392e3722SAlex Deucher 1155392e3722SAlex Deucher switch ((tmp & 0xf0) >> 4) { 1156392e3722SAlex Deucher case 0: /* 4 banks */ 1157392e3722SAlex Deucher fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK); 1158392e3722SAlex Deucher break; 1159392e3722SAlex Deucher case 1: /* 8 banks */ 1160392e3722SAlex Deucher default: 1161392e3722SAlex Deucher fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK); 1162392e3722SAlex Deucher break; 1163392e3722SAlex Deucher case 2: /* 16 banks */ 1164392e3722SAlex Deucher fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK); 1165392e3722SAlex Deucher break; 1166392e3722SAlex Deucher } 1167392e3722SAlex Deucher 116897d66328SAlex Deucher fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); 1169285484e2SJerome Glisse 1170285484e2SJerome Glisse evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); 1171285484e2SJerome Glisse fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split); 1172285484e2SJerome Glisse fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); 1173285484e2SJerome Glisse fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh); 1174285484e2SJerome Glisse fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); 11758da0e500SAlex Deucher if (rdev->family >= CHIP_BONAIRE) { 11768da0e500SAlex Deucher /* XXX need to know more about the surface tiling mode */ 11778da0e500SAlex Deucher fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING); 11788da0e500SAlex Deucher } 1179392e3722SAlex Deucher } else if (tiling_flags & RADEON_TILING_MICRO) 118097d66328SAlex Deucher fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); 118197d66328SAlex Deucher 11828da0e500SAlex Deucher if (rdev->family >= CHIP_BONAIRE) { 11838da0e500SAlex Deucher u32 num_pipe_configs = rdev->config.cik.max_tile_pipes; 11848da0e500SAlex Deucher u32 num_rb = rdev->config.cik.max_backends_per_se; 11858da0e500SAlex Deucher if (num_pipe_configs > 8) 11868da0e500SAlex Deucher num_pipe_configs = 8; 11878da0e500SAlex Deucher if (num_pipe_configs == 8) 11888da0e500SAlex Deucher fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P8_32x32_16x16); 11898da0e500SAlex Deucher else if (num_pipe_configs == 4) { 11908da0e500SAlex Deucher if (num_rb == 4) 11918da0e500SAlex Deucher fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P4_16x16); 11928da0e500SAlex Deucher else if (num_rb < 4) 11938da0e500SAlex Deucher fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P4_8x16); 11948da0e500SAlex Deucher } else if (num_pipe_configs == 2) 11958da0e500SAlex Deucher fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P2); 11968da0e500SAlex Deucher } else if ((rdev->family == CHIP_TAHITI) || 1197b7019b2fSAlex Deucher (rdev->family == CHIP_PITCAIRN)) 1198b7019b2fSAlex Deucher fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16); 1199b7019b2fSAlex Deucher else if (rdev->family == CHIP_VERDE) 1200b7019b2fSAlex Deucher fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16); 1201b7019b2fSAlex Deucher 1202bcc1c2a1SAlex Deucher switch (radeon_crtc->crtc_id) { 1203bcc1c2a1SAlex Deucher case 0: 1204bcc1c2a1SAlex Deucher WREG32(AVIVO_D1VGA_CONTROL, 0); 1205bcc1c2a1SAlex Deucher break; 1206bcc1c2a1SAlex Deucher case 1: 1207bcc1c2a1SAlex Deucher WREG32(AVIVO_D2VGA_CONTROL, 0); 1208bcc1c2a1SAlex Deucher break; 1209bcc1c2a1SAlex Deucher case 2: 1210bcc1c2a1SAlex Deucher WREG32(EVERGREEN_D3VGA_CONTROL, 0); 1211bcc1c2a1SAlex Deucher break; 1212bcc1c2a1SAlex Deucher case 3: 1213bcc1c2a1SAlex Deucher WREG32(EVERGREEN_D4VGA_CONTROL, 0); 1214bcc1c2a1SAlex Deucher break; 1215bcc1c2a1SAlex Deucher case 4: 1216bcc1c2a1SAlex Deucher WREG32(EVERGREEN_D5VGA_CONTROL, 0); 1217bcc1c2a1SAlex Deucher break; 1218bcc1c2a1SAlex Deucher case 5: 1219bcc1c2a1SAlex Deucher WREG32(EVERGREEN_D6VGA_CONTROL, 0); 1220bcc1c2a1SAlex Deucher break; 1221bcc1c2a1SAlex Deucher default: 1222bcc1c2a1SAlex Deucher break; 1223bcc1c2a1SAlex Deucher } 1224bcc1c2a1SAlex Deucher 1225bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 1226bcc1c2a1SAlex Deucher upper_32_bits(fb_location)); 1227bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 1228bcc1c2a1SAlex Deucher upper_32_bits(fb_location)); 1229bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1230bcc1c2a1SAlex Deucher (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1231bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1232bcc1c2a1SAlex Deucher (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1233bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1234fa6bee46SAlex Deucher WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1235bcc1c2a1SAlex Deucher 1236bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1237bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1238bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); 1239bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); 12404dd19b0dSChris Ball WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); 12414dd19b0dSChris Ball WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); 1242bcc1c2a1SAlex Deucher 124301f2c773SVille Syrjälä fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 1244bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 1245bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1246bcc1c2a1SAlex Deucher 12478da0e500SAlex Deucher if (rdev->family >= CHIP_BONAIRE) 12488da0e500SAlex Deucher WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 12498da0e500SAlex Deucher target_fb->height); 12508da0e500SAlex Deucher else 1251bcc1c2a1SAlex Deucher WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 12521b619250SMichel Dänzer target_fb->height); 1253bcc1c2a1SAlex Deucher x &= ~3; 1254bcc1c2a1SAlex Deucher y &= ~1; 1255bcc1c2a1SAlex Deucher WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, 1256bcc1c2a1SAlex Deucher (x << 16) | y); 1257adcfde51SAlex Deucher viewport_w = crtc->mode.hdisplay; 1258adcfde51SAlex Deucher viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1259bcc1c2a1SAlex Deucher WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1260adcfde51SAlex Deucher (viewport_w << 16) | viewport_h); 1261bcc1c2a1SAlex Deucher 1262fb9674bdSAlex Deucher /* pageflip setup */ 1263fb9674bdSAlex Deucher /* make sure flip is at vb rather than hb */ 1264fb9674bdSAlex Deucher tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); 1265fb9674bdSAlex Deucher tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN; 1266fb9674bdSAlex Deucher WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); 1267fb9674bdSAlex Deucher 1268fb9674bdSAlex Deucher /* set pageflip to happen anywhere in vblank interval */ 1269fb9674bdSAlex Deucher WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); 1270fb9674bdSAlex Deucher 12714dd19b0dSChris Ball if (!atomic && fb && fb != crtc->fb) { 12724dd19b0dSChris Ball radeon_fb = to_radeon_framebuffer(fb); 12737e4d15d9SDaniel Vetter rbo = gem_to_radeon_bo(radeon_fb->obj); 1274bcc1c2a1SAlex Deucher r = radeon_bo_reserve(rbo, false); 1275bcc1c2a1SAlex Deucher if (unlikely(r != 0)) 1276bcc1c2a1SAlex Deucher return r; 1277bcc1c2a1SAlex Deucher radeon_bo_unpin(rbo); 1278bcc1c2a1SAlex Deucher radeon_bo_unreserve(rbo); 1279bcc1c2a1SAlex Deucher } 1280bcc1c2a1SAlex Deucher 1281bcc1c2a1SAlex Deucher /* Bytes per pixel may have changed */ 1282bcc1c2a1SAlex Deucher radeon_bandwidth_update(rdev); 1283bcc1c2a1SAlex Deucher 1284bcc1c2a1SAlex Deucher return 0; 1285bcc1c2a1SAlex Deucher } 1286bcc1c2a1SAlex Deucher 12874dd19b0dSChris Ball static int avivo_crtc_do_set_base(struct drm_crtc *crtc, 12884dd19b0dSChris Ball struct drm_framebuffer *fb, 12894dd19b0dSChris Ball int x, int y, int atomic) 1290771fe6b9SJerome Glisse { 1291771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1292771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 1293771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 1294771fe6b9SJerome Glisse struct radeon_framebuffer *radeon_fb; 1295771fe6b9SJerome Glisse struct drm_gem_object *obj; 12964c788679SJerome Glisse struct radeon_bo *rbo; 12974dd19b0dSChris Ball struct drm_framebuffer *target_fb; 1298771fe6b9SJerome Glisse uint64_t fb_location; 1299e024e110SDave Airlie uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1300fa6bee46SAlex Deucher u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; 1301adcfde51SAlex Deucher u32 tmp, viewport_w, viewport_h; 13024c788679SJerome Glisse int r; 1303771fe6b9SJerome Glisse 13042de3b484SJerome Glisse /* no fb bound */ 13054dd19b0dSChris Ball if (!atomic && !crtc->fb) { 1306d9fdaafbSDave Airlie DRM_DEBUG_KMS("No FB bound\n"); 13072de3b484SJerome Glisse return 0; 13082de3b484SJerome Glisse } 1309771fe6b9SJerome Glisse 13104dd19b0dSChris Ball if (atomic) { 13114dd19b0dSChris Ball radeon_fb = to_radeon_framebuffer(fb); 13124dd19b0dSChris Ball target_fb = fb; 13134dd19b0dSChris Ball } 13144dd19b0dSChris Ball else { 1315771fe6b9SJerome Glisse radeon_fb = to_radeon_framebuffer(crtc->fb); 13164dd19b0dSChris Ball target_fb = crtc->fb; 13174dd19b0dSChris Ball } 1318771fe6b9SJerome Glisse 1319771fe6b9SJerome Glisse obj = radeon_fb->obj; 13207e4d15d9SDaniel Vetter rbo = gem_to_radeon_bo(obj); 13214c788679SJerome Glisse r = radeon_bo_reserve(rbo, false); 13224c788679SJerome Glisse if (unlikely(r != 0)) 13234c788679SJerome Glisse return r; 13244dd19b0dSChris Ball 13254dd19b0dSChris Ball /* If atomic, assume fb object is pinned & idle & fenced and 13264dd19b0dSChris Ball * just update base pointers 13274dd19b0dSChris Ball */ 13284dd19b0dSChris Ball if (atomic) 13294dd19b0dSChris Ball fb_location = radeon_bo_gpu_offset(rbo); 13304dd19b0dSChris Ball else { 13314c788679SJerome Glisse r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); 13324c788679SJerome Glisse if (unlikely(r != 0)) { 13334c788679SJerome Glisse radeon_bo_unreserve(rbo); 1334771fe6b9SJerome Glisse return -EINVAL; 1335771fe6b9SJerome Glisse } 13364dd19b0dSChris Ball } 13374c788679SJerome Glisse radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 13384c788679SJerome Glisse radeon_bo_unreserve(rbo); 1339771fe6b9SJerome Glisse 13404dd19b0dSChris Ball switch (target_fb->bits_per_pixel) { 134141456df2SDave Airlie case 8: 134241456df2SDave Airlie fb_format = 134341456df2SDave Airlie AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | 134441456df2SDave Airlie AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; 134541456df2SDave Airlie break; 1346771fe6b9SJerome Glisse case 15: 1347771fe6b9SJerome Glisse fb_format = 1348771fe6b9SJerome Glisse AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1349771fe6b9SJerome Glisse AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; 1350771fe6b9SJerome Glisse break; 1351771fe6b9SJerome Glisse case 16: 1352771fe6b9SJerome Glisse fb_format = 1353771fe6b9SJerome Glisse AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1354771fe6b9SJerome Glisse AVIVO_D1GRPH_CONTROL_16BPP_RGB565; 1355fa6bee46SAlex Deucher #ifdef __BIG_ENDIAN 1356fa6bee46SAlex Deucher fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 1357fa6bee46SAlex Deucher #endif 1358771fe6b9SJerome Glisse break; 1359771fe6b9SJerome Glisse case 24: 1360771fe6b9SJerome Glisse case 32: 1361771fe6b9SJerome Glisse fb_format = 1362771fe6b9SJerome Glisse AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | 1363771fe6b9SJerome Glisse AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; 1364fa6bee46SAlex Deucher #ifdef __BIG_ENDIAN 1365fa6bee46SAlex Deucher fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; 1366fa6bee46SAlex Deucher #endif 1367771fe6b9SJerome Glisse break; 1368771fe6b9SJerome Glisse default: 1369771fe6b9SJerome Glisse DRM_ERROR("Unsupported screen depth %d\n", 13704dd19b0dSChris Ball target_fb->bits_per_pixel); 1371771fe6b9SJerome Glisse return -EINVAL; 1372771fe6b9SJerome Glisse } 1373771fe6b9SJerome Glisse 137440c4ac1cSAlex Deucher if (rdev->family >= CHIP_R600) { 137540c4ac1cSAlex Deucher if (tiling_flags & RADEON_TILING_MACRO) 137640c4ac1cSAlex Deucher fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1; 137740c4ac1cSAlex Deucher else if (tiling_flags & RADEON_TILING_MICRO) 137840c4ac1cSAlex Deucher fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1; 137940c4ac1cSAlex Deucher } else { 1380cf2f05d3SDave Airlie if (tiling_flags & RADEON_TILING_MACRO) 1381cf2f05d3SDave Airlie fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; 1382cf2f05d3SDave Airlie 1383e024e110SDave Airlie if (tiling_flags & RADEON_TILING_MICRO) 1384e024e110SDave Airlie fb_format |= AVIVO_D1GRPH_TILED; 138540c4ac1cSAlex Deucher } 1386e024e110SDave Airlie 1387771fe6b9SJerome Glisse if (radeon_crtc->crtc_id == 0) 1388771fe6b9SJerome Glisse WREG32(AVIVO_D1VGA_CONTROL, 0); 1389771fe6b9SJerome Glisse else 1390771fe6b9SJerome Glisse WREG32(AVIVO_D2VGA_CONTROL, 0); 1391c290dadfSAlex Deucher 1392c290dadfSAlex Deucher if (rdev->family >= CHIP_RV770) { 1393c290dadfSAlex Deucher if (radeon_crtc->crtc_id) { 139495347871SAlex Deucher WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 139595347871SAlex Deucher WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1396c290dadfSAlex Deucher } else { 139795347871SAlex Deucher WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 139895347871SAlex Deucher WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1399c290dadfSAlex Deucher } 1400c290dadfSAlex Deucher } 1401771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1402771fe6b9SJerome Glisse (u32) fb_location); 1403771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + 1404771fe6b9SJerome Glisse radeon_crtc->crtc_offset, (u32) fb_location); 1405771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1406fa6bee46SAlex Deucher if (rdev->family >= CHIP_R600) 1407fa6bee46SAlex Deucher WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1408771fe6b9SJerome Glisse 1409771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1410771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1411771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); 1412771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); 14134dd19b0dSChris Ball WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); 14144dd19b0dSChris Ball WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); 1415771fe6b9SJerome Glisse 141601f2c773SVille Syrjälä fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 1417771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 1418771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1419771fe6b9SJerome Glisse 1420771fe6b9SJerome Glisse WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 14211b619250SMichel Dänzer target_fb->height); 1422771fe6b9SJerome Glisse x &= ~3; 1423771fe6b9SJerome Glisse y &= ~1; 1424771fe6b9SJerome Glisse WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, 1425771fe6b9SJerome Glisse (x << 16) | y); 1426adcfde51SAlex Deucher viewport_w = crtc->mode.hdisplay; 1427adcfde51SAlex Deucher viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1428771fe6b9SJerome Glisse WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1429adcfde51SAlex Deucher (viewport_w << 16) | viewport_h); 1430771fe6b9SJerome Glisse 1431fb9674bdSAlex Deucher /* pageflip setup */ 1432fb9674bdSAlex Deucher /* make sure flip is at vb rather than hb */ 1433fb9674bdSAlex Deucher tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); 1434fb9674bdSAlex Deucher tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN; 1435fb9674bdSAlex Deucher WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); 1436fb9674bdSAlex Deucher 1437fb9674bdSAlex Deucher /* set pageflip to happen anywhere in vblank interval */ 1438fb9674bdSAlex Deucher WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); 1439fb9674bdSAlex Deucher 14404dd19b0dSChris Ball if (!atomic && fb && fb != crtc->fb) { 14414dd19b0dSChris Ball radeon_fb = to_radeon_framebuffer(fb); 14427e4d15d9SDaniel Vetter rbo = gem_to_radeon_bo(radeon_fb->obj); 14434c788679SJerome Glisse r = radeon_bo_reserve(rbo, false); 14444c788679SJerome Glisse if (unlikely(r != 0)) 14454c788679SJerome Glisse return r; 14464c788679SJerome Glisse radeon_bo_unpin(rbo); 14474c788679SJerome Glisse radeon_bo_unreserve(rbo); 1448771fe6b9SJerome Glisse } 1449f30f37deSMichel Dänzer 1450f30f37deSMichel Dänzer /* Bytes per pixel may have changed */ 1451f30f37deSMichel Dänzer radeon_bandwidth_update(rdev); 1452f30f37deSMichel Dänzer 1453771fe6b9SJerome Glisse return 0; 1454771fe6b9SJerome Glisse } 1455771fe6b9SJerome Glisse 145654f088a9SAlex Deucher int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 145754f088a9SAlex Deucher struct drm_framebuffer *old_fb) 145854f088a9SAlex Deucher { 145954f088a9SAlex Deucher struct drm_device *dev = crtc->dev; 146054f088a9SAlex Deucher struct radeon_device *rdev = dev->dev_private; 146154f088a9SAlex Deucher 1462bcc1c2a1SAlex Deucher if (ASIC_IS_DCE4(rdev)) 1463c9417bddSAlex Deucher return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0); 1464bcc1c2a1SAlex Deucher else if (ASIC_IS_AVIVO(rdev)) 14654dd19b0dSChris Ball return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0); 146654f088a9SAlex Deucher else 14674dd19b0dSChris Ball return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); 14684dd19b0dSChris Ball } 14694dd19b0dSChris Ball 14704dd19b0dSChris Ball int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 14714dd19b0dSChris Ball struct drm_framebuffer *fb, 147221c74a8eSJason Wessel int x, int y, enum mode_set_atomic state) 14734dd19b0dSChris Ball { 14744dd19b0dSChris Ball struct drm_device *dev = crtc->dev; 14754dd19b0dSChris Ball struct radeon_device *rdev = dev->dev_private; 14764dd19b0dSChris Ball 14774dd19b0dSChris Ball if (ASIC_IS_DCE4(rdev)) 1478c9417bddSAlex Deucher return dce4_crtc_do_set_base(crtc, fb, x, y, 1); 14794dd19b0dSChris Ball else if (ASIC_IS_AVIVO(rdev)) 14804dd19b0dSChris Ball return avivo_crtc_do_set_base(crtc, fb, x, y, 1); 14814dd19b0dSChris Ball else 14824dd19b0dSChris Ball return radeon_crtc_do_set_base(crtc, fb, x, y, 1); 148354f088a9SAlex Deucher } 148454f088a9SAlex Deucher 1485615e0cb6SAlex Deucher /* properly set additional regs when using atombios */ 1486615e0cb6SAlex Deucher static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) 1487615e0cb6SAlex Deucher { 1488615e0cb6SAlex Deucher struct drm_device *dev = crtc->dev; 1489615e0cb6SAlex Deucher struct radeon_device *rdev = dev->dev_private; 1490615e0cb6SAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1491615e0cb6SAlex Deucher u32 disp_merge_cntl; 1492615e0cb6SAlex Deucher 1493615e0cb6SAlex Deucher switch (radeon_crtc->crtc_id) { 1494615e0cb6SAlex Deucher case 0: 1495615e0cb6SAlex Deucher disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); 1496615e0cb6SAlex Deucher disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 1497615e0cb6SAlex Deucher WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); 1498615e0cb6SAlex Deucher break; 1499615e0cb6SAlex Deucher case 1: 1500615e0cb6SAlex Deucher disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 1501615e0cb6SAlex Deucher disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 1502615e0cb6SAlex Deucher WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); 1503615e0cb6SAlex Deucher WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); 1504615e0cb6SAlex Deucher WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); 1505615e0cb6SAlex Deucher break; 1506615e0cb6SAlex Deucher } 1507615e0cb6SAlex Deucher } 1508615e0cb6SAlex Deucher 1509f3dd8508SAlex Deucher /** 1510f3dd8508SAlex Deucher * radeon_get_pll_use_mask - look up a mask of which pplls are in use 1511f3dd8508SAlex Deucher * 1512f3dd8508SAlex Deucher * @crtc: drm crtc 1513f3dd8508SAlex Deucher * 1514f3dd8508SAlex Deucher * Returns the mask of which PPLLs (Pixel PLLs) are in use. 1515f3dd8508SAlex Deucher */ 1516f3dd8508SAlex Deucher static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc) 1517f3dd8508SAlex Deucher { 1518f3dd8508SAlex Deucher struct drm_device *dev = crtc->dev; 1519f3dd8508SAlex Deucher struct drm_crtc *test_crtc; 152057b35e29SAlex Deucher struct radeon_crtc *test_radeon_crtc; 1521f3dd8508SAlex Deucher u32 pll_in_use = 0; 1522f3dd8508SAlex Deucher 1523f3dd8508SAlex Deucher list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1524f3dd8508SAlex Deucher if (crtc == test_crtc) 1525f3dd8508SAlex Deucher continue; 1526f3dd8508SAlex Deucher 152757b35e29SAlex Deucher test_radeon_crtc = to_radeon_crtc(test_crtc); 152857b35e29SAlex Deucher if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 152957b35e29SAlex Deucher pll_in_use |= (1 << test_radeon_crtc->pll_id); 1530f3dd8508SAlex Deucher } 1531f3dd8508SAlex Deucher return pll_in_use; 1532f3dd8508SAlex Deucher } 1533f3dd8508SAlex Deucher 1534f3dd8508SAlex Deucher /** 1535f3dd8508SAlex Deucher * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP 1536f3dd8508SAlex Deucher * 1537f3dd8508SAlex Deucher * @crtc: drm crtc 1538f3dd8508SAlex Deucher * 1539f3dd8508SAlex Deucher * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is 1540f3dd8508SAlex Deucher * also in DP mode. For DP, a single PPLL can be used for all DP 1541f3dd8508SAlex Deucher * crtcs/encoders. 1542f3dd8508SAlex Deucher */ 1543f3dd8508SAlex Deucher static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) 1544f3dd8508SAlex Deucher { 1545f3dd8508SAlex Deucher struct drm_device *dev = crtc->dev; 154657b35e29SAlex Deucher struct drm_crtc *test_crtc; 15475df3196bSAlex Deucher struct radeon_crtc *test_radeon_crtc; 1548f3dd8508SAlex Deucher 154957b35e29SAlex Deucher list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 155057b35e29SAlex Deucher if (crtc == test_crtc) 155157b35e29SAlex Deucher continue; 155257b35e29SAlex Deucher test_radeon_crtc = to_radeon_crtc(test_crtc); 155357b35e29SAlex Deucher if (test_radeon_crtc->encoder && 155457b35e29SAlex Deucher ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { 1555f3dd8508SAlex Deucher /* for DP use the same PLL for all */ 15565df3196bSAlex Deucher if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 15575df3196bSAlex Deucher return test_radeon_crtc->pll_id; 1558f3dd8508SAlex Deucher } 1559f3dd8508SAlex Deucher } 1560f3dd8508SAlex Deucher return ATOM_PPLL_INVALID; 1561f3dd8508SAlex Deucher } 1562f3dd8508SAlex Deucher 1563f3dd8508SAlex Deucher /** 15642f454cf1SAlex Deucher * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc 15652f454cf1SAlex Deucher * 15662f454cf1SAlex Deucher * @crtc: drm crtc 15672f454cf1SAlex Deucher * @encoder: drm encoder 15682f454cf1SAlex Deucher * 15692f454cf1SAlex Deucher * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can 15702f454cf1SAlex Deucher * be shared (i.e., same clock). 15712f454cf1SAlex Deucher */ 15725df3196bSAlex Deucher static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc) 15732f454cf1SAlex Deucher { 15745df3196bSAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 15752f454cf1SAlex Deucher struct drm_device *dev = crtc->dev; 15769642ac0eSAlex Deucher struct drm_crtc *test_crtc; 15775df3196bSAlex Deucher struct radeon_crtc *test_radeon_crtc; 15789642ac0eSAlex Deucher u32 adjusted_clock, test_adjusted_clock; 15792f454cf1SAlex Deucher 15809642ac0eSAlex Deucher adjusted_clock = radeon_crtc->adjusted_clock; 15819642ac0eSAlex Deucher 15829642ac0eSAlex Deucher if (adjusted_clock == 0) 15839642ac0eSAlex Deucher return ATOM_PPLL_INVALID; 15842f454cf1SAlex Deucher 158557b35e29SAlex Deucher list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 158657b35e29SAlex Deucher if (crtc == test_crtc) 158757b35e29SAlex Deucher continue; 15889642ac0eSAlex Deucher test_radeon_crtc = to_radeon_crtc(test_crtc); 158957b35e29SAlex Deucher if (test_radeon_crtc->encoder && 159057b35e29SAlex Deucher !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { 159157b35e29SAlex Deucher /* check if we are already driving this connector with another crtc */ 159257b35e29SAlex Deucher if (test_radeon_crtc->connector == radeon_crtc->connector) { 159357b35e29SAlex Deucher /* if we are, return that pll */ 159457b35e29SAlex Deucher if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 159557b35e29SAlex Deucher return test_radeon_crtc->pll_id; 159657b35e29SAlex Deucher } 15972f454cf1SAlex Deucher /* for non-DP check the clock */ 15989642ac0eSAlex Deucher test_adjusted_clock = test_radeon_crtc->adjusted_clock; 15999642ac0eSAlex Deucher if ((crtc->mode.clock == test_crtc->mode.clock) && 16009642ac0eSAlex Deucher (adjusted_clock == test_adjusted_clock) && 16019642ac0eSAlex Deucher (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) && 16025df3196bSAlex Deucher (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)) 16035df3196bSAlex Deucher return test_radeon_crtc->pll_id; 16042f454cf1SAlex Deucher } 16052f454cf1SAlex Deucher } 16062f454cf1SAlex Deucher return ATOM_PPLL_INVALID; 16072f454cf1SAlex Deucher } 16082f454cf1SAlex Deucher 16092f454cf1SAlex Deucher /** 1610f3dd8508SAlex Deucher * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc. 1611f3dd8508SAlex Deucher * 1612f3dd8508SAlex Deucher * @crtc: drm crtc 1613f3dd8508SAlex Deucher * 1614f3dd8508SAlex Deucher * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 1615f3dd8508SAlex Deucher * a single PPLL can be used for all DP crtcs/encoders. For non-DP 1616f3dd8508SAlex Deucher * monitors a dedicated PPLL must be used. If a particular board has 1617f3dd8508SAlex Deucher * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 1618f3dd8508SAlex Deucher * as there is no need to program the PLL itself. If we are not able to 1619f3dd8508SAlex Deucher * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 1620f3dd8508SAlex Deucher * avoid messing up an existing monitor. 1621f3dd8508SAlex Deucher * 1622f3dd8508SAlex Deucher * Asic specific PLL information 1623f3dd8508SAlex Deucher * 16240331f674SAlex Deucher * DCE 8.x 16250331f674SAlex Deucher * KB/KV 16260331f674SAlex Deucher * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 16270331f674SAlex Deucher * CI 16280331f674SAlex Deucher * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 16290331f674SAlex Deucher * 1630f3dd8508SAlex Deucher * DCE 6.1 1631f3dd8508SAlex Deucher * - PPLL2 is only available to UNIPHYA (both DP and non-DP) 1632f3dd8508SAlex Deucher * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP) 1633f3dd8508SAlex Deucher * 1634f3dd8508SAlex Deucher * DCE 6.0 1635f3dd8508SAlex Deucher * - PPLL0 is available to all UNIPHY (DP only) 1636f3dd8508SAlex Deucher * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1637f3dd8508SAlex Deucher * 1638f3dd8508SAlex Deucher * DCE 5.0 1639f3dd8508SAlex Deucher * - DCPLL is available to all UNIPHY (DP only) 1640f3dd8508SAlex Deucher * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1641f3dd8508SAlex Deucher * 1642f3dd8508SAlex Deucher * DCE 3.0/4.0/4.1 1643f3dd8508SAlex Deucher * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1644f3dd8508SAlex Deucher * 1645f3dd8508SAlex Deucher */ 1646bcc1c2a1SAlex Deucher static int radeon_atom_pick_pll(struct drm_crtc *crtc) 1647bcc1c2a1SAlex Deucher { 16485df3196bSAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1649bcc1c2a1SAlex Deucher struct drm_device *dev = crtc->dev; 1650bcc1c2a1SAlex Deucher struct radeon_device *rdev = dev->dev_private; 16515df3196bSAlex Deucher struct radeon_encoder *radeon_encoder = 16525df3196bSAlex Deucher to_radeon_encoder(radeon_crtc->encoder); 1653f3dd8508SAlex Deucher u32 pll_in_use; 1654f3dd8508SAlex Deucher int pll; 1655bcc1c2a1SAlex Deucher 16560331f674SAlex Deucher if (ASIC_IS_DCE8(rdev)) { 16570331f674SAlex Deucher if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 16580331f674SAlex Deucher if (rdev->clock.dp_extclk) 16590331f674SAlex Deucher /* skip PPLL programming if using ext clock */ 16600331f674SAlex Deucher return ATOM_PPLL_INVALID; 16610331f674SAlex Deucher else { 16620331f674SAlex Deucher /* use the same PPLL for all DP monitors */ 16630331f674SAlex Deucher pll = radeon_get_shared_dp_ppll(crtc); 16640331f674SAlex Deucher if (pll != ATOM_PPLL_INVALID) 16650331f674SAlex Deucher return pll; 16660331f674SAlex Deucher } 16670331f674SAlex Deucher } else { 16680331f674SAlex Deucher /* use the same PPLL for all monitors with the same clock */ 16690331f674SAlex Deucher pll = radeon_get_shared_nondp_ppll(crtc); 16700331f674SAlex Deucher if (pll != ATOM_PPLL_INVALID) 16710331f674SAlex Deucher return pll; 16720331f674SAlex Deucher } 16730331f674SAlex Deucher /* otherwise, pick one of the plls */ 16740331f674SAlex Deucher if ((rdev->family == CHIP_KAVERI) || 16750331f674SAlex Deucher (rdev->family == CHIP_KABINI)) { 16760331f674SAlex Deucher /* KB/KV has PPLL1 and PPLL2 */ 16770331f674SAlex Deucher pll_in_use = radeon_get_pll_use_mask(crtc); 16780331f674SAlex Deucher if (!(pll_in_use & (1 << ATOM_PPLL2))) 16790331f674SAlex Deucher return ATOM_PPLL2; 16800331f674SAlex Deucher if (!(pll_in_use & (1 << ATOM_PPLL1))) 16810331f674SAlex Deucher return ATOM_PPLL1; 16820331f674SAlex Deucher DRM_ERROR("unable to allocate a PPLL\n"); 16830331f674SAlex Deucher return ATOM_PPLL_INVALID; 16840331f674SAlex Deucher } else { 16850331f674SAlex Deucher /* CI has PPLL0, PPLL1, and PPLL2 */ 16860331f674SAlex Deucher pll_in_use = radeon_get_pll_use_mask(crtc); 16870331f674SAlex Deucher if (!(pll_in_use & (1 << ATOM_PPLL2))) 16880331f674SAlex Deucher return ATOM_PPLL2; 16890331f674SAlex Deucher if (!(pll_in_use & (1 << ATOM_PPLL1))) 16900331f674SAlex Deucher return ATOM_PPLL1; 16910331f674SAlex Deucher if (!(pll_in_use & (1 << ATOM_PPLL0))) 16920331f674SAlex Deucher return ATOM_PPLL0; 16930331f674SAlex Deucher DRM_ERROR("unable to allocate a PPLL\n"); 16940331f674SAlex Deucher return ATOM_PPLL_INVALID; 16950331f674SAlex Deucher } 16960331f674SAlex Deucher } else if (ASIC_IS_DCE61(rdev)) { 169724e1f794SAlex Deucher struct radeon_encoder_atom_dig *dig = 16985df3196bSAlex Deucher radeon_encoder->enc_priv; 169924e1f794SAlex Deucher 17005df3196bSAlex Deucher if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) && 1701f3dd8508SAlex Deucher (dig->linkb == false)) 1702f3dd8508SAlex Deucher /* UNIPHY A uses PPLL2 */ 170324e1f794SAlex Deucher return ATOM_PPLL2; 17045df3196bSAlex Deucher else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1705f3dd8508SAlex Deucher /* UNIPHY B/C/D/E/F */ 1706f3dd8508SAlex Deucher if (rdev->clock.dp_extclk) 1707f3dd8508SAlex Deucher /* skip PPLL programming if using ext clock */ 1708f3dd8508SAlex Deucher return ATOM_PPLL_INVALID; 1709f3dd8508SAlex Deucher else { 1710f3dd8508SAlex Deucher /* use the same PPLL for all DP monitors */ 1711f3dd8508SAlex Deucher pll = radeon_get_shared_dp_ppll(crtc); 1712f3dd8508SAlex Deucher if (pll != ATOM_PPLL_INVALID) 1713f3dd8508SAlex Deucher return pll; 1714f3dd8508SAlex Deucher } 17152f454cf1SAlex Deucher } else { 17162f454cf1SAlex Deucher /* use the same PPLL for all monitors with the same clock */ 17175df3196bSAlex Deucher pll = radeon_get_shared_nondp_ppll(crtc); 17182f454cf1SAlex Deucher if (pll != ATOM_PPLL_INVALID) 17192f454cf1SAlex Deucher return pll; 1720f3dd8508SAlex Deucher } 172124e1f794SAlex Deucher /* UNIPHY B/C/D/E/F */ 1722f3dd8508SAlex Deucher pll_in_use = radeon_get_pll_use_mask(crtc); 1723f3dd8508SAlex Deucher if (!(pll_in_use & (1 << ATOM_PPLL0))) 172424e1f794SAlex Deucher return ATOM_PPLL0; 1725f3dd8508SAlex Deucher if (!(pll_in_use & (1 << ATOM_PPLL1))) 172624e1f794SAlex Deucher return ATOM_PPLL1; 1727f3dd8508SAlex Deucher DRM_ERROR("unable to allocate a PPLL\n"); 1728f3dd8508SAlex Deucher return ATOM_PPLL_INVALID; 172924e1f794SAlex Deucher } else if (ASIC_IS_DCE4(rdev)) { 173086a94defSAlex Deucher /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, 173186a94defSAlex Deucher * depending on the asic: 173286a94defSAlex Deucher * DCE4: PPLL or ext clock 1733f3dd8508SAlex Deucher * DCE5: PPLL, DCPLL, or ext clock 1734f3dd8508SAlex Deucher * DCE6: PPLL, PPLL0, or ext clock 173586a94defSAlex Deucher * 173686a94defSAlex Deucher * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip 173786a94defSAlex Deucher * PPLL/DCPLL programming and only program the DP DTO for the 173886a94defSAlex Deucher * crtc virtual pixel clock. 173986a94defSAlex Deucher */ 17405df3196bSAlex Deucher if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1741ecd67955SAlex Deucher if (rdev->clock.dp_extclk) 1742f3dd8508SAlex Deucher /* skip PPLL programming if using ext clock */ 1743ecd67955SAlex Deucher return ATOM_PPLL_INVALID; 174426fe45a0SAlex Deucher else if (ASIC_IS_DCE6(rdev)) 1745f3dd8508SAlex Deucher /* use PPLL0 for all DP */ 174626fe45a0SAlex Deucher return ATOM_PPLL0; 1747ecd67955SAlex Deucher else if (ASIC_IS_DCE5(rdev)) 1748f3dd8508SAlex Deucher /* use DCPLL for all DP */ 1749ecd67955SAlex Deucher return ATOM_DCPLL; 1750f3dd8508SAlex Deucher else { 1751f3dd8508SAlex Deucher /* use the same PPLL for all DP monitors */ 1752f3dd8508SAlex Deucher pll = radeon_get_shared_dp_ppll(crtc); 1753f3dd8508SAlex Deucher if (pll != ATOM_PPLL_INVALID) 1754f3dd8508SAlex Deucher return pll; 1755bcc1c2a1SAlex Deucher } 17562f454cf1SAlex Deucher } else { 17572f454cf1SAlex Deucher /* use the same PPLL for all monitors with the same clock */ 17585df3196bSAlex Deucher pll = radeon_get_shared_nondp_ppll(crtc); 17599dbbcfc6SAlex Deucher if (pll != ATOM_PPLL_INVALID) 17609dbbcfc6SAlex Deucher return pll; 17619dbbcfc6SAlex Deucher } 17625df3196bSAlex Deucher /* all other cases */ 17635df3196bSAlex Deucher pll_in_use = radeon_get_pll_use_mask(crtc); 17645df3196bSAlex Deucher if (!(pll_in_use & (1 << ATOM_PPLL1))) 17655df3196bSAlex Deucher return ATOM_PPLL1; 176629dbe3bcSAlex Deucher if (!(pll_in_use & (1 << ATOM_PPLL2))) 176729dbe3bcSAlex Deucher return ATOM_PPLL2; 17685df3196bSAlex Deucher DRM_ERROR("unable to allocate a PPLL\n"); 17695df3196bSAlex Deucher return ATOM_PPLL_INVALID; 17702f454cf1SAlex Deucher } else { 17712f454cf1SAlex Deucher /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ 1772fc58acdbSJerome Glisse /* some atombios (observed in some DCE2/DCE3) code have a bug, 1773fc58acdbSJerome Glisse * the matching btw pll and crtc is done through 1774fc58acdbSJerome Glisse * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the 1775fc58acdbSJerome Glisse * pll (1 or 2) to select which register to write. ie if using 1776fc58acdbSJerome Glisse * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2 1777fc58acdbSJerome Glisse * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to 1778fc58acdbSJerome Glisse * choose which value to write. Which is reverse order from 1779fc58acdbSJerome Glisse * register logic. So only case that works is when pllid is 1780fc58acdbSJerome Glisse * same as crtcid or when both pll and crtc are enabled and 1781fc58acdbSJerome Glisse * both use same clock. 1782fc58acdbSJerome Glisse * 1783fc58acdbSJerome Glisse * So just return crtc id as if crtc and pll were hard linked 1784fc58acdbSJerome Glisse * together even if they aren't 1785fc58acdbSJerome Glisse */ 1786bcc1c2a1SAlex Deucher return radeon_crtc->crtc_id; 17872f454cf1SAlex Deucher } 17882f454cf1SAlex Deucher } 1789bcc1c2a1SAlex Deucher 1790f3f1f03eSAlex Deucher void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev) 17913fa47d9eSAlex Deucher { 17923fa47d9eSAlex Deucher /* always set DCPLL */ 1793f3f1f03eSAlex Deucher if (ASIC_IS_DCE6(rdev)) 1794f3f1f03eSAlex Deucher atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); 1795f3f1f03eSAlex Deucher else if (ASIC_IS_DCE4(rdev)) { 17963fa47d9eSAlex Deucher struct radeon_atom_ss ss; 17973fa47d9eSAlex Deucher bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, 17983fa47d9eSAlex Deucher ASIC_INTERNAL_SS_ON_DCPLL, 17993fa47d9eSAlex Deucher rdev->clock.default_dispclk); 18003fa47d9eSAlex Deucher if (ss_enabled) 18015efcc76cSJerome Glisse atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss); 18023fa47d9eSAlex Deucher /* XXX: DCE5, make sure voltage, dispclk is high enough */ 1803f3f1f03eSAlex Deucher atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); 18043fa47d9eSAlex Deucher if (ss_enabled) 18055efcc76cSJerome Glisse atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss); 18063fa47d9eSAlex Deucher } 18073fa47d9eSAlex Deucher 18083fa47d9eSAlex Deucher } 18093fa47d9eSAlex Deucher 1810771fe6b9SJerome Glisse int atombios_crtc_mode_set(struct drm_crtc *crtc, 1811771fe6b9SJerome Glisse struct drm_display_mode *mode, 1812771fe6b9SJerome Glisse struct drm_display_mode *adjusted_mode, 1813771fe6b9SJerome Glisse int x, int y, struct drm_framebuffer *old_fb) 1814771fe6b9SJerome Glisse { 1815771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1816771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 1817771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 18185df3196bSAlex Deucher struct radeon_encoder *radeon_encoder = 18195df3196bSAlex Deucher to_radeon_encoder(radeon_crtc->encoder); 182054bfe496SAlex Deucher bool is_tvcv = false; 1821771fe6b9SJerome Glisse 182254bfe496SAlex Deucher if (radeon_encoder->active_device & 182354bfe496SAlex Deucher (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 182454bfe496SAlex Deucher is_tvcv = true; 1825771fe6b9SJerome Glisse 1826771fe6b9SJerome Glisse atombios_crtc_set_pll(crtc, adjusted_mode); 1827771fe6b9SJerome Glisse 182854bfe496SAlex Deucher if (ASIC_IS_DCE4(rdev)) 1829bcc1c2a1SAlex Deucher atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 183054bfe496SAlex Deucher else if (ASIC_IS_AVIVO(rdev)) { 183154bfe496SAlex Deucher if (is_tvcv) 183254bfe496SAlex Deucher atombios_crtc_set_timing(crtc, adjusted_mode); 183354bfe496SAlex Deucher else 183454bfe496SAlex Deucher atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 183554bfe496SAlex Deucher } else { 1836bcc1c2a1SAlex Deucher atombios_crtc_set_timing(crtc, adjusted_mode); 18375a9bcaccSAlex Deucher if (radeon_crtc->crtc_id == 0) 18385a9bcaccSAlex Deucher atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1839615e0cb6SAlex Deucher radeon_legacy_atom_fixup(crtc); 1840771fe6b9SJerome Glisse } 1841bcc1c2a1SAlex Deucher atombios_crtc_set_base(crtc, x, y, old_fb); 1842c93bb85bSJerome Glisse atombios_overscan_setup(crtc, mode, adjusted_mode); 1843c93bb85bSJerome Glisse atombios_scaler_setup(crtc); 184466edc1c9SAlex Deucher /* update the hw version fpr dpm */ 184566edc1c9SAlex Deucher radeon_crtc->hw_mode = *adjusted_mode; 184666edc1c9SAlex Deucher 1847771fe6b9SJerome Glisse return 0; 1848771fe6b9SJerome Glisse } 1849771fe6b9SJerome Glisse 1850771fe6b9SJerome Glisse static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, 1851e811f5aeSLaurent Pinchart const struct drm_display_mode *mode, 1852771fe6b9SJerome Glisse struct drm_display_mode *adjusted_mode) 1853771fe6b9SJerome Glisse { 18545df3196bSAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 18555df3196bSAlex Deucher struct drm_device *dev = crtc->dev; 18565df3196bSAlex Deucher struct drm_encoder *encoder; 18575df3196bSAlex Deucher 18585df3196bSAlex Deucher /* assign the encoder to the radeon crtc to avoid repeated lookups later */ 18595df3196bSAlex Deucher list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 18605df3196bSAlex Deucher if (encoder->crtc == crtc) { 18615df3196bSAlex Deucher radeon_crtc->encoder = encoder; 186257b35e29SAlex Deucher radeon_crtc->connector = radeon_get_connector_for_encoder(encoder); 18635df3196bSAlex Deucher break; 18645df3196bSAlex Deucher } 18655df3196bSAlex Deucher } 186657b35e29SAlex Deucher if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) { 186757b35e29SAlex Deucher radeon_crtc->encoder = NULL; 186857b35e29SAlex Deucher radeon_crtc->connector = NULL; 18695df3196bSAlex Deucher return false; 187057b35e29SAlex Deucher } 1871c93bb85bSJerome Glisse if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 1872c93bb85bSJerome Glisse return false; 187319eca43eSAlex Deucher if (!atombios_crtc_prepare_pll(crtc, adjusted_mode)) 187419eca43eSAlex Deucher return false; 1875c0fd0834SAlex Deucher /* pick pll */ 1876c0fd0834SAlex Deucher radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); 1877c0fd0834SAlex Deucher /* if we can't get a PPLL for a non-DP encoder, fail */ 1878c0fd0834SAlex Deucher if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) && 1879c0fd0834SAlex Deucher !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) 1880c0fd0834SAlex Deucher return false; 1881c0fd0834SAlex Deucher 1882771fe6b9SJerome Glisse return true; 1883771fe6b9SJerome Glisse } 1884771fe6b9SJerome Glisse 1885771fe6b9SJerome Glisse static void atombios_crtc_prepare(struct drm_crtc *crtc) 1886771fe6b9SJerome Glisse { 18876c0ae2abSAlex Deucher struct drm_device *dev = crtc->dev; 18886c0ae2abSAlex Deucher struct radeon_device *rdev = dev->dev_private; 1889267364acSAlex Deucher 18906c0ae2abSAlex Deucher /* disable crtc pair power gating before programming */ 18916c0ae2abSAlex Deucher if (ASIC_IS_DCE6(rdev)) 18926c0ae2abSAlex Deucher atombios_powergate_crtc(crtc, ATOM_DISABLE); 18936c0ae2abSAlex Deucher 189437b4390eSAlex Deucher atombios_lock_crtc(crtc, ATOM_ENABLE); 1895a348c84dSAlex Deucher atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1896771fe6b9SJerome Glisse } 1897771fe6b9SJerome Glisse 1898771fe6b9SJerome Glisse static void atombios_crtc_commit(struct drm_crtc *crtc) 1899771fe6b9SJerome Glisse { 1900771fe6b9SJerome Glisse atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 190137b4390eSAlex Deucher atombios_lock_crtc(crtc, ATOM_DISABLE); 1902771fe6b9SJerome Glisse } 1903771fe6b9SJerome Glisse 190437f9003bSAlex Deucher static void atombios_crtc_disable(struct drm_crtc *crtc) 190537f9003bSAlex Deucher { 190637f9003bSAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 190764199870SAlex Deucher struct drm_device *dev = crtc->dev; 190864199870SAlex Deucher struct radeon_device *rdev = dev->dev_private; 19098e8e523dSAlex Deucher struct radeon_atom_ss ss; 19104e58591cSAlex Deucher int i; 19118e8e523dSAlex Deucher 191237f9003bSAlex Deucher atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 19130e3d50bfSAlex Deucher if (ASIC_IS_DCE6(rdev)) 19140e3d50bfSAlex Deucher atombios_powergate_crtc(crtc, ATOM_ENABLE); 191537f9003bSAlex Deucher 19164e58591cSAlex Deucher for (i = 0; i < rdev->num_crtc; i++) { 19174e58591cSAlex Deucher if (rdev->mode_info.crtcs[i] && 19184e58591cSAlex Deucher rdev->mode_info.crtcs[i]->enabled && 19194e58591cSAlex Deucher i != radeon_crtc->crtc_id && 19204e58591cSAlex Deucher radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) { 19214e58591cSAlex Deucher /* one other crtc is using this pll don't turn 19224e58591cSAlex Deucher * off the pll 19234e58591cSAlex Deucher */ 19244e58591cSAlex Deucher goto done; 19254e58591cSAlex Deucher } 19264e58591cSAlex Deucher } 19274e58591cSAlex Deucher 192837f9003bSAlex Deucher switch (radeon_crtc->pll_id) { 192937f9003bSAlex Deucher case ATOM_PPLL1: 193037f9003bSAlex Deucher case ATOM_PPLL2: 193137f9003bSAlex Deucher /* disable the ppll */ 193237f9003bSAlex Deucher atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 19338e8e523dSAlex Deucher 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 193437f9003bSAlex Deucher break; 193564199870SAlex Deucher case ATOM_PPLL0: 193664199870SAlex Deucher /* disable the ppll */ 19372f0047b2SAlex Deucher if ((rdev->family == CHIP_ARUBA) || (rdev->family == CHIP_BONAIRE)) 193864199870SAlex Deucher atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 193964199870SAlex Deucher 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 194064199870SAlex Deucher break; 194137f9003bSAlex Deucher default: 194237f9003bSAlex Deucher break; 194337f9003bSAlex Deucher } 19444e58591cSAlex Deucher done: 1945f3dd8508SAlex Deucher radeon_crtc->pll_id = ATOM_PPLL_INVALID; 19469642ac0eSAlex Deucher radeon_crtc->adjusted_clock = 0; 19475df3196bSAlex Deucher radeon_crtc->encoder = NULL; 194857b35e29SAlex Deucher radeon_crtc->connector = NULL; 194937f9003bSAlex Deucher } 195037f9003bSAlex Deucher 1951771fe6b9SJerome Glisse static const struct drm_crtc_helper_funcs atombios_helper_funcs = { 1952771fe6b9SJerome Glisse .dpms = atombios_crtc_dpms, 1953771fe6b9SJerome Glisse .mode_fixup = atombios_crtc_mode_fixup, 1954771fe6b9SJerome Glisse .mode_set = atombios_crtc_mode_set, 1955771fe6b9SJerome Glisse .mode_set_base = atombios_crtc_set_base, 19564dd19b0dSChris Ball .mode_set_base_atomic = atombios_crtc_set_base_atomic, 1957771fe6b9SJerome Glisse .prepare = atombios_crtc_prepare, 1958771fe6b9SJerome Glisse .commit = atombios_crtc_commit, 1959068143d3SDave Airlie .load_lut = radeon_crtc_load_lut, 196037f9003bSAlex Deucher .disable = atombios_crtc_disable, 1961771fe6b9SJerome Glisse }; 1962771fe6b9SJerome Glisse 1963771fe6b9SJerome Glisse void radeon_atombios_init_crtc(struct drm_device *dev, 1964771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc) 1965771fe6b9SJerome Glisse { 1966bcc1c2a1SAlex Deucher struct radeon_device *rdev = dev->dev_private; 1967bcc1c2a1SAlex Deucher 1968bcc1c2a1SAlex Deucher if (ASIC_IS_DCE4(rdev)) { 1969bcc1c2a1SAlex Deucher switch (radeon_crtc->crtc_id) { 1970bcc1c2a1SAlex Deucher case 0: 1971bcc1c2a1SAlex Deucher default: 197212d7798fSAlex Deucher radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; 1973bcc1c2a1SAlex Deucher break; 1974bcc1c2a1SAlex Deucher case 1: 197512d7798fSAlex Deucher radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; 1976bcc1c2a1SAlex Deucher break; 1977bcc1c2a1SAlex Deucher case 2: 197812d7798fSAlex Deucher radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; 1979bcc1c2a1SAlex Deucher break; 1980bcc1c2a1SAlex Deucher case 3: 198112d7798fSAlex Deucher radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; 1982bcc1c2a1SAlex Deucher break; 1983bcc1c2a1SAlex Deucher case 4: 198412d7798fSAlex Deucher radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; 1985bcc1c2a1SAlex Deucher break; 1986bcc1c2a1SAlex Deucher case 5: 198712d7798fSAlex Deucher radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; 1988bcc1c2a1SAlex Deucher break; 1989bcc1c2a1SAlex Deucher } 1990bcc1c2a1SAlex Deucher } else { 1991771fe6b9SJerome Glisse if (radeon_crtc->crtc_id == 1) 1992771fe6b9SJerome Glisse radeon_crtc->crtc_offset = 1993771fe6b9SJerome Glisse AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; 1994bcc1c2a1SAlex Deucher else 1995bcc1c2a1SAlex Deucher radeon_crtc->crtc_offset = 0; 1996bcc1c2a1SAlex Deucher } 1997f3dd8508SAlex Deucher radeon_crtc->pll_id = ATOM_PPLL_INVALID; 19989642ac0eSAlex Deucher radeon_crtc->adjusted_clock = 0; 19995df3196bSAlex Deucher radeon_crtc->encoder = NULL; 200057b35e29SAlex Deucher radeon_crtc->connector = NULL; 2001771fe6b9SJerome Glisse drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); 2002771fe6b9SJerome Glisse } 2003