1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2007-8 Advanced Micro Devices, Inc. 3771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 4771fe6b9SJerome Glisse * 5771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 6771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 7771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 8771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 10771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 11771fe6b9SJerome Glisse * 12771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 13771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 14771fe6b9SJerome Glisse * 15771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 22771fe6b9SJerome Glisse * 23771fe6b9SJerome Glisse * Authors: Dave Airlie 24771fe6b9SJerome Glisse * Alex Deucher 25771fe6b9SJerome Glisse */ 26771fe6b9SJerome Glisse #include <drm/drmP.h> 27771fe6b9SJerome Glisse #include <drm/drm_crtc_helper.h> 28771fe6b9SJerome Glisse #include <drm/radeon_drm.h> 29771fe6b9SJerome Glisse #include "radeon_fixed.h" 30771fe6b9SJerome Glisse #include "radeon.h" 31771fe6b9SJerome Glisse #include "atom.h" 32771fe6b9SJerome Glisse #include "atom-bits.h" 33771fe6b9SJerome Glisse 34c93bb85bSJerome Glisse static void atombios_overscan_setup(struct drm_crtc *crtc, 35c93bb85bSJerome Glisse struct drm_display_mode *mode, 36c93bb85bSJerome Glisse struct drm_display_mode *adjusted_mode) 37c93bb85bSJerome Glisse { 38c93bb85bSJerome Glisse struct drm_device *dev = crtc->dev; 39c93bb85bSJerome Glisse struct radeon_device *rdev = dev->dev_private; 40c93bb85bSJerome Glisse struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 41c93bb85bSJerome Glisse SET_CRTC_OVERSCAN_PS_ALLOCATION args; 42c93bb85bSJerome Glisse int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); 43c93bb85bSJerome Glisse int a1, a2; 44c93bb85bSJerome Glisse 45c93bb85bSJerome Glisse memset(&args, 0, sizeof(args)); 46c93bb85bSJerome Glisse 47c93bb85bSJerome Glisse args.usOverscanRight = 0; 48c93bb85bSJerome Glisse args.usOverscanLeft = 0; 49c93bb85bSJerome Glisse args.usOverscanBottom = 0; 50c93bb85bSJerome Glisse args.usOverscanTop = 0; 51c93bb85bSJerome Glisse args.ucCRTC = radeon_crtc->crtc_id; 52c93bb85bSJerome Glisse 53c93bb85bSJerome Glisse switch (radeon_crtc->rmx_type) { 54c93bb85bSJerome Glisse case RMX_CENTER: 55c93bb85bSJerome Glisse args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; 56c93bb85bSJerome Glisse args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; 57c93bb85bSJerome Glisse args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; 58c93bb85bSJerome Glisse args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; 59c93bb85bSJerome Glisse atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 60c93bb85bSJerome Glisse break; 61c93bb85bSJerome Glisse case RMX_ASPECT: 62c93bb85bSJerome Glisse a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; 63c93bb85bSJerome Glisse a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; 64c93bb85bSJerome Glisse 65c93bb85bSJerome Glisse if (a1 > a2) { 66c93bb85bSJerome Glisse args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; 67c93bb85bSJerome Glisse args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; 68c93bb85bSJerome Glisse } else if (a2 > a1) { 69c93bb85bSJerome Glisse args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; 70c93bb85bSJerome Glisse args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; 71c93bb85bSJerome Glisse } 72c93bb85bSJerome Glisse atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 73c93bb85bSJerome Glisse break; 74c93bb85bSJerome Glisse case RMX_FULL: 75c93bb85bSJerome Glisse default: 76c93bb85bSJerome Glisse args.usOverscanRight = 0; 77c93bb85bSJerome Glisse args.usOverscanLeft = 0; 78c93bb85bSJerome Glisse args.usOverscanBottom = 0; 79c93bb85bSJerome Glisse args.usOverscanTop = 0; 80c93bb85bSJerome Glisse atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 81c93bb85bSJerome Glisse break; 82c93bb85bSJerome Glisse } 83c93bb85bSJerome Glisse } 84c93bb85bSJerome Glisse 85c93bb85bSJerome Glisse static void atombios_scaler_setup(struct drm_crtc *crtc) 86c93bb85bSJerome Glisse { 87c93bb85bSJerome Glisse struct drm_device *dev = crtc->dev; 88c93bb85bSJerome Glisse struct radeon_device *rdev = dev->dev_private; 89c93bb85bSJerome Glisse struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 90c93bb85bSJerome Glisse ENABLE_SCALER_PS_ALLOCATION args; 91c93bb85bSJerome Glisse int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); 924ce001abSDave Airlie 93c93bb85bSJerome Glisse /* fixme - fill in enc_priv for atom dac */ 94c93bb85bSJerome Glisse enum radeon_tv_std tv_std = TV_STD_NTSC; 954ce001abSDave Airlie bool is_tv = false, is_cv = false; 964ce001abSDave Airlie struct drm_encoder *encoder; 97c93bb85bSJerome Glisse 98c93bb85bSJerome Glisse if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) 99c93bb85bSJerome Glisse return; 100c93bb85bSJerome Glisse 1014ce001abSDave Airlie list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1024ce001abSDave Airlie /* find tv std */ 1034ce001abSDave Airlie if (encoder->crtc == crtc) { 1044ce001abSDave Airlie struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1054ce001abSDave Airlie if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 1064ce001abSDave Airlie struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 1074ce001abSDave Airlie tv_std = tv_dac->tv_std; 1084ce001abSDave Airlie is_tv = true; 1094ce001abSDave Airlie } 1104ce001abSDave Airlie } 1114ce001abSDave Airlie } 1124ce001abSDave Airlie 113c93bb85bSJerome Glisse memset(&args, 0, sizeof(args)); 114c93bb85bSJerome Glisse 115c93bb85bSJerome Glisse args.ucScaler = radeon_crtc->crtc_id; 116c93bb85bSJerome Glisse 1174ce001abSDave Airlie if (is_tv) { 118c93bb85bSJerome Glisse switch (tv_std) { 119c93bb85bSJerome Glisse case TV_STD_NTSC: 120c93bb85bSJerome Glisse default: 121c93bb85bSJerome Glisse args.ucTVStandard = ATOM_TV_NTSC; 122c93bb85bSJerome Glisse break; 123c93bb85bSJerome Glisse case TV_STD_PAL: 124c93bb85bSJerome Glisse args.ucTVStandard = ATOM_TV_PAL; 125c93bb85bSJerome Glisse break; 126c93bb85bSJerome Glisse case TV_STD_PAL_M: 127c93bb85bSJerome Glisse args.ucTVStandard = ATOM_TV_PALM; 128c93bb85bSJerome Glisse break; 129c93bb85bSJerome Glisse case TV_STD_PAL_60: 130c93bb85bSJerome Glisse args.ucTVStandard = ATOM_TV_PAL60; 131c93bb85bSJerome Glisse break; 132c93bb85bSJerome Glisse case TV_STD_NTSC_J: 133c93bb85bSJerome Glisse args.ucTVStandard = ATOM_TV_NTSCJ; 134c93bb85bSJerome Glisse break; 135c93bb85bSJerome Glisse case TV_STD_SCART_PAL: 136c93bb85bSJerome Glisse args.ucTVStandard = ATOM_TV_PAL; /* ??? */ 137c93bb85bSJerome Glisse break; 138c93bb85bSJerome Glisse case TV_STD_SECAM: 139c93bb85bSJerome Glisse args.ucTVStandard = ATOM_TV_SECAM; 140c93bb85bSJerome Glisse break; 141c93bb85bSJerome Glisse case TV_STD_PAL_CN: 142c93bb85bSJerome Glisse args.ucTVStandard = ATOM_TV_PALCN; 143c93bb85bSJerome Glisse break; 144c93bb85bSJerome Glisse } 145c93bb85bSJerome Glisse args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 1464ce001abSDave Airlie } else if (is_cv) { 147c93bb85bSJerome Glisse args.ucTVStandard = ATOM_TV_CV; 148c93bb85bSJerome Glisse args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 149c93bb85bSJerome Glisse } else { 150c93bb85bSJerome Glisse switch (radeon_crtc->rmx_type) { 151c93bb85bSJerome Glisse case RMX_FULL: 152c93bb85bSJerome Glisse args.ucEnable = ATOM_SCALER_EXPANSION; 153c93bb85bSJerome Glisse break; 154c93bb85bSJerome Glisse case RMX_CENTER: 155c93bb85bSJerome Glisse args.ucEnable = ATOM_SCALER_CENTER; 156c93bb85bSJerome Glisse break; 157c93bb85bSJerome Glisse case RMX_ASPECT: 158c93bb85bSJerome Glisse args.ucEnable = ATOM_SCALER_EXPANSION; 159c93bb85bSJerome Glisse break; 160c93bb85bSJerome Glisse default: 161c93bb85bSJerome Glisse if (ASIC_IS_AVIVO(rdev)) 162c93bb85bSJerome Glisse args.ucEnable = ATOM_SCALER_DISABLE; 163c93bb85bSJerome Glisse else 164c93bb85bSJerome Glisse args.ucEnable = ATOM_SCALER_CENTER; 165c93bb85bSJerome Glisse break; 166c93bb85bSJerome Glisse } 167c93bb85bSJerome Glisse } 168c93bb85bSJerome Glisse atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1694ce001abSDave Airlie if ((is_tv || is_cv) 1704ce001abSDave Airlie && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { 1714ce001abSDave Airlie atom_rv515_force_tv_scaler(rdev, radeon_crtc); 172c93bb85bSJerome Glisse } 173c93bb85bSJerome Glisse } 174c93bb85bSJerome Glisse 175771fe6b9SJerome Glisse static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) 176771fe6b9SJerome Glisse { 177771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 178771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 179771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 180771fe6b9SJerome Glisse int index = 181771fe6b9SJerome Glisse GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); 182771fe6b9SJerome Glisse ENABLE_CRTC_PS_ALLOCATION args; 183771fe6b9SJerome Glisse 184771fe6b9SJerome Glisse memset(&args, 0, sizeof(args)); 185771fe6b9SJerome Glisse 186771fe6b9SJerome Glisse args.ucCRTC = radeon_crtc->crtc_id; 187771fe6b9SJerome Glisse args.ucEnable = lock; 188771fe6b9SJerome Glisse 189771fe6b9SJerome Glisse atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 190771fe6b9SJerome Glisse } 191771fe6b9SJerome Glisse 192771fe6b9SJerome Glisse static void atombios_enable_crtc(struct drm_crtc *crtc, int state) 193771fe6b9SJerome Glisse { 194771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 195771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 196771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 197771fe6b9SJerome Glisse int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); 198771fe6b9SJerome Glisse ENABLE_CRTC_PS_ALLOCATION args; 199771fe6b9SJerome Glisse 200771fe6b9SJerome Glisse memset(&args, 0, sizeof(args)); 201771fe6b9SJerome Glisse 202771fe6b9SJerome Glisse args.ucCRTC = radeon_crtc->crtc_id; 203771fe6b9SJerome Glisse args.ucEnable = state; 204771fe6b9SJerome Glisse 205771fe6b9SJerome Glisse atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 206771fe6b9SJerome Glisse } 207771fe6b9SJerome Glisse 208771fe6b9SJerome Glisse static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) 209771fe6b9SJerome Glisse { 210771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 211771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 212771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 213771fe6b9SJerome Glisse int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); 214771fe6b9SJerome Glisse ENABLE_CRTC_PS_ALLOCATION args; 215771fe6b9SJerome Glisse 216771fe6b9SJerome Glisse memset(&args, 0, sizeof(args)); 217771fe6b9SJerome Glisse 218771fe6b9SJerome Glisse args.ucCRTC = radeon_crtc->crtc_id; 219771fe6b9SJerome Glisse args.ucEnable = state; 220771fe6b9SJerome Glisse 221771fe6b9SJerome Glisse atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 222771fe6b9SJerome Glisse } 223771fe6b9SJerome Glisse 224771fe6b9SJerome Glisse static void atombios_blank_crtc(struct drm_crtc *crtc, int state) 225771fe6b9SJerome Glisse { 226771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 227771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 228771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 229771fe6b9SJerome Glisse int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); 230771fe6b9SJerome Glisse BLANK_CRTC_PS_ALLOCATION args; 231771fe6b9SJerome Glisse 232771fe6b9SJerome Glisse memset(&args, 0, sizeof(args)); 233771fe6b9SJerome Glisse 234771fe6b9SJerome Glisse args.ucCRTC = radeon_crtc->crtc_id; 235771fe6b9SJerome Glisse args.ucBlanking = state; 236771fe6b9SJerome Glisse 237771fe6b9SJerome Glisse atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 238771fe6b9SJerome Glisse } 239771fe6b9SJerome Glisse 240771fe6b9SJerome Glisse void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) 241771fe6b9SJerome Glisse { 242771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 243771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 244500b7587SAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 245771fe6b9SJerome Glisse 246771fe6b9SJerome Glisse switch (mode) { 247771fe6b9SJerome Glisse case DRM_MODE_DPMS_ON: 24837b4390eSAlex Deucher atombios_enable_crtc(crtc, ATOM_ENABLE); 249771fe6b9SJerome Glisse if (ASIC_IS_DCE3(rdev)) 25037b4390eSAlex Deucher atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); 25137b4390eSAlex Deucher atombios_blank_crtc(crtc, ATOM_DISABLE); 252bcc1c2a1SAlex Deucher /* XXX re-enable when interrupt support is added */ 253bcc1c2a1SAlex Deucher if (!ASIC_IS_DCE4(rdev)) 254500b7587SAlex Deucher drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); 255500b7587SAlex Deucher radeon_crtc_load_lut(crtc); 256771fe6b9SJerome Glisse break; 257771fe6b9SJerome Glisse case DRM_MODE_DPMS_STANDBY: 258771fe6b9SJerome Glisse case DRM_MODE_DPMS_SUSPEND: 259771fe6b9SJerome Glisse case DRM_MODE_DPMS_OFF: 260bcc1c2a1SAlex Deucher /* XXX re-enable when interrupt support is added */ 261bcc1c2a1SAlex Deucher if (!ASIC_IS_DCE4(rdev)) 262500b7587SAlex Deucher drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); 26337b4390eSAlex Deucher atombios_blank_crtc(crtc, ATOM_ENABLE); 264771fe6b9SJerome Glisse if (ASIC_IS_DCE3(rdev)) 26537b4390eSAlex Deucher atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); 26637b4390eSAlex Deucher atombios_enable_crtc(crtc, ATOM_DISABLE); 267771fe6b9SJerome Glisse break; 268771fe6b9SJerome Glisse } 269771fe6b9SJerome Glisse } 270771fe6b9SJerome Glisse 271771fe6b9SJerome Glisse static void 272771fe6b9SJerome Glisse atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, 2735a9bcaccSAlex Deucher struct drm_display_mode *mode) 274771fe6b9SJerome Glisse { 2755a9bcaccSAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 276771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 277771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 2785a9bcaccSAlex Deucher SET_CRTC_USING_DTD_TIMING_PARAMETERS args; 279771fe6b9SJerome Glisse int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); 2805a9bcaccSAlex Deucher u16 misc = 0; 281771fe6b9SJerome Glisse 2825a9bcaccSAlex Deucher memset(&args, 0, sizeof(args)); 2835a9bcaccSAlex Deucher args.usH_Size = cpu_to_le16(mode->crtc_hdisplay); 2845a9bcaccSAlex Deucher args.usH_Blanking_Time = 2855a9bcaccSAlex Deucher cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay); 2865a9bcaccSAlex Deucher args.usV_Size = cpu_to_le16(mode->crtc_vdisplay); 2875a9bcaccSAlex Deucher args.usV_Blanking_Time = 2885a9bcaccSAlex Deucher cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay); 2895a9bcaccSAlex Deucher args.usH_SyncOffset = 2905a9bcaccSAlex Deucher cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay); 2915a9bcaccSAlex Deucher args.usH_SyncWidth = 2925a9bcaccSAlex Deucher cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 2935a9bcaccSAlex Deucher args.usV_SyncOffset = 2945a9bcaccSAlex Deucher cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay); 2955a9bcaccSAlex Deucher args.usV_SyncWidth = 2965a9bcaccSAlex Deucher cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 2975a9bcaccSAlex Deucher /*args.ucH_Border = mode->hborder;*/ 2985a9bcaccSAlex Deucher /*args.ucV_Border = mode->vborder;*/ 2995a9bcaccSAlex Deucher 3005a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_NVSYNC) 3015a9bcaccSAlex Deucher misc |= ATOM_VSYNC_POLARITY; 3025a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_NHSYNC) 3035a9bcaccSAlex Deucher misc |= ATOM_HSYNC_POLARITY; 3045a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_CSYNC) 3055a9bcaccSAlex Deucher misc |= ATOM_COMPOSITESYNC; 3065a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_INTERLACE) 3075a9bcaccSAlex Deucher misc |= ATOM_INTERLACE; 3085a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 3095a9bcaccSAlex Deucher misc |= ATOM_DOUBLE_CLOCK_MODE; 3105a9bcaccSAlex Deucher 3115a9bcaccSAlex Deucher args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 3125a9bcaccSAlex Deucher args.ucCRTC = radeon_crtc->crtc_id; 313771fe6b9SJerome Glisse 3145a9bcaccSAlex Deucher atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 315771fe6b9SJerome Glisse } 316771fe6b9SJerome Glisse 3175a9bcaccSAlex Deucher static void atombios_crtc_set_timing(struct drm_crtc *crtc, 3185a9bcaccSAlex Deucher struct drm_display_mode *mode) 319771fe6b9SJerome Glisse { 3205a9bcaccSAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 321771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 322771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 3235a9bcaccSAlex Deucher SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; 324771fe6b9SJerome Glisse int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); 3255a9bcaccSAlex Deucher u16 misc = 0; 326771fe6b9SJerome Glisse 3275a9bcaccSAlex Deucher memset(&args, 0, sizeof(args)); 3285a9bcaccSAlex Deucher args.usH_Total = cpu_to_le16(mode->crtc_htotal); 3295a9bcaccSAlex Deucher args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); 3305a9bcaccSAlex Deucher args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); 3315a9bcaccSAlex Deucher args.usH_SyncWidth = 3325a9bcaccSAlex Deucher cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 3335a9bcaccSAlex Deucher args.usV_Total = cpu_to_le16(mode->crtc_vtotal); 3345a9bcaccSAlex Deucher args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); 3355a9bcaccSAlex Deucher args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); 3365a9bcaccSAlex Deucher args.usV_SyncWidth = 3375a9bcaccSAlex Deucher cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 3385a9bcaccSAlex Deucher 3395a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_NVSYNC) 3405a9bcaccSAlex Deucher misc |= ATOM_VSYNC_POLARITY; 3415a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_NHSYNC) 3425a9bcaccSAlex Deucher misc |= ATOM_HSYNC_POLARITY; 3435a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_CSYNC) 3445a9bcaccSAlex Deucher misc |= ATOM_COMPOSITESYNC; 3455a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_INTERLACE) 3465a9bcaccSAlex Deucher misc |= ATOM_INTERLACE; 3475a9bcaccSAlex Deucher if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 3485a9bcaccSAlex Deucher misc |= ATOM_DOUBLE_CLOCK_MODE; 3495a9bcaccSAlex Deucher 3505a9bcaccSAlex Deucher args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 3515a9bcaccSAlex Deucher args.ucCRTC = radeon_crtc->crtc_id; 352771fe6b9SJerome Glisse 3535a9bcaccSAlex Deucher atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 354771fe6b9SJerome Glisse } 355771fe6b9SJerome Glisse 35626b9fc3aSAlex Deucher union atom_enable_ss { 35726b9fc3aSAlex Deucher ENABLE_LVDS_SS_PARAMETERS legacy; 35826b9fc3aSAlex Deucher ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; 35926b9fc3aSAlex Deucher }; 36026b9fc3aSAlex Deucher 361ebbe1cb9SAlex Deucher static void atombios_set_ss(struct drm_crtc *crtc, int enable) 362ebbe1cb9SAlex Deucher { 363ebbe1cb9SAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 364ebbe1cb9SAlex Deucher struct drm_device *dev = crtc->dev; 365ebbe1cb9SAlex Deucher struct radeon_device *rdev = dev->dev_private; 366ebbe1cb9SAlex Deucher struct drm_encoder *encoder = NULL; 367ebbe1cb9SAlex Deucher struct radeon_encoder *radeon_encoder = NULL; 368ebbe1cb9SAlex Deucher struct radeon_encoder_atom_dig *dig = NULL; 369ebbe1cb9SAlex Deucher int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); 37026b9fc3aSAlex Deucher union atom_enable_ss args; 371ebbe1cb9SAlex Deucher uint16_t percentage = 0; 372ebbe1cb9SAlex Deucher uint8_t type = 0, step = 0, delay = 0, range = 0; 373ebbe1cb9SAlex Deucher 374bcc1c2a1SAlex Deucher /* XXX add ss support for DCE4 */ 375bcc1c2a1SAlex Deucher if (ASIC_IS_DCE4(rdev)) 376bcc1c2a1SAlex Deucher return; 377bcc1c2a1SAlex Deucher 378ebbe1cb9SAlex Deucher list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 379ebbe1cb9SAlex Deucher if (encoder->crtc == crtc) { 380ebbe1cb9SAlex Deucher radeon_encoder = to_radeon_encoder(encoder); 381ebbe1cb9SAlex Deucher /* only enable spread spectrum on LVDS */ 382d11aa88bSAlex Deucher if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 383d11aa88bSAlex Deucher dig = radeon_encoder->enc_priv; 384ebbe1cb9SAlex Deucher if (dig && dig->ss) { 385ebbe1cb9SAlex Deucher percentage = dig->ss->percentage; 386ebbe1cb9SAlex Deucher type = dig->ss->type; 387ebbe1cb9SAlex Deucher step = dig->ss->step; 388ebbe1cb9SAlex Deucher delay = dig->ss->delay; 389ebbe1cb9SAlex Deucher range = dig->ss->range; 390ebbe1cb9SAlex Deucher } else if (enable) 391ebbe1cb9SAlex Deucher return; 392d11aa88bSAlex Deucher } else if (enable) 393d11aa88bSAlex Deucher return; 394ebbe1cb9SAlex Deucher break; 395ebbe1cb9SAlex Deucher } 396ebbe1cb9SAlex Deucher } 397ebbe1cb9SAlex Deucher 398ebbe1cb9SAlex Deucher if (!radeon_encoder) 399ebbe1cb9SAlex Deucher return; 400ebbe1cb9SAlex Deucher 401ebbe1cb9SAlex Deucher memset(&args, 0, sizeof(args)); 40226b9fc3aSAlex Deucher if (ASIC_IS_AVIVO(rdev)) { 40326b9fc3aSAlex Deucher args.v1.usSpreadSpectrumPercentage = cpu_to_le16(percentage); 40426b9fc3aSAlex Deucher args.v1.ucSpreadSpectrumType = type; 40526b9fc3aSAlex Deucher args.v1.ucSpreadSpectrumStep = step; 40626b9fc3aSAlex Deucher args.v1.ucSpreadSpectrumDelay = delay; 40726b9fc3aSAlex Deucher args.v1.ucSpreadSpectrumRange = range; 40826b9fc3aSAlex Deucher args.v1.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; 40926b9fc3aSAlex Deucher args.v1.ucEnable = enable; 410ebbe1cb9SAlex Deucher } else { 41126b9fc3aSAlex Deucher args.legacy.usSpreadSpectrumPercentage = cpu_to_le16(percentage); 41226b9fc3aSAlex Deucher args.legacy.ucSpreadSpectrumType = type; 41326b9fc3aSAlex Deucher args.legacy.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2; 41426b9fc3aSAlex Deucher args.legacy.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4; 41526b9fc3aSAlex Deucher args.legacy.ucEnable = enable; 416ebbe1cb9SAlex Deucher } 41726b9fc3aSAlex Deucher atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 418ebbe1cb9SAlex Deucher } 419ebbe1cb9SAlex Deucher 4204eaeca33SAlex Deucher union adjust_pixel_clock { 4214eaeca33SAlex Deucher ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; 422bcc1c2a1SAlex Deucher ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; 4234eaeca33SAlex Deucher }; 4244eaeca33SAlex Deucher 4254eaeca33SAlex Deucher static u32 atombios_adjust_pll(struct drm_crtc *crtc, 4264eaeca33SAlex Deucher struct drm_display_mode *mode, 4274eaeca33SAlex Deucher struct radeon_pll *pll) 428771fe6b9SJerome Glisse { 429771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 430771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 431771fe6b9SJerome Glisse struct drm_encoder *encoder = NULL; 432771fe6b9SJerome Glisse struct radeon_encoder *radeon_encoder = NULL; 4334eaeca33SAlex Deucher u32 adjusted_clock = mode->clock; 434bcc1c2a1SAlex Deucher int encoder_mode = 0; 435fc10332bSAlex Deucher 4364eaeca33SAlex Deucher /* reset the pll flags */ 4374eaeca33SAlex Deucher pll->flags = 0; 438771fe6b9SJerome Glisse 4397c27f87dSAlex Deucher /* select the PLL algo */ 4407c27f87dSAlex Deucher if (ASIC_IS_AVIVO(rdev)) { 4417c27f87dSAlex Deucher if (radeon_new_pll) 4427c27f87dSAlex Deucher pll->algo = PLL_ALGO_AVIVO; 4437c27f87dSAlex Deucher else 4447c27f87dSAlex Deucher pll->algo = PLL_ALGO_LEGACY; 4457c27f87dSAlex Deucher } else 4467c27f87dSAlex Deucher pll->algo = PLL_ALGO_LEGACY; 4477c27f87dSAlex Deucher 448771fe6b9SJerome Glisse if (ASIC_IS_AVIVO(rdev)) { 449eb1300bcSAlex Deucher if ((rdev->family == CHIP_RS600) || 450eb1300bcSAlex Deucher (rdev->family == CHIP_RS690) || 451eb1300bcSAlex Deucher (rdev->family == CHIP_RS740)) 452fc10332bSAlex Deucher pll->flags |= (RADEON_PLL_USE_FRAC_FB_DIV | 453eb1300bcSAlex Deucher RADEON_PLL_PREFER_CLOSEST_LOWER); 454eb1300bcSAlex Deucher 455771fe6b9SJerome Glisse if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ 456fc10332bSAlex Deucher pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 457771fe6b9SJerome Glisse else 458fc10332bSAlex Deucher pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 459771fe6b9SJerome Glisse } else { 460fc10332bSAlex Deucher pll->flags |= RADEON_PLL_LEGACY; 461771fe6b9SJerome Glisse 462771fe6b9SJerome Glisse if (mode->clock > 200000) /* range limits??? */ 463fc10332bSAlex Deucher pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 464771fe6b9SJerome Glisse else 465fc10332bSAlex Deucher pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 466771fe6b9SJerome Glisse 467771fe6b9SJerome Glisse } 468771fe6b9SJerome Glisse 469771fe6b9SJerome Glisse list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 470771fe6b9SJerome Glisse if (encoder->crtc == crtc) { 4714eaeca33SAlex Deucher radeon_encoder = to_radeon_encoder(encoder); 472bcc1c2a1SAlex Deucher encoder_mode = atombios_get_encoder_mode(encoder); 4734eaeca33SAlex Deucher if (ASIC_IS_AVIVO(rdev)) { 4744eaeca33SAlex Deucher /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ 4754eaeca33SAlex Deucher if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) 4764eaeca33SAlex Deucher adjusted_clock = mode->clock * 2; 4777c27f87dSAlex Deucher /* LVDS PLL quirks */ 4787c27f87dSAlex Deucher if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { 4797c27f87dSAlex Deucher struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 4807c27f87dSAlex Deucher pll->algo = dig->pll_algo; 4817c27f87dSAlex Deucher } 4824eaeca33SAlex Deucher } else { 4834eaeca33SAlex Deucher if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 484fc10332bSAlex Deucher pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; 4854eaeca33SAlex Deucher if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) 486fc10332bSAlex Deucher pll->flags |= RADEON_PLL_USE_REF_DIV; 487771fe6b9SJerome Glisse } 4883ce0a23dSJerome Glisse break; 489771fe6b9SJerome Glisse } 490771fe6b9SJerome Glisse } 491771fe6b9SJerome Glisse 4922606c886SAlex Deucher /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock 4932606c886SAlex Deucher * accordingly based on the encoder/transmitter to work around 4942606c886SAlex Deucher * special hw requirements. 4952606c886SAlex Deucher */ 4962606c886SAlex Deucher if (ASIC_IS_DCE3(rdev)) { 4974eaeca33SAlex Deucher union adjust_pixel_clock args; 4984eaeca33SAlex Deucher u8 frev, crev; 4994eaeca33SAlex Deucher int index; 5002606c886SAlex Deucher 5012606c886SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); 5024eaeca33SAlex Deucher atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 5034eaeca33SAlex Deucher &crev); 5044eaeca33SAlex Deucher 5054eaeca33SAlex Deucher memset(&args, 0, sizeof(args)); 5064eaeca33SAlex Deucher 5074eaeca33SAlex Deucher switch (frev) { 5084eaeca33SAlex Deucher case 1: 5094eaeca33SAlex Deucher switch (crev) { 5104eaeca33SAlex Deucher case 1: 5114eaeca33SAlex Deucher case 2: 5124eaeca33SAlex Deucher args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); 5134eaeca33SAlex Deucher args.v1.ucTransmitterID = radeon_encoder->encoder_id; 514bcc1c2a1SAlex Deucher args.v1.ucEncodeMode = encoder_mode; 5154eaeca33SAlex Deucher 5162606c886SAlex Deucher atom_execute_table(rdev->mode_info.atom_context, 5174eaeca33SAlex Deucher index, (uint32_t *)&args); 5184eaeca33SAlex Deucher adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; 5194eaeca33SAlex Deucher break; 520bcc1c2a1SAlex Deucher case 3: 521bcc1c2a1SAlex Deucher args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10); 522bcc1c2a1SAlex Deucher args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; 523bcc1c2a1SAlex Deucher args.v3.sInput.ucEncodeMode = encoder_mode; 524bcc1c2a1SAlex Deucher args.v3.sInput.ucDispPllConfig = 0; 525bcc1c2a1SAlex Deucher if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 526bcc1c2a1SAlex Deucher struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 527bcc1c2a1SAlex Deucher 528bcc1c2a1SAlex Deucher if (encoder_mode == ATOM_ENCODER_MODE_DP) 529bcc1c2a1SAlex Deucher args.v3.sInput.ucDispPllConfig |= 530bcc1c2a1SAlex Deucher DISPPLL_CONFIG_COHERENT_MODE; 531bcc1c2a1SAlex Deucher else { 532bcc1c2a1SAlex Deucher if (dig->coherent_mode) 533bcc1c2a1SAlex Deucher args.v3.sInput.ucDispPllConfig |= 534bcc1c2a1SAlex Deucher DISPPLL_CONFIG_COHERENT_MODE; 535bcc1c2a1SAlex Deucher if (mode->clock > 165000) 536bcc1c2a1SAlex Deucher args.v3.sInput.ucDispPllConfig |= 537bcc1c2a1SAlex Deucher DISPPLL_CONFIG_DUAL_LINK; 538bcc1c2a1SAlex Deucher } 539bcc1c2a1SAlex Deucher } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 540bcc1c2a1SAlex Deucher /* may want to enable SS on DP/eDP eventually */ 541bcc1c2a1SAlex Deucher args.v3.sInput.ucDispPllConfig |= 542bcc1c2a1SAlex Deucher DISPPLL_CONFIG_SS_ENABLE; 543bcc1c2a1SAlex Deucher if (mode->clock > 165000) 544bcc1c2a1SAlex Deucher args.v3.sInput.ucDispPllConfig |= 545bcc1c2a1SAlex Deucher DISPPLL_CONFIG_DUAL_LINK; 546bcc1c2a1SAlex Deucher } 547bcc1c2a1SAlex Deucher atom_execute_table(rdev->mode_info.atom_context, 548bcc1c2a1SAlex Deucher index, (uint32_t *)&args); 549bcc1c2a1SAlex Deucher adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; 550bcc1c2a1SAlex Deucher if (args.v3.sOutput.ucRefDiv) { 551bcc1c2a1SAlex Deucher pll->flags |= RADEON_PLL_USE_REF_DIV; 552bcc1c2a1SAlex Deucher pll->reference_div = args.v3.sOutput.ucRefDiv; 553bcc1c2a1SAlex Deucher } 554bcc1c2a1SAlex Deucher if (args.v3.sOutput.ucPostDiv) { 555bcc1c2a1SAlex Deucher pll->flags |= RADEON_PLL_USE_POST_DIV; 556bcc1c2a1SAlex Deucher pll->post_div = args.v3.sOutput.ucPostDiv; 557bcc1c2a1SAlex Deucher } 558bcc1c2a1SAlex Deucher break; 5594eaeca33SAlex Deucher default: 5604eaeca33SAlex Deucher DRM_ERROR("Unknown table version %d %d\n", frev, crev); 5614eaeca33SAlex Deucher return adjusted_clock; 562d56ef9c8SAlex Deucher } 5634eaeca33SAlex Deucher break; 5644eaeca33SAlex Deucher default: 5654eaeca33SAlex Deucher DRM_ERROR("Unknown table version %d %d\n", frev, crev); 5664eaeca33SAlex Deucher return adjusted_clock; 5674eaeca33SAlex Deucher } 5684eaeca33SAlex Deucher } 5694eaeca33SAlex Deucher return adjusted_clock; 5704eaeca33SAlex Deucher } 5714eaeca33SAlex Deucher 5724eaeca33SAlex Deucher union set_pixel_clock { 5734eaeca33SAlex Deucher SET_PIXEL_CLOCK_PS_ALLOCATION base; 5744eaeca33SAlex Deucher PIXEL_CLOCK_PARAMETERS v1; 5754eaeca33SAlex Deucher PIXEL_CLOCK_PARAMETERS_V2 v2; 5764eaeca33SAlex Deucher PIXEL_CLOCK_PARAMETERS_V3 v3; 577bcc1c2a1SAlex Deucher PIXEL_CLOCK_PARAMETERS_V5 v5; 5784eaeca33SAlex Deucher }; 5794eaeca33SAlex Deucher 580bcc1c2a1SAlex Deucher static void atombios_crtc_set_dcpll(struct drm_crtc *crtc) 581bcc1c2a1SAlex Deucher { 582bcc1c2a1SAlex Deucher struct drm_device *dev = crtc->dev; 583bcc1c2a1SAlex Deucher struct radeon_device *rdev = dev->dev_private; 584bcc1c2a1SAlex Deucher u8 frev, crev; 585bcc1c2a1SAlex Deucher int index; 586bcc1c2a1SAlex Deucher union set_pixel_clock args; 587bcc1c2a1SAlex Deucher 588bcc1c2a1SAlex Deucher memset(&args, 0, sizeof(args)); 589bcc1c2a1SAlex Deucher 590bcc1c2a1SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 591bcc1c2a1SAlex Deucher atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 592bcc1c2a1SAlex Deucher &crev); 593bcc1c2a1SAlex Deucher 594bcc1c2a1SAlex Deucher switch (frev) { 595bcc1c2a1SAlex Deucher case 1: 596bcc1c2a1SAlex Deucher switch (crev) { 597bcc1c2a1SAlex Deucher case 5: 598bcc1c2a1SAlex Deucher /* if the default dcpll clock is specified, 599bcc1c2a1SAlex Deucher * SetPixelClock provides the dividers 600bcc1c2a1SAlex Deucher */ 601bcc1c2a1SAlex Deucher args.v5.ucCRTC = ATOM_CRTC_INVALID; 602bcc1c2a1SAlex Deucher args.v5.usPixelClock = rdev->clock.default_dispclk; 603bcc1c2a1SAlex Deucher args.v5.ucPpll = ATOM_DCPLL; 604bcc1c2a1SAlex Deucher break; 605bcc1c2a1SAlex Deucher default: 606bcc1c2a1SAlex Deucher DRM_ERROR("Unknown table version %d %d\n", frev, crev); 607bcc1c2a1SAlex Deucher return; 608bcc1c2a1SAlex Deucher } 609bcc1c2a1SAlex Deucher break; 610bcc1c2a1SAlex Deucher default: 611bcc1c2a1SAlex Deucher DRM_ERROR("Unknown table version %d %d\n", frev, crev); 612bcc1c2a1SAlex Deucher return; 613bcc1c2a1SAlex Deucher } 614bcc1c2a1SAlex Deucher atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 615bcc1c2a1SAlex Deucher } 616bcc1c2a1SAlex Deucher 617bcc1c2a1SAlex Deucher static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 6184eaeca33SAlex Deucher { 6194eaeca33SAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 6204eaeca33SAlex Deucher struct drm_device *dev = crtc->dev; 6214eaeca33SAlex Deucher struct radeon_device *rdev = dev->dev_private; 6224eaeca33SAlex Deucher struct drm_encoder *encoder = NULL; 6234eaeca33SAlex Deucher struct radeon_encoder *radeon_encoder = NULL; 6244eaeca33SAlex Deucher u8 frev, crev; 6254eaeca33SAlex Deucher int index; 6264eaeca33SAlex Deucher union set_pixel_clock args; 6274eaeca33SAlex Deucher u32 pll_clock = mode->clock; 6284eaeca33SAlex Deucher u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; 6294eaeca33SAlex Deucher struct radeon_pll *pll; 6304eaeca33SAlex Deucher u32 adjusted_clock; 631bcc1c2a1SAlex Deucher int encoder_mode = 0; 6324eaeca33SAlex Deucher 6334eaeca33SAlex Deucher memset(&args, 0, sizeof(args)); 6344eaeca33SAlex Deucher 6354eaeca33SAlex Deucher list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 6364eaeca33SAlex Deucher if (encoder->crtc == crtc) { 6374eaeca33SAlex Deucher radeon_encoder = to_radeon_encoder(encoder); 638bcc1c2a1SAlex Deucher encoder_mode = atombios_get_encoder_mode(encoder); 6394eaeca33SAlex Deucher break; 6404eaeca33SAlex Deucher } 6414eaeca33SAlex Deucher } 6424eaeca33SAlex Deucher 6434eaeca33SAlex Deucher if (!radeon_encoder) 6444eaeca33SAlex Deucher return; 6454eaeca33SAlex Deucher 646bcc1c2a1SAlex Deucher switch (radeon_crtc->pll_id) { 647bcc1c2a1SAlex Deucher case ATOM_PPLL1: 6484eaeca33SAlex Deucher pll = &rdev->clock.p1pll; 649bcc1c2a1SAlex Deucher break; 650bcc1c2a1SAlex Deucher case ATOM_PPLL2: 6514eaeca33SAlex Deucher pll = &rdev->clock.p2pll; 652bcc1c2a1SAlex Deucher break; 653bcc1c2a1SAlex Deucher case ATOM_DCPLL: 654bcc1c2a1SAlex Deucher case ATOM_PPLL_INVALID: 655bcc1c2a1SAlex Deucher pll = &rdev->clock.dcpll; 656bcc1c2a1SAlex Deucher break; 657bcc1c2a1SAlex Deucher } 6584eaeca33SAlex Deucher 6594eaeca33SAlex Deucher /* adjust pixel clock as needed */ 6604eaeca33SAlex Deucher adjusted_clock = atombios_adjust_pll(crtc, mode, pll); 6612606c886SAlex Deucher 6622606c886SAlex Deucher radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, 663fc10332bSAlex Deucher &ref_div, &post_div); 664771fe6b9SJerome Glisse 66539deb2d6SDave Airlie index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 666771fe6b9SJerome Glisse atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 667771fe6b9SJerome Glisse &crev); 668771fe6b9SJerome Glisse 669771fe6b9SJerome Glisse switch (frev) { 670771fe6b9SJerome Glisse case 1: 671771fe6b9SJerome Glisse switch (crev) { 672771fe6b9SJerome Glisse case 1: 6734eaeca33SAlex Deucher args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); 6744eaeca33SAlex Deucher args.v1.usRefDiv = cpu_to_le16(ref_div); 6754eaeca33SAlex Deucher args.v1.usFbDiv = cpu_to_le16(fb_div); 6764eaeca33SAlex Deucher args.v1.ucFracFbDiv = frac_fb_div; 6774eaeca33SAlex Deucher args.v1.ucPostDiv = post_div; 678bcc1c2a1SAlex Deucher args.v1.ucPpll = radeon_crtc->pll_id; 6794eaeca33SAlex Deucher args.v1.ucCRTC = radeon_crtc->crtc_id; 6804eaeca33SAlex Deucher args.v1.ucRefDivSrc = 1; 681771fe6b9SJerome Glisse break; 682771fe6b9SJerome Glisse case 2: 6834eaeca33SAlex Deucher args.v2.usPixelClock = cpu_to_le16(mode->clock / 10); 6844eaeca33SAlex Deucher args.v2.usRefDiv = cpu_to_le16(ref_div); 6854eaeca33SAlex Deucher args.v2.usFbDiv = cpu_to_le16(fb_div); 6864eaeca33SAlex Deucher args.v2.ucFracFbDiv = frac_fb_div; 6874eaeca33SAlex Deucher args.v2.ucPostDiv = post_div; 688bcc1c2a1SAlex Deucher args.v2.ucPpll = radeon_crtc->pll_id; 6894eaeca33SAlex Deucher args.v2.ucCRTC = radeon_crtc->crtc_id; 6904eaeca33SAlex Deucher args.v2.ucRefDivSrc = 1; 691771fe6b9SJerome Glisse break; 692771fe6b9SJerome Glisse case 3: 6934eaeca33SAlex Deucher args.v3.usPixelClock = cpu_to_le16(mode->clock / 10); 6944eaeca33SAlex Deucher args.v3.usRefDiv = cpu_to_le16(ref_div); 6954eaeca33SAlex Deucher args.v3.usFbDiv = cpu_to_le16(fb_div); 6964eaeca33SAlex Deucher args.v3.ucFracFbDiv = frac_fb_div; 6974eaeca33SAlex Deucher args.v3.ucPostDiv = post_div; 698bcc1c2a1SAlex Deucher args.v3.ucPpll = radeon_crtc->pll_id; 699bcc1c2a1SAlex Deucher args.v3.ucMiscInfo = (radeon_crtc->pll_id << 2); 7004eaeca33SAlex Deucher args.v3.ucTransmitterId = radeon_encoder->encoder_id; 701bcc1c2a1SAlex Deucher args.v3.ucEncoderMode = encoder_mode; 702bcc1c2a1SAlex Deucher break; 703bcc1c2a1SAlex Deucher case 5: 704bcc1c2a1SAlex Deucher args.v5.ucCRTC = radeon_crtc->crtc_id; 705bcc1c2a1SAlex Deucher args.v5.usPixelClock = cpu_to_le16(mode->clock / 10); 706bcc1c2a1SAlex Deucher args.v5.ucRefDiv = ref_div; 707bcc1c2a1SAlex Deucher args.v5.usFbDiv = cpu_to_le16(fb_div); 708bcc1c2a1SAlex Deucher args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 709bcc1c2a1SAlex Deucher args.v5.ucPostDiv = post_div; 710bcc1c2a1SAlex Deucher args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ 711bcc1c2a1SAlex Deucher args.v5.ucTransmitterID = radeon_encoder->encoder_id; 712bcc1c2a1SAlex Deucher args.v5.ucEncoderMode = encoder_mode; 713bcc1c2a1SAlex Deucher args.v5.ucPpll = radeon_crtc->pll_id; 714771fe6b9SJerome Glisse break; 715771fe6b9SJerome Glisse default: 716771fe6b9SJerome Glisse DRM_ERROR("Unknown table version %d %d\n", frev, crev); 717771fe6b9SJerome Glisse return; 718771fe6b9SJerome Glisse } 719771fe6b9SJerome Glisse break; 720771fe6b9SJerome Glisse default: 721771fe6b9SJerome Glisse DRM_ERROR("Unknown table version %d %d\n", frev, crev); 722771fe6b9SJerome Glisse return; 723771fe6b9SJerome Glisse } 724771fe6b9SJerome Glisse 725771fe6b9SJerome Glisse atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 726771fe6b9SJerome Glisse } 727771fe6b9SJerome Glisse 728bcc1c2a1SAlex Deucher static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y, 729bcc1c2a1SAlex Deucher struct drm_framebuffer *old_fb) 730bcc1c2a1SAlex Deucher { 731bcc1c2a1SAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 732bcc1c2a1SAlex Deucher struct drm_device *dev = crtc->dev; 733bcc1c2a1SAlex Deucher struct radeon_device *rdev = dev->dev_private; 734bcc1c2a1SAlex Deucher struct radeon_framebuffer *radeon_fb; 735bcc1c2a1SAlex Deucher struct drm_gem_object *obj; 736bcc1c2a1SAlex Deucher struct radeon_bo *rbo; 737bcc1c2a1SAlex Deucher uint64_t fb_location; 738bcc1c2a1SAlex Deucher uint32_t fb_format, fb_pitch_pixels, tiling_flags; 739bcc1c2a1SAlex Deucher int r; 740bcc1c2a1SAlex Deucher 741bcc1c2a1SAlex Deucher /* no fb bound */ 742bcc1c2a1SAlex Deucher if (!crtc->fb) { 743bcc1c2a1SAlex Deucher DRM_DEBUG("No FB bound\n"); 744bcc1c2a1SAlex Deucher return 0; 745bcc1c2a1SAlex Deucher } 746bcc1c2a1SAlex Deucher 747bcc1c2a1SAlex Deucher radeon_fb = to_radeon_framebuffer(crtc->fb); 748bcc1c2a1SAlex Deucher 749bcc1c2a1SAlex Deucher /* Pin framebuffer & get tilling informations */ 750bcc1c2a1SAlex Deucher obj = radeon_fb->obj; 751bcc1c2a1SAlex Deucher rbo = obj->driver_private; 752bcc1c2a1SAlex Deucher r = radeon_bo_reserve(rbo, false); 753bcc1c2a1SAlex Deucher if (unlikely(r != 0)) 754bcc1c2a1SAlex Deucher return r; 755bcc1c2a1SAlex Deucher r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); 756bcc1c2a1SAlex Deucher if (unlikely(r != 0)) { 757bcc1c2a1SAlex Deucher radeon_bo_unreserve(rbo); 758bcc1c2a1SAlex Deucher return -EINVAL; 759bcc1c2a1SAlex Deucher } 760bcc1c2a1SAlex Deucher radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 761bcc1c2a1SAlex Deucher radeon_bo_unreserve(rbo); 762bcc1c2a1SAlex Deucher 763bcc1c2a1SAlex Deucher switch (crtc->fb->bits_per_pixel) { 764bcc1c2a1SAlex Deucher case 8: 765bcc1c2a1SAlex Deucher fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | 766bcc1c2a1SAlex Deucher EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); 767bcc1c2a1SAlex Deucher break; 768bcc1c2a1SAlex Deucher case 15: 769bcc1c2a1SAlex Deucher fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 770bcc1c2a1SAlex Deucher EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); 771bcc1c2a1SAlex Deucher break; 772bcc1c2a1SAlex Deucher case 16: 773bcc1c2a1SAlex Deucher fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 774bcc1c2a1SAlex Deucher EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); 775bcc1c2a1SAlex Deucher break; 776bcc1c2a1SAlex Deucher case 24: 777bcc1c2a1SAlex Deucher case 32: 778bcc1c2a1SAlex Deucher fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 779bcc1c2a1SAlex Deucher EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); 780bcc1c2a1SAlex Deucher break; 781bcc1c2a1SAlex Deucher default: 782bcc1c2a1SAlex Deucher DRM_ERROR("Unsupported screen depth %d\n", 783bcc1c2a1SAlex Deucher crtc->fb->bits_per_pixel); 784bcc1c2a1SAlex Deucher return -EINVAL; 785bcc1c2a1SAlex Deucher } 786bcc1c2a1SAlex Deucher 787bcc1c2a1SAlex Deucher switch (radeon_crtc->crtc_id) { 788bcc1c2a1SAlex Deucher case 0: 789bcc1c2a1SAlex Deucher WREG32(AVIVO_D1VGA_CONTROL, 0); 790bcc1c2a1SAlex Deucher break; 791bcc1c2a1SAlex Deucher case 1: 792bcc1c2a1SAlex Deucher WREG32(AVIVO_D2VGA_CONTROL, 0); 793bcc1c2a1SAlex Deucher break; 794bcc1c2a1SAlex Deucher case 2: 795bcc1c2a1SAlex Deucher WREG32(EVERGREEN_D3VGA_CONTROL, 0); 796bcc1c2a1SAlex Deucher break; 797bcc1c2a1SAlex Deucher case 3: 798bcc1c2a1SAlex Deucher WREG32(EVERGREEN_D4VGA_CONTROL, 0); 799bcc1c2a1SAlex Deucher break; 800bcc1c2a1SAlex Deucher case 4: 801bcc1c2a1SAlex Deucher WREG32(EVERGREEN_D5VGA_CONTROL, 0); 802bcc1c2a1SAlex Deucher break; 803bcc1c2a1SAlex Deucher case 5: 804bcc1c2a1SAlex Deucher WREG32(EVERGREEN_D6VGA_CONTROL, 0); 805bcc1c2a1SAlex Deucher break; 806bcc1c2a1SAlex Deucher default: 807bcc1c2a1SAlex Deucher break; 808bcc1c2a1SAlex Deucher } 809bcc1c2a1SAlex Deucher 810bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 811bcc1c2a1SAlex Deucher upper_32_bits(fb_location)); 812bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 813bcc1c2a1SAlex Deucher upper_32_bits(fb_location)); 814bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 815bcc1c2a1SAlex Deucher (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 816bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 817bcc1c2a1SAlex Deucher (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 818bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 819bcc1c2a1SAlex Deucher 820bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 821bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 822bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); 823bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); 824bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width); 825bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height); 826bcc1c2a1SAlex Deucher 827bcc1c2a1SAlex Deucher fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8); 828bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 829bcc1c2a1SAlex Deucher WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 830bcc1c2a1SAlex Deucher 831bcc1c2a1SAlex Deucher WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 832bcc1c2a1SAlex Deucher crtc->mode.vdisplay); 833bcc1c2a1SAlex Deucher x &= ~3; 834bcc1c2a1SAlex Deucher y &= ~1; 835bcc1c2a1SAlex Deucher WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, 836bcc1c2a1SAlex Deucher (x << 16) | y); 837bcc1c2a1SAlex Deucher WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 838bcc1c2a1SAlex Deucher (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); 839bcc1c2a1SAlex Deucher 840bcc1c2a1SAlex Deucher if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) 841bcc1c2a1SAlex Deucher WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 842bcc1c2a1SAlex Deucher EVERGREEN_INTERLEAVE_EN); 843bcc1c2a1SAlex Deucher else 844bcc1c2a1SAlex Deucher WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 845bcc1c2a1SAlex Deucher 846bcc1c2a1SAlex Deucher if (old_fb && old_fb != crtc->fb) { 847bcc1c2a1SAlex Deucher radeon_fb = to_radeon_framebuffer(old_fb); 848bcc1c2a1SAlex Deucher rbo = radeon_fb->obj->driver_private; 849bcc1c2a1SAlex Deucher r = radeon_bo_reserve(rbo, false); 850bcc1c2a1SAlex Deucher if (unlikely(r != 0)) 851bcc1c2a1SAlex Deucher return r; 852bcc1c2a1SAlex Deucher radeon_bo_unpin(rbo); 853bcc1c2a1SAlex Deucher radeon_bo_unreserve(rbo); 854bcc1c2a1SAlex Deucher } 855bcc1c2a1SAlex Deucher 856bcc1c2a1SAlex Deucher /* Bytes per pixel may have changed */ 857bcc1c2a1SAlex Deucher radeon_bandwidth_update(rdev); 858bcc1c2a1SAlex Deucher 859bcc1c2a1SAlex Deucher return 0; 860bcc1c2a1SAlex Deucher } 861bcc1c2a1SAlex Deucher 86254f088a9SAlex Deucher static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y, 863771fe6b9SJerome Glisse struct drm_framebuffer *old_fb) 864771fe6b9SJerome Glisse { 865771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 866771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 867771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 868771fe6b9SJerome Glisse struct radeon_framebuffer *radeon_fb; 869771fe6b9SJerome Glisse struct drm_gem_object *obj; 8704c788679SJerome Glisse struct radeon_bo *rbo; 871771fe6b9SJerome Glisse uint64_t fb_location; 872e024e110SDave Airlie uint32_t fb_format, fb_pitch_pixels, tiling_flags; 8734c788679SJerome Glisse int r; 874771fe6b9SJerome Glisse 8752de3b484SJerome Glisse /* no fb bound */ 8762de3b484SJerome Glisse if (!crtc->fb) { 8772de3b484SJerome Glisse DRM_DEBUG("No FB bound\n"); 8782de3b484SJerome Glisse return 0; 8792de3b484SJerome Glisse } 880771fe6b9SJerome Glisse 881771fe6b9SJerome Glisse radeon_fb = to_radeon_framebuffer(crtc->fb); 882771fe6b9SJerome Glisse 8834c788679SJerome Glisse /* Pin framebuffer & get tilling informations */ 884771fe6b9SJerome Glisse obj = radeon_fb->obj; 8854c788679SJerome Glisse rbo = obj->driver_private; 8864c788679SJerome Glisse r = radeon_bo_reserve(rbo, false); 8874c788679SJerome Glisse if (unlikely(r != 0)) 8884c788679SJerome Glisse return r; 8894c788679SJerome Glisse r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); 8904c788679SJerome Glisse if (unlikely(r != 0)) { 8914c788679SJerome Glisse radeon_bo_unreserve(rbo); 892771fe6b9SJerome Glisse return -EINVAL; 893771fe6b9SJerome Glisse } 8944c788679SJerome Glisse radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 8954c788679SJerome Glisse radeon_bo_unreserve(rbo); 896771fe6b9SJerome Glisse 897771fe6b9SJerome Glisse switch (crtc->fb->bits_per_pixel) { 89841456df2SDave Airlie case 8: 89941456df2SDave Airlie fb_format = 90041456df2SDave Airlie AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | 90141456df2SDave Airlie AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; 90241456df2SDave Airlie break; 903771fe6b9SJerome Glisse case 15: 904771fe6b9SJerome Glisse fb_format = 905771fe6b9SJerome Glisse AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 906771fe6b9SJerome Glisse AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; 907771fe6b9SJerome Glisse break; 908771fe6b9SJerome Glisse case 16: 909771fe6b9SJerome Glisse fb_format = 910771fe6b9SJerome Glisse AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 911771fe6b9SJerome Glisse AVIVO_D1GRPH_CONTROL_16BPP_RGB565; 912771fe6b9SJerome Glisse break; 913771fe6b9SJerome Glisse case 24: 914771fe6b9SJerome Glisse case 32: 915771fe6b9SJerome Glisse fb_format = 916771fe6b9SJerome Glisse AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | 917771fe6b9SJerome Glisse AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; 918771fe6b9SJerome Glisse break; 919771fe6b9SJerome Glisse default: 920771fe6b9SJerome Glisse DRM_ERROR("Unsupported screen depth %d\n", 921771fe6b9SJerome Glisse crtc->fb->bits_per_pixel); 922771fe6b9SJerome Glisse return -EINVAL; 923771fe6b9SJerome Glisse } 924771fe6b9SJerome Glisse 925cf2f05d3SDave Airlie if (tiling_flags & RADEON_TILING_MACRO) 926cf2f05d3SDave Airlie fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; 927cf2f05d3SDave Airlie 928e024e110SDave Airlie if (tiling_flags & RADEON_TILING_MICRO) 929e024e110SDave Airlie fb_format |= AVIVO_D1GRPH_TILED; 930e024e110SDave Airlie 931771fe6b9SJerome Glisse if (radeon_crtc->crtc_id == 0) 932771fe6b9SJerome Glisse WREG32(AVIVO_D1VGA_CONTROL, 0); 933771fe6b9SJerome Glisse else 934771fe6b9SJerome Glisse WREG32(AVIVO_D2VGA_CONTROL, 0); 935c290dadfSAlex Deucher 936c290dadfSAlex Deucher if (rdev->family >= CHIP_RV770) { 937c290dadfSAlex Deucher if (radeon_crtc->crtc_id) { 938c290dadfSAlex Deucher WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0); 939c290dadfSAlex Deucher WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0); 940c290dadfSAlex Deucher } else { 941c290dadfSAlex Deucher WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0); 942c290dadfSAlex Deucher WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0); 943c290dadfSAlex Deucher } 944c290dadfSAlex Deucher } 945771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 946771fe6b9SJerome Glisse (u32) fb_location); 947771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + 948771fe6b9SJerome Glisse radeon_crtc->crtc_offset, (u32) fb_location); 949771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 950771fe6b9SJerome Glisse 951771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 952771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 953771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); 954771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); 955771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width); 956771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height); 957771fe6b9SJerome Glisse 958771fe6b9SJerome Glisse fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8); 959771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 960771fe6b9SJerome Glisse WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 961771fe6b9SJerome Glisse 962771fe6b9SJerome Glisse WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 963771fe6b9SJerome Glisse crtc->mode.vdisplay); 964771fe6b9SJerome Glisse x &= ~3; 965771fe6b9SJerome Glisse y &= ~1; 966771fe6b9SJerome Glisse WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, 967771fe6b9SJerome Glisse (x << 16) | y); 968771fe6b9SJerome Glisse WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 969771fe6b9SJerome Glisse (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); 970771fe6b9SJerome Glisse 971771fe6b9SJerome Glisse if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) 972771fe6b9SJerome Glisse WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 973771fe6b9SJerome Glisse AVIVO_D1MODE_INTERLEAVE_EN); 974771fe6b9SJerome Glisse else 975771fe6b9SJerome Glisse WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 976771fe6b9SJerome Glisse 977771fe6b9SJerome Glisse if (old_fb && old_fb != crtc->fb) { 978771fe6b9SJerome Glisse radeon_fb = to_radeon_framebuffer(old_fb); 9794c788679SJerome Glisse rbo = radeon_fb->obj->driver_private; 9804c788679SJerome Glisse r = radeon_bo_reserve(rbo, false); 9814c788679SJerome Glisse if (unlikely(r != 0)) 9824c788679SJerome Glisse return r; 9834c788679SJerome Glisse radeon_bo_unpin(rbo); 9844c788679SJerome Glisse radeon_bo_unreserve(rbo); 985771fe6b9SJerome Glisse } 986f30f37deSMichel Dänzer 987f30f37deSMichel Dänzer /* Bytes per pixel may have changed */ 988f30f37deSMichel Dänzer radeon_bandwidth_update(rdev); 989f30f37deSMichel Dänzer 990771fe6b9SJerome Glisse return 0; 991771fe6b9SJerome Glisse } 992771fe6b9SJerome Glisse 99354f088a9SAlex Deucher int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 99454f088a9SAlex Deucher struct drm_framebuffer *old_fb) 99554f088a9SAlex Deucher { 99654f088a9SAlex Deucher struct drm_device *dev = crtc->dev; 99754f088a9SAlex Deucher struct radeon_device *rdev = dev->dev_private; 99854f088a9SAlex Deucher 999bcc1c2a1SAlex Deucher if (ASIC_IS_DCE4(rdev)) 1000bcc1c2a1SAlex Deucher return evergreen_crtc_set_base(crtc, x, y, old_fb); 1001bcc1c2a1SAlex Deucher else if (ASIC_IS_AVIVO(rdev)) 100254f088a9SAlex Deucher return avivo_crtc_set_base(crtc, x, y, old_fb); 100354f088a9SAlex Deucher else 100454f088a9SAlex Deucher return radeon_crtc_set_base(crtc, x, y, old_fb); 100554f088a9SAlex Deucher } 100654f088a9SAlex Deucher 1007615e0cb6SAlex Deucher /* properly set additional regs when using atombios */ 1008615e0cb6SAlex Deucher static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) 1009615e0cb6SAlex Deucher { 1010615e0cb6SAlex Deucher struct drm_device *dev = crtc->dev; 1011615e0cb6SAlex Deucher struct radeon_device *rdev = dev->dev_private; 1012615e0cb6SAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1013615e0cb6SAlex Deucher u32 disp_merge_cntl; 1014615e0cb6SAlex Deucher 1015615e0cb6SAlex Deucher switch (radeon_crtc->crtc_id) { 1016615e0cb6SAlex Deucher case 0: 1017615e0cb6SAlex Deucher disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); 1018615e0cb6SAlex Deucher disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 1019615e0cb6SAlex Deucher WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); 1020615e0cb6SAlex Deucher break; 1021615e0cb6SAlex Deucher case 1: 1022615e0cb6SAlex Deucher disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 1023615e0cb6SAlex Deucher disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 1024615e0cb6SAlex Deucher WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); 1025615e0cb6SAlex Deucher WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); 1026615e0cb6SAlex Deucher WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); 1027615e0cb6SAlex Deucher break; 1028615e0cb6SAlex Deucher } 1029615e0cb6SAlex Deucher } 1030615e0cb6SAlex Deucher 1031bcc1c2a1SAlex Deucher static int radeon_atom_pick_pll(struct drm_crtc *crtc) 1032bcc1c2a1SAlex Deucher { 1033bcc1c2a1SAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1034bcc1c2a1SAlex Deucher struct drm_device *dev = crtc->dev; 1035bcc1c2a1SAlex Deucher struct radeon_device *rdev = dev->dev_private; 1036bcc1c2a1SAlex Deucher struct drm_encoder *test_encoder; 1037bcc1c2a1SAlex Deucher struct drm_crtc *test_crtc; 1038bcc1c2a1SAlex Deucher uint32_t pll_in_use = 0; 1039bcc1c2a1SAlex Deucher 1040bcc1c2a1SAlex Deucher if (ASIC_IS_DCE4(rdev)) { 1041bcc1c2a1SAlex Deucher /* if crtc is driving DP and we have an ext clock, use that */ 1042bcc1c2a1SAlex Deucher list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 1043bcc1c2a1SAlex Deucher if (test_encoder->crtc && (test_encoder->crtc == crtc)) { 1044bcc1c2a1SAlex Deucher if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) { 1045bcc1c2a1SAlex Deucher if (rdev->clock.dp_extclk) 1046bcc1c2a1SAlex Deucher return ATOM_PPLL_INVALID; 1047bcc1c2a1SAlex Deucher } 1048bcc1c2a1SAlex Deucher } 1049bcc1c2a1SAlex Deucher } 1050bcc1c2a1SAlex Deucher 1051bcc1c2a1SAlex Deucher /* otherwise, pick one of the plls */ 1052bcc1c2a1SAlex Deucher list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1053bcc1c2a1SAlex Deucher struct radeon_crtc *radeon_test_crtc; 1054bcc1c2a1SAlex Deucher 1055bcc1c2a1SAlex Deucher if (crtc == test_crtc) 1056bcc1c2a1SAlex Deucher continue; 1057bcc1c2a1SAlex Deucher 1058bcc1c2a1SAlex Deucher radeon_test_crtc = to_radeon_crtc(test_crtc); 1059bcc1c2a1SAlex Deucher if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) && 1060bcc1c2a1SAlex Deucher (radeon_test_crtc->pll_id <= ATOM_PPLL2)) 1061bcc1c2a1SAlex Deucher pll_in_use |= (1 << radeon_test_crtc->pll_id); 1062bcc1c2a1SAlex Deucher } 1063bcc1c2a1SAlex Deucher if (!(pll_in_use & 1)) 1064bcc1c2a1SAlex Deucher return ATOM_PPLL1; 1065bcc1c2a1SAlex Deucher return ATOM_PPLL2; 1066bcc1c2a1SAlex Deucher } else 1067bcc1c2a1SAlex Deucher return radeon_crtc->crtc_id; 1068bcc1c2a1SAlex Deucher 1069bcc1c2a1SAlex Deucher } 1070bcc1c2a1SAlex Deucher 1071771fe6b9SJerome Glisse int atombios_crtc_mode_set(struct drm_crtc *crtc, 1072771fe6b9SJerome Glisse struct drm_display_mode *mode, 1073771fe6b9SJerome Glisse struct drm_display_mode *adjusted_mode, 1074771fe6b9SJerome Glisse int x, int y, struct drm_framebuffer *old_fb) 1075771fe6b9SJerome Glisse { 1076771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1077771fe6b9SJerome Glisse struct drm_device *dev = crtc->dev; 1078771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 1079771fe6b9SJerome Glisse 1080771fe6b9SJerome Glisse /* TODO color tiling */ 1081771fe6b9SJerome Glisse 1082bcc1c2a1SAlex Deucher /* pick pll */ 1083bcc1c2a1SAlex Deucher radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); 1084bcc1c2a1SAlex Deucher 1085ebbe1cb9SAlex Deucher atombios_set_ss(crtc, 0); 1086bcc1c2a1SAlex Deucher /* always set DCPLL */ 1087bcc1c2a1SAlex Deucher if (ASIC_IS_DCE4(rdev)) 1088bcc1c2a1SAlex Deucher atombios_crtc_set_dcpll(crtc); 1089771fe6b9SJerome Glisse atombios_crtc_set_pll(crtc, adjusted_mode); 1090ebbe1cb9SAlex Deucher atombios_set_ss(crtc, 1); 1091771fe6b9SJerome Glisse 1092bcc1c2a1SAlex Deucher if (ASIC_IS_DCE4(rdev)) 1093bcc1c2a1SAlex Deucher atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1094bcc1c2a1SAlex Deucher else if (ASIC_IS_AVIVO(rdev)) 1095bcc1c2a1SAlex Deucher atombios_crtc_set_timing(crtc, adjusted_mode); 1096771fe6b9SJerome Glisse else { 1097bcc1c2a1SAlex Deucher atombios_crtc_set_timing(crtc, adjusted_mode); 10985a9bcaccSAlex Deucher if (radeon_crtc->crtc_id == 0) 10995a9bcaccSAlex Deucher atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1100615e0cb6SAlex Deucher radeon_legacy_atom_fixup(crtc); 1101771fe6b9SJerome Glisse } 1102bcc1c2a1SAlex Deucher atombios_crtc_set_base(crtc, x, y, old_fb); 1103c93bb85bSJerome Glisse atombios_overscan_setup(crtc, mode, adjusted_mode); 1104c93bb85bSJerome Glisse atombios_scaler_setup(crtc); 1105771fe6b9SJerome Glisse return 0; 1106771fe6b9SJerome Glisse } 1107771fe6b9SJerome Glisse 1108771fe6b9SJerome Glisse static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, 1109771fe6b9SJerome Glisse struct drm_display_mode *mode, 1110771fe6b9SJerome Glisse struct drm_display_mode *adjusted_mode) 1111771fe6b9SJerome Glisse { 1112c93bb85bSJerome Glisse if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 1113c93bb85bSJerome Glisse return false; 1114771fe6b9SJerome Glisse return true; 1115771fe6b9SJerome Glisse } 1116771fe6b9SJerome Glisse 1117771fe6b9SJerome Glisse static void atombios_crtc_prepare(struct drm_crtc *crtc) 1118771fe6b9SJerome Glisse { 111937b4390eSAlex Deucher atombios_lock_crtc(crtc, ATOM_ENABLE); 1120a348c84dSAlex Deucher atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1121771fe6b9SJerome Glisse } 1122771fe6b9SJerome Glisse 1123771fe6b9SJerome Glisse static void atombios_crtc_commit(struct drm_crtc *crtc) 1124771fe6b9SJerome Glisse { 1125771fe6b9SJerome Glisse atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 112637b4390eSAlex Deucher atombios_lock_crtc(crtc, ATOM_DISABLE); 1127771fe6b9SJerome Glisse } 1128771fe6b9SJerome Glisse 1129771fe6b9SJerome Glisse static const struct drm_crtc_helper_funcs atombios_helper_funcs = { 1130771fe6b9SJerome Glisse .dpms = atombios_crtc_dpms, 1131771fe6b9SJerome Glisse .mode_fixup = atombios_crtc_mode_fixup, 1132771fe6b9SJerome Glisse .mode_set = atombios_crtc_mode_set, 1133771fe6b9SJerome Glisse .mode_set_base = atombios_crtc_set_base, 1134771fe6b9SJerome Glisse .prepare = atombios_crtc_prepare, 1135771fe6b9SJerome Glisse .commit = atombios_crtc_commit, 1136068143d3SDave Airlie .load_lut = radeon_crtc_load_lut, 1137771fe6b9SJerome Glisse }; 1138771fe6b9SJerome Glisse 1139771fe6b9SJerome Glisse void radeon_atombios_init_crtc(struct drm_device *dev, 1140771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc) 1141771fe6b9SJerome Glisse { 1142bcc1c2a1SAlex Deucher struct radeon_device *rdev = dev->dev_private; 1143bcc1c2a1SAlex Deucher 1144bcc1c2a1SAlex Deucher if (ASIC_IS_DCE4(rdev)) { 1145bcc1c2a1SAlex Deucher switch (radeon_crtc->crtc_id) { 1146bcc1c2a1SAlex Deucher case 0: 1147bcc1c2a1SAlex Deucher default: 1148bcc1c2a1SAlex Deucher radeon_crtc->crtc_id = EVERGREEN_CRTC0_REGISTER_OFFSET; 1149bcc1c2a1SAlex Deucher break; 1150bcc1c2a1SAlex Deucher case 1: 1151bcc1c2a1SAlex Deucher radeon_crtc->crtc_id = EVERGREEN_CRTC1_REGISTER_OFFSET; 1152bcc1c2a1SAlex Deucher break; 1153bcc1c2a1SAlex Deucher case 2: 1154bcc1c2a1SAlex Deucher radeon_crtc->crtc_id = EVERGREEN_CRTC2_REGISTER_OFFSET; 1155bcc1c2a1SAlex Deucher break; 1156bcc1c2a1SAlex Deucher case 3: 1157bcc1c2a1SAlex Deucher radeon_crtc->crtc_id = EVERGREEN_CRTC3_REGISTER_OFFSET; 1158bcc1c2a1SAlex Deucher break; 1159bcc1c2a1SAlex Deucher case 4: 1160bcc1c2a1SAlex Deucher radeon_crtc->crtc_id = EVERGREEN_CRTC4_REGISTER_OFFSET; 1161bcc1c2a1SAlex Deucher break; 1162bcc1c2a1SAlex Deucher case 5: 1163bcc1c2a1SAlex Deucher radeon_crtc->crtc_id = EVERGREEN_CRTC5_REGISTER_OFFSET; 1164bcc1c2a1SAlex Deucher break; 1165bcc1c2a1SAlex Deucher } 1166bcc1c2a1SAlex Deucher } else { 1167771fe6b9SJerome Glisse if (radeon_crtc->crtc_id == 1) 1168771fe6b9SJerome Glisse radeon_crtc->crtc_offset = 1169771fe6b9SJerome Glisse AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; 1170bcc1c2a1SAlex Deucher else 1171bcc1c2a1SAlex Deucher radeon_crtc->crtc_offset = 0; 1172bcc1c2a1SAlex Deucher } 1173bcc1c2a1SAlex Deucher radeon_crtc->pll_id = -1; 1174771fe6b9SJerome Glisse drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); 1175771fe6b9SJerome Glisse } 1176