1bed41005STom Cooksey /* 2bed41005STom Cooksey * 3bed41005STom Cooksey * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved. 4bed41005STom Cooksey * 5bed41005STom Cooksey * 6bed41005STom Cooksey * Parts of this file were based on sources as follows: 7bed41005STom Cooksey * 8bed41005STom Cooksey * Copyright (c) 2006-2008 Intel Corporation 9bed41005STom Cooksey * Copyright (c) 2007 Dave Airlie <airlied@linux.ie> 10bed41005STom Cooksey * Copyright (C) 2011 Texas Instruments 11bed41005STom Cooksey * 12bed41005STom Cooksey * This program is free software and is provided to you under the terms of the 13bed41005STom Cooksey * GNU General Public License version 2 as published by the Free Software 14bed41005STom Cooksey * Foundation, and any use by you of this program is subject to the terms of 15bed41005STom Cooksey * such GNU licence. 16bed41005STom Cooksey * 17bed41005STom Cooksey */ 18bed41005STom Cooksey 19bed41005STom Cooksey #ifndef _PL111_DRM_H_ 20bed41005STom Cooksey #define _PL111_DRM_H_ 21bed41005STom Cooksey 22bed41005STom Cooksey #include <drm/drm_gem.h> 23bed41005STom Cooksey #include <drm/drm_simple_kms_helper.h> 24001485d5SLinus Walleij #include <drm/drm_connector.h> 25001485d5SLinus Walleij #include <drm/drm_encoder.h> 26001485d5SLinus Walleij #include <drm/drm_panel.h> 27001485d5SLinus Walleij #include <drm/drm_bridge.h> 28032838f9SEric Anholt #include <linux/clk-provider.h> 29bed41005STom Cooksey 30bed41005STom Cooksey #define CLCD_IRQ_NEXTBASE_UPDATE BIT(2) 31bed41005STom Cooksey 32141518d2SEric Anholt struct drm_minor; 33141518d2SEric Anholt 34fa83306cSLinus Walleij /** 35fa83306cSLinus Walleij * struct pl111_variant_data - encodes IP differences 36fa83306cSLinus Walleij * @name: the name of this variant 37fa83306cSLinus Walleij * @is_pl110: this is the early PL110 variant 38fa83306cSLinus Walleij * @formats: array of supported pixel formats on this variant 39fa83306cSLinus Walleij * @nformats: the length of the array of supported pixel formats 40fa83306cSLinus Walleij */ 41fa83306cSLinus Walleij struct pl111_variant_data { 42fa83306cSLinus Walleij const char *name; 43fa83306cSLinus Walleij bool is_pl110; 44fa83306cSLinus Walleij const u32 *formats; 45fa83306cSLinus Walleij unsigned int nformats; 46fa83306cSLinus Walleij }; 47fa83306cSLinus Walleij 48bed41005STom Cooksey struct pl111_drm_dev_private { 49bed41005STom Cooksey struct drm_device *drm; 50bed41005STom Cooksey 51001485d5SLinus Walleij struct drm_connector *connector; 52001485d5SLinus Walleij struct drm_panel *panel; 53001485d5SLinus Walleij struct drm_bridge *bridge; 54bed41005STom Cooksey struct drm_simple_display_pipe pipe; 55bed41005STom Cooksey struct drm_fbdev_cma *fbdev; 56bed41005STom Cooksey 57bed41005STom Cooksey void *regs; 58fa83306cSLinus Walleij u32 ienb; 59fa83306cSLinus Walleij u32 ctrl; 60032838f9SEric Anholt /* The pixel clock (a reference to our clock divider off of CLCDCLK). */ 61bed41005STom Cooksey struct clk *clk; 62032838f9SEric Anholt /* pl111's internal clock divider. */ 63032838f9SEric Anholt struct clk_hw clk_div; 64032838f9SEric Anholt /* Lock to sync access to CLCD_TIM2 between the common clock 65032838f9SEric Anholt * subsystem and pl111_display_enable(). 66032838f9SEric Anholt */ 67032838f9SEric Anholt spinlock_t tim2_lock; 68fa83306cSLinus Walleij const struct pl111_variant_data *variant; 69bed41005STom Cooksey }; 70bed41005STom Cooksey 71bed41005STom Cooksey int pl111_display_init(struct drm_device *dev); 72bed41005STom Cooksey int pl111_enable_vblank(struct drm_device *drm, unsigned int crtc); 73bed41005STom Cooksey void pl111_disable_vblank(struct drm_device *drm, unsigned int crtc); 74bed41005STom Cooksey irqreturn_t pl111_irq(int irq, void *data); 75141518d2SEric Anholt int pl111_debugfs_init(struct drm_minor *minor); 76bed41005STom Cooksey 77bed41005STom Cooksey #endif /* _PL111_DRM_H_ */ 78