1 /* 2 * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved. 3 * 4 * Parts of this file were based on sources as follows: 5 * 6 * Copyright (c) 2006-2008 Intel Corporation 7 * Copyright (c) 2007 Dave Airlie <airlied@linux.ie> 8 * Copyright (C) 2011 Texas Instruments 9 * 10 * This program is free software and is provided to you under the terms of the 11 * GNU General Public License version 2 as published by the Free Software 12 * Foundation, and any use by you of this program is subject to the terms of 13 * such GNU licence. 14 * 15 */ 16 17 #include <linux/amba/clcd-regs.h> 18 #include <linux/clk.h> 19 #include <linux/version.h> 20 #include <linux/dma-buf.h> 21 #include <linux/of_graph.h> 22 23 #include <drm/drmP.h> 24 #include <drm/drm_gem_cma_helper.h> 25 #include <drm/drm_gem_framebuffer_helper.h> 26 #include <drm/drm_fb_cma_helper.h> 27 28 #include "pl111_drm.h" 29 30 irqreturn_t pl111_irq(int irq, void *data) 31 { 32 struct pl111_drm_dev_private *priv = data; 33 u32 irq_stat; 34 irqreturn_t status = IRQ_NONE; 35 36 irq_stat = readl(priv->regs + CLCD_PL111_MIS); 37 38 if (!irq_stat) 39 return IRQ_NONE; 40 41 if (irq_stat & CLCD_IRQ_NEXTBASE_UPDATE) { 42 drm_crtc_handle_vblank(&priv->pipe.crtc); 43 44 status = IRQ_HANDLED; 45 } 46 47 /* Clear the interrupt once done */ 48 writel(irq_stat, priv->regs + CLCD_PL111_ICR); 49 50 return status; 51 } 52 53 static enum drm_mode_status 54 pl111_mode_valid(struct drm_crtc *crtc, 55 const struct drm_display_mode *mode) 56 { 57 struct drm_device *drm = crtc->dev; 58 struct pl111_drm_dev_private *priv = drm->dev_private; 59 u32 cpp = priv->variant->fb_bpp / 8; 60 u64 bw; 61 62 /* 63 * We use the pixelclock to also account for interlaced modes, the 64 * resulting bandwidth is in bytes per second. 65 */ 66 bw = mode->clock * 1000; /* In Hz */ 67 bw = bw * mode->hdisplay * mode->vdisplay * cpp; 68 bw = div_u64(bw, mode->htotal * mode->vtotal); 69 70 /* 71 * If no bandwidth constraints, anything goes, else 72 * check if we are too fast. 73 */ 74 if (priv->memory_bw && (bw > priv->memory_bw)) { 75 DRM_DEBUG_KMS("%d x %d @ %d Hz, %d cpp, bw %llu too fast\n", 76 mode->hdisplay, mode->vdisplay, 77 mode->clock * 1000, cpp, bw); 78 79 return MODE_BAD; 80 } 81 DRM_DEBUG_KMS("%d x %d @ %d Hz, %d cpp, bw %llu bytes/s OK\n", 82 mode->hdisplay, mode->vdisplay, 83 mode->clock * 1000, cpp, bw); 84 85 return MODE_OK; 86 } 87 88 static int pl111_display_check(struct drm_simple_display_pipe *pipe, 89 struct drm_plane_state *pstate, 90 struct drm_crtc_state *cstate) 91 { 92 const struct drm_display_mode *mode = &cstate->mode; 93 struct drm_framebuffer *old_fb = pipe->plane.state->fb; 94 struct drm_framebuffer *fb = pstate->fb; 95 96 if (mode->hdisplay % 16) 97 return -EINVAL; 98 99 if (fb) { 100 u32 offset = drm_fb_cma_get_gem_addr(fb, pstate, 0); 101 102 /* FB base address must be dword aligned. */ 103 if (offset & 3) 104 return -EINVAL; 105 106 /* There's no pitch register -- the mode's hdisplay 107 * controls it. 108 */ 109 if (fb->pitches[0] != mode->hdisplay * fb->format->cpp[0]) 110 return -EINVAL; 111 112 /* We can't change the FB format in a flicker-free 113 * manner (and only update it during CRTC enable). 114 */ 115 if (old_fb && old_fb->format != fb->format) 116 cstate->mode_changed = true; 117 } 118 119 return 0; 120 } 121 122 static void pl111_display_enable(struct drm_simple_display_pipe *pipe, 123 struct drm_crtc_state *cstate, 124 struct drm_plane_state *plane_state) 125 { 126 struct drm_crtc *crtc = &pipe->crtc; 127 struct drm_plane *plane = &pipe->plane; 128 struct drm_device *drm = crtc->dev; 129 struct pl111_drm_dev_private *priv = drm->dev_private; 130 const struct drm_display_mode *mode = &cstate->mode; 131 struct drm_framebuffer *fb = plane->state->fb; 132 struct drm_connector *connector = priv->connector; 133 struct drm_bridge *bridge = priv->bridge; 134 u32 cntl; 135 u32 ppl, hsw, hfp, hbp; 136 u32 lpp, vsw, vfp, vbp; 137 u32 cpl, tim2; 138 int ret; 139 140 ret = clk_set_rate(priv->clk, mode->clock * 1000); 141 if (ret) { 142 dev_err(drm->dev, 143 "Failed to set pixel clock rate to %d: %d\n", 144 mode->clock * 1000, ret); 145 } 146 147 clk_prepare_enable(priv->clk); 148 149 ppl = (mode->hdisplay / 16) - 1; 150 hsw = mode->hsync_end - mode->hsync_start - 1; 151 hfp = mode->hsync_start - mode->hdisplay - 1; 152 hbp = mode->htotal - mode->hsync_end - 1; 153 154 lpp = mode->vdisplay - 1; 155 vsw = mode->vsync_end - mode->vsync_start - 1; 156 vfp = mode->vsync_start - mode->vdisplay; 157 vbp = mode->vtotal - mode->vsync_end; 158 159 cpl = mode->hdisplay - 1; 160 161 writel((ppl << 2) | 162 (hsw << 8) | 163 (hfp << 16) | 164 (hbp << 24), 165 priv->regs + CLCD_TIM0); 166 writel(lpp | 167 (vsw << 10) | 168 (vfp << 16) | 169 (vbp << 24), 170 priv->regs + CLCD_TIM1); 171 172 spin_lock(&priv->tim2_lock); 173 174 tim2 = readl(priv->regs + CLCD_TIM2); 175 tim2 &= (TIM2_BCD | TIM2_PCD_LO_MASK | TIM2_PCD_HI_MASK); 176 177 if (priv->variant->broken_clockdivider) 178 tim2 |= TIM2_BCD; 179 180 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 181 tim2 |= TIM2_IHS; 182 183 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 184 tim2 |= TIM2_IVS; 185 186 if (connector) { 187 if (connector->display_info.bus_flags & DRM_BUS_FLAG_DE_LOW) 188 tim2 |= TIM2_IOE; 189 190 if (connector->display_info.bus_flags & 191 DRM_BUS_FLAG_PIXDATA_NEGEDGE) 192 tim2 |= TIM2_IPC; 193 } 194 195 if (bridge) { 196 const struct drm_bridge_timings *btimings = bridge->timings; 197 198 /* 199 * Here is when things get really fun. Sometimes the bridge 200 * timings are such that the signal out from PL11x is not 201 * stable before the receiving bridge (such as a dumb VGA DAC 202 * or similar) samples it. If that happens, we compensate by 203 * the only method we have: output the data on the opposite 204 * edge of the clock so it is for sure stable when it gets 205 * sampled. 206 * 207 * The PL111 manual does not contain proper timining diagrams 208 * or data for these details, but we know from experiments 209 * that the setup time is more than 3000 picoseconds (3 ns). 210 * If we have a bridge that requires the signal to be stable 211 * earlier than 3000 ps before the clock pulse, we have to 212 * output the data on the opposite edge to avoid flicker. 213 */ 214 if (btimings && btimings->setup_time_ps >= 3000) 215 tim2 ^= TIM2_IPC; 216 } 217 218 tim2 |= cpl << 16; 219 writel(tim2, priv->regs + CLCD_TIM2); 220 spin_unlock(&priv->tim2_lock); 221 222 writel(0, priv->regs + CLCD_TIM3); 223 224 /* Hard-code TFT panel */ 225 cntl = CNTL_LCDEN | CNTL_LCDTFT | CNTL_LCDVCOMP(1); 226 /* On the ST Micro variant, assume all 24 bits are connected */ 227 if (priv->variant->st_bitmux_control) 228 cntl |= CNTL_ST_CDWID_24; 229 230 /* 231 * Note that the the ARM hardware's format reader takes 'r' from 232 * the low bit, while DRM formats list channels from high bit 233 * to low bit as you read left to right. The ST Micro version of 234 * the PL110 (LCDC) however uses the standard DRM format. 235 */ 236 switch (fb->format->format) { 237 case DRM_FORMAT_BGR888: 238 /* Only supported on the ST Micro variant */ 239 if (priv->variant->st_bitmux_control) 240 cntl |= CNTL_ST_LCDBPP24_PACKED | CNTL_BGR; 241 break; 242 case DRM_FORMAT_RGB888: 243 /* Only supported on the ST Micro variant */ 244 if (priv->variant->st_bitmux_control) 245 cntl |= CNTL_ST_LCDBPP24_PACKED; 246 break; 247 case DRM_FORMAT_ABGR8888: 248 case DRM_FORMAT_XBGR8888: 249 if (priv->variant->st_bitmux_control) 250 cntl |= CNTL_LCDBPP24 | CNTL_BGR; 251 else 252 cntl |= CNTL_LCDBPP24; 253 break; 254 case DRM_FORMAT_ARGB8888: 255 case DRM_FORMAT_XRGB8888: 256 if (priv->variant->st_bitmux_control) 257 cntl |= CNTL_LCDBPP24; 258 else 259 cntl |= CNTL_LCDBPP24 | CNTL_BGR; 260 break; 261 case DRM_FORMAT_BGR565: 262 if (priv->variant->is_pl110) 263 cntl |= CNTL_LCDBPP16; 264 else if (priv->variant->st_bitmux_control) 265 cntl |= CNTL_LCDBPP16 | CNTL_ST_1XBPP_565 | CNTL_BGR; 266 else 267 cntl |= CNTL_LCDBPP16_565; 268 break; 269 case DRM_FORMAT_RGB565: 270 if (priv->variant->is_pl110) 271 cntl |= CNTL_LCDBPP16 | CNTL_BGR; 272 else if (priv->variant->st_bitmux_control) 273 cntl |= CNTL_LCDBPP16 | CNTL_ST_1XBPP_565; 274 else 275 cntl |= CNTL_LCDBPP16_565 | CNTL_BGR; 276 break; 277 case DRM_FORMAT_ABGR1555: 278 case DRM_FORMAT_XBGR1555: 279 cntl |= CNTL_LCDBPP16; 280 if (priv->variant->st_bitmux_control) 281 cntl |= CNTL_ST_1XBPP_5551 | CNTL_BGR; 282 break; 283 case DRM_FORMAT_ARGB1555: 284 case DRM_FORMAT_XRGB1555: 285 cntl |= CNTL_LCDBPP16; 286 if (priv->variant->st_bitmux_control) 287 cntl |= CNTL_ST_1XBPP_5551; 288 else 289 cntl |= CNTL_BGR; 290 break; 291 case DRM_FORMAT_ABGR4444: 292 case DRM_FORMAT_XBGR4444: 293 cntl |= CNTL_LCDBPP16_444; 294 if (priv->variant->st_bitmux_control) 295 cntl |= CNTL_ST_1XBPP_444 | CNTL_BGR; 296 break; 297 case DRM_FORMAT_ARGB4444: 298 case DRM_FORMAT_XRGB4444: 299 cntl |= CNTL_LCDBPP16_444; 300 if (priv->variant->st_bitmux_control) 301 cntl |= CNTL_ST_1XBPP_444; 302 else 303 cntl |= CNTL_BGR; 304 break; 305 default: 306 WARN_ONCE(true, "Unknown FB format 0x%08x\n", 307 fb->format->format); 308 break; 309 } 310 311 /* The PL110 in Integrator/Versatile does the BGR routing externally */ 312 if (priv->variant->external_bgr) 313 cntl &= ~CNTL_BGR; 314 315 /* Power sequence: first enable and chill */ 316 writel(cntl, priv->regs + priv->ctrl); 317 318 /* 319 * We expect this delay to stabilize the contrast 320 * voltage Vee as stipulated by the manual 321 */ 322 msleep(20); 323 324 if (priv->variant_display_enable) 325 priv->variant_display_enable(drm, fb->format->format); 326 327 /* Power Up */ 328 cntl |= CNTL_LCDPWR; 329 writel(cntl, priv->regs + priv->ctrl); 330 331 if (!priv->variant->broken_vblank) 332 drm_crtc_vblank_on(crtc); 333 } 334 335 void pl111_display_disable(struct drm_simple_display_pipe *pipe) 336 { 337 struct drm_crtc *crtc = &pipe->crtc; 338 struct drm_device *drm = crtc->dev; 339 struct pl111_drm_dev_private *priv = drm->dev_private; 340 u32 cntl; 341 342 if (!priv->variant->broken_vblank) 343 drm_crtc_vblank_off(crtc); 344 345 /* Power Down */ 346 cntl = readl(priv->regs + priv->ctrl); 347 if (cntl & CNTL_LCDPWR) { 348 cntl &= ~CNTL_LCDPWR; 349 writel(cntl, priv->regs + priv->ctrl); 350 } 351 352 /* 353 * We expect this delay to stabilize the contrast voltage Vee as 354 * stipulated by the manual 355 */ 356 msleep(20); 357 358 if (priv->variant_display_disable) 359 priv->variant_display_disable(drm); 360 361 /* Disable */ 362 writel(0, priv->regs + priv->ctrl); 363 364 clk_disable_unprepare(priv->clk); 365 } 366 367 static void pl111_display_update(struct drm_simple_display_pipe *pipe, 368 struct drm_plane_state *old_pstate) 369 { 370 struct drm_crtc *crtc = &pipe->crtc; 371 struct drm_device *drm = crtc->dev; 372 struct pl111_drm_dev_private *priv = drm->dev_private; 373 struct drm_pending_vblank_event *event = crtc->state->event; 374 struct drm_plane *plane = &pipe->plane; 375 struct drm_plane_state *pstate = plane->state; 376 struct drm_framebuffer *fb = pstate->fb; 377 378 if (fb) { 379 u32 addr = drm_fb_cma_get_gem_addr(fb, pstate, 0); 380 381 writel(addr, priv->regs + CLCD_UBAS); 382 } 383 384 if (event) { 385 crtc->state->event = NULL; 386 387 spin_lock_irq(&crtc->dev->event_lock); 388 if (crtc->state->active && drm_crtc_vblank_get(crtc) == 0) 389 drm_crtc_arm_vblank_event(crtc, event); 390 else 391 drm_crtc_send_vblank_event(crtc, event); 392 spin_unlock_irq(&crtc->dev->event_lock); 393 } 394 } 395 396 static int pl111_display_enable_vblank(struct drm_simple_display_pipe *pipe) 397 { 398 struct drm_crtc *crtc = &pipe->crtc; 399 struct drm_device *drm = crtc->dev; 400 struct pl111_drm_dev_private *priv = drm->dev_private; 401 402 writel(CLCD_IRQ_NEXTBASE_UPDATE, priv->regs + priv->ienb); 403 404 return 0; 405 } 406 407 static void pl111_display_disable_vblank(struct drm_simple_display_pipe *pipe) 408 { 409 struct drm_crtc *crtc = &pipe->crtc; 410 struct drm_device *drm = crtc->dev; 411 struct pl111_drm_dev_private *priv = drm->dev_private; 412 413 writel(0, priv->regs + priv->ienb); 414 } 415 416 static struct drm_simple_display_pipe_funcs pl111_display_funcs = { 417 .mode_valid = pl111_mode_valid, 418 .check = pl111_display_check, 419 .enable = pl111_display_enable, 420 .disable = pl111_display_disable, 421 .update = pl111_display_update, 422 .prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb, 423 }; 424 425 static int pl111_clk_div_choose_div(struct clk_hw *hw, unsigned long rate, 426 unsigned long *prate, bool set_parent) 427 { 428 int best_div = 1, div; 429 struct clk_hw *parent = clk_hw_get_parent(hw); 430 unsigned long best_prate = 0; 431 unsigned long best_diff = ~0ul; 432 int max_div = (1 << (TIM2_PCD_LO_BITS + TIM2_PCD_HI_BITS)) - 1; 433 434 for (div = 1; div < max_div; div++) { 435 unsigned long this_prate, div_rate, diff; 436 437 if (set_parent) 438 this_prate = clk_hw_round_rate(parent, rate * div); 439 else 440 this_prate = *prate; 441 div_rate = DIV_ROUND_UP_ULL(this_prate, div); 442 diff = abs(rate - div_rate); 443 444 if (diff < best_diff) { 445 best_div = div; 446 best_diff = diff; 447 best_prate = this_prate; 448 } 449 } 450 451 *prate = best_prate; 452 return best_div; 453 } 454 455 static long pl111_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, 456 unsigned long *prate) 457 { 458 int div = pl111_clk_div_choose_div(hw, rate, prate, true); 459 460 return DIV_ROUND_UP_ULL(*prate, div); 461 } 462 463 static unsigned long pl111_clk_div_recalc_rate(struct clk_hw *hw, 464 unsigned long prate) 465 { 466 struct pl111_drm_dev_private *priv = 467 container_of(hw, struct pl111_drm_dev_private, clk_div); 468 u32 tim2 = readl(priv->regs + CLCD_TIM2); 469 int div; 470 471 if (tim2 & TIM2_BCD) 472 return prate; 473 474 div = tim2 & TIM2_PCD_LO_MASK; 475 div |= (tim2 & TIM2_PCD_HI_MASK) >> 476 (TIM2_PCD_HI_SHIFT - TIM2_PCD_LO_BITS); 477 div += 2; 478 479 return DIV_ROUND_UP_ULL(prate, div); 480 } 481 482 static int pl111_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, 483 unsigned long prate) 484 { 485 struct pl111_drm_dev_private *priv = 486 container_of(hw, struct pl111_drm_dev_private, clk_div); 487 int div = pl111_clk_div_choose_div(hw, rate, &prate, false); 488 u32 tim2; 489 490 spin_lock(&priv->tim2_lock); 491 tim2 = readl(priv->regs + CLCD_TIM2); 492 tim2 &= ~(TIM2_BCD | TIM2_PCD_LO_MASK | TIM2_PCD_HI_MASK); 493 494 if (div == 1) { 495 tim2 |= TIM2_BCD; 496 } else { 497 div -= 2; 498 tim2 |= div & TIM2_PCD_LO_MASK; 499 tim2 |= (div >> TIM2_PCD_LO_BITS) << TIM2_PCD_HI_SHIFT; 500 } 501 502 writel(tim2, priv->regs + CLCD_TIM2); 503 spin_unlock(&priv->tim2_lock); 504 505 return 0; 506 } 507 508 static const struct clk_ops pl111_clk_div_ops = { 509 .recalc_rate = pl111_clk_div_recalc_rate, 510 .round_rate = pl111_clk_div_round_rate, 511 .set_rate = pl111_clk_div_set_rate, 512 }; 513 514 static int 515 pl111_init_clock_divider(struct drm_device *drm) 516 { 517 struct pl111_drm_dev_private *priv = drm->dev_private; 518 struct clk *parent = devm_clk_get(drm->dev, "clcdclk"); 519 struct clk_hw *div = &priv->clk_div; 520 const char *parent_name; 521 struct clk_init_data init = { 522 .name = "pl111_div", 523 .ops = &pl111_clk_div_ops, 524 .parent_names = &parent_name, 525 .num_parents = 1, 526 .flags = CLK_SET_RATE_PARENT, 527 }; 528 int ret; 529 530 if (IS_ERR(parent)) { 531 dev_err(drm->dev, "CLCD: unable to get clcdclk.\n"); 532 return PTR_ERR(parent); 533 } 534 /* If the clock divider is broken, use the parent directly */ 535 if (priv->variant->broken_clockdivider) { 536 priv->clk = parent; 537 return 0; 538 } 539 parent_name = __clk_get_name(parent); 540 541 spin_lock_init(&priv->tim2_lock); 542 div->init = &init; 543 544 ret = devm_clk_hw_register(drm->dev, div); 545 546 priv->clk = div->clk; 547 return ret; 548 } 549 550 int pl111_display_init(struct drm_device *drm) 551 { 552 struct pl111_drm_dev_private *priv = drm->dev_private; 553 struct device *dev = drm->dev; 554 struct device_node *endpoint; 555 u32 tft_r0b0g0[3]; 556 int ret; 557 558 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL); 559 if (!endpoint) 560 return -ENODEV; 561 562 if (of_property_read_u32_array(endpoint, 563 "arm,pl11x,tft-r0g0b0-pads", 564 tft_r0b0g0, 565 ARRAY_SIZE(tft_r0b0g0)) != 0) { 566 dev_err(dev, "arm,pl11x,tft-r0g0b0-pads should be 3 ints\n"); 567 of_node_put(endpoint); 568 return -ENOENT; 569 } 570 of_node_put(endpoint); 571 572 ret = pl111_init_clock_divider(drm); 573 if (ret) 574 return ret; 575 576 if (!priv->variant->broken_vblank) { 577 pl111_display_funcs.enable_vblank = pl111_display_enable_vblank; 578 pl111_display_funcs.disable_vblank = pl111_display_disable_vblank; 579 } 580 581 ret = drm_simple_display_pipe_init(drm, &priv->pipe, 582 &pl111_display_funcs, 583 priv->variant->formats, 584 priv->variant->nformats, 585 NULL, 586 priv->connector); 587 if (ret) 588 return ret; 589 590 return 0; 591 } 592