1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved.
4  *
5  * Parts of this file were based on sources as follows:
6  *
7  * Copyright (c) 2006-2008 Intel Corporation
8  * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
9  * Copyright (C) 2011 Texas Instruments
10  */
11 
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/version.h>
15 #include <linux/dma-buf.h>
16 #include <linux/of_graph.h>
17 
18 #include <drm/drm_fb_cma_helper.h>
19 #include <drm/drm_fourcc.h>
20 #include <drm/drm_gem_cma_helper.h>
21 #include <drm/drm_gem_framebuffer_helper.h>
22 #include <drm/drm_vblank.h>
23 
24 #include "pl111_drm.h"
25 
26 irqreturn_t pl111_irq(int irq, void *data)
27 {
28 	struct pl111_drm_dev_private *priv = data;
29 	u32 irq_stat;
30 	irqreturn_t status = IRQ_NONE;
31 
32 	irq_stat = readl(priv->regs + CLCD_PL111_MIS);
33 
34 	if (!irq_stat)
35 		return IRQ_NONE;
36 
37 	if (irq_stat & CLCD_IRQ_NEXTBASE_UPDATE) {
38 		drm_crtc_handle_vblank(&priv->pipe.crtc);
39 
40 		status = IRQ_HANDLED;
41 	}
42 
43 	/* Clear the interrupt once done */
44 	writel(irq_stat, priv->regs + CLCD_PL111_ICR);
45 
46 	return status;
47 }
48 
49 static enum drm_mode_status
50 pl111_mode_valid(struct drm_simple_display_pipe *pipe,
51 		 const struct drm_display_mode *mode)
52 {
53 	struct drm_device *drm = pipe->crtc.dev;
54 	struct pl111_drm_dev_private *priv = drm->dev_private;
55 	u32 cpp = priv->variant->fb_bpp / 8;
56 	u64 bw;
57 
58 	/*
59 	 * We use the pixelclock to also account for interlaced modes, the
60 	 * resulting bandwidth is in bytes per second.
61 	 */
62 	bw = mode->clock * 1000ULL; /* In Hz */
63 	bw = bw * mode->hdisplay * mode->vdisplay * cpp;
64 	bw = div_u64(bw, mode->htotal * mode->vtotal);
65 
66 	/*
67 	 * If no bandwidth constraints, anything goes, else
68 	 * check if we are too fast.
69 	 */
70 	if (priv->memory_bw && (bw > priv->memory_bw)) {
71 		DRM_DEBUG_KMS("%d x %d @ %d Hz, %d cpp, bw %llu too fast\n",
72 			      mode->hdisplay, mode->vdisplay,
73 			      mode->clock * 1000, cpp, bw);
74 
75 		return MODE_BAD;
76 	}
77 	DRM_DEBUG_KMS("%d x %d @ %d Hz, %d cpp, bw %llu bytes/s OK\n",
78 		      mode->hdisplay, mode->vdisplay,
79 		      mode->clock * 1000, cpp, bw);
80 
81 	return MODE_OK;
82 }
83 
84 static int pl111_display_check(struct drm_simple_display_pipe *pipe,
85 			       struct drm_plane_state *pstate,
86 			       struct drm_crtc_state *cstate)
87 {
88 	const struct drm_display_mode *mode = &cstate->mode;
89 	struct drm_framebuffer *old_fb = pipe->plane.state->fb;
90 	struct drm_framebuffer *fb = pstate->fb;
91 
92 	if (mode->hdisplay % 16)
93 		return -EINVAL;
94 
95 	if (fb) {
96 		u32 offset = drm_fb_cma_get_gem_addr(fb, pstate, 0);
97 
98 		/* FB base address must be dword aligned. */
99 		if (offset & 3)
100 			return -EINVAL;
101 
102 		/* There's no pitch register -- the mode's hdisplay
103 		 * controls it.
104 		 */
105 		if (fb->pitches[0] != mode->hdisplay * fb->format->cpp[0])
106 			return -EINVAL;
107 
108 		/* We can't change the FB format in a flicker-free
109 		 * manner (and only update it during CRTC enable).
110 		 */
111 		if (old_fb && old_fb->format != fb->format)
112 			cstate->mode_changed = true;
113 	}
114 
115 	return 0;
116 }
117 
118 static void pl111_display_enable(struct drm_simple_display_pipe *pipe,
119 				 struct drm_crtc_state *cstate,
120 				 struct drm_plane_state *plane_state)
121 {
122 	struct drm_crtc *crtc = &pipe->crtc;
123 	struct drm_plane *plane = &pipe->plane;
124 	struct drm_device *drm = crtc->dev;
125 	struct pl111_drm_dev_private *priv = drm->dev_private;
126 	const struct drm_display_mode *mode = &cstate->mode;
127 	struct drm_framebuffer *fb = plane->state->fb;
128 	struct drm_connector *connector = priv->connector;
129 	struct drm_bridge *bridge = priv->bridge;
130 	bool grayscale = false;
131 	u32 cntl;
132 	u32 ppl, hsw, hfp, hbp;
133 	u32 lpp, vsw, vfp, vbp;
134 	u32 cpl, tim2;
135 	int ret;
136 
137 	ret = clk_set_rate(priv->clk, mode->clock * 1000);
138 	if (ret) {
139 		dev_err(drm->dev,
140 			"Failed to set pixel clock rate to %d: %d\n",
141 			mode->clock * 1000, ret);
142 	}
143 
144 	clk_prepare_enable(priv->clk);
145 
146 	ppl = (mode->hdisplay / 16) - 1;
147 	hsw = mode->hsync_end - mode->hsync_start - 1;
148 	hfp = mode->hsync_start - mode->hdisplay - 1;
149 	hbp = mode->htotal - mode->hsync_end - 1;
150 
151 	lpp = mode->vdisplay - 1;
152 	vsw = mode->vsync_end - mode->vsync_start - 1;
153 	vfp = mode->vsync_start - mode->vdisplay;
154 	vbp = mode->vtotal - mode->vsync_end;
155 
156 	cpl = mode->hdisplay - 1;
157 
158 	writel((ppl << 2) |
159 	       (hsw << 8) |
160 	       (hfp << 16) |
161 	       (hbp << 24),
162 	       priv->regs + CLCD_TIM0);
163 	writel(lpp |
164 	       (vsw << 10) |
165 	       (vfp << 16) |
166 	       (vbp << 24),
167 	       priv->regs + CLCD_TIM1);
168 
169 	spin_lock(&priv->tim2_lock);
170 
171 	tim2 = readl(priv->regs + CLCD_TIM2);
172 	tim2 &= (TIM2_BCD | TIM2_PCD_LO_MASK | TIM2_PCD_HI_MASK);
173 
174 	if (priv->variant->broken_clockdivider)
175 		tim2 |= TIM2_BCD;
176 
177 	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
178 		tim2 |= TIM2_IHS;
179 
180 	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
181 		tim2 |= TIM2_IVS;
182 
183 	if (connector) {
184 		if (connector->display_info.bus_flags & DRM_BUS_FLAG_DE_LOW)
185 			tim2 |= TIM2_IOE;
186 
187 		if (connector->display_info.bus_flags &
188 		    DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
189 			tim2 |= TIM2_IPC;
190 
191 		if (connector->display_info.num_bus_formats == 1 &&
192 		    connector->display_info.bus_formats[0] ==
193 		    MEDIA_BUS_FMT_Y8_1X8)
194 			grayscale = true;
195 
196 		/*
197 		 * The AC pin bias frequency is set to max count when using
198 		 * grayscale so at least once in a while we will reverse
199 		 * polarity and get rid of any DC built up that could
200 		 * damage the display.
201 		 */
202 		if (grayscale)
203 			tim2 |= TIM2_ACB_MASK;
204 	}
205 
206 	if (bridge) {
207 		const struct drm_bridge_timings *btimings = bridge->timings;
208 
209 		/*
210 		 * Here is when things get really fun. Sometimes the bridge
211 		 * timings are such that the signal out from PL11x is not
212 		 * stable before the receiving bridge (such as a dumb VGA DAC
213 		 * or similar) samples it. If that happens, we compensate by
214 		 * the only method we have: output the data on the opposite
215 		 * edge of the clock so it is for sure stable when it gets
216 		 * sampled.
217 		 *
218 		 * The PL111 manual does not contain proper timining diagrams
219 		 * or data for these details, but we know from experiments
220 		 * that the setup time is more than 3000 picoseconds (3 ns).
221 		 * If we have a bridge that requires the signal to be stable
222 		 * earlier than 3000 ps before the clock pulse, we have to
223 		 * output the data on the opposite edge to avoid flicker.
224 		 */
225 		if (btimings && btimings->setup_time_ps >= 3000)
226 			tim2 ^= TIM2_IPC;
227 	}
228 
229 	tim2 |= cpl << 16;
230 	writel(tim2, priv->regs + CLCD_TIM2);
231 	spin_unlock(&priv->tim2_lock);
232 
233 	writel(0, priv->regs + CLCD_TIM3);
234 
235 	/*
236 	 * Detect grayscale bus format. We do not support a grayscale mode
237 	 * toward userspace, instead we expose an RGB24 buffer and then the
238 	 * hardware will activate its grayscaler to convert to the grayscale
239 	 * format.
240 	 */
241 	if (grayscale)
242 		cntl = CNTL_LCDEN | CNTL_LCDMONO8;
243 	else
244 		/* Else we assume TFT display */
245 		cntl = CNTL_LCDEN | CNTL_LCDTFT | CNTL_LCDVCOMP(1);
246 
247 	/* On the ST Micro variant, assume all 24 bits are connected */
248 	if (priv->variant->st_bitmux_control)
249 		cntl |= CNTL_ST_CDWID_24;
250 
251 	/*
252 	 * Note that the the ARM hardware's format reader takes 'r' from
253 	 * the low bit, while DRM formats list channels from high bit
254 	 * to low bit as you read left to right. The ST Micro version of
255 	 * the PL110 (LCDC) however uses the standard DRM format.
256 	 */
257 	switch (fb->format->format) {
258 	case DRM_FORMAT_BGR888:
259 		/* Only supported on the ST Micro variant */
260 		if (priv->variant->st_bitmux_control)
261 			cntl |= CNTL_ST_LCDBPP24_PACKED | CNTL_BGR;
262 		break;
263 	case DRM_FORMAT_RGB888:
264 		/* Only supported on the ST Micro variant */
265 		if (priv->variant->st_bitmux_control)
266 			cntl |= CNTL_ST_LCDBPP24_PACKED;
267 		break;
268 	case DRM_FORMAT_ABGR8888:
269 	case DRM_FORMAT_XBGR8888:
270 		if (priv->variant->st_bitmux_control)
271 			cntl |= CNTL_LCDBPP24 | CNTL_BGR;
272 		else
273 			cntl |= CNTL_LCDBPP24;
274 		break;
275 	case DRM_FORMAT_ARGB8888:
276 	case DRM_FORMAT_XRGB8888:
277 		if (priv->variant->st_bitmux_control)
278 			cntl |= CNTL_LCDBPP24;
279 		else
280 			cntl |= CNTL_LCDBPP24 | CNTL_BGR;
281 		break;
282 	case DRM_FORMAT_BGR565:
283 		if (priv->variant->is_pl110)
284 			cntl |= CNTL_LCDBPP16;
285 		else if (priv->variant->st_bitmux_control)
286 			cntl |= CNTL_LCDBPP16 | CNTL_ST_1XBPP_565 | CNTL_BGR;
287 		else
288 			cntl |= CNTL_LCDBPP16_565;
289 		break;
290 	case DRM_FORMAT_RGB565:
291 		if (priv->variant->is_pl110)
292 			cntl |= CNTL_LCDBPP16 | CNTL_BGR;
293 		else if (priv->variant->st_bitmux_control)
294 			cntl |= CNTL_LCDBPP16 | CNTL_ST_1XBPP_565;
295 		else
296 			cntl |= CNTL_LCDBPP16_565 | CNTL_BGR;
297 		break;
298 	case DRM_FORMAT_ABGR1555:
299 	case DRM_FORMAT_XBGR1555:
300 		cntl |= CNTL_LCDBPP16;
301 		if (priv->variant->st_bitmux_control)
302 			cntl |= CNTL_ST_1XBPP_5551 | CNTL_BGR;
303 		break;
304 	case DRM_FORMAT_ARGB1555:
305 	case DRM_FORMAT_XRGB1555:
306 		cntl |= CNTL_LCDBPP16;
307 		if (priv->variant->st_bitmux_control)
308 			cntl |= CNTL_ST_1XBPP_5551;
309 		else
310 			cntl |= CNTL_BGR;
311 		break;
312 	case DRM_FORMAT_ABGR4444:
313 	case DRM_FORMAT_XBGR4444:
314 		cntl |= CNTL_LCDBPP16_444;
315 		if (priv->variant->st_bitmux_control)
316 			cntl |= CNTL_ST_1XBPP_444 | CNTL_BGR;
317 		break;
318 	case DRM_FORMAT_ARGB4444:
319 	case DRM_FORMAT_XRGB4444:
320 		cntl |= CNTL_LCDBPP16_444;
321 		if (priv->variant->st_bitmux_control)
322 			cntl |= CNTL_ST_1XBPP_444;
323 		else
324 			cntl |= CNTL_BGR;
325 		break;
326 	default:
327 		WARN_ONCE(true, "Unknown FB format 0x%08x\n",
328 			  fb->format->format);
329 		break;
330 	}
331 
332 	/* The PL110 in Integrator/Versatile does the BGR routing externally */
333 	if (priv->variant->external_bgr)
334 		cntl &= ~CNTL_BGR;
335 
336 	/* Power sequence: first enable and chill */
337 	writel(cntl, priv->regs + priv->ctrl);
338 
339 	/*
340 	 * We expect this delay to stabilize the contrast
341 	 * voltage Vee as stipulated by the manual
342 	 */
343 	msleep(20);
344 
345 	if (priv->variant_display_enable)
346 		priv->variant_display_enable(drm, fb->format->format);
347 
348 	/* Power Up */
349 	cntl |= CNTL_LCDPWR;
350 	writel(cntl, priv->regs + priv->ctrl);
351 
352 	if (!priv->variant->broken_vblank)
353 		drm_crtc_vblank_on(crtc);
354 }
355 
356 static void pl111_display_disable(struct drm_simple_display_pipe *pipe)
357 {
358 	struct drm_crtc *crtc = &pipe->crtc;
359 	struct drm_device *drm = crtc->dev;
360 	struct pl111_drm_dev_private *priv = drm->dev_private;
361 	u32 cntl;
362 
363 	if (!priv->variant->broken_vblank)
364 		drm_crtc_vblank_off(crtc);
365 
366 	/* Power Down */
367 	cntl = readl(priv->regs + priv->ctrl);
368 	if (cntl & CNTL_LCDPWR) {
369 		cntl &= ~CNTL_LCDPWR;
370 		writel(cntl, priv->regs + priv->ctrl);
371 	}
372 
373 	/*
374 	 * We expect this delay to stabilize the contrast voltage Vee as
375 	 * stipulated by the manual
376 	 */
377 	msleep(20);
378 
379 	if (priv->variant_display_disable)
380 		priv->variant_display_disable(drm);
381 
382 	/* Disable */
383 	writel(0, priv->regs + priv->ctrl);
384 
385 	clk_disable_unprepare(priv->clk);
386 }
387 
388 static void pl111_display_update(struct drm_simple_display_pipe *pipe,
389 				 struct drm_plane_state *old_pstate)
390 {
391 	struct drm_crtc *crtc = &pipe->crtc;
392 	struct drm_device *drm = crtc->dev;
393 	struct pl111_drm_dev_private *priv = drm->dev_private;
394 	struct drm_pending_vblank_event *event = crtc->state->event;
395 	struct drm_plane *plane = &pipe->plane;
396 	struct drm_plane_state *pstate = plane->state;
397 	struct drm_framebuffer *fb = pstate->fb;
398 
399 	if (fb) {
400 		u32 addr = drm_fb_cma_get_gem_addr(fb, pstate, 0);
401 
402 		writel(addr, priv->regs + CLCD_UBAS);
403 	}
404 
405 	if (event) {
406 		crtc->state->event = NULL;
407 
408 		spin_lock_irq(&crtc->dev->event_lock);
409 		if (crtc->state->active && drm_crtc_vblank_get(crtc) == 0)
410 			drm_crtc_arm_vblank_event(crtc, event);
411 		else
412 			drm_crtc_send_vblank_event(crtc, event);
413 		spin_unlock_irq(&crtc->dev->event_lock);
414 	}
415 }
416 
417 static int pl111_display_enable_vblank(struct drm_simple_display_pipe *pipe)
418 {
419 	struct drm_crtc *crtc = &pipe->crtc;
420 	struct drm_device *drm = crtc->dev;
421 	struct pl111_drm_dev_private *priv = drm->dev_private;
422 
423 	writel(CLCD_IRQ_NEXTBASE_UPDATE, priv->regs + priv->ienb);
424 
425 	return 0;
426 }
427 
428 static void pl111_display_disable_vblank(struct drm_simple_display_pipe *pipe)
429 {
430 	struct drm_crtc *crtc = &pipe->crtc;
431 	struct drm_device *drm = crtc->dev;
432 	struct pl111_drm_dev_private *priv = drm->dev_private;
433 
434 	writel(0, priv->regs + priv->ienb);
435 }
436 
437 static struct drm_simple_display_pipe_funcs pl111_display_funcs = {
438 	.mode_valid = pl111_mode_valid,
439 	.check = pl111_display_check,
440 	.enable = pl111_display_enable,
441 	.disable = pl111_display_disable,
442 	.update = pl111_display_update,
443 	.prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
444 };
445 
446 static int pl111_clk_div_choose_div(struct clk_hw *hw, unsigned long rate,
447 				    unsigned long *prate, bool set_parent)
448 {
449 	int best_div = 1, div;
450 	struct clk_hw *parent = clk_hw_get_parent(hw);
451 	unsigned long best_prate = 0;
452 	unsigned long best_diff = ~0ul;
453 	int max_div = (1 << (TIM2_PCD_LO_BITS + TIM2_PCD_HI_BITS)) - 1;
454 
455 	for (div = 1; div < max_div; div++) {
456 		unsigned long this_prate, div_rate, diff;
457 
458 		if (set_parent)
459 			this_prate = clk_hw_round_rate(parent, rate * div);
460 		else
461 			this_prate = *prate;
462 		div_rate = DIV_ROUND_UP_ULL(this_prate, div);
463 		diff = abs(rate - div_rate);
464 
465 		if (diff < best_diff) {
466 			best_div = div;
467 			best_diff = diff;
468 			best_prate = this_prate;
469 		}
470 	}
471 
472 	*prate = best_prate;
473 	return best_div;
474 }
475 
476 static long pl111_clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
477 				     unsigned long *prate)
478 {
479 	int div = pl111_clk_div_choose_div(hw, rate, prate, true);
480 
481 	return DIV_ROUND_UP_ULL(*prate, div);
482 }
483 
484 static unsigned long pl111_clk_div_recalc_rate(struct clk_hw *hw,
485 					       unsigned long prate)
486 {
487 	struct pl111_drm_dev_private *priv =
488 		container_of(hw, struct pl111_drm_dev_private, clk_div);
489 	u32 tim2 = readl(priv->regs + CLCD_TIM2);
490 	int div;
491 
492 	if (tim2 & TIM2_BCD)
493 		return prate;
494 
495 	div = tim2 & TIM2_PCD_LO_MASK;
496 	div |= (tim2 & TIM2_PCD_HI_MASK) >>
497 		(TIM2_PCD_HI_SHIFT - TIM2_PCD_LO_BITS);
498 	div += 2;
499 
500 	return DIV_ROUND_UP_ULL(prate, div);
501 }
502 
503 static int pl111_clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
504 				  unsigned long prate)
505 {
506 	struct pl111_drm_dev_private *priv =
507 		container_of(hw, struct pl111_drm_dev_private, clk_div);
508 	int div = pl111_clk_div_choose_div(hw, rate, &prate, false);
509 	u32 tim2;
510 
511 	spin_lock(&priv->tim2_lock);
512 	tim2 = readl(priv->regs + CLCD_TIM2);
513 	tim2 &= ~(TIM2_BCD | TIM2_PCD_LO_MASK | TIM2_PCD_HI_MASK);
514 
515 	if (div == 1) {
516 		tim2 |= TIM2_BCD;
517 	} else {
518 		div -= 2;
519 		tim2 |= div & TIM2_PCD_LO_MASK;
520 		tim2 |= (div >> TIM2_PCD_LO_BITS) << TIM2_PCD_HI_SHIFT;
521 	}
522 
523 	writel(tim2, priv->regs + CLCD_TIM2);
524 	spin_unlock(&priv->tim2_lock);
525 
526 	return 0;
527 }
528 
529 static const struct clk_ops pl111_clk_div_ops = {
530 	.recalc_rate = pl111_clk_div_recalc_rate,
531 	.round_rate = pl111_clk_div_round_rate,
532 	.set_rate = pl111_clk_div_set_rate,
533 };
534 
535 static int
536 pl111_init_clock_divider(struct drm_device *drm)
537 {
538 	struct pl111_drm_dev_private *priv = drm->dev_private;
539 	struct clk *parent = devm_clk_get(drm->dev, "clcdclk");
540 	struct clk_hw *div = &priv->clk_div;
541 	const char *parent_name;
542 	struct clk_init_data init = {
543 		.name = "pl111_div",
544 		.ops = &pl111_clk_div_ops,
545 		.parent_names = &parent_name,
546 		.num_parents = 1,
547 		.flags = CLK_SET_RATE_PARENT,
548 	};
549 	int ret;
550 
551 	if (IS_ERR(parent)) {
552 		dev_err(drm->dev, "CLCD: unable to get clcdclk.\n");
553 		return PTR_ERR(parent);
554 	}
555 
556 	spin_lock_init(&priv->tim2_lock);
557 
558 	/* If the clock divider is broken, use the parent directly */
559 	if (priv->variant->broken_clockdivider) {
560 		priv->clk = parent;
561 		return 0;
562 	}
563 	parent_name = __clk_get_name(parent);
564 	div->init = &init;
565 
566 	ret = devm_clk_hw_register(drm->dev, div);
567 
568 	priv->clk = div->clk;
569 	return ret;
570 }
571 
572 int pl111_display_init(struct drm_device *drm)
573 {
574 	struct pl111_drm_dev_private *priv = drm->dev_private;
575 	int ret;
576 
577 	ret = pl111_init_clock_divider(drm);
578 	if (ret)
579 		return ret;
580 
581 	if (!priv->variant->broken_vblank) {
582 		pl111_display_funcs.enable_vblank = pl111_display_enable_vblank;
583 		pl111_display_funcs.disable_vblank = pl111_display_disable_vblank;
584 	}
585 
586 	ret = drm_simple_display_pipe_init(drm, &priv->pipe,
587 					   &pl111_display_funcs,
588 					   priv->variant->formats,
589 					   priv->variant->nformats,
590 					   NULL,
591 					   priv->connector);
592 	if (ret)
593 		return ret;
594 
595 	return 0;
596 }
597