1 /* 2 * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved. 3 * 4 * Parts of this file were based on sources as follows: 5 * 6 * Copyright (c) 2006-2008 Intel Corporation 7 * Copyright (c) 2007 Dave Airlie <airlied@linux.ie> 8 * Copyright (C) 2011 Texas Instruments 9 * 10 * This program is free software and is provided to you under the terms of the 11 * GNU General Public License version 2 as published by the Free Software 12 * Foundation, and any use by you of this program is subject to the terms of 13 * such GNU licence. 14 * 15 */ 16 17 #include <linux/amba/clcd-regs.h> 18 #include <linux/clk.h> 19 #include <linux/version.h> 20 #include <linux/dma-buf.h> 21 #include <linux/of_graph.h> 22 23 #include <drm/drmP.h> 24 #include <drm/drm_gem_cma_helper.h> 25 #include <drm/drm_gem_framebuffer_helper.h> 26 #include <drm/drm_fb_cma_helper.h> 27 28 #include "pl111_drm.h" 29 30 irqreturn_t pl111_irq(int irq, void *data) 31 { 32 struct pl111_drm_dev_private *priv = data; 33 u32 irq_stat; 34 irqreturn_t status = IRQ_NONE; 35 36 irq_stat = readl(priv->regs + CLCD_PL111_MIS); 37 38 if (!irq_stat) 39 return IRQ_NONE; 40 41 if (irq_stat & CLCD_IRQ_NEXTBASE_UPDATE) { 42 drm_crtc_handle_vblank(&priv->pipe.crtc); 43 44 status = IRQ_HANDLED; 45 } 46 47 /* Clear the interrupt once done */ 48 writel(irq_stat, priv->regs + CLCD_PL111_ICR); 49 50 return status; 51 } 52 53 static int pl111_display_check(struct drm_simple_display_pipe *pipe, 54 struct drm_plane_state *pstate, 55 struct drm_crtc_state *cstate) 56 { 57 const struct drm_display_mode *mode = &cstate->mode; 58 struct drm_framebuffer *old_fb = pipe->plane.state->fb; 59 struct drm_framebuffer *fb = pstate->fb; 60 61 if (mode->hdisplay % 16) 62 return -EINVAL; 63 64 if (fb) { 65 u32 offset = drm_fb_cma_get_gem_addr(fb, pstate, 0); 66 67 /* FB base address must be dword aligned. */ 68 if (offset & 3) 69 return -EINVAL; 70 71 /* There's no pitch register -- the mode's hdisplay 72 * controls it. 73 */ 74 if (fb->pitches[0] != mode->hdisplay * fb->format->cpp[0]) 75 return -EINVAL; 76 77 /* We can't change the FB format in a flicker-free 78 * manner (and only update it during CRTC enable). 79 */ 80 if (old_fb && old_fb->format != fb->format) 81 cstate->mode_changed = true; 82 } 83 84 return 0; 85 } 86 87 static void pl111_display_enable(struct drm_simple_display_pipe *pipe, 88 struct drm_crtc_state *cstate) 89 { 90 struct drm_crtc *crtc = &pipe->crtc; 91 struct drm_plane *plane = &pipe->plane; 92 struct drm_device *drm = crtc->dev; 93 struct pl111_drm_dev_private *priv = drm->dev_private; 94 const struct drm_display_mode *mode = &cstate->mode; 95 struct drm_framebuffer *fb = plane->state->fb; 96 struct drm_connector *connector = priv->connector; 97 struct drm_bridge *bridge = priv->bridge; 98 u32 cntl; 99 u32 ppl, hsw, hfp, hbp; 100 u32 lpp, vsw, vfp, vbp; 101 u32 cpl, tim2; 102 int ret; 103 104 ret = clk_set_rate(priv->clk, mode->clock * 1000); 105 if (ret) { 106 dev_err(drm->dev, 107 "Failed to set pixel clock rate to %d: %d\n", 108 mode->clock * 1000, ret); 109 } 110 111 clk_prepare_enable(priv->clk); 112 113 ppl = (mode->hdisplay / 16) - 1; 114 hsw = mode->hsync_end - mode->hsync_start - 1; 115 hfp = mode->hsync_start - mode->hdisplay - 1; 116 hbp = mode->htotal - mode->hsync_end - 1; 117 118 lpp = mode->vdisplay - 1; 119 vsw = mode->vsync_end - mode->vsync_start - 1; 120 vfp = mode->vsync_start - mode->vdisplay; 121 vbp = mode->vtotal - mode->vsync_end; 122 123 cpl = mode->hdisplay - 1; 124 125 writel((ppl << 2) | 126 (hsw << 8) | 127 (hfp << 16) | 128 (hbp << 24), 129 priv->regs + CLCD_TIM0); 130 writel(lpp | 131 (vsw << 10) | 132 (vfp << 16) | 133 (vbp << 24), 134 priv->regs + CLCD_TIM1); 135 136 spin_lock(&priv->tim2_lock); 137 138 tim2 = readl(priv->regs + CLCD_TIM2); 139 tim2 &= (TIM2_BCD | TIM2_PCD_LO_MASK | TIM2_PCD_HI_MASK); 140 141 if (priv->variant->broken_clockdivider) 142 tim2 |= TIM2_BCD; 143 144 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 145 tim2 |= TIM2_IHS; 146 147 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 148 tim2 |= TIM2_IVS; 149 150 if (connector) { 151 if (connector->display_info.bus_flags & DRM_BUS_FLAG_DE_LOW) 152 tim2 |= TIM2_IOE; 153 154 if (connector->display_info.bus_flags & 155 DRM_BUS_FLAG_PIXDATA_NEGEDGE) 156 tim2 |= TIM2_IPC; 157 } 158 159 if (bridge) { 160 const struct drm_bridge_timings *btimings = bridge->timings; 161 162 /* 163 * Here is when things get really fun. Sometimes the bridge 164 * timings are such that the signal out from PL11x is not 165 * stable before the receiving bridge (such as a dumb VGA DAC 166 * or similar) samples it. If that happens, we compensate by 167 * the only method we have: output the data on the opposite 168 * edge of the clock so it is for sure stable when it gets 169 * sampled. 170 * 171 * The PL111 manual does not contain proper timining diagrams 172 * or data for these details, but we know from experiments 173 * that the setup time is more than 3000 picoseconds (3 ns). 174 * If we have a bridge that requires the signal to be stable 175 * earlier than 3000 ps before the clock pulse, we have to 176 * output the data on the opposite edge to avoid flicker. 177 */ 178 if (btimings && btimings->setup_time_ps >= 3000) 179 tim2 ^= TIM2_IPC; 180 } 181 182 tim2 |= cpl << 16; 183 writel(tim2, priv->regs + CLCD_TIM2); 184 spin_unlock(&priv->tim2_lock); 185 186 writel(0, priv->regs + CLCD_TIM3); 187 188 /* Hard-code TFT panel */ 189 cntl = CNTL_LCDEN | CNTL_LCDTFT | CNTL_LCDVCOMP(1); 190 191 /* Note that the the hardware's format reader takes 'r' from 192 * the low bit, while DRM formats list channels from high bit 193 * to low bit as you read left to right. 194 */ 195 switch (fb->format->format) { 196 case DRM_FORMAT_ABGR8888: 197 case DRM_FORMAT_XBGR8888: 198 cntl |= CNTL_LCDBPP24; 199 break; 200 case DRM_FORMAT_ARGB8888: 201 case DRM_FORMAT_XRGB8888: 202 cntl |= CNTL_LCDBPP24 | CNTL_BGR; 203 break; 204 case DRM_FORMAT_BGR565: 205 if (priv->variant->is_pl110) 206 cntl |= CNTL_LCDBPP16; 207 else 208 cntl |= CNTL_LCDBPP16_565; 209 break; 210 case DRM_FORMAT_RGB565: 211 if (priv->variant->is_pl110) 212 cntl |= CNTL_LCDBPP16; 213 else 214 cntl |= CNTL_LCDBPP16_565; 215 cntl |= CNTL_BGR; 216 break; 217 case DRM_FORMAT_ABGR1555: 218 case DRM_FORMAT_XBGR1555: 219 cntl |= CNTL_LCDBPP16; 220 break; 221 case DRM_FORMAT_ARGB1555: 222 case DRM_FORMAT_XRGB1555: 223 cntl |= CNTL_LCDBPP16 | CNTL_BGR; 224 break; 225 case DRM_FORMAT_ABGR4444: 226 case DRM_FORMAT_XBGR4444: 227 cntl |= CNTL_LCDBPP16_444; 228 break; 229 case DRM_FORMAT_ARGB4444: 230 case DRM_FORMAT_XRGB4444: 231 cntl |= CNTL_LCDBPP16_444 | CNTL_BGR; 232 break; 233 default: 234 WARN_ONCE(true, "Unknown FB format 0x%08x\n", 235 fb->format->format); 236 break; 237 } 238 239 /* The PL110 in Integrator/Versatile does the BGR routing externally */ 240 if (priv->variant->external_bgr) 241 cntl &= ~CNTL_BGR; 242 243 /* Power sequence: first enable and chill */ 244 writel(cntl, priv->regs + priv->ctrl); 245 246 /* 247 * We expect this delay to stabilize the contrast 248 * voltage Vee as stipulated by the manual 249 */ 250 msleep(20); 251 252 if (priv->variant_display_enable) 253 priv->variant_display_enable(drm, fb->format->format); 254 255 /* Power Up */ 256 cntl |= CNTL_LCDPWR; 257 writel(cntl, priv->regs + priv->ctrl); 258 259 if (!priv->variant->broken_vblank) 260 drm_crtc_vblank_on(crtc); 261 } 262 263 void pl111_display_disable(struct drm_simple_display_pipe *pipe) 264 { 265 struct drm_crtc *crtc = &pipe->crtc; 266 struct drm_device *drm = crtc->dev; 267 struct pl111_drm_dev_private *priv = drm->dev_private; 268 u32 cntl; 269 270 if (!priv->variant->broken_vblank) 271 drm_crtc_vblank_off(crtc); 272 273 /* Power Down */ 274 cntl = readl(priv->regs + priv->ctrl); 275 if (cntl & CNTL_LCDPWR) { 276 cntl &= ~CNTL_LCDPWR; 277 writel(cntl, priv->regs + priv->ctrl); 278 } 279 280 /* 281 * We expect this delay to stabilize the contrast voltage Vee as 282 * stipulated by the manual 283 */ 284 msleep(20); 285 286 if (priv->variant_display_disable) 287 priv->variant_display_disable(drm); 288 289 /* Disable */ 290 writel(0, priv->regs + priv->ctrl); 291 292 clk_disable_unprepare(priv->clk); 293 } 294 295 static void pl111_display_update(struct drm_simple_display_pipe *pipe, 296 struct drm_plane_state *old_pstate) 297 { 298 struct drm_crtc *crtc = &pipe->crtc; 299 struct drm_device *drm = crtc->dev; 300 struct pl111_drm_dev_private *priv = drm->dev_private; 301 struct drm_pending_vblank_event *event = crtc->state->event; 302 struct drm_plane *plane = &pipe->plane; 303 struct drm_plane_state *pstate = plane->state; 304 struct drm_framebuffer *fb = pstate->fb; 305 306 if (fb) { 307 u32 addr = drm_fb_cma_get_gem_addr(fb, pstate, 0); 308 309 writel(addr, priv->regs + CLCD_UBAS); 310 } 311 312 if (event) { 313 crtc->state->event = NULL; 314 315 spin_lock_irq(&crtc->dev->event_lock); 316 if (crtc->state->active && drm_crtc_vblank_get(crtc) == 0) 317 drm_crtc_arm_vblank_event(crtc, event); 318 else 319 drm_crtc_send_vblank_event(crtc, event); 320 spin_unlock_irq(&crtc->dev->event_lock); 321 } 322 } 323 324 int pl111_enable_vblank(struct drm_device *drm, unsigned int crtc) 325 { 326 struct pl111_drm_dev_private *priv = drm->dev_private; 327 328 writel(CLCD_IRQ_NEXTBASE_UPDATE, priv->regs + priv->ienb); 329 330 return 0; 331 } 332 333 void pl111_disable_vblank(struct drm_device *drm, unsigned int crtc) 334 { 335 struct pl111_drm_dev_private *priv = drm->dev_private; 336 337 writel(0, priv->regs + priv->ienb); 338 } 339 340 static int pl111_display_prepare_fb(struct drm_simple_display_pipe *pipe, 341 struct drm_plane_state *plane_state) 342 { 343 return drm_gem_fb_prepare_fb(&pipe->plane, plane_state); 344 } 345 346 static const struct drm_simple_display_pipe_funcs pl111_display_funcs = { 347 .check = pl111_display_check, 348 .enable = pl111_display_enable, 349 .disable = pl111_display_disable, 350 .update = pl111_display_update, 351 .prepare_fb = pl111_display_prepare_fb, 352 }; 353 354 static int pl111_clk_div_choose_div(struct clk_hw *hw, unsigned long rate, 355 unsigned long *prate, bool set_parent) 356 { 357 int best_div = 1, div; 358 struct clk_hw *parent = clk_hw_get_parent(hw); 359 unsigned long best_prate = 0; 360 unsigned long best_diff = ~0ul; 361 int max_div = (1 << (TIM2_PCD_LO_BITS + TIM2_PCD_HI_BITS)) - 1; 362 363 for (div = 1; div < max_div; div++) { 364 unsigned long this_prate, div_rate, diff; 365 366 if (set_parent) 367 this_prate = clk_hw_round_rate(parent, rate * div); 368 else 369 this_prate = *prate; 370 div_rate = DIV_ROUND_UP_ULL(this_prate, div); 371 diff = abs(rate - div_rate); 372 373 if (diff < best_diff) { 374 best_div = div; 375 best_diff = diff; 376 best_prate = this_prate; 377 } 378 } 379 380 *prate = best_prate; 381 return best_div; 382 } 383 384 static long pl111_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, 385 unsigned long *prate) 386 { 387 int div = pl111_clk_div_choose_div(hw, rate, prate, true); 388 389 return DIV_ROUND_UP_ULL(*prate, div); 390 } 391 392 static unsigned long pl111_clk_div_recalc_rate(struct clk_hw *hw, 393 unsigned long prate) 394 { 395 struct pl111_drm_dev_private *priv = 396 container_of(hw, struct pl111_drm_dev_private, clk_div); 397 u32 tim2 = readl(priv->regs + CLCD_TIM2); 398 int div; 399 400 if (tim2 & TIM2_BCD) 401 return prate; 402 403 div = tim2 & TIM2_PCD_LO_MASK; 404 div |= (tim2 & TIM2_PCD_HI_MASK) >> 405 (TIM2_PCD_HI_SHIFT - TIM2_PCD_LO_BITS); 406 div += 2; 407 408 return DIV_ROUND_UP_ULL(prate, div); 409 } 410 411 static int pl111_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, 412 unsigned long prate) 413 { 414 struct pl111_drm_dev_private *priv = 415 container_of(hw, struct pl111_drm_dev_private, clk_div); 416 int div = pl111_clk_div_choose_div(hw, rate, &prate, false); 417 u32 tim2; 418 419 spin_lock(&priv->tim2_lock); 420 tim2 = readl(priv->regs + CLCD_TIM2); 421 tim2 &= ~(TIM2_BCD | TIM2_PCD_LO_MASK | TIM2_PCD_HI_MASK); 422 423 if (div == 1) { 424 tim2 |= TIM2_BCD; 425 } else { 426 div -= 2; 427 tim2 |= div & TIM2_PCD_LO_MASK; 428 tim2 |= (div >> TIM2_PCD_LO_BITS) << TIM2_PCD_HI_SHIFT; 429 } 430 431 writel(tim2, priv->regs + CLCD_TIM2); 432 spin_unlock(&priv->tim2_lock); 433 434 return 0; 435 } 436 437 static const struct clk_ops pl111_clk_div_ops = { 438 .recalc_rate = pl111_clk_div_recalc_rate, 439 .round_rate = pl111_clk_div_round_rate, 440 .set_rate = pl111_clk_div_set_rate, 441 }; 442 443 static int 444 pl111_init_clock_divider(struct drm_device *drm) 445 { 446 struct pl111_drm_dev_private *priv = drm->dev_private; 447 struct clk *parent = devm_clk_get(drm->dev, "clcdclk"); 448 struct clk_hw *div = &priv->clk_div; 449 const char *parent_name; 450 struct clk_init_data init = { 451 .name = "pl111_div", 452 .ops = &pl111_clk_div_ops, 453 .parent_names = &parent_name, 454 .num_parents = 1, 455 .flags = CLK_SET_RATE_PARENT, 456 }; 457 int ret; 458 459 if (IS_ERR(parent)) { 460 dev_err(drm->dev, "CLCD: unable to get clcdclk.\n"); 461 return PTR_ERR(parent); 462 } 463 /* If the clock divider is broken, use the parent directly */ 464 if (priv->variant->broken_clockdivider) { 465 priv->clk = parent; 466 return 0; 467 } 468 parent_name = __clk_get_name(parent); 469 470 spin_lock_init(&priv->tim2_lock); 471 div->init = &init; 472 473 ret = devm_clk_hw_register(drm->dev, div); 474 475 priv->clk = div->clk; 476 return ret; 477 } 478 479 int pl111_display_init(struct drm_device *drm) 480 { 481 struct pl111_drm_dev_private *priv = drm->dev_private; 482 struct device *dev = drm->dev; 483 struct device_node *endpoint; 484 u32 tft_r0b0g0[3]; 485 int ret; 486 487 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL); 488 if (!endpoint) 489 return -ENODEV; 490 491 if (of_property_read_u32_array(endpoint, 492 "arm,pl11x,tft-r0g0b0-pads", 493 tft_r0b0g0, 494 ARRAY_SIZE(tft_r0b0g0)) != 0) { 495 dev_err(dev, "arm,pl11x,tft-r0g0b0-pads should be 3 ints\n"); 496 of_node_put(endpoint); 497 return -ENOENT; 498 } 499 of_node_put(endpoint); 500 501 ret = pl111_init_clock_divider(drm); 502 if (ret) 503 return ret; 504 505 ret = drm_simple_display_pipe_init(drm, &priv->pipe, 506 &pl111_display_funcs, 507 priv->variant->formats, 508 priv->variant->nformats, 509 NULL, 510 priv->connector); 511 if (ret) 512 return ret; 513 514 return 0; 515 } 516