1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */ 3 4 #include <drm/panfrost_drm.h> 5 6 #include <linux/atomic.h> 7 #include <linux/bitfield.h> 8 #include <linux/delay.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/iopoll.h> 13 #include <linux/io-pgtable.h> 14 #include <linux/iommu.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/shmem_fs.h> 18 #include <linux/sizes.h> 19 20 #include "panfrost_device.h" 21 #include "panfrost_mmu.h" 22 #include "panfrost_gem.h" 23 #include "panfrost_features.h" 24 #include "panfrost_regs.h" 25 26 #define mmu_write(dev, reg, data) writel(data, dev->iomem + reg) 27 #define mmu_read(dev, reg) readl(dev->iomem + reg) 28 29 static int wait_ready(struct panfrost_device *pfdev, u32 as_nr) 30 { 31 int ret; 32 u32 val; 33 34 /* Wait for the MMU status to indicate there is no active command, in 35 * case one is pending. */ 36 ret = readl_relaxed_poll_timeout_atomic(pfdev->iomem + AS_STATUS(as_nr), 37 val, !(val & AS_STATUS_AS_ACTIVE), 10, 100000); 38 39 if (ret) { 40 /* The GPU hung, let's trigger a reset */ 41 panfrost_device_schedule_reset(pfdev); 42 dev_err(pfdev->dev, "AS_ACTIVE bit stuck\n"); 43 } 44 45 return ret; 46 } 47 48 static int write_cmd(struct panfrost_device *pfdev, u32 as_nr, u32 cmd) 49 { 50 int status; 51 52 /* write AS_COMMAND when MMU is ready to accept another command */ 53 status = wait_ready(pfdev, as_nr); 54 if (!status) 55 mmu_write(pfdev, AS_COMMAND(as_nr), cmd); 56 57 return status; 58 } 59 60 static void lock_region(struct panfrost_device *pfdev, u32 as_nr, 61 u64 region_start, u64 size) 62 { 63 u8 region_width; 64 u64 region; 65 u64 region_end = region_start + size; 66 67 if (!size) 68 return; 69 70 /* 71 * The locked region is a naturally aligned power of 2 block encoded as 72 * log2 minus(1). 73 * Calculate the desired start/end and look for the highest bit which 74 * differs. The smallest naturally aligned block must include this bit 75 * change, the desired region starts with this bit (and subsequent bits) 76 * zeroed and ends with the bit (and subsequent bits) set to one. 77 */ 78 region_width = max(fls64(region_start ^ (region_end - 1)), 79 const_ilog2(AS_LOCK_REGION_MIN_SIZE)) - 1; 80 81 /* 82 * Mask off the low bits of region_start (which would be ignored by 83 * the hardware anyway) 84 */ 85 region_start &= GENMASK_ULL(63, region_width); 86 87 region = region_width | region_start; 88 89 /* Lock the region that needs to be updated */ 90 mmu_write(pfdev, AS_LOCKADDR_LO(as_nr), lower_32_bits(region)); 91 mmu_write(pfdev, AS_LOCKADDR_HI(as_nr), upper_32_bits(region)); 92 write_cmd(pfdev, as_nr, AS_COMMAND_LOCK); 93 } 94 95 96 static int mmu_hw_do_operation_locked(struct panfrost_device *pfdev, int as_nr, 97 u64 iova, u64 size, u32 op) 98 { 99 if (as_nr < 0) 100 return 0; 101 102 if (op != AS_COMMAND_UNLOCK) 103 lock_region(pfdev, as_nr, iova, size); 104 105 /* Run the MMU operation */ 106 write_cmd(pfdev, as_nr, op); 107 108 /* Wait for the flush to complete */ 109 return wait_ready(pfdev, as_nr); 110 } 111 112 static int mmu_hw_do_operation(struct panfrost_device *pfdev, 113 struct panfrost_mmu *mmu, 114 u64 iova, u64 size, u32 op) 115 { 116 int ret; 117 118 spin_lock(&pfdev->as_lock); 119 ret = mmu_hw_do_operation_locked(pfdev, mmu->as, iova, size, op); 120 spin_unlock(&pfdev->as_lock); 121 return ret; 122 } 123 124 static void panfrost_mmu_enable(struct panfrost_device *pfdev, struct panfrost_mmu *mmu) 125 { 126 int as_nr = mmu->as; 127 struct io_pgtable_cfg *cfg = &mmu->pgtbl_cfg; 128 u64 transtab = cfg->arm_mali_lpae_cfg.transtab; 129 u64 memattr = cfg->arm_mali_lpae_cfg.memattr; 130 131 mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM); 132 133 mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), lower_32_bits(transtab)); 134 mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), upper_32_bits(transtab)); 135 136 /* Need to revisit mem attrs. 137 * NC is the default, Mali driver is inner WT. 138 */ 139 mmu_write(pfdev, AS_MEMATTR_LO(as_nr), lower_32_bits(memattr)); 140 mmu_write(pfdev, AS_MEMATTR_HI(as_nr), upper_32_bits(memattr)); 141 142 write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE); 143 } 144 145 static void panfrost_mmu_disable(struct panfrost_device *pfdev, u32 as_nr) 146 { 147 mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM); 148 149 mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), 0); 150 mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), 0); 151 152 mmu_write(pfdev, AS_MEMATTR_LO(as_nr), 0); 153 mmu_write(pfdev, AS_MEMATTR_HI(as_nr), 0); 154 155 write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE); 156 } 157 158 u32 panfrost_mmu_as_get(struct panfrost_device *pfdev, struct panfrost_mmu *mmu) 159 { 160 int as; 161 162 spin_lock(&pfdev->as_lock); 163 164 as = mmu->as; 165 if (as >= 0) { 166 int en = atomic_inc_return(&mmu->as_count); 167 u32 mask = BIT(as) | BIT(16 + as); 168 169 /* 170 * AS can be retained by active jobs or a perfcnt context, 171 * hence the '+ 1' here. 172 */ 173 WARN_ON(en >= (NUM_JOB_SLOTS + 1)); 174 175 list_move(&mmu->list, &pfdev->as_lru_list); 176 177 if (pfdev->as_faulty_mask & mask) { 178 /* Unhandled pagefault on this AS, the MMU was 179 * disabled. We need to re-enable the MMU after 180 * clearing+unmasking the AS interrupts. 181 */ 182 mmu_write(pfdev, MMU_INT_CLEAR, mask); 183 mmu_write(pfdev, MMU_INT_MASK, ~pfdev->as_faulty_mask); 184 pfdev->as_faulty_mask &= ~mask; 185 panfrost_mmu_enable(pfdev, mmu); 186 } 187 188 goto out; 189 } 190 191 /* Check for a free AS */ 192 as = ffz(pfdev->as_alloc_mask); 193 if (!(BIT(as) & pfdev->features.as_present)) { 194 struct panfrost_mmu *lru_mmu; 195 196 list_for_each_entry_reverse(lru_mmu, &pfdev->as_lru_list, list) { 197 if (!atomic_read(&lru_mmu->as_count)) 198 break; 199 } 200 WARN_ON(&lru_mmu->list == &pfdev->as_lru_list); 201 202 list_del_init(&lru_mmu->list); 203 as = lru_mmu->as; 204 205 WARN_ON(as < 0); 206 lru_mmu->as = -1; 207 } 208 209 /* Assign the free or reclaimed AS to the FD */ 210 mmu->as = as; 211 set_bit(as, &pfdev->as_alloc_mask); 212 atomic_set(&mmu->as_count, 1); 213 list_add(&mmu->list, &pfdev->as_lru_list); 214 215 dev_dbg(pfdev->dev, "Assigned AS%d to mmu %p, alloc_mask=%lx", as, mmu, pfdev->as_alloc_mask); 216 217 panfrost_mmu_enable(pfdev, mmu); 218 219 out: 220 spin_unlock(&pfdev->as_lock); 221 return as; 222 } 223 224 void panfrost_mmu_as_put(struct panfrost_device *pfdev, struct panfrost_mmu *mmu) 225 { 226 atomic_dec(&mmu->as_count); 227 WARN_ON(atomic_read(&mmu->as_count) < 0); 228 } 229 230 void panfrost_mmu_reset(struct panfrost_device *pfdev) 231 { 232 struct panfrost_mmu *mmu, *mmu_tmp; 233 234 spin_lock(&pfdev->as_lock); 235 236 pfdev->as_alloc_mask = 0; 237 pfdev->as_faulty_mask = 0; 238 239 list_for_each_entry_safe(mmu, mmu_tmp, &pfdev->as_lru_list, list) { 240 mmu->as = -1; 241 atomic_set(&mmu->as_count, 0); 242 list_del_init(&mmu->list); 243 } 244 245 spin_unlock(&pfdev->as_lock); 246 247 mmu_write(pfdev, MMU_INT_CLEAR, ~0); 248 mmu_write(pfdev, MMU_INT_MASK, ~0); 249 } 250 251 static size_t get_pgsize(u64 addr, size_t size) 252 { 253 if (addr & (SZ_2M - 1) || size < SZ_2M) 254 return SZ_4K; 255 256 return SZ_2M; 257 } 258 259 static void panfrost_mmu_flush_range(struct panfrost_device *pfdev, 260 struct panfrost_mmu *mmu, 261 u64 iova, u64 size) 262 { 263 if (mmu->as < 0) 264 return; 265 266 pm_runtime_get_noresume(pfdev->dev); 267 268 /* Flush the PTs only if we're already awake */ 269 if (pm_runtime_active(pfdev->dev)) 270 mmu_hw_do_operation(pfdev, mmu, iova, size, AS_COMMAND_FLUSH_PT); 271 272 pm_runtime_put_sync_autosuspend(pfdev->dev); 273 } 274 275 static int mmu_map_sg(struct panfrost_device *pfdev, struct panfrost_mmu *mmu, 276 u64 iova, int prot, struct sg_table *sgt) 277 { 278 unsigned int count; 279 struct scatterlist *sgl; 280 struct io_pgtable_ops *ops = mmu->pgtbl_ops; 281 u64 start_iova = iova; 282 283 for_each_sgtable_dma_sg(sgt, sgl, count) { 284 unsigned long paddr = sg_dma_address(sgl); 285 size_t len = sg_dma_len(sgl); 286 287 dev_dbg(pfdev->dev, "map: as=%d, iova=%llx, paddr=%lx, len=%zx", mmu->as, iova, paddr, len); 288 289 while (len) { 290 size_t pgsize = get_pgsize(iova | paddr, len); 291 292 ops->map(ops, iova, paddr, pgsize, prot, GFP_KERNEL); 293 iova += pgsize; 294 paddr += pgsize; 295 len -= pgsize; 296 } 297 } 298 299 panfrost_mmu_flush_range(pfdev, mmu, start_iova, iova - start_iova); 300 301 return 0; 302 } 303 304 int panfrost_mmu_map(struct panfrost_gem_mapping *mapping) 305 { 306 struct panfrost_gem_object *bo = mapping->obj; 307 struct drm_gem_object *obj = &bo->base.base; 308 struct panfrost_device *pfdev = to_panfrost_device(obj->dev); 309 struct sg_table *sgt; 310 int prot = IOMMU_READ | IOMMU_WRITE; 311 312 if (WARN_ON(mapping->active)) 313 return 0; 314 315 if (bo->noexec) 316 prot |= IOMMU_NOEXEC; 317 318 sgt = drm_gem_shmem_get_pages_sgt(obj); 319 if (WARN_ON(IS_ERR(sgt))) 320 return PTR_ERR(sgt); 321 322 mmu_map_sg(pfdev, mapping->mmu, mapping->mmnode.start << PAGE_SHIFT, 323 prot, sgt); 324 mapping->active = true; 325 326 return 0; 327 } 328 329 void panfrost_mmu_unmap(struct panfrost_gem_mapping *mapping) 330 { 331 struct panfrost_gem_object *bo = mapping->obj; 332 struct drm_gem_object *obj = &bo->base.base; 333 struct panfrost_device *pfdev = to_panfrost_device(obj->dev); 334 struct io_pgtable_ops *ops = mapping->mmu->pgtbl_ops; 335 u64 iova = mapping->mmnode.start << PAGE_SHIFT; 336 size_t len = mapping->mmnode.size << PAGE_SHIFT; 337 size_t unmapped_len = 0; 338 339 if (WARN_ON(!mapping->active)) 340 return; 341 342 dev_dbg(pfdev->dev, "unmap: as=%d, iova=%llx, len=%zx", 343 mapping->mmu->as, iova, len); 344 345 while (unmapped_len < len) { 346 size_t unmapped_page; 347 size_t pgsize = get_pgsize(iova, len - unmapped_len); 348 349 if (ops->iova_to_phys(ops, iova)) { 350 unmapped_page = ops->unmap(ops, iova, pgsize, NULL); 351 WARN_ON(unmapped_page != pgsize); 352 } 353 iova += pgsize; 354 unmapped_len += pgsize; 355 } 356 357 panfrost_mmu_flush_range(pfdev, mapping->mmu, 358 mapping->mmnode.start << PAGE_SHIFT, len); 359 mapping->active = false; 360 } 361 362 static void mmu_tlb_inv_context_s1(void *cookie) 363 {} 364 365 static void mmu_tlb_sync_context(void *cookie) 366 { 367 //struct panfrost_mmu *mmu = cookie; 368 // TODO: Wait 1000 GPU cycles for HW_ISSUE_6367/T60X 369 } 370 371 static void mmu_tlb_flush_walk(unsigned long iova, size_t size, size_t granule, 372 void *cookie) 373 { 374 mmu_tlb_sync_context(cookie); 375 } 376 377 static const struct iommu_flush_ops mmu_tlb_ops = { 378 .tlb_flush_all = mmu_tlb_inv_context_s1, 379 .tlb_flush_walk = mmu_tlb_flush_walk, 380 }; 381 382 static struct panfrost_gem_mapping * 383 addr_to_mapping(struct panfrost_device *pfdev, int as, u64 addr) 384 { 385 struct panfrost_gem_mapping *mapping = NULL; 386 struct drm_mm_node *node; 387 u64 offset = addr >> PAGE_SHIFT; 388 struct panfrost_mmu *mmu; 389 390 spin_lock(&pfdev->as_lock); 391 list_for_each_entry(mmu, &pfdev->as_lru_list, list) { 392 if (as == mmu->as) 393 goto found_mmu; 394 } 395 goto out; 396 397 found_mmu: 398 399 spin_lock(&mmu->mm_lock); 400 401 drm_mm_for_each_node(node, &mmu->mm) { 402 if (offset >= node->start && 403 offset < (node->start + node->size)) { 404 mapping = drm_mm_node_to_panfrost_mapping(node); 405 406 kref_get(&mapping->refcount); 407 break; 408 } 409 } 410 411 spin_unlock(&mmu->mm_lock); 412 out: 413 spin_unlock(&pfdev->as_lock); 414 return mapping; 415 } 416 417 #define NUM_FAULT_PAGES (SZ_2M / PAGE_SIZE) 418 419 static int panfrost_mmu_map_fault_addr(struct panfrost_device *pfdev, int as, 420 u64 addr) 421 { 422 int ret, i; 423 struct panfrost_gem_mapping *bomapping; 424 struct panfrost_gem_object *bo; 425 struct address_space *mapping; 426 pgoff_t page_offset; 427 struct sg_table *sgt; 428 struct page **pages; 429 430 bomapping = addr_to_mapping(pfdev, as, addr); 431 if (!bomapping) 432 return -ENOENT; 433 434 bo = bomapping->obj; 435 if (!bo->is_heap) { 436 dev_WARN(pfdev->dev, "matching BO is not heap type (GPU VA = %llx)", 437 bomapping->mmnode.start << PAGE_SHIFT); 438 ret = -EINVAL; 439 goto err_bo; 440 } 441 WARN_ON(bomapping->mmu->as != as); 442 443 /* Assume 2MB alignment and size multiple */ 444 addr &= ~((u64)SZ_2M - 1); 445 page_offset = addr >> PAGE_SHIFT; 446 page_offset -= bomapping->mmnode.start; 447 448 mutex_lock(&bo->base.pages_lock); 449 450 if (!bo->base.pages) { 451 bo->sgts = kvmalloc_array(bo->base.base.size / SZ_2M, 452 sizeof(struct sg_table), GFP_KERNEL | __GFP_ZERO); 453 if (!bo->sgts) { 454 mutex_unlock(&bo->base.pages_lock); 455 ret = -ENOMEM; 456 goto err_bo; 457 } 458 459 pages = kvmalloc_array(bo->base.base.size >> PAGE_SHIFT, 460 sizeof(struct page *), GFP_KERNEL | __GFP_ZERO); 461 if (!pages) { 462 kvfree(bo->sgts); 463 bo->sgts = NULL; 464 mutex_unlock(&bo->base.pages_lock); 465 ret = -ENOMEM; 466 goto err_bo; 467 } 468 bo->base.pages = pages; 469 bo->base.pages_use_count = 1; 470 } else { 471 pages = bo->base.pages; 472 if (pages[page_offset]) { 473 /* Pages are already mapped, bail out. */ 474 mutex_unlock(&bo->base.pages_lock); 475 goto out; 476 } 477 } 478 479 mapping = bo->base.base.filp->f_mapping; 480 mapping_set_unevictable(mapping); 481 482 for (i = page_offset; i < page_offset + NUM_FAULT_PAGES; i++) { 483 pages[i] = shmem_read_mapping_page(mapping, i); 484 if (IS_ERR(pages[i])) { 485 mutex_unlock(&bo->base.pages_lock); 486 ret = PTR_ERR(pages[i]); 487 goto err_pages; 488 } 489 } 490 491 mutex_unlock(&bo->base.pages_lock); 492 493 sgt = &bo->sgts[page_offset / (SZ_2M / PAGE_SIZE)]; 494 ret = sg_alloc_table_from_pages(sgt, pages + page_offset, 495 NUM_FAULT_PAGES, 0, SZ_2M, GFP_KERNEL); 496 if (ret) 497 goto err_pages; 498 499 ret = dma_map_sgtable(pfdev->dev, sgt, DMA_BIDIRECTIONAL, 0); 500 if (ret) 501 goto err_map; 502 503 mmu_map_sg(pfdev, bomapping->mmu, addr, 504 IOMMU_WRITE | IOMMU_READ | IOMMU_NOEXEC, sgt); 505 506 bomapping->active = true; 507 508 dev_dbg(pfdev->dev, "mapped page fault @ AS%d %llx", as, addr); 509 510 out: 511 panfrost_gem_mapping_put(bomapping); 512 513 return 0; 514 515 err_map: 516 sg_free_table(sgt); 517 err_pages: 518 drm_gem_shmem_put_pages(&bo->base); 519 err_bo: 520 drm_gem_object_put(&bo->base.base); 521 return ret; 522 } 523 524 static void panfrost_mmu_release_ctx(struct kref *kref) 525 { 526 struct panfrost_mmu *mmu = container_of(kref, struct panfrost_mmu, 527 refcount); 528 struct panfrost_device *pfdev = mmu->pfdev; 529 530 spin_lock(&pfdev->as_lock); 531 if (mmu->as >= 0) { 532 pm_runtime_get_noresume(pfdev->dev); 533 if (pm_runtime_active(pfdev->dev)) 534 panfrost_mmu_disable(pfdev, mmu->as); 535 pm_runtime_put_autosuspend(pfdev->dev); 536 537 clear_bit(mmu->as, &pfdev->as_alloc_mask); 538 clear_bit(mmu->as, &pfdev->as_in_use_mask); 539 list_del(&mmu->list); 540 } 541 spin_unlock(&pfdev->as_lock); 542 543 free_io_pgtable_ops(mmu->pgtbl_ops); 544 drm_mm_takedown(&mmu->mm); 545 kfree(mmu); 546 } 547 548 void panfrost_mmu_ctx_put(struct panfrost_mmu *mmu) 549 { 550 kref_put(&mmu->refcount, panfrost_mmu_release_ctx); 551 } 552 553 struct panfrost_mmu *panfrost_mmu_ctx_get(struct panfrost_mmu *mmu) 554 { 555 kref_get(&mmu->refcount); 556 557 return mmu; 558 } 559 560 #define PFN_4G (SZ_4G >> PAGE_SHIFT) 561 #define PFN_4G_MASK (PFN_4G - 1) 562 #define PFN_16M (SZ_16M >> PAGE_SHIFT) 563 564 static void panfrost_drm_mm_color_adjust(const struct drm_mm_node *node, 565 unsigned long color, 566 u64 *start, u64 *end) 567 { 568 /* Executable buffers can't start or end on a 4GB boundary */ 569 if (!(color & PANFROST_BO_NOEXEC)) { 570 u64 next_seg; 571 572 if ((*start & PFN_4G_MASK) == 0) 573 (*start)++; 574 575 if ((*end & PFN_4G_MASK) == 0) 576 (*end)--; 577 578 next_seg = ALIGN(*start, PFN_4G); 579 if (next_seg - *start <= PFN_16M) 580 *start = next_seg + 1; 581 582 *end = min(*end, ALIGN(*start, PFN_4G) - 1); 583 } 584 } 585 586 struct panfrost_mmu *panfrost_mmu_ctx_create(struct panfrost_device *pfdev) 587 { 588 struct panfrost_mmu *mmu; 589 590 mmu = kzalloc(sizeof(*mmu), GFP_KERNEL); 591 if (!mmu) 592 return ERR_PTR(-ENOMEM); 593 594 mmu->pfdev = pfdev; 595 spin_lock_init(&mmu->mm_lock); 596 597 /* 4G enough for now. can be 48-bit */ 598 drm_mm_init(&mmu->mm, SZ_32M >> PAGE_SHIFT, (SZ_4G - SZ_32M) >> PAGE_SHIFT); 599 mmu->mm.color_adjust = panfrost_drm_mm_color_adjust; 600 601 INIT_LIST_HEAD(&mmu->list); 602 mmu->as = -1; 603 604 mmu->pgtbl_cfg = (struct io_pgtable_cfg) { 605 .pgsize_bitmap = SZ_4K | SZ_2M, 606 .ias = FIELD_GET(0xff, pfdev->features.mmu_features), 607 .oas = FIELD_GET(0xff00, pfdev->features.mmu_features), 608 .coherent_walk = pfdev->coherent, 609 .tlb = &mmu_tlb_ops, 610 .iommu_dev = pfdev->dev, 611 }; 612 613 mmu->pgtbl_ops = alloc_io_pgtable_ops(ARM_MALI_LPAE, &mmu->pgtbl_cfg, 614 mmu); 615 if (!mmu->pgtbl_ops) { 616 kfree(mmu); 617 return ERR_PTR(-EINVAL); 618 } 619 620 kref_init(&mmu->refcount); 621 622 return mmu; 623 } 624 625 static const char *access_type_name(struct panfrost_device *pfdev, 626 u32 fault_status) 627 { 628 switch (fault_status & AS_FAULTSTATUS_ACCESS_TYPE_MASK) { 629 case AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC: 630 if (panfrost_has_hw_feature(pfdev, HW_FEATURE_AARCH64_MMU)) 631 return "ATOMIC"; 632 else 633 return "UNKNOWN"; 634 case AS_FAULTSTATUS_ACCESS_TYPE_READ: 635 return "READ"; 636 case AS_FAULTSTATUS_ACCESS_TYPE_WRITE: 637 return "WRITE"; 638 case AS_FAULTSTATUS_ACCESS_TYPE_EX: 639 return "EXECUTE"; 640 default: 641 WARN_ON(1); 642 return NULL; 643 } 644 } 645 646 static irqreturn_t panfrost_mmu_irq_handler(int irq, void *data) 647 { 648 struct panfrost_device *pfdev = data; 649 650 if (!mmu_read(pfdev, MMU_INT_STAT)) 651 return IRQ_NONE; 652 653 mmu_write(pfdev, MMU_INT_MASK, 0); 654 return IRQ_WAKE_THREAD; 655 } 656 657 static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data) 658 { 659 struct panfrost_device *pfdev = data; 660 u32 status = mmu_read(pfdev, MMU_INT_RAWSTAT); 661 int ret; 662 663 while (status) { 664 u32 as = ffs(status | (status >> 16)) - 1; 665 u32 mask = BIT(as) | BIT(as + 16); 666 u64 addr; 667 u32 fault_status; 668 u32 exception_type; 669 u32 access_type; 670 u32 source_id; 671 672 fault_status = mmu_read(pfdev, AS_FAULTSTATUS(as)); 673 addr = mmu_read(pfdev, AS_FAULTADDRESS_LO(as)); 674 addr |= (u64)mmu_read(pfdev, AS_FAULTADDRESS_HI(as)) << 32; 675 676 /* decode the fault status */ 677 exception_type = fault_status & 0xFF; 678 access_type = (fault_status >> 8) & 0x3; 679 source_id = (fault_status >> 16); 680 681 mmu_write(pfdev, MMU_INT_CLEAR, mask); 682 683 /* Page fault only */ 684 ret = -1; 685 if ((status & mask) == BIT(as) && (exception_type & 0xF8) == 0xC0) 686 ret = panfrost_mmu_map_fault_addr(pfdev, as, addr); 687 688 if (ret) { 689 /* terminal fault, print info about the fault */ 690 dev_err(pfdev->dev, 691 "Unhandled Page fault in AS%d at VA 0x%016llX\n" 692 "Reason: %s\n" 693 "raw fault status: 0x%X\n" 694 "decoded fault status: %s\n" 695 "exception type 0x%X: %s\n" 696 "access type 0x%X: %s\n" 697 "source id 0x%X\n", 698 as, addr, 699 "TODO", 700 fault_status, 701 (fault_status & (1 << 10) ? "DECODER FAULT" : "SLAVE FAULT"), 702 exception_type, panfrost_exception_name(exception_type), 703 access_type, access_type_name(pfdev, fault_status), 704 source_id); 705 706 spin_lock(&pfdev->as_lock); 707 /* Ignore MMU interrupts on this AS until it's been 708 * re-enabled. 709 */ 710 pfdev->as_faulty_mask |= mask; 711 712 /* Disable the MMU to kill jobs on this AS. */ 713 panfrost_mmu_disable(pfdev, as); 714 spin_unlock(&pfdev->as_lock); 715 } 716 717 status &= ~mask; 718 719 /* If we received new MMU interrupts, process them before returning. */ 720 if (!status) 721 status = mmu_read(pfdev, MMU_INT_RAWSTAT) & ~pfdev->as_faulty_mask; 722 } 723 724 spin_lock(&pfdev->as_lock); 725 mmu_write(pfdev, MMU_INT_MASK, ~pfdev->as_faulty_mask); 726 spin_unlock(&pfdev->as_lock); 727 728 return IRQ_HANDLED; 729 }; 730 731 int panfrost_mmu_init(struct panfrost_device *pfdev) 732 { 733 int err, irq; 734 735 irq = platform_get_irq_byname(to_platform_device(pfdev->dev), "mmu"); 736 if (irq <= 0) 737 return -ENODEV; 738 739 err = devm_request_threaded_irq(pfdev->dev, irq, 740 panfrost_mmu_irq_handler, 741 panfrost_mmu_irq_handler_thread, 742 IRQF_SHARED, KBUILD_MODNAME "-mmu", 743 pfdev); 744 745 if (err) { 746 dev_err(pfdev->dev, "failed to request mmu irq"); 747 return err; 748 } 749 750 return 0; 751 } 752 753 void panfrost_mmu_fini(struct panfrost_device *pfdev) 754 { 755 mmu_write(pfdev, MMU_INT_MASK, 0); 756 } 757