1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */ 3 #include <linux/atomic.h> 4 #include <linux/bitfield.h> 5 #include <linux/delay.h> 6 #include <linux/dma-mapping.h> 7 #include <linux/interrupt.h> 8 #include <linux/io.h> 9 #include <linux/iopoll.h> 10 #include <linux/io-pgtable.h> 11 #include <linux/iommu.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/shmem_fs.h> 15 #include <linux/sizes.h> 16 17 #include "panfrost_device.h" 18 #include "panfrost_mmu.h" 19 #include "panfrost_gem.h" 20 #include "panfrost_features.h" 21 #include "panfrost_regs.h" 22 23 #define mmu_write(dev, reg, data) writel(data, dev->iomem + reg) 24 #define mmu_read(dev, reg) readl(dev->iomem + reg) 25 26 static int wait_ready(struct panfrost_device *pfdev, u32 as_nr) 27 { 28 int ret; 29 u32 val; 30 31 /* Wait for the MMU status to indicate there is no active command, in 32 * case one is pending. */ 33 ret = readl_relaxed_poll_timeout_atomic(pfdev->iomem + AS_STATUS(as_nr), 34 val, !(val & AS_STATUS_AS_ACTIVE), 10, 1000); 35 36 if (ret) 37 dev_err(pfdev->dev, "AS_ACTIVE bit stuck\n"); 38 39 return ret; 40 } 41 42 static int write_cmd(struct panfrost_device *pfdev, u32 as_nr, u32 cmd) 43 { 44 int status; 45 46 /* write AS_COMMAND when MMU is ready to accept another command */ 47 status = wait_ready(pfdev, as_nr); 48 if (!status) 49 mmu_write(pfdev, AS_COMMAND(as_nr), cmd); 50 51 return status; 52 } 53 54 static void lock_region(struct panfrost_device *pfdev, u32 as_nr, 55 u64 iova, size_t size) 56 { 57 u8 region_width; 58 u64 region = iova & PAGE_MASK; 59 /* 60 * fls returns: 61 * 1 .. 32 62 * 63 * 10 + fls(num_pages) 64 * results in the range (11 .. 42) 65 */ 66 67 size = round_up(size, PAGE_SIZE); 68 69 region_width = 10 + fls(size >> PAGE_SHIFT); 70 if ((size >> PAGE_SHIFT) != (1ul << (region_width - 11))) { 71 /* not pow2, so must go up to the next pow2 */ 72 region_width += 1; 73 } 74 region |= region_width; 75 76 /* Lock the region that needs to be updated */ 77 mmu_write(pfdev, AS_LOCKADDR_LO(as_nr), region & 0xFFFFFFFFUL); 78 mmu_write(pfdev, AS_LOCKADDR_HI(as_nr), (region >> 32) & 0xFFFFFFFFUL); 79 write_cmd(pfdev, as_nr, AS_COMMAND_LOCK); 80 } 81 82 83 static int mmu_hw_do_operation(struct panfrost_device *pfdev, 84 struct panfrost_mmu *mmu, 85 u64 iova, size_t size, u32 op) 86 { 87 int ret, as_nr; 88 89 spin_lock(&pfdev->as_lock); 90 as_nr = mmu->as; 91 92 if (as_nr < 0) { 93 spin_unlock(&pfdev->as_lock); 94 return 0; 95 } 96 97 if (op != AS_COMMAND_UNLOCK) 98 lock_region(pfdev, as_nr, iova, size); 99 100 /* Run the MMU operation */ 101 write_cmd(pfdev, as_nr, op); 102 103 /* Wait for the flush to complete */ 104 ret = wait_ready(pfdev, as_nr); 105 106 spin_unlock(&pfdev->as_lock); 107 108 return ret; 109 } 110 111 static void panfrost_mmu_enable(struct panfrost_device *pfdev, struct panfrost_mmu *mmu) 112 { 113 int as_nr = mmu->as; 114 struct io_pgtable_cfg *cfg = &mmu->pgtbl_cfg; 115 u64 transtab = cfg->arm_mali_lpae_cfg.transtab; 116 u64 memattr = cfg->arm_mali_lpae_cfg.memattr; 117 118 mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), transtab & 0xffffffffUL); 119 mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), transtab >> 32); 120 121 /* Need to revisit mem attrs. 122 * NC is the default, Mali driver is inner WT. 123 */ 124 mmu_write(pfdev, AS_MEMATTR_LO(as_nr), memattr & 0xffffffffUL); 125 mmu_write(pfdev, AS_MEMATTR_HI(as_nr), memattr >> 32); 126 127 write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE); 128 } 129 130 static void mmu_disable(struct panfrost_device *pfdev, u32 as_nr) 131 { 132 mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), 0); 133 mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), 0); 134 135 mmu_write(pfdev, AS_MEMATTR_LO(as_nr), 0); 136 mmu_write(pfdev, AS_MEMATTR_HI(as_nr), 0); 137 138 write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE); 139 } 140 141 u32 panfrost_mmu_as_get(struct panfrost_device *pfdev, struct panfrost_mmu *mmu) 142 { 143 int as; 144 145 spin_lock(&pfdev->as_lock); 146 147 as = mmu->as; 148 if (as >= 0) { 149 int en = atomic_inc_return(&mmu->as_count); 150 WARN_ON(en >= NUM_JOB_SLOTS); 151 152 list_move(&mmu->list, &pfdev->as_lru_list); 153 goto out; 154 } 155 156 /* Check for a free AS */ 157 as = ffz(pfdev->as_alloc_mask); 158 if (!(BIT(as) & pfdev->features.as_present)) { 159 struct panfrost_mmu *lru_mmu; 160 161 list_for_each_entry_reverse(lru_mmu, &pfdev->as_lru_list, list) { 162 if (!atomic_read(&lru_mmu->as_count)) 163 break; 164 } 165 WARN_ON(&lru_mmu->list == &pfdev->as_lru_list); 166 167 list_del_init(&lru_mmu->list); 168 as = lru_mmu->as; 169 170 WARN_ON(as < 0); 171 lru_mmu->as = -1; 172 } 173 174 /* Assign the free or reclaimed AS to the FD */ 175 mmu->as = as; 176 set_bit(as, &pfdev->as_alloc_mask); 177 atomic_set(&mmu->as_count, 1); 178 list_add(&mmu->list, &pfdev->as_lru_list); 179 180 dev_dbg(pfdev->dev, "Assigned AS%d to mmu %p, alloc_mask=%lx", as, mmu, pfdev->as_alloc_mask); 181 182 panfrost_mmu_enable(pfdev, mmu); 183 184 out: 185 spin_unlock(&pfdev->as_lock); 186 return as; 187 } 188 189 void panfrost_mmu_as_put(struct panfrost_device *pfdev, struct panfrost_mmu *mmu) 190 { 191 atomic_dec(&mmu->as_count); 192 WARN_ON(atomic_read(&mmu->as_count) < 0); 193 } 194 195 void panfrost_mmu_reset(struct panfrost_device *pfdev) 196 { 197 struct panfrost_mmu *mmu, *mmu_tmp; 198 199 spin_lock(&pfdev->as_lock); 200 201 pfdev->as_alloc_mask = 0; 202 203 list_for_each_entry_safe(mmu, mmu_tmp, &pfdev->as_lru_list, list) { 204 mmu->as = -1; 205 atomic_set(&mmu->as_count, 0); 206 list_del_init(&mmu->list); 207 } 208 209 spin_unlock(&pfdev->as_lock); 210 211 mmu_write(pfdev, MMU_INT_CLEAR, ~0); 212 mmu_write(pfdev, MMU_INT_MASK, ~0); 213 } 214 215 static size_t get_pgsize(u64 addr, size_t size) 216 { 217 if (addr & (SZ_2M - 1) || size < SZ_2M) 218 return SZ_4K; 219 220 return SZ_2M; 221 } 222 223 static int mmu_map_sg(struct panfrost_device *pfdev, struct panfrost_mmu *mmu, 224 u64 iova, int prot, struct sg_table *sgt) 225 { 226 unsigned int count; 227 struct scatterlist *sgl; 228 struct io_pgtable_ops *ops = mmu->pgtbl_ops; 229 u64 start_iova = iova; 230 231 mutex_lock(&mmu->lock); 232 233 for_each_sg(sgt->sgl, sgl, sgt->nents, count) { 234 unsigned long paddr = sg_dma_address(sgl); 235 size_t len = sg_dma_len(sgl); 236 237 dev_dbg(pfdev->dev, "map: as=%d, iova=%llx, paddr=%lx, len=%zx", mmu->as, iova, paddr, len); 238 239 while (len) { 240 size_t pgsize = get_pgsize(iova | paddr, len); 241 242 ops->map(ops, iova, paddr, pgsize, prot); 243 iova += pgsize; 244 paddr += pgsize; 245 len -= pgsize; 246 } 247 } 248 249 mmu_hw_do_operation(pfdev, mmu, start_iova, iova - start_iova, 250 AS_COMMAND_FLUSH_PT); 251 252 mutex_unlock(&mmu->lock); 253 254 return 0; 255 } 256 257 int panfrost_mmu_map(struct panfrost_gem_object *bo) 258 { 259 struct drm_gem_object *obj = &bo->base.base; 260 struct panfrost_device *pfdev = to_panfrost_device(obj->dev); 261 struct sg_table *sgt; 262 int ret; 263 int prot = IOMMU_READ | IOMMU_WRITE; 264 265 if (WARN_ON(bo->is_mapped)) 266 return 0; 267 268 if (bo->noexec) 269 prot |= IOMMU_NOEXEC; 270 271 sgt = drm_gem_shmem_get_pages_sgt(obj); 272 if (WARN_ON(IS_ERR(sgt))) 273 return PTR_ERR(sgt); 274 275 ret = pm_runtime_get_sync(pfdev->dev); 276 if (ret < 0) 277 return ret; 278 279 mmu_map_sg(pfdev, bo->mmu, bo->node.start << PAGE_SHIFT, prot, sgt); 280 281 pm_runtime_mark_last_busy(pfdev->dev); 282 pm_runtime_put_autosuspend(pfdev->dev); 283 bo->is_mapped = true; 284 285 return 0; 286 } 287 288 void panfrost_mmu_unmap(struct panfrost_gem_object *bo) 289 { 290 struct drm_gem_object *obj = &bo->base.base; 291 struct panfrost_device *pfdev = to_panfrost_device(obj->dev); 292 struct io_pgtable_ops *ops = bo->mmu->pgtbl_ops; 293 u64 iova = bo->node.start << PAGE_SHIFT; 294 size_t len = bo->node.size << PAGE_SHIFT; 295 size_t unmapped_len = 0; 296 int ret; 297 298 if (WARN_ON(!bo->is_mapped)) 299 return; 300 301 dev_dbg(pfdev->dev, "unmap: as=%d, iova=%llx, len=%zx", bo->mmu->as, iova, len); 302 303 ret = pm_runtime_get_sync(pfdev->dev); 304 if (ret < 0) 305 return; 306 307 mutex_lock(&bo->mmu->lock); 308 309 while (unmapped_len < len) { 310 size_t unmapped_page; 311 size_t pgsize = get_pgsize(iova, len - unmapped_len); 312 313 if (ops->iova_to_phys(ops, iova)) { 314 unmapped_page = ops->unmap(ops, iova, pgsize); 315 WARN_ON(unmapped_page != pgsize); 316 } 317 iova += pgsize; 318 unmapped_len += pgsize; 319 } 320 321 mmu_hw_do_operation(pfdev, bo->mmu, bo->node.start << PAGE_SHIFT, 322 bo->node.size << PAGE_SHIFT, AS_COMMAND_FLUSH_PT); 323 324 mutex_unlock(&bo->mmu->lock); 325 326 pm_runtime_mark_last_busy(pfdev->dev); 327 pm_runtime_put_autosuspend(pfdev->dev); 328 bo->is_mapped = false; 329 } 330 331 static void mmu_tlb_inv_context_s1(void *cookie) 332 { 333 struct panfrost_file_priv *priv = cookie; 334 335 mmu_hw_do_operation(priv->pfdev, &priv->mmu, 0, ~0UL, AS_COMMAND_FLUSH_MEM); 336 } 337 338 static void mmu_tlb_inv_range_nosync(unsigned long iova, size_t size, 339 size_t granule, bool leaf, void *cookie) 340 {} 341 342 static void mmu_tlb_sync_context(void *cookie) 343 { 344 //struct panfrost_device *pfdev = cookie; 345 // TODO: Wait 1000 GPU cycles for HW_ISSUE_6367/T60X 346 } 347 348 static const struct iommu_gather_ops mmu_tlb_ops = { 349 .tlb_flush_all = mmu_tlb_inv_context_s1, 350 .tlb_add_flush = mmu_tlb_inv_range_nosync, 351 .tlb_sync = mmu_tlb_sync_context, 352 }; 353 354 int panfrost_mmu_pgtable_alloc(struct panfrost_file_priv *priv) 355 { 356 struct panfrost_mmu *mmu = &priv->mmu; 357 struct panfrost_device *pfdev = priv->pfdev; 358 359 mutex_init(&mmu->lock); 360 INIT_LIST_HEAD(&mmu->list); 361 mmu->as = -1; 362 363 mmu->pgtbl_cfg = (struct io_pgtable_cfg) { 364 .pgsize_bitmap = SZ_4K | SZ_2M, 365 .ias = FIELD_GET(0xff, pfdev->features.mmu_features), 366 .oas = FIELD_GET(0xff00, pfdev->features.mmu_features), 367 .tlb = &mmu_tlb_ops, 368 .iommu_dev = pfdev->dev, 369 }; 370 371 mmu->pgtbl_ops = alloc_io_pgtable_ops(ARM_MALI_LPAE, &mmu->pgtbl_cfg, 372 priv); 373 if (!mmu->pgtbl_ops) 374 return -EINVAL; 375 376 return 0; 377 } 378 379 void panfrost_mmu_pgtable_free(struct panfrost_file_priv *priv) 380 { 381 struct panfrost_device *pfdev = priv->pfdev; 382 struct panfrost_mmu *mmu = &priv->mmu; 383 384 spin_lock(&pfdev->as_lock); 385 if (mmu->as >= 0) { 386 clear_bit(mmu->as, &pfdev->as_alloc_mask); 387 clear_bit(mmu->as, &pfdev->as_in_use_mask); 388 list_del(&mmu->list); 389 } 390 spin_unlock(&pfdev->as_lock); 391 392 free_io_pgtable_ops(mmu->pgtbl_ops); 393 } 394 395 static struct drm_mm_node *addr_to_drm_mm_node(struct panfrost_device *pfdev, int as, u64 addr) 396 { 397 struct drm_mm_node *node = NULL; 398 u64 offset = addr >> PAGE_SHIFT; 399 struct panfrost_mmu *mmu; 400 401 spin_lock(&pfdev->as_lock); 402 list_for_each_entry(mmu, &pfdev->as_lru_list, list) { 403 struct panfrost_file_priv *priv; 404 if (as != mmu->as) 405 continue; 406 407 priv = container_of(mmu, struct panfrost_file_priv, mmu); 408 drm_mm_for_each_node(node, &priv->mm) { 409 if (offset >= node->start && offset < (node->start + node->size)) 410 goto out; 411 } 412 } 413 414 out: 415 spin_unlock(&pfdev->as_lock); 416 return node; 417 } 418 419 #define NUM_FAULT_PAGES (SZ_2M / PAGE_SIZE) 420 421 int panfrost_mmu_map_fault_addr(struct panfrost_device *pfdev, int as, u64 addr) 422 { 423 int ret, i; 424 struct drm_mm_node *node; 425 struct panfrost_gem_object *bo; 426 struct address_space *mapping; 427 pgoff_t page_offset; 428 struct sg_table *sgt; 429 struct page **pages; 430 431 node = addr_to_drm_mm_node(pfdev, as, addr); 432 if (!node) 433 return -ENOENT; 434 435 bo = drm_mm_node_to_panfrost_bo(node); 436 if (!bo->is_heap) { 437 dev_WARN(pfdev->dev, "matching BO is not heap type (GPU VA = %llx)", 438 node->start << PAGE_SHIFT); 439 return -EINVAL; 440 } 441 WARN_ON(bo->mmu->as != as); 442 443 /* Assume 2MB alignment and size multiple */ 444 addr &= ~((u64)SZ_2M - 1); 445 page_offset = addr >> PAGE_SHIFT; 446 page_offset -= node->start; 447 448 mutex_lock(&bo->base.pages_lock); 449 450 if (!bo->base.pages) { 451 bo->sgts = kvmalloc_array(bo->base.base.size / SZ_2M, 452 sizeof(struct sg_table), GFP_KERNEL | __GFP_ZERO); 453 if (!bo->sgts) { 454 mutex_unlock(&bo->base.pages_lock); 455 return -ENOMEM; 456 } 457 458 pages = kvmalloc_array(bo->base.base.size >> PAGE_SHIFT, 459 sizeof(struct page *), GFP_KERNEL | __GFP_ZERO); 460 if (!pages) { 461 kfree(bo->sgts); 462 bo->sgts = NULL; 463 mutex_unlock(&bo->base.pages_lock); 464 return -ENOMEM; 465 } 466 bo->base.pages = pages; 467 bo->base.pages_use_count = 1; 468 } else 469 pages = bo->base.pages; 470 471 mapping = bo->base.base.filp->f_mapping; 472 mapping_set_unevictable(mapping); 473 474 for (i = page_offset; i < page_offset + NUM_FAULT_PAGES; i++) { 475 pages[i] = shmem_read_mapping_page(mapping, i); 476 if (IS_ERR(pages[i])) { 477 mutex_unlock(&bo->base.pages_lock); 478 ret = PTR_ERR(pages[i]); 479 goto err_pages; 480 } 481 } 482 483 mutex_unlock(&bo->base.pages_lock); 484 485 sgt = &bo->sgts[page_offset / (SZ_2M / PAGE_SIZE)]; 486 ret = sg_alloc_table_from_pages(sgt, pages + page_offset, 487 NUM_FAULT_PAGES, 0, SZ_2M, GFP_KERNEL); 488 if (ret) 489 goto err_pages; 490 491 if (!dma_map_sg(pfdev->dev, sgt->sgl, sgt->nents, DMA_BIDIRECTIONAL)) { 492 ret = -EINVAL; 493 goto err_map; 494 } 495 496 mmu_map_sg(pfdev, bo->mmu, addr, IOMMU_WRITE | IOMMU_READ | IOMMU_NOEXEC, sgt); 497 498 bo->is_mapped = true; 499 500 dev_dbg(pfdev->dev, "mapped page fault @ AS%d %llx", as, addr); 501 502 return 0; 503 504 err_map: 505 sg_free_table(sgt); 506 err_pages: 507 drm_gem_shmem_put_pages(&bo->base); 508 return ret; 509 } 510 511 static const char *access_type_name(struct panfrost_device *pfdev, 512 u32 fault_status) 513 { 514 switch (fault_status & AS_FAULTSTATUS_ACCESS_TYPE_MASK) { 515 case AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC: 516 if (panfrost_has_hw_feature(pfdev, HW_FEATURE_AARCH64_MMU)) 517 return "ATOMIC"; 518 else 519 return "UNKNOWN"; 520 case AS_FAULTSTATUS_ACCESS_TYPE_READ: 521 return "READ"; 522 case AS_FAULTSTATUS_ACCESS_TYPE_WRITE: 523 return "WRITE"; 524 case AS_FAULTSTATUS_ACCESS_TYPE_EX: 525 return "EXECUTE"; 526 default: 527 WARN_ON(1); 528 return NULL; 529 } 530 } 531 532 static irqreturn_t panfrost_mmu_irq_handler(int irq, void *data) 533 { 534 struct panfrost_device *pfdev = data; 535 536 if (!mmu_read(pfdev, MMU_INT_STAT)) 537 return IRQ_NONE; 538 539 mmu_write(pfdev, MMU_INT_MASK, 0); 540 return IRQ_WAKE_THREAD; 541 } 542 543 static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data) 544 { 545 struct panfrost_device *pfdev = data; 546 u32 status = mmu_read(pfdev, MMU_INT_RAWSTAT); 547 int i, ret; 548 549 for (i = 0; status; i++) { 550 u32 mask = BIT(i) | BIT(i + 16); 551 u64 addr; 552 u32 fault_status; 553 u32 exception_type; 554 u32 access_type; 555 u32 source_id; 556 557 if (!(status & mask)) 558 continue; 559 560 fault_status = mmu_read(pfdev, AS_FAULTSTATUS(i)); 561 addr = mmu_read(pfdev, AS_FAULTADDRESS_LO(i)); 562 addr |= (u64)mmu_read(pfdev, AS_FAULTADDRESS_HI(i)) << 32; 563 564 /* decode the fault status */ 565 exception_type = fault_status & 0xFF; 566 access_type = (fault_status >> 8) & 0x3; 567 source_id = (fault_status >> 16); 568 569 /* Page fault only */ 570 if ((status & mask) == BIT(i)) { 571 WARN_ON(exception_type < 0xC1 || exception_type > 0xC4); 572 573 ret = panfrost_mmu_map_fault_addr(pfdev, i, addr); 574 if (!ret) { 575 mmu_write(pfdev, MMU_INT_CLEAR, BIT(i)); 576 status &= ~mask; 577 continue; 578 } 579 } 580 581 /* terminal fault, print info about the fault */ 582 dev_err(pfdev->dev, 583 "Unhandled Page fault in AS%d at VA 0x%016llX\n" 584 "Reason: %s\n" 585 "raw fault status: 0x%X\n" 586 "decoded fault status: %s\n" 587 "exception type 0x%X: %s\n" 588 "access type 0x%X: %s\n" 589 "source id 0x%X\n", 590 i, addr, 591 "TODO", 592 fault_status, 593 (fault_status & (1 << 10) ? "DECODER FAULT" : "SLAVE FAULT"), 594 exception_type, panfrost_exception_name(pfdev, exception_type), 595 access_type, access_type_name(pfdev, fault_status), 596 source_id); 597 598 mmu_write(pfdev, MMU_INT_CLEAR, mask); 599 600 status &= ~mask; 601 } 602 603 mmu_write(pfdev, MMU_INT_MASK, ~0); 604 return IRQ_HANDLED; 605 }; 606 607 int panfrost_mmu_init(struct panfrost_device *pfdev) 608 { 609 int err, irq; 610 611 irq = platform_get_irq_byname(to_platform_device(pfdev->dev), "mmu"); 612 if (irq <= 0) 613 return -ENODEV; 614 615 err = devm_request_threaded_irq(pfdev->dev, irq, panfrost_mmu_irq_handler, 616 panfrost_mmu_irq_handler_thread, 617 IRQF_SHARED, "mmu", pfdev); 618 619 if (err) { 620 dev_err(pfdev->dev, "failed to request mmu irq"); 621 return err; 622 } 623 624 return 0; 625 } 626 627 void panfrost_mmu_fini(struct panfrost_device *pfdev) 628 { 629 mmu_write(pfdev, MMU_INT_MASK, 0); 630 mmu_disable(pfdev, 0); 631 } 632