1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */ 3 4 #include <drm/panfrost_drm.h> 5 6 #include <linux/atomic.h> 7 #include <linux/bitfield.h> 8 #include <linux/delay.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/iopoll.h> 13 #include <linux/io-pgtable.h> 14 #include <linux/iommu.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/shmem_fs.h> 18 #include <linux/sizes.h> 19 20 #include "panfrost_device.h" 21 #include "panfrost_mmu.h" 22 #include "panfrost_gem.h" 23 #include "panfrost_features.h" 24 #include "panfrost_regs.h" 25 26 #define mmu_write(dev, reg, data) writel(data, dev->iomem + reg) 27 #define mmu_read(dev, reg) readl(dev->iomem + reg) 28 29 static int wait_ready(struct panfrost_device *pfdev, u32 as_nr) 30 { 31 int ret; 32 u32 val; 33 34 /* Wait for the MMU status to indicate there is no active command, in 35 * case one is pending. */ 36 ret = readl_relaxed_poll_timeout_atomic(pfdev->iomem + AS_STATUS(as_nr), 37 val, !(val & AS_STATUS_AS_ACTIVE), 10, 100000); 38 39 if (ret) { 40 /* The GPU hung, let's trigger a reset */ 41 panfrost_device_schedule_reset(pfdev); 42 dev_err(pfdev->dev, "AS_ACTIVE bit stuck\n"); 43 } 44 45 return ret; 46 } 47 48 static int write_cmd(struct panfrost_device *pfdev, u32 as_nr, u32 cmd) 49 { 50 int status; 51 52 /* write AS_COMMAND when MMU is ready to accept another command */ 53 status = wait_ready(pfdev, as_nr); 54 if (!status) 55 mmu_write(pfdev, AS_COMMAND(as_nr), cmd); 56 57 return status; 58 } 59 60 static void lock_region(struct panfrost_device *pfdev, u32 as_nr, 61 u64 iova, u64 size) 62 { 63 u8 region_width; 64 u64 region = iova & PAGE_MASK; 65 66 /* The size is encoded as ceil(log2) minus(1), which may be calculated 67 * with fls. The size must be clamped to hardware bounds. 68 */ 69 size = max_t(u64, size, AS_LOCK_REGION_MIN_SIZE); 70 region_width = fls64(size - 1) - 1; 71 region |= region_width; 72 73 /* Lock the region that needs to be updated */ 74 mmu_write(pfdev, AS_LOCKADDR_LO(as_nr), region & 0xFFFFFFFFUL); 75 mmu_write(pfdev, AS_LOCKADDR_HI(as_nr), (region >> 32) & 0xFFFFFFFFUL); 76 write_cmd(pfdev, as_nr, AS_COMMAND_LOCK); 77 } 78 79 80 static int mmu_hw_do_operation_locked(struct panfrost_device *pfdev, int as_nr, 81 u64 iova, u64 size, u32 op) 82 { 83 if (as_nr < 0) 84 return 0; 85 86 if (op != AS_COMMAND_UNLOCK) 87 lock_region(pfdev, as_nr, iova, size); 88 89 /* Run the MMU operation */ 90 write_cmd(pfdev, as_nr, op); 91 92 /* Wait for the flush to complete */ 93 return wait_ready(pfdev, as_nr); 94 } 95 96 static int mmu_hw_do_operation(struct panfrost_device *pfdev, 97 struct panfrost_mmu *mmu, 98 u64 iova, u64 size, u32 op) 99 { 100 int ret; 101 102 spin_lock(&pfdev->as_lock); 103 ret = mmu_hw_do_operation_locked(pfdev, mmu->as, iova, size, op); 104 spin_unlock(&pfdev->as_lock); 105 return ret; 106 } 107 108 static void panfrost_mmu_enable(struct panfrost_device *pfdev, struct panfrost_mmu *mmu) 109 { 110 int as_nr = mmu->as; 111 struct io_pgtable_cfg *cfg = &mmu->pgtbl_cfg; 112 u64 transtab = cfg->arm_mali_lpae_cfg.transtab; 113 u64 memattr = cfg->arm_mali_lpae_cfg.memattr; 114 115 mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM); 116 117 mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), transtab & 0xffffffffUL); 118 mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), transtab >> 32); 119 120 /* Need to revisit mem attrs. 121 * NC is the default, Mali driver is inner WT. 122 */ 123 mmu_write(pfdev, AS_MEMATTR_LO(as_nr), memattr & 0xffffffffUL); 124 mmu_write(pfdev, AS_MEMATTR_HI(as_nr), memattr >> 32); 125 126 write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE); 127 } 128 129 static void panfrost_mmu_disable(struct panfrost_device *pfdev, u32 as_nr) 130 { 131 mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM); 132 133 mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), 0); 134 mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), 0); 135 136 mmu_write(pfdev, AS_MEMATTR_LO(as_nr), 0); 137 mmu_write(pfdev, AS_MEMATTR_HI(as_nr), 0); 138 139 write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE); 140 } 141 142 u32 panfrost_mmu_as_get(struct panfrost_device *pfdev, struct panfrost_mmu *mmu) 143 { 144 int as; 145 146 spin_lock(&pfdev->as_lock); 147 148 as = mmu->as; 149 if (as >= 0) { 150 int en = atomic_inc_return(&mmu->as_count); 151 u32 mask = BIT(as) | BIT(16 + as); 152 153 /* 154 * AS can be retained by active jobs or a perfcnt context, 155 * hence the '+ 1' here. 156 */ 157 WARN_ON(en >= (NUM_JOB_SLOTS + 1)); 158 159 list_move(&mmu->list, &pfdev->as_lru_list); 160 161 if (pfdev->as_faulty_mask & mask) { 162 /* Unhandled pagefault on this AS, the MMU was 163 * disabled. We need to re-enable the MMU after 164 * clearing+unmasking the AS interrupts. 165 */ 166 mmu_write(pfdev, MMU_INT_CLEAR, mask); 167 mmu_write(pfdev, MMU_INT_MASK, ~pfdev->as_faulty_mask); 168 pfdev->as_faulty_mask &= ~mask; 169 panfrost_mmu_enable(pfdev, mmu); 170 } 171 172 goto out; 173 } 174 175 /* Check for a free AS */ 176 as = ffz(pfdev->as_alloc_mask); 177 if (!(BIT(as) & pfdev->features.as_present)) { 178 struct panfrost_mmu *lru_mmu; 179 180 list_for_each_entry_reverse(lru_mmu, &pfdev->as_lru_list, list) { 181 if (!atomic_read(&lru_mmu->as_count)) 182 break; 183 } 184 WARN_ON(&lru_mmu->list == &pfdev->as_lru_list); 185 186 list_del_init(&lru_mmu->list); 187 as = lru_mmu->as; 188 189 WARN_ON(as < 0); 190 lru_mmu->as = -1; 191 } 192 193 /* Assign the free or reclaimed AS to the FD */ 194 mmu->as = as; 195 set_bit(as, &pfdev->as_alloc_mask); 196 atomic_set(&mmu->as_count, 1); 197 list_add(&mmu->list, &pfdev->as_lru_list); 198 199 dev_dbg(pfdev->dev, "Assigned AS%d to mmu %p, alloc_mask=%lx", as, mmu, pfdev->as_alloc_mask); 200 201 panfrost_mmu_enable(pfdev, mmu); 202 203 out: 204 spin_unlock(&pfdev->as_lock); 205 return as; 206 } 207 208 void panfrost_mmu_as_put(struct panfrost_device *pfdev, struct panfrost_mmu *mmu) 209 { 210 atomic_dec(&mmu->as_count); 211 WARN_ON(atomic_read(&mmu->as_count) < 0); 212 } 213 214 void panfrost_mmu_reset(struct panfrost_device *pfdev) 215 { 216 struct panfrost_mmu *mmu, *mmu_tmp; 217 218 spin_lock(&pfdev->as_lock); 219 220 pfdev->as_alloc_mask = 0; 221 pfdev->as_faulty_mask = 0; 222 223 list_for_each_entry_safe(mmu, mmu_tmp, &pfdev->as_lru_list, list) { 224 mmu->as = -1; 225 atomic_set(&mmu->as_count, 0); 226 list_del_init(&mmu->list); 227 } 228 229 spin_unlock(&pfdev->as_lock); 230 231 mmu_write(pfdev, MMU_INT_CLEAR, ~0); 232 mmu_write(pfdev, MMU_INT_MASK, ~0); 233 } 234 235 static size_t get_pgsize(u64 addr, size_t size) 236 { 237 if (addr & (SZ_2M - 1) || size < SZ_2M) 238 return SZ_4K; 239 240 return SZ_2M; 241 } 242 243 static void panfrost_mmu_flush_range(struct panfrost_device *pfdev, 244 struct panfrost_mmu *mmu, 245 u64 iova, u64 size) 246 { 247 if (mmu->as < 0) 248 return; 249 250 pm_runtime_get_noresume(pfdev->dev); 251 252 /* Flush the PTs only if we're already awake */ 253 if (pm_runtime_active(pfdev->dev)) 254 mmu_hw_do_operation(pfdev, mmu, iova, size, AS_COMMAND_FLUSH_PT); 255 256 pm_runtime_put_sync_autosuspend(pfdev->dev); 257 } 258 259 static int mmu_map_sg(struct panfrost_device *pfdev, struct panfrost_mmu *mmu, 260 u64 iova, int prot, struct sg_table *sgt) 261 { 262 unsigned int count; 263 struct scatterlist *sgl; 264 struct io_pgtable_ops *ops = mmu->pgtbl_ops; 265 u64 start_iova = iova; 266 267 for_each_sgtable_dma_sg(sgt, sgl, count) { 268 unsigned long paddr = sg_dma_address(sgl); 269 size_t len = sg_dma_len(sgl); 270 271 dev_dbg(pfdev->dev, "map: as=%d, iova=%llx, paddr=%lx, len=%zx", mmu->as, iova, paddr, len); 272 273 while (len) { 274 size_t pgsize = get_pgsize(iova | paddr, len); 275 276 ops->map(ops, iova, paddr, pgsize, prot, GFP_KERNEL); 277 iova += pgsize; 278 paddr += pgsize; 279 len -= pgsize; 280 } 281 } 282 283 panfrost_mmu_flush_range(pfdev, mmu, start_iova, iova - start_iova); 284 285 return 0; 286 } 287 288 int panfrost_mmu_map(struct panfrost_gem_mapping *mapping) 289 { 290 struct panfrost_gem_object *bo = mapping->obj; 291 struct drm_gem_object *obj = &bo->base.base; 292 struct panfrost_device *pfdev = to_panfrost_device(obj->dev); 293 struct sg_table *sgt; 294 int prot = IOMMU_READ | IOMMU_WRITE; 295 296 if (WARN_ON(mapping->active)) 297 return 0; 298 299 if (bo->noexec) 300 prot |= IOMMU_NOEXEC; 301 302 sgt = drm_gem_shmem_get_pages_sgt(obj); 303 if (WARN_ON(IS_ERR(sgt))) 304 return PTR_ERR(sgt); 305 306 mmu_map_sg(pfdev, mapping->mmu, mapping->mmnode.start << PAGE_SHIFT, 307 prot, sgt); 308 mapping->active = true; 309 310 return 0; 311 } 312 313 void panfrost_mmu_unmap(struct panfrost_gem_mapping *mapping) 314 { 315 struct panfrost_gem_object *bo = mapping->obj; 316 struct drm_gem_object *obj = &bo->base.base; 317 struct panfrost_device *pfdev = to_panfrost_device(obj->dev); 318 struct io_pgtable_ops *ops = mapping->mmu->pgtbl_ops; 319 u64 iova = mapping->mmnode.start << PAGE_SHIFT; 320 size_t len = mapping->mmnode.size << PAGE_SHIFT; 321 size_t unmapped_len = 0; 322 323 if (WARN_ON(!mapping->active)) 324 return; 325 326 dev_dbg(pfdev->dev, "unmap: as=%d, iova=%llx, len=%zx", 327 mapping->mmu->as, iova, len); 328 329 while (unmapped_len < len) { 330 size_t unmapped_page; 331 size_t pgsize = get_pgsize(iova, len - unmapped_len); 332 333 if (ops->iova_to_phys(ops, iova)) { 334 unmapped_page = ops->unmap(ops, iova, pgsize, NULL); 335 WARN_ON(unmapped_page != pgsize); 336 } 337 iova += pgsize; 338 unmapped_len += pgsize; 339 } 340 341 panfrost_mmu_flush_range(pfdev, mapping->mmu, 342 mapping->mmnode.start << PAGE_SHIFT, len); 343 mapping->active = false; 344 } 345 346 static void mmu_tlb_inv_context_s1(void *cookie) 347 {} 348 349 static void mmu_tlb_sync_context(void *cookie) 350 { 351 //struct panfrost_mmu *mmu = cookie; 352 // TODO: Wait 1000 GPU cycles for HW_ISSUE_6367/T60X 353 } 354 355 static void mmu_tlb_flush_walk(unsigned long iova, size_t size, size_t granule, 356 void *cookie) 357 { 358 mmu_tlb_sync_context(cookie); 359 } 360 361 static const struct iommu_flush_ops mmu_tlb_ops = { 362 .tlb_flush_all = mmu_tlb_inv_context_s1, 363 .tlb_flush_walk = mmu_tlb_flush_walk, 364 }; 365 366 static struct panfrost_gem_mapping * 367 addr_to_mapping(struct panfrost_device *pfdev, int as, u64 addr) 368 { 369 struct panfrost_gem_mapping *mapping = NULL; 370 struct drm_mm_node *node; 371 u64 offset = addr >> PAGE_SHIFT; 372 struct panfrost_mmu *mmu; 373 374 spin_lock(&pfdev->as_lock); 375 list_for_each_entry(mmu, &pfdev->as_lru_list, list) { 376 if (as == mmu->as) 377 goto found_mmu; 378 } 379 goto out; 380 381 found_mmu: 382 383 spin_lock(&mmu->mm_lock); 384 385 drm_mm_for_each_node(node, &mmu->mm) { 386 if (offset >= node->start && 387 offset < (node->start + node->size)) { 388 mapping = drm_mm_node_to_panfrost_mapping(node); 389 390 kref_get(&mapping->refcount); 391 break; 392 } 393 } 394 395 spin_unlock(&mmu->mm_lock); 396 out: 397 spin_unlock(&pfdev->as_lock); 398 return mapping; 399 } 400 401 #define NUM_FAULT_PAGES (SZ_2M / PAGE_SIZE) 402 403 static int panfrost_mmu_map_fault_addr(struct panfrost_device *pfdev, int as, 404 u64 addr) 405 { 406 int ret, i; 407 struct panfrost_gem_mapping *bomapping; 408 struct panfrost_gem_object *bo; 409 struct address_space *mapping; 410 pgoff_t page_offset; 411 struct sg_table *sgt; 412 struct page **pages; 413 414 bomapping = addr_to_mapping(pfdev, as, addr); 415 if (!bomapping) 416 return -ENOENT; 417 418 bo = bomapping->obj; 419 if (!bo->is_heap) { 420 dev_WARN(pfdev->dev, "matching BO is not heap type (GPU VA = %llx)", 421 bomapping->mmnode.start << PAGE_SHIFT); 422 ret = -EINVAL; 423 goto err_bo; 424 } 425 WARN_ON(bomapping->mmu->as != as); 426 427 /* Assume 2MB alignment and size multiple */ 428 addr &= ~((u64)SZ_2M - 1); 429 page_offset = addr >> PAGE_SHIFT; 430 page_offset -= bomapping->mmnode.start; 431 432 mutex_lock(&bo->base.pages_lock); 433 434 if (!bo->base.pages) { 435 bo->sgts = kvmalloc_array(bo->base.base.size / SZ_2M, 436 sizeof(struct sg_table), GFP_KERNEL | __GFP_ZERO); 437 if (!bo->sgts) { 438 mutex_unlock(&bo->base.pages_lock); 439 ret = -ENOMEM; 440 goto err_bo; 441 } 442 443 pages = kvmalloc_array(bo->base.base.size >> PAGE_SHIFT, 444 sizeof(struct page *), GFP_KERNEL | __GFP_ZERO); 445 if (!pages) { 446 kvfree(bo->sgts); 447 bo->sgts = NULL; 448 mutex_unlock(&bo->base.pages_lock); 449 ret = -ENOMEM; 450 goto err_bo; 451 } 452 bo->base.pages = pages; 453 bo->base.pages_use_count = 1; 454 } else { 455 pages = bo->base.pages; 456 if (pages[page_offset]) { 457 /* Pages are already mapped, bail out. */ 458 mutex_unlock(&bo->base.pages_lock); 459 goto out; 460 } 461 } 462 463 mapping = bo->base.base.filp->f_mapping; 464 mapping_set_unevictable(mapping); 465 466 for (i = page_offset; i < page_offset + NUM_FAULT_PAGES; i++) { 467 pages[i] = shmem_read_mapping_page(mapping, i); 468 if (IS_ERR(pages[i])) { 469 mutex_unlock(&bo->base.pages_lock); 470 ret = PTR_ERR(pages[i]); 471 goto err_pages; 472 } 473 } 474 475 mutex_unlock(&bo->base.pages_lock); 476 477 sgt = &bo->sgts[page_offset / (SZ_2M / PAGE_SIZE)]; 478 ret = sg_alloc_table_from_pages(sgt, pages + page_offset, 479 NUM_FAULT_PAGES, 0, SZ_2M, GFP_KERNEL); 480 if (ret) 481 goto err_pages; 482 483 ret = dma_map_sgtable(pfdev->dev, sgt, DMA_BIDIRECTIONAL, 0); 484 if (ret) 485 goto err_map; 486 487 mmu_map_sg(pfdev, bomapping->mmu, addr, 488 IOMMU_WRITE | IOMMU_READ | IOMMU_NOEXEC, sgt); 489 490 bomapping->active = true; 491 492 dev_dbg(pfdev->dev, "mapped page fault @ AS%d %llx", as, addr); 493 494 out: 495 panfrost_gem_mapping_put(bomapping); 496 497 return 0; 498 499 err_map: 500 sg_free_table(sgt); 501 err_pages: 502 drm_gem_shmem_put_pages(&bo->base); 503 err_bo: 504 drm_gem_object_put(&bo->base.base); 505 return ret; 506 } 507 508 static void panfrost_mmu_release_ctx(struct kref *kref) 509 { 510 struct panfrost_mmu *mmu = container_of(kref, struct panfrost_mmu, 511 refcount); 512 struct panfrost_device *pfdev = mmu->pfdev; 513 514 spin_lock(&pfdev->as_lock); 515 if (mmu->as >= 0) { 516 pm_runtime_get_noresume(pfdev->dev); 517 if (pm_runtime_active(pfdev->dev)) 518 panfrost_mmu_disable(pfdev, mmu->as); 519 pm_runtime_put_autosuspend(pfdev->dev); 520 521 clear_bit(mmu->as, &pfdev->as_alloc_mask); 522 clear_bit(mmu->as, &pfdev->as_in_use_mask); 523 list_del(&mmu->list); 524 } 525 spin_unlock(&pfdev->as_lock); 526 527 free_io_pgtable_ops(mmu->pgtbl_ops); 528 drm_mm_takedown(&mmu->mm); 529 kfree(mmu); 530 } 531 532 void panfrost_mmu_ctx_put(struct panfrost_mmu *mmu) 533 { 534 kref_put(&mmu->refcount, panfrost_mmu_release_ctx); 535 } 536 537 struct panfrost_mmu *panfrost_mmu_ctx_get(struct panfrost_mmu *mmu) 538 { 539 kref_get(&mmu->refcount); 540 541 return mmu; 542 } 543 544 #define PFN_4G (SZ_4G >> PAGE_SHIFT) 545 #define PFN_4G_MASK (PFN_4G - 1) 546 #define PFN_16M (SZ_16M >> PAGE_SHIFT) 547 548 static void panfrost_drm_mm_color_adjust(const struct drm_mm_node *node, 549 unsigned long color, 550 u64 *start, u64 *end) 551 { 552 /* Executable buffers can't start or end on a 4GB boundary */ 553 if (!(color & PANFROST_BO_NOEXEC)) { 554 u64 next_seg; 555 556 if ((*start & PFN_4G_MASK) == 0) 557 (*start)++; 558 559 if ((*end & PFN_4G_MASK) == 0) 560 (*end)--; 561 562 next_seg = ALIGN(*start, PFN_4G); 563 if (next_seg - *start <= PFN_16M) 564 *start = next_seg + 1; 565 566 *end = min(*end, ALIGN(*start, PFN_4G) - 1); 567 } 568 } 569 570 struct panfrost_mmu *panfrost_mmu_ctx_create(struct panfrost_device *pfdev) 571 { 572 struct panfrost_mmu *mmu; 573 574 mmu = kzalloc(sizeof(*mmu), GFP_KERNEL); 575 if (!mmu) 576 return ERR_PTR(-ENOMEM); 577 578 mmu->pfdev = pfdev; 579 spin_lock_init(&mmu->mm_lock); 580 581 /* 4G enough for now. can be 48-bit */ 582 drm_mm_init(&mmu->mm, SZ_32M >> PAGE_SHIFT, (SZ_4G - SZ_32M) >> PAGE_SHIFT); 583 mmu->mm.color_adjust = panfrost_drm_mm_color_adjust; 584 585 INIT_LIST_HEAD(&mmu->list); 586 mmu->as = -1; 587 588 mmu->pgtbl_cfg = (struct io_pgtable_cfg) { 589 .pgsize_bitmap = SZ_4K | SZ_2M, 590 .ias = FIELD_GET(0xff, pfdev->features.mmu_features), 591 .oas = FIELD_GET(0xff00, pfdev->features.mmu_features), 592 .coherent_walk = pfdev->coherent, 593 .tlb = &mmu_tlb_ops, 594 .iommu_dev = pfdev->dev, 595 }; 596 597 mmu->pgtbl_ops = alloc_io_pgtable_ops(ARM_MALI_LPAE, &mmu->pgtbl_cfg, 598 mmu); 599 if (!mmu->pgtbl_ops) { 600 kfree(mmu); 601 return ERR_PTR(-EINVAL); 602 } 603 604 kref_init(&mmu->refcount); 605 606 return mmu; 607 } 608 609 static const char *access_type_name(struct panfrost_device *pfdev, 610 u32 fault_status) 611 { 612 switch (fault_status & AS_FAULTSTATUS_ACCESS_TYPE_MASK) { 613 case AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC: 614 if (panfrost_has_hw_feature(pfdev, HW_FEATURE_AARCH64_MMU)) 615 return "ATOMIC"; 616 else 617 return "UNKNOWN"; 618 case AS_FAULTSTATUS_ACCESS_TYPE_READ: 619 return "READ"; 620 case AS_FAULTSTATUS_ACCESS_TYPE_WRITE: 621 return "WRITE"; 622 case AS_FAULTSTATUS_ACCESS_TYPE_EX: 623 return "EXECUTE"; 624 default: 625 WARN_ON(1); 626 return NULL; 627 } 628 } 629 630 static irqreturn_t panfrost_mmu_irq_handler(int irq, void *data) 631 { 632 struct panfrost_device *pfdev = data; 633 634 if (!mmu_read(pfdev, MMU_INT_STAT)) 635 return IRQ_NONE; 636 637 mmu_write(pfdev, MMU_INT_MASK, 0); 638 return IRQ_WAKE_THREAD; 639 } 640 641 static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data) 642 { 643 struct panfrost_device *pfdev = data; 644 u32 status = mmu_read(pfdev, MMU_INT_RAWSTAT); 645 int ret; 646 647 while (status) { 648 u32 as = ffs(status | (status >> 16)) - 1; 649 u32 mask = BIT(as) | BIT(as + 16); 650 u64 addr; 651 u32 fault_status; 652 u32 exception_type; 653 u32 access_type; 654 u32 source_id; 655 656 fault_status = mmu_read(pfdev, AS_FAULTSTATUS(as)); 657 addr = mmu_read(pfdev, AS_FAULTADDRESS_LO(as)); 658 addr |= (u64)mmu_read(pfdev, AS_FAULTADDRESS_HI(as)) << 32; 659 660 /* decode the fault status */ 661 exception_type = fault_status & 0xFF; 662 access_type = (fault_status >> 8) & 0x3; 663 source_id = (fault_status >> 16); 664 665 mmu_write(pfdev, MMU_INT_CLEAR, mask); 666 667 /* Page fault only */ 668 ret = -1; 669 if ((status & mask) == BIT(as) && (exception_type & 0xF8) == 0xC0) 670 ret = panfrost_mmu_map_fault_addr(pfdev, as, addr); 671 672 if (ret) { 673 /* terminal fault, print info about the fault */ 674 dev_err(pfdev->dev, 675 "Unhandled Page fault in AS%d at VA 0x%016llX\n" 676 "Reason: %s\n" 677 "raw fault status: 0x%X\n" 678 "decoded fault status: %s\n" 679 "exception type 0x%X: %s\n" 680 "access type 0x%X: %s\n" 681 "source id 0x%X\n", 682 as, addr, 683 "TODO", 684 fault_status, 685 (fault_status & (1 << 10) ? "DECODER FAULT" : "SLAVE FAULT"), 686 exception_type, panfrost_exception_name(exception_type), 687 access_type, access_type_name(pfdev, fault_status), 688 source_id); 689 690 spin_lock(&pfdev->as_lock); 691 /* Ignore MMU interrupts on this AS until it's been 692 * re-enabled. 693 */ 694 pfdev->as_faulty_mask |= mask; 695 696 /* Disable the MMU to kill jobs on this AS. */ 697 panfrost_mmu_disable(pfdev, as); 698 spin_unlock(&pfdev->as_lock); 699 } 700 701 status &= ~mask; 702 703 /* If we received new MMU interrupts, process them before returning. */ 704 if (!status) 705 status = mmu_read(pfdev, MMU_INT_RAWSTAT) & ~pfdev->as_faulty_mask; 706 } 707 708 spin_lock(&pfdev->as_lock); 709 mmu_write(pfdev, MMU_INT_MASK, ~pfdev->as_faulty_mask); 710 spin_unlock(&pfdev->as_lock); 711 712 return IRQ_HANDLED; 713 }; 714 715 int panfrost_mmu_init(struct panfrost_device *pfdev) 716 { 717 int err, irq; 718 719 irq = platform_get_irq_byname(to_platform_device(pfdev->dev), "mmu"); 720 if (irq <= 0) 721 return -ENODEV; 722 723 err = devm_request_threaded_irq(pfdev->dev, irq, 724 panfrost_mmu_irq_handler, 725 panfrost_mmu_irq_handler_thread, 726 IRQF_SHARED, KBUILD_MODNAME "-mmu", 727 pfdev); 728 729 if (err) { 730 dev_err(pfdev->dev, "failed to request mmu irq"); 731 return err; 732 } 733 734 return 0; 735 } 736 737 void panfrost_mmu_fini(struct panfrost_device *pfdev) 738 { 739 mmu_write(pfdev, MMU_INT_MASK, 0); 740 } 741