1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */ 3 /* Copyright 2019 Linaro, Ltd., Rob Herring <robh@kernel.org> */ 4 /* Copyright 2019 Collabora ltd. */ 5 #include <linux/bitfield.h> 6 #include <linux/bitmap.h> 7 #include <linux/delay.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/interrupt.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_runtime.h> 14 15 #include "panfrost_device.h" 16 #include "panfrost_features.h" 17 #include "panfrost_issues.h" 18 #include "panfrost_gpu.h" 19 #include "panfrost_perfcnt.h" 20 #include "panfrost_regs.h" 21 22 static irqreturn_t panfrost_gpu_irq_handler(int irq, void *data) 23 { 24 struct panfrost_device *pfdev = data; 25 u32 state = gpu_read(pfdev, GPU_INT_STAT); 26 u32 fault_status = gpu_read(pfdev, GPU_FAULT_STATUS); 27 28 if (!state) 29 return IRQ_NONE; 30 31 if (state & GPU_IRQ_MASK_ERROR) { 32 u64 address = (u64) gpu_read(pfdev, GPU_FAULT_ADDRESS_HI) << 32; 33 address |= gpu_read(pfdev, GPU_FAULT_ADDRESS_LO); 34 35 dev_warn(pfdev->dev, "GPU Fault 0x%08x (%s) at 0x%016llx\n", 36 fault_status, panfrost_exception_name(fault_status & 0xFF), 37 address); 38 39 if (state & GPU_IRQ_MULTIPLE_FAULT) 40 dev_warn(pfdev->dev, "There were multiple GPU faults - some have not been reported\n"); 41 42 gpu_write(pfdev, GPU_INT_MASK, 0); 43 } 44 45 if (state & GPU_IRQ_PERFCNT_SAMPLE_COMPLETED) 46 panfrost_perfcnt_sample_done(pfdev); 47 48 if (state & GPU_IRQ_CLEAN_CACHES_COMPLETED) 49 panfrost_perfcnt_clean_cache_done(pfdev); 50 51 gpu_write(pfdev, GPU_INT_CLEAR, state); 52 53 return IRQ_HANDLED; 54 } 55 56 int panfrost_gpu_soft_reset(struct panfrost_device *pfdev) 57 { 58 int ret; 59 u32 val; 60 61 gpu_write(pfdev, GPU_INT_MASK, 0); 62 gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED); 63 gpu_write(pfdev, GPU_CMD, GPU_CMD_SOFT_RESET); 64 65 ret = readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT, 66 val, val & GPU_IRQ_RESET_COMPLETED, 100, 10000); 67 68 if (ret) { 69 dev_err(pfdev->dev, "gpu soft reset timed out\n"); 70 return ret; 71 } 72 73 gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_MASK_ALL); 74 75 /* Only enable the interrupts we care about */ 76 gpu_write(pfdev, GPU_INT_MASK, 77 GPU_IRQ_MASK_ERROR | 78 GPU_IRQ_PERFCNT_SAMPLE_COMPLETED | 79 GPU_IRQ_CLEAN_CACHES_COMPLETED); 80 81 return 0; 82 } 83 84 void panfrost_gpu_amlogic_quirk(struct panfrost_device *pfdev) 85 { 86 /* 87 * The Amlogic integrated Mali-T820, Mali-G31 & Mali-G52 needs 88 * these undocumented bits in GPU_PWR_OVERRIDE1 to be set in order 89 * to operate correctly. 90 */ 91 gpu_write(pfdev, GPU_PWR_KEY, GPU_PWR_KEY_UNLOCK); 92 gpu_write(pfdev, GPU_PWR_OVERRIDE1, 0xfff | (0x20 << 16)); 93 } 94 95 static void panfrost_gpu_init_quirks(struct panfrost_device *pfdev) 96 { 97 u32 quirks = 0; 98 99 if (panfrost_has_hw_issue(pfdev, HW_ISSUE_8443) || 100 panfrost_has_hw_issue(pfdev, HW_ISSUE_11035)) 101 quirks |= SC_LS_PAUSEBUFFER_DISABLE; 102 103 if (panfrost_has_hw_issue(pfdev, HW_ISSUE_10327)) 104 quirks |= SC_SDC_DISABLE_OQ_DISCARD; 105 106 if (panfrost_has_hw_issue(pfdev, HW_ISSUE_10797)) 107 quirks |= SC_ENABLE_TEXGRD_FLAGS; 108 109 if (!panfrost_has_hw_issue(pfdev, GPUCORE_1619)) { 110 if (panfrost_model_cmp(pfdev, 0x750) < 0) /* T60x, T62x, T72x */ 111 quirks |= SC_LS_ATTR_CHECK_DISABLE; 112 else if (panfrost_model_cmp(pfdev, 0x880) <= 0) /* T76x, T8xx */ 113 quirks |= SC_LS_ALLOW_ATTR_TYPES; 114 } 115 116 if (panfrost_has_hw_issue(pfdev, HW_ISSUE_TTRX_2968_TTRX_3162)) 117 quirks |= SC_VAR_ALGORITHM; 118 119 if (panfrost_has_hw_feature(pfdev, HW_FEATURE_TLS_HASHING)) 120 quirks |= SC_TLS_HASH_ENABLE; 121 122 if (quirks) 123 gpu_write(pfdev, GPU_SHADER_CONFIG, quirks); 124 125 126 quirks = gpu_read(pfdev, GPU_TILER_CONFIG); 127 128 /* Set tiler clock gate override if required */ 129 if (panfrost_has_hw_issue(pfdev, HW_ISSUE_T76X_3953)) 130 quirks |= TC_CLOCK_GATE_OVERRIDE; 131 132 gpu_write(pfdev, GPU_TILER_CONFIG, quirks); 133 134 135 quirks = 0; 136 if ((panfrost_model_eq(pfdev, 0x860) || panfrost_model_eq(pfdev, 0x880)) && 137 pfdev->features.revision >= 0x2000) 138 quirks |= JM_MAX_JOB_THROTTLE_LIMIT << JM_JOB_THROTTLE_LIMIT_SHIFT; 139 else if (panfrost_model_eq(pfdev, 0x6000) && 140 pfdev->features.coherency_features == COHERENCY_ACE) 141 quirks |= (COHERENCY_ACE_LITE | COHERENCY_ACE) << 142 JM_FORCE_COHERENCY_FEATURES_SHIFT; 143 144 if (panfrost_has_hw_feature(pfdev, HW_FEATURE_IDVS_GROUP_SIZE)) 145 quirks |= JM_DEFAULT_IDVS_GROUP_SIZE << JM_IDVS_GROUP_SIZE_SHIFT; 146 147 if (quirks) 148 gpu_write(pfdev, GPU_JM_CONFIG, quirks); 149 150 /* Here goes platform specific quirks */ 151 if (pfdev->comp->vendor_quirk) 152 pfdev->comp->vendor_quirk(pfdev); 153 } 154 155 #define MAX_HW_REVS 6 156 157 struct panfrost_model { 158 const char *name; 159 u32 id; 160 u64 features; 161 u64 issues; 162 struct { 163 u32 revision; 164 u64 issues; 165 } revs[MAX_HW_REVS]; 166 }; 167 168 #define GPU_MODEL(_name, _id, ...) \ 169 {\ 170 .name = __stringify(_name), \ 171 .id = _id, \ 172 .features = hw_features_##_name, \ 173 .issues = hw_issues_##_name, \ 174 .revs = { __VA_ARGS__ }, \ 175 } 176 177 #define GPU_REV_EXT(name, _rev, _p, _s, stat) \ 178 {\ 179 .revision = (_rev) << 12 | (_p) << 4 | (_s), \ 180 .issues = hw_issues_##name##_r##_rev##p##_p##stat, \ 181 } 182 #define GPU_REV(name, r, p) GPU_REV_EXT(name, r, p, 0, ) 183 184 static const struct panfrost_model gpu_models[] = { 185 /* T60x has an oddball version */ 186 GPU_MODEL(t600, 0x600, 187 GPU_REV_EXT(t600, 0, 0, 1, _15dev0)), 188 GPU_MODEL(t620, 0x620, 189 GPU_REV(t620, 0, 1), GPU_REV(t620, 1, 0)), 190 GPU_MODEL(t720, 0x720), 191 GPU_MODEL(t760, 0x750, 192 GPU_REV(t760, 0, 0), GPU_REV(t760, 0, 1), 193 GPU_REV_EXT(t760, 0, 1, 0, _50rel0), 194 GPU_REV(t760, 0, 2), GPU_REV(t760, 0, 3)), 195 GPU_MODEL(t820, 0x820), 196 GPU_MODEL(t830, 0x830), 197 GPU_MODEL(t860, 0x860), 198 GPU_MODEL(t880, 0x880), 199 200 GPU_MODEL(g71, 0x6000, 201 GPU_REV_EXT(g71, 0, 0, 1, _05dev0)), 202 GPU_MODEL(g72, 0x6001), 203 GPU_MODEL(g51, 0x7000), 204 GPU_MODEL(g76, 0x7001), 205 GPU_MODEL(g52, 0x7002), 206 GPU_MODEL(g31, 0x7003, 207 GPU_REV(g31, 1, 0)), 208 209 GPU_MODEL(g57, 0x9001, 210 GPU_REV(g57, 0, 0)), 211 212 /* MediaTek MT8192 has a Mali-G57 with a different GPU ID from the 213 * standard. Arm's driver does not appear to handle this model. 214 * ChromeOS has a hack downstream for it. Treat it as equivalent to 215 * standard Mali-G57 for now. 216 */ 217 GPU_MODEL(g57, 0x9003, 218 GPU_REV(g57, 0, 0)), 219 }; 220 221 static void panfrost_gpu_init_features(struct panfrost_device *pfdev) 222 { 223 u32 gpu_id, num_js, major, minor, status, rev; 224 const char *name = "unknown"; 225 u64 hw_feat = 0; 226 u64 hw_issues = hw_issues_all; 227 const struct panfrost_model *model; 228 int i; 229 230 pfdev->features.l2_features = gpu_read(pfdev, GPU_L2_FEATURES); 231 pfdev->features.core_features = gpu_read(pfdev, GPU_CORE_FEATURES); 232 pfdev->features.tiler_features = gpu_read(pfdev, GPU_TILER_FEATURES); 233 pfdev->features.mem_features = gpu_read(pfdev, GPU_MEM_FEATURES); 234 pfdev->features.mmu_features = gpu_read(pfdev, GPU_MMU_FEATURES); 235 pfdev->features.thread_features = gpu_read(pfdev, GPU_THREAD_FEATURES); 236 pfdev->features.max_threads = gpu_read(pfdev, GPU_THREAD_MAX_THREADS); 237 pfdev->features.thread_max_workgroup_sz = gpu_read(pfdev, GPU_THREAD_MAX_WORKGROUP_SIZE); 238 pfdev->features.thread_max_barrier_sz = gpu_read(pfdev, GPU_THREAD_MAX_BARRIER_SIZE); 239 pfdev->features.coherency_features = gpu_read(pfdev, GPU_COHERENCY_FEATURES); 240 pfdev->features.afbc_features = gpu_read(pfdev, GPU_AFBC_FEATURES); 241 for (i = 0; i < 4; i++) 242 pfdev->features.texture_features[i] = gpu_read(pfdev, GPU_TEXTURE_FEATURES(i)); 243 244 pfdev->features.as_present = gpu_read(pfdev, GPU_AS_PRESENT); 245 246 pfdev->features.js_present = gpu_read(pfdev, GPU_JS_PRESENT); 247 num_js = hweight32(pfdev->features.js_present); 248 for (i = 0; i < num_js; i++) 249 pfdev->features.js_features[i] = gpu_read(pfdev, GPU_JS_FEATURES(i)); 250 251 pfdev->features.shader_present = gpu_read(pfdev, GPU_SHADER_PRESENT_LO); 252 pfdev->features.shader_present |= (u64)gpu_read(pfdev, GPU_SHADER_PRESENT_HI) << 32; 253 254 pfdev->features.tiler_present = gpu_read(pfdev, GPU_TILER_PRESENT_LO); 255 pfdev->features.tiler_present |= (u64)gpu_read(pfdev, GPU_TILER_PRESENT_HI) << 32; 256 257 pfdev->features.l2_present = gpu_read(pfdev, GPU_L2_PRESENT_LO); 258 pfdev->features.l2_present |= (u64)gpu_read(pfdev, GPU_L2_PRESENT_HI) << 32; 259 pfdev->features.nr_core_groups = hweight64(pfdev->features.l2_present); 260 261 pfdev->features.stack_present = gpu_read(pfdev, GPU_STACK_PRESENT_LO); 262 pfdev->features.stack_present |= (u64)gpu_read(pfdev, GPU_STACK_PRESENT_HI) << 32; 263 264 pfdev->features.thread_tls_alloc = gpu_read(pfdev, GPU_THREAD_TLS_ALLOC); 265 266 gpu_id = gpu_read(pfdev, GPU_ID); 267 pfdev->features.revision = gpu_id & 0xffff; 268 pfdev->features.id = gpu_id >> 16; 269 270 /* The T60x has an oddball ID value. Fix it up to the standard Midgard 271 * format so we (and userspace) don't have to special case it. 272 */ 273 if (pfdev->features.id == 0x6956) 274 pfdev->features.id = 0x0600; 275 276 major = (pfdev->features.revision >> 12) & 0xf; 277 minor = (pfdev->features.revision >> 4) & 0xff; 278 status = pfdev->features.revision & 0xf; 279 rev = pfdev->features.revision; 280 281 gpu_id = pfdev->features.id; 282 283 for (model = gpu_models; model->name; model++) { 284 int best = -1; 285 286 if (!panfrost_model_eq(pfdev, model->id)) 287 continue; 288 289 name = model->name; 290 hw_feat = model->features; 291 hw_issues |= model->issues; 292 for (i = 0; i < MAX_HW_REVS; i++) { 293 if (model->revs[i].revision == rev) { 294 best = i; 295 break; 296 } else if (model->revs[i].revision == (rev & ~0xf)) 297 best = i; 298 } 299 300 if (best >= 0) 301 hw_issues |= model->revs[best].issues; 302 303 break; 304 } 305 306 bitmap_from_u64(pfdev->features.hw_features, hw_feat); 307 bitmap_from_u64(pfdev->features.hw_issues, hw_issues); 308 309 dev_info(pfdev->dev, "mali-%s id 0x%x major 0x%x minor 0x%x status 0x%x", 310 name, gpu_id, major, minor, status); 311 dev_info(pfdev->dev, "features: %64pb, issues: %64pb", 312 pfdev->features.hw_features, 313 pfdev->features.hw_issues); 314 315 dev_info(pfdev->dev, "Features: L2:0x%08x Shader:0x%08x Tiler:0x%08x Mem:0x%0x MMU:0x%08x AS:0x%x JS:0x%x", 316 pfdev->features.l2_features, 317 pfdev->features.core_features, 318 pfdev->features.tiler_features, 319 pfdev->features.mem_features, 320 pfdev->features.mmu_features, 321 pfdev->features.as_present, 322 pfdev->features.js_present); 323 324 dev_info(pfdev->dev, "shader_present=0x%0llx l2_present=0x%0llx", 325 pfdev->features.shader_present, pfdev->features.l2_present); 326 } 327 328 static u64 panfrost_get_core_mask(struct panfrost_device *pfdev) 329 { 330 u64 core_mask; 331 332 if (pfdev->features.l2_present == 1) 333 return U64_MAX; 334 335 /* 336 * Only support one core group now. 337 * ~(l2_present - 1) unsets all bits in l2_present except 338 * the bottom bit. (l2_present - 2) has all the bits in 339 * the first core group set. AND them together to generate 340 * a mask of cores in the first core group. 341 */ 342 core_mask = ~(pfdev->features.l2_present - 1) & 343 (pfdev->features.l2_present - 2); 344 dev_info_once(pfdev->dev, "using only 1st core group (%lu cores from %lu)\n", 345 hweight64(core_mask), 346 hweight64(pfdev->features.shader_present)); 347 348 return core_mask; 349 } 350 351 void panfrost_gpu_power_on(struct panfrost_device *pfdev) 352 { 353 int ret; 354 u32 val; 355 u64 core_mask; 356 357 panfrost_gpu_init_quirks(pfdev); 358 core_mask = panfrost_get_core_mask(pfdev); 359 360 gpu_write(pfdev, L2_PWRON_LO, pfdev->features.l2_present & core_mask); 361 ret = readl_relaxed_poll_timeout(pfdev->iomem + L2_READY_LO, 362 val, val == (pfdev->features.l2_present & core_mask), 363 100, 20000); 364 if (ret) 365 dev_err(pfdev->dev, "error powering up gpu L2"); 366 367 gpu_write(pfdev, SHADER_PWRON_LO, 368 pfdev->features.shader_present & core_mask); 369 ret = readl_relaxed_poll_timeout(pfdev->iomem + SHADER_READY_LO, 370 val, val == (pfdev->features.shader_present & core_mask), 371 100, 20000); 372 if (ret) 373 dev_err(pfdev->dev, "error powering up gpu shader"); 374 375 gpu_write(pfdev, TILER_PWRON_LO, pfdev->features.tiler_present); 376 ret = readl_relaxed_poll_timeout(pfdev->iomem + TILER_READY_LO, 377 val, val == pfdev->features.tiler_present, 100, 1000); 378 if (ret) 379 dev_err(pfdev->dev, "error powering up gpu tiler"); 380 } 381 382 void panfrost_gpu_power_off(struct panfrost_device *pfdev) 383 { 384 int ret; 385 u32 val; 386 387 gpu_write(pfdev, SHADER_PWROFF_LO, pfdev->features.shader_present); 388 ret = readl_relaxed_poll_timeout(pfdev->iomem + SHADER_PWRTRANS_LO, 389 val, !val, 1, 2000); 390 if (ret) 391 dev_err(pfdev->dev, "shader power transition timeout"); 392 393 gpu_write(pfdev, TILER_PWROFF_LO, pfdev->features.tiler_present); 394 ret = readl_relaxed_poll_timeout(pfdev->iomem + TILER_PWRTRANS_LO, 395 val, !val, 1, 2000); 396 if (ret) 397 dev_err(pfdev->dev, "tiler power transition timeout"); 398 399 gpu_write(pfdev, L2_PWROFF_LO, pfdev->features.l2_present); 400 ret = readl_poll_timeout(pfdev->iomem + L2_PWRTRANS_LO, 401 val, !val, 0, 2000); 402 if (ret) 403 dev_err(pfdev->dev, "l2 power transition timeout"); 404 } 405 406 int panfrost_gpu_init(struct panfrost_device *pfdev) 407 { 408 int err, irq; 409 410 err = panfrost_gpu_soft_reset(pfdev); 411 if (err) 412 return err; 413 414 panfrost_gpu_init_features(pfdev); 415 416 err = dma_set_mask_and_coherent(pfdev->dev, 417 DMA_BIT_MASK(FIELD_GET(0xff00, pfdev->features.mmu_features))); 418 if (err) 419 return err; 420 421 dma_set_max_seg_size(pfdev->dev, UINT_MAX); 422 423 irq = platform_get_irq_byname(to_platform_device(pfdev->dev), "gpu"); 424 if (irq <= 0) 425 return -ENODEV; 426 427 err = devm_request_irq(pfdev->dev, irq, panfrost_gpu_irq_handler, 428 IRQF_SHARED, KBUILD_MODNAME "-gpu", pfdev); 429 if (err) { 430 dev_err(pfdev->dev, "failed to request gpu irq"); 431 return err; 432 } 433 434 panfrost_gpu_power_on(pfdev); 435 436 return 0; 437 } 438 439 void panfrost_gpu_fini(struct panfrost_device *pfdev) 440 { 441 panfrost_gpu_power_off(pfdev); 442 } 443 444 u32 panfrost_gpu_get_latest_flush_id(struct panfrost_device *pfdev) 445 { 446 u32 flush_id; 447 448 if (panfrost_has_hw_feature(pfdev, HW_FEATURE_FLUSH_REDUCTION)) { 449 /* Flush reduction only makes sense when the GPU is kept powered on between jobs */ 450 if (pm_runtime_get_if_in_use(pfdev->dev)) { 451 flush_id = gpu_read(pfdev, GPU_LATEST_FLUSH_ID); 452 pm_runtime_put(pfdev->dev); 453 return flush_id; 454 } 455 } 456 457 return 0; 458 } 459